1*8119dad8SRobert Mustacchi /* 2*8119dad8SRobert Mustacchi * This file and its contents are supplied under the terms of the 3*8119dad8SRobert Mustacchi * Common Development and Distribution License ("CDDL"), version 1.0. 4*8119dad8SRobert Mustacchi * You may only use this file in accordance with the terms of version 5*8119dad8SRobert Mustacchi * 1.0 of the CDDL. 6*8119dad8SRobert Mustacchi * 7*8119dad8SRobert Mustacchi * A full copy of the text of the CDDL should have accompanied this 8*8119dad8SRobert Mustacchi * source. A copy of the CDDL is also available via the Internet at 9*8119dad8SRobert Mustacchi * http://www.illumos.org/license/CDDL. 10*8119dad8SRobert Mustacchi */ 11*8119dad8SRobert Mustacchi 12*8119dad8SRobert Mustacchi /* 13*8119dad8SRobert Mustacchi * Copyright 2024 Oxide Computer Company 14*8119dad8SRobert Mustacchi */ 15*8119dad8SRobert Mustacchi 16*8119dad8SRobert Mustacchi #ifndef _SPD_LP4_H 17*8119dad8SRobert Mustacchi #define _SPD_LP4_H 18*8119dad8SRobert Mustacchi 19*8119dad8SRobert Mustacchi /* 20*8119dad8SRobert Mustacchi * Definitions for use in LPDDR3, LPDDR4, and LPDDR4x Serial Presence Decoding 21*8119dad8SRobert Mustacchi * based on JEDEC Standard 21-C Section Title: Annex M: Serial Presence Detect 22*8119dad8SRobert Mustacchi * (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Release 2. While this covers 23*8119dad8SRobert Mustacchi * multiple revisions, we'll generally refer to this collectively as LPDDR4. 24*8119dad8SRobert Mustacchi * 25*8119dad8SRobert Mustacchi * LPDDR4 modules are organized into a few regions that are generally similar to 26*8119dad8SRobert Mustacchi * DDR4, though the contents vary: 27*8119dad8SRobert Mustacchi * 28*8119dad8SRobert Mustacchi * o Base Configuration and DRAM parameters (bytes 0x00-0x7f) 29*8119dad8SRobert Mustacchi * o Standard Module Parameters (bytes 0x80-0xff) these vary on whether 30*8119dad8SRobert Mustacchi * something is an LP-DIMM or soldered down. 31*8119dad8SRobert Mustacchi * o Hybrid Module Extended Parameters (bytes 0x100-0x13f). 32*8119dad8SRobert Mustacchi * o Manufacturing Information (bytes 0x140-0x17f) 33*8119dad8SRobert Mustacchi * o End User Programmable data (0x180-0x1ff). 34*8119dad8SRobert Mustacchi */ 35*8119dad8SRobert Mustacchi 36*8119dad8SRobert Mustacchi #include <sys/bitext.h> 37*8119dad8SRobert Mustacchi #include "spd_common.h" 38*8119dad8SRobert Mustacchi 39*8119dad8SRobert Mustacchi #ifdef __cplusplus 40*8119dad8SRobert Mustacchi extern "C" { 41*8119dad8SRobert Mustacchi #endif 42*8119dad8SRobert Mustacchi 43*8119dad8SRobert Mustacchi /* 44*8119dad8SRobert Mustacchi * S3.1.1 Number of Bytes Used / Number of Bytes in SPD Device. 45*8119dad8SRobert Mustacchi */ 46*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES 0x000 47*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_TOTAL(r) bitx8(r, 6, 4) 48*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_TOTAL_UNDEF 0 49*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_TOTAL_256 1 50*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_TOTAL_512 2 51*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_USED(r) bitx8(r, 3, 0) 52*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_USED_UNDEF 0 53*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_USED_128 1 54*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_USED_256 2 55*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_USED_384 3 56*8119dad8SRobert Mustacchi #define SPD_LP4_NBYTES_USED_512 4 57*8119dad8SRobert Mustacchi 58*8119dad8SRobert Mustacchi 59*8119dad8SRobert Mustacchi /* 60*8119dad8SRobert Mustacchi * S3.1.2 SPD Revision. This is the same as described in SPD_DDR4_SPD_REV as 61*8119dad8SRobert Mustacchi * defined in spd_ddr4.h. 62*8119dad8SRobert Mustacchi */ 63*8119dad8SRobert Mustacchi #define SPD_LP4_SPD_REV 0x001 64*8119dad8SRobert Mustacchi #define SPD_LP4_SPD_REV_ENC(r) bitx8(r, 7, 4) 65*8119dad8SRobert Mustacchi #define SPD_LP4_SPD_REV_ADD(r) bitx8(r, 3, 0) 66*8119dad8SRobert Mustacchi #define SPD_LP4_SPD_REV_V1 1 67*8119dad8SRobert Mustacchi 68*8119dad8SRobert Mustacchi /* 69*8119dad8SRobert Mustacchi * Key Byte / DRAM Device Type. This field identifies the type of DDR device and 70*8119dad8SRobert Mustacchi * is actually consistent across all SPD versions. Known values are in the 71*8119dad8SRobert Mustacchi * spd_dram_type_t enumeration. 72*8119dad8SRobert Mustacchi */ 73*8119dad8SRobert Mustacchi #define SPD_LP4_DRAM_TYPE 0x002 74*8119dad8SRobert Mustacchi 75*8119dad8SRobert Mustacchi /* 76*8119dad8SRobert Mustacchi * S3.1.4: Key Byte / Module type. This is used to describe what kind of DDR 77*8119dad8SRobert Mustacchi * module it is, which tell us what the module-specific section contents are. 78*8119dad8SRobert Mustacchi * These bits, unlike the one above are device specific. 79*8119dad8SRobert Mustacchi */ 80*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_TYPE 0x003 81*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_TYPE_ISHYBRID(r) bitx8(r, 7, 7) 82*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_TYPE_HYBRID(r) bitx8(r, 6, 4) 83*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_TYPE_HYBRID_NONE 0 84*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_TYPE_TYPE(r) bitx8(r, 3, 0) 85*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_TYPE_TYPE_EXT 0 86*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_TYPE_TYPE_LPDIMM 0x7 87*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_TYPE_TYPE_SOLDER 0xe 88*8119dad8SRobert Mustacchi 89*8119dad8SRobert Mustacchi /* 90*8119dad8SRobert Mustacchi * S3.1.5 SDRAM Density and Banks. 91*8119dad8SRobert Mustacchi */ 92*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY 0x004 93*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_NBG_BITS(r) bitx8(r, 7, 6) 94*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_NBG_BITS_MAX 2 95*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_NBA_BITS(r) bitx8(r, 5, 4) 96*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_NBA_BITS_BASE 2 97*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_NBA_BITS_MAX 3 98*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY(r) bitx8(r, 3, 0) 99*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_1Gb 2 100*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_2Gb 3 101*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_4Gb 4 102*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_8Gb 5 103*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_16Gb 6 104*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_32Gb 7 105*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_12Gb 8 106*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_24Gb 9 107*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_3Gb 10 108*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_6Gb 11 109*8119dad8SRobert Mustacchi #define SPD_LP4_DENSITY_DENSITY_18Gb 12 110*8119dad8SRobert Mustacchi 111*8119dad8SRobert Mustacchi /* 112*8119dad8SRobert Mustacchi * S3.1.6 SDRAM Addressing. 113*8119dad8SRobert Mustacchi */ 114*8119dad8SRobert Mustacchi #define SPD_LP4_ADDR 0x005 115*8119dad8SRobert Mustacchi #define SPD_LP4_ADDR_NROWS(r) bitx8(r, 5, 3) 116*8119dad8SRobert Mustacchi #define SPD_LP4_ADDR_NROWS_BASE 12 117*8119dad8SRobert Mustacchi #define SPD_LP4_ADDR_NROWS_MAX 18 118*8119dad8SRobert Mustacchi #define SPD_LP4_ADDR_NCOLS(r) bitx8(r, 2, 0) 119*8119dad8SRobert Mustacchi #define SPD_LP4_ADDR_NCOLS_BASE 9 120*8119dad8SRobert Mustacchi #define SPD_LP4_ADDR_NCOLS_MAX 12 121*8119dad8SRobert Mustacchi 122*8119dad8SRobert Mustacchi /* 123*8119dad8SRobert Mustacchi * S3.1.7 SDRAM Package Type 124*8119dad8SRobert Mustacchi */ 125*8119dad8SRobert Mustacchi #define SPD_LP4_PKG 0x006 126*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_TYPE(r) bitx8(r, 7, 7) 127*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_TYPE_MONO 0 128*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_TYPE_NOT 1 129*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_DIE_CNT(r) bitx8(r, 6, 4) 130*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_DIE_CNT_BASE 1 131*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_NCHAN(r) bitx8(r, 3, 2) 132*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_NCHAN_MAX 4 133*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_SL(r) bitx8(r, 1, 0) 134*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_SL_M1 1 135*8119dad8SRobert Mustacchi #define SPD_LP4_PKG_SL_M2 3 136*8119dad8SRobert Mustacchi 137*8119dad8SRobert Mustacchi /* 138*8119dad8SRobert Mustacchi * S3.1.8 SDRAM Optional Features. 139*8119dad8SRobert Mustacchi */ 140*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT 0x007 141*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAW(r) bitx8(r, 5, 4) 142*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAW_8192X 0 143*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAW_4096X 1 144*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAW_2048X 2 145*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAC(r) bitx8(r, 3, 0) 146*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAC_UNTESTED 0 147*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAC_700K 1 148*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAC_600K 2 149*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAC_500K 3 150*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAC_400K 4 151*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAC_300K 5 152*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAC_200K 6 153*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT_MAC_UNLIMITED 8 154*8119dad8SRobert Mustacchi 155*8119dad8SRobert Mustacchi /* 156*8119dad8SRobert Mustacchi * S3.1.10 Other SDRAM Optional Features. These are even more that aren't in the 157*8119dad8SRobert Mustacchi * first set of optional features. 158*8119dad8SRobert Mustacchi */ 159*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT2 0x009 160*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT2_PPR(r) bitx8(r, 7, 6) 161*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT2_PPR_NOTSUP 0 162*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT2_PPR_1RPBG 1 163*8119dad8SRobert Mustacchi #define SPD_LP4_OPT_FEAT2_SOFT_PPR(r) bitx8(r, 5, 5) 164*8119dad8SRobert Mustacchi 165*8119dad8SRobert Mustacchi /* 166*8119dad8SRobert Mustacchi * S3.1.13 Module Organization 167*8119dad8SRobert Mustacchi */ 168*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG 0x00c 169*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_IDENT(r) bitx8(r, 6, 6) 170*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_IDENT_STD 0 171*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_IDENT_BYTE 1 172*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_RANK_MIX(r) bitx8(r, 6, 6) 173*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_RANK_MIX_SYM 0 174*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_RANK_MIX_ASYM 1 175*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_NPKG_RANK(r) bitx8(r, 5, 3) 176*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_NPKG_RANK_BASE 1 177*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_NPKG_RANK_MAX 4 178*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_WIDTH(r) bitx8(r, 2, 0) 179*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_WIDTH_BASE 2 180*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_ORG_WIDTH_MAX 32 181*8119dad8SRobert Mustacchi 182*8119dad8SRobert Mustacchi /* 183*8119dad8SRobert Mustacchi * S3.1.14 Memory Bus Width. 184*8119dad8SRobert Mustacchi */ 185*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH 0x00d 186*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_NCHAN(r) bitx8(r, 7, 5) 187*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_NCHAN_1ch 0 188*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_NCHAN_2ch 1 189*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_NCHAN_3ch 2 190*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_NCHAN_4ch 3 191*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_NCHAN_8ch 4 192*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_EXT(r) bitx8(r, 4, 3) 193*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_EXT_NONE 0 194*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_PRI(r) bitx8(r, 2, 0) 195*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_PRI_BASE 3 196*8119dad8SRobert Mustacchi #define SPD_LP4_BUS_WIDTH_PRI_MAX 64 197*8119dad8SRobert Mustacchi 198*8119dad8SRobert Mustacchi /* 199*8119dad8SRobert Mustacchi * S8.1.15 Module Thermal Sensor. 200*8119dad8SRobert Mustacchi */ 201*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_THERM 0x00e 202*8119dad8SRobert Mustacchi #define SPD_LP4_MOD_THERM_PRES(r) bitx8(r, 7, 7) 203*8119dad8SRobert Mustacchi 204*8119dad8SRobert Mustacchi /* 205*8119dad8SRobert Mustacchi * S3.1.17 Signal Loading 206*8119dad8SRobert Mustacchi * 207*8119dad8SRobert Mustacchi * The values of the signal loading are dependent on the value found in the 208*8119dad8SRobert Mustacchi * SPD_LP4_PKG (byte 6) register, The interpretation varies based on the value 209*8119dad8SRobert Mustacchi * of SPD_LP4_PKG_SL(). However, the only defined signal loading matrix is 210*8119dad8SRobert Mustacchi * matrix 1. 211*8119dad8SRobert Mustacchi */ 212*8119dad8SRobert Mustacchi #define SPD_LP4_SIGLOAD 0x010 213*8119dad8SRobert Mustacchi #define SPD_LP4_SIGLOAD1_DSM_LOAD(r) bitx8(r, 7, 6) 214*8119dad8SRobert Mustacchi #define SPD_LP4_SIGLOAD1_DSM_LOAD_MAX 4 215*8119dad8SRobert Mustacchi #define SPD_LP4_SIGLOAD1_CAC_LOAD(r) bitx8(r, 5, 3) 216*8119dad8SRobert Mustacchi #define SPD_LP4_SIGLOAD1_CAC_LOAD_MAX 8 217*8119dad8SRobert Mustacchi #define SPD_LP4_SIGLOAD1_CS_LOAD(r) bitx8(r, 2, 0) 218*8119dad8SRobert Mustacchi #define SPD_LP4_SIGLOAD1_CS_LOAD_MAX 8 219*8119dad8SRobert Mustacchi 220*8119dad8SRobert Mustacchi /* 221*8119dad8SRobert Mustacchi * Timebases 222*8119dad8SRobert Mustacchi * 223*8119dad8SRobert Mustacchi * Like with DDR4, there are strictly speaking timebase values encoded in the 224*8119dad8SRobert Mustacchi * registers that describe how to calculate other values. These are broken into 225*8119dad8SRobert Mustacchi * the Medium and Fine timebases respectively which as of v1.0 have fixed 226*8119dad8SRobert Mustacchi * values of 125ps and 1ps respectively. See the DDR4 version for more 227*8119dad8SRobert Mustacchi * information. 228*8119dad8SRobert Mustacchi */ 229*8119dad8SRobert Mustacchi #define SPD_LP4_TIMEBASE 0x011 230*8119dad8SRobert Mustacchi #define SPD_LP4_TIMEBASE_MTB(r) bitx8(r, 3, 2) 231*8119dad8SRobert Mustacchi #define SPD_LP4_TIMEBASE_MTB_125ps 0 232*8119dad8SRobert Mustacchi #define SPD_LP4_TIMEBASE_FTB(r) bitx8(r, 1, 0) 233*8119dad8SRobert Mustacchi #define SPD_LP4_TIMEBASE_FTB_1ps 0 234*8119dad8SRobert Mustacchi #define SPD_LP4_MTB_PS 125 235*8119dad8SRobert Mustacchi #define SPD_LP4_FTB_PS 1 236*8119dad8SRobert Mustacchi 237*8119dad8SRobert Mustacchi /* 238*8119dad8SRobert Mustacchi * S3.1.19 SDRAM Minimum Cycle Time t~ckavg~min. 239*8119dad8SRobert Mustacchi * S3.1.37 Fine Offset for ^ 240*8119dad8SRobert Mustacchi * S3.1.20 SDRAM Maximum Cycle Time t~ckavg~max. 241*8119dad8SRobert Mustacchi * S3.1.36 Fine Offset for ^ 242*8119dad8SRobert Mustacchi */ 243*8119dad8SRobert Mustacchi #define SPD_LP4_TCKAVG_MIN 0x012 244*8119dad8SRobert Mustacchi #define SPD_LP4_TCKAVG_MIN_FINE 0x07d 245*8119dad8SRobert Mustacchi #define SPD_LP4_TCKAVG_MAX 0x013 246*8119dad8SRobert Mustacchi #define SPD_LP4_TCKAVG_MAX_FINE 0x07c 247*8119dad8SRobert Mustacchi 248*8119dad8SRobert Mustacchi /* 249*8119dad8SRobert Mustacchi * S3.1.21 CAS Latencies. These are four bytes that are used to get at what 250*8119dad8SRobert Mustacchi * speeds are supported. These always start at CL3, but the mapping of bits to 251*8119dad8SRobert Mustacchi * CL values is not uniform. 252*8119dad8SRobert Mustacchi */ 253*8119dad8SRobert Mustacchi #define SPD_LP4_CAS_SUP0 0x014 254*8119dad8SRobert Mustacchi #define SPD_LP4_CAS_SUP1 0x015 255*8119dad8SRobert Mustacchi #define SPD_LP4_CAS_SUP2 0x016 256*8119dad8SRobert Mustacchi #define SPD_LP4_CAS_SUP3 0x017 257*8119dad8SRobert Mustacchi 258*8119dad8SRobert Mustacchi /* 259*8119dad8SRobert Mustacchi * S3.1.22 Minimum CAS Latency Time t~AA~min. This uses the MTB. 260*8119dad8SRobert Mustacchi * S3.1.35 Fine Offset for ^ 261*8119dad8SRobert Mustacchi */ 262*8119dad8SRobert Mustacchi #define SPD_LP4_TAA_MIN 0x018 263*8119dad8SRobert Mustacchi #define SPD_LP4_TAA_MIN_FINE 0x07b 264*8119dad8SRobert Mustacchi 265*8119dad8SRobert Mustacchi /* 266*8119dad8SRobert Mustacchi * S3.1.23 Read and Write Latency Set Options 267*8119dad8SRobert Mustacchi */ 268*8119dad8SRobert Mustacchi #define SPD_LP4_RWLAT 0x019 269*8119dad8SRobert Mustacchi #define SPD_LP4_RWLAT_WRITE(r) bitx8(r, 3, 2) 270*8119dad8SRobert Mustacchi #define SPD_LP4_RWLAT_WRITE_A 0 271*8119dad8SRobert Mustacchi #define SPD_LP4_RWLAT_WRITE_B 1 272*8119dad8SRobert Mustacchi #define SPD_LP4_RWLAT_READ(r) bitx8(r, 1, 0) 273*8119dad8SRobert Mustacchi #define SPD_LP4_RWLAT_DBIRD_DIS 0 274*8119dad8SRobert Mustacchi #define SPD_LP4_RWLAT_DBIRD_EN 1 275*8119dad8SRobert Mustacchi 276*8119dad8SRobert Mustacchi /* 277*8119dad8SRobert Mustacchi * S3.1.24 Minimum RAS to CAS Delay Time t~RCD~min. 278*8119dad8SRobert Mustacchi * S3.1.34 Fine Offset for ^ 279*8119dad8SRobert Mustacchi */ 280*8119dad8SRobert Mustacchi #define SPD_LP4_TRCD_MIN 0x01a 281*8119dad8SRobert Mustacchi #define SPD_LP4_TRCD_MIN_FINE 0x07a 282*8119dad8SRobert Mustacchi 283*8119dad8SRobert Mustacchi /* 284*8119dad8SRobert Mustacchi * S3.1.25 All Banks Minimum Row Precharge Delay Time t~RPab~min. 285*8119dad8SRobert Mustacchi * S3.1.33 Fine Offset for ^ 286*8119dad8SRobert Mustacchi */ 287*8119dad8SRobert Mustacchi #define SPD_LP4_TRPAB_MIN 0x01b 288*8119dad8SRobert Mustacchi #define SPD_LP4_TRPAB_MIN_FINE 0x079 289*8119dad8SRobert Mustacchi 290*8119dad8SRobert Mustacchi /* 291*8119dad8SRobert Mustacchi * S3.1.26 Per Bank Minimum Row Precharge Delay Time t~RPpb~min. 292*8119dad8SRobert Mustacchi * S3.1.32 Fine Offset for ^ 293*8119dad8SRobert Mustacchi */ 294*8119dad8SRobert Mustacchi #define SPD_LP4_TRPPB_MIN 0x01c 295*8119dad8SRobert Mustacchi #define SPD_LP4_TRPPB_MIN_FINE 0x078 296*8119dad8SRobert Mustacchi 297*8119dad8SRobert Mustacchi /* 298*8119dad8SRobert Mustacchi * S3.1.27 All Banks Minimum Refresh Recovery Delay Time t~RFCab~min. This is a 299*8119dad8SRobert Mustacchi * 16-bit quantity that is split between a lower and upper value. Both registers 300*8119dad8SRobert Mustacchi * are in terms of the medium time base. 301*8119dad8SRobert Mustacchi */ 302*8119dad8SRobert Mustacchi #define SPD_LP4_TRFCAB_MIN_LO 0x1d 303*8119dad8SRobert Mustacchi #define SPD_LP4_TRFCAB_MIN_HI 0x1e 304*8119dad8SRobert Mustacchi 305*8119dad8SRobert Mustacchi /* 306*8119dad8SRobert Mustacchi * S3.1.28 Per Bank Minimum Refresh Recovery Delay Time t~RFCpb~min. This is a 307*8119dad8SRobert Mustacchi * 16-bit quantity that is split between a lower and upper value. Both registers 308*8119dad8SRobert Mustacchi * are in terms of the medium time base. 309*8119dad8SRobert Mustacchi */ 310*8119dad8SRobert Mustacchi #define SPD_LP4_TRFCPB_MIN_LO 0x1f 311*8119dad8SRobert Mustacchi #define SPD_LP4_TRFCPB_MIN_HI 0x20 312*8119dad8SRobert Mustacchi 313*8119dad8SRobert Mustacchi /* 314*8119dad8SRobert Mustacchi * S3.1.30 Connector to SDRAM bit mapping. Each of the bytes defines a different 315*8119dad8SRobert Mustacchi * set of pins here. These all have a fairly standard set of transformations 316*8119dad8SRobert Mustacchi * that can be applied. These include a package rank map which only has a single 317*8119dad8SRobert Mustacchi * identity transformation applied and a separate nibble map encoding. 318*8119dad8SRobert Mustacchi */ 319*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ0 0x03c 320*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ4 0x03d 321*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ8 0x03e 322*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ12 0x03f 323*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ16 0x040 324*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ20 0x041 325*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ24 0x042 326*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ28 0x043 327*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_CB0 0x044 328*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_CB4 0x045 329*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ32 0x046 330*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ36 0x047 331*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ40 0x048 332*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ44 0x049 333*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ48 0x04a 334*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ52 0x04b 335*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ56 0x04c 336*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_DQ60 0x04d 337*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_PKG(r) bitx8(r, 7, 6) 338*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_PKG_FLIP 0 339*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_NIBBLE(r) bitx8(r, 5, 5) 340*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_IDX(r) bitx8(r, 4, 0) 341*8119dad8SRobert Mustacchi #define SPD_LP4_MAP_IDX_UNSPEC 0 342*8119dad8SRobert Mustacchi 343*8119dad8SRobert Mustacchi /* 344*8119dad8SRobert Mustacchi * S3.1.38 CRC For Base Configuration Section. This is a CRC that covers bytes 345*8119dad8SRobert Mustacchi * 0x00 to 0x7D using a specific CRC16. 346*8119dad8SRobert Mustacchi */ 347*8119dad8SRobert Mustacchi #define SPD_LP4_CRC_LSB 0x07e 348*8119dad8SRobert Mustacchi #define SPD_LP4_CRC_MSB 0x07f 349*8119dad8SRobert Mustacchi 350*8119dad8SRobert Mustacchi /* 351*8119dad8SRobert Mustacchi * The manufacturing information section is identical to DDR4. 352*8119dad8SRobert Mustacchi */ 353*8119dad8SRobert Mustacchi 354*8119dad8SRobert Mustacchi /* 355*8119dad8SRobert Mustacchi * LPDDR3/4 only define an annex for the LP-DIMM form factor. 356*8119dad8SRobert Mustacchi */ 357*8119dad8SRobert Mustacchi 358*8119dad8SRobert Mustacchi /* 359*8119dad8SRobert Mustacchi * S4.1.1 LP-DIMM: Raw Card Extension, Module Nominal Height. Bits 7-5 here have 360*8119dad8SRobert Mustacchi * a raw card revision. The revision extension, bits 7:5, are only valid when 361*8119dad8SRobert Mustacchi * the value of the normal reference card used in byte 0x82 is set to 0b11 (3). 362*8119dad8SRobert Mustacchi */ 363*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_HEIGHT 0x080 364*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_HEIGHT_REV(r) bitx8(r, 7, 5) 365*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_HEIGHT_MM(r) bitx8(r, 4, 0) 366*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_HEIGHT_LT15MM 0 367*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_HEIGHT_BASE 15 368*8119dad8SRobert Mustacchi 369*8119dad8SRobert Mustacchi /* 370*8119dad8SRobert Mustacchi * S4.1.2 LP-DIMM: Module Maximum Thickness. These measure thicknesses in mm, 371*8119dad8SRobert Mustacchi * with zero value meaning less than or equal to 1mm. 372*8119dad8SRobert Mustacchi */ 373*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_THICK 0x081 374*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_THICK_BACK(r) bitx8(r, 7, 4) 375*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_THICK_FRONT(r) bitx8(r, 3, 0) 376*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_THICK_BASE 1 377*8119dad8SRobert Mustacchi 378*8119dad8SRobert Mustacchi /* 379*8119dad8SRobert Mustacchi * S4.1.3 LP-DIMM: Reference Raw Card Used. Bit 7 is used as basically another 380*8119dad8SRobert Mustacchi * bit for bits 4-0. We do not define each meaning of these bit combinations in 381*8119dad8SRobert Mustacchi * this header, that is left for tables in the library. When bits 6:5 are 0b11 382*8119dad8SRobert Mustacchi * (3) then we must add in the reference card value in byte 0x80 to bits 6:5. 383*8119dad8SRobert Mustacchi */ 384*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_REF 0x082 385*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_REF_EXT(r) bitx8(r, 7, 7) 386*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_REF_REV(r) bitx8(r, 6, 5) 387*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_REV_USE_HEIGHT 3 388*8119dad8SRobert Mustacchi #define SPD_LP4_LPDIMM_REF_CARD(r) bitx8(r, 4, 0) 389*8119dad8SRobert Mustacchi 390*8119dad8SRobert Mustacchi /* 391*8119dad8SRobert Mustacchi * S4.1.5 LP-DIMM: CRC. Like DDR4, this is the CRC for the upper page. However, 392*8119dad8SRobert Mustacchi * it is only defined on a per-Annex basis. 393*8119dad8SRobert Mustacchi */ 394*8119dad8SRobert Mustacchi #define SPD_LP4_BLK1_CRC_START 0x80 395*8119dad8SRobert Mustacchi #define SPD_LP4_BLK1_CRC_LSB 0xfe 396*8119dad8SRobert Mustacchi #define SPD_LP4_BLK1_CRC_MSB 0xff 397*8119dad8SRobert Mustacchi 398*8119dad8SRobert Mustacchi #ifdef __cplusplus 399*8119dad8SRobert Mustacchi } 400*8119dad8SRobert Mustacchi #endif 401*8119dad8SRobert Mustacchi 402*8119dad8SRobert Mustacchi #endif /* _SPD_LP4_H */ 403