1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2026 Oxide Computer Company 14 */ 15 16 #ifndef _SPD_DDR5_H 17 #define _SPD_DDR5_H 18 19 /* 20 * Definitions for use in DDR5 Serial Presence Detect decoding based on JEDEC 21 * Standard JESD400-5D.01 DDR5 Serial Presence Detect (SPD) Contents. Release 22 * 1.4. This does not cover LPDDR5. While the two are similar, there are enough 23 * differences that we maintain LPDDR5 in its own header (spd_lp5.h). 24 * 25 * DDR5 modules are organized into a few main regions: 26 * 27 * o Base Configuration and DRAM parameters (0x00-0x7f) 28 * o Common Module Parameters (0xc0-0xef) 29 * o Standard Module Parameters (0xf0-0x1bf) which vary on whether something 30 * is an RDIMM, UDIMM, etc. 31 * o A CRC check for the first 510 bytes (0x1fe-0x1ff) 32 * o Manufacturing Information (0x200-0x27f) 33 * o Optional end-user programmable regions (0x280-0x3ff) 34 * 35 * This covers all DDR5 variants other than NVDIMMs. 36 */ 37 38 #include <sys/bitext.h> 39 #include "spd_common.h" 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* 46 * S8.1.1 Number of Bytes in SPD Device and Beta Level 47 */ 48 #define SPD_DDR5_NBYTES 0x000 49 #define SPD_DDR5_NBYTES_BETAHI(r) bitx8(r, 7, 7) 50 #define SPD_DDR5_NBYTES_TOTAL(r) bitx8(r, 6, 4) 51 #define SPD_DDR5_NBYTES_TOTAL_UNDEF 0 52 #define SPD_DDR5_NBYTES_TOTAL_256 1 53 #define SPD_DDR5_NBYTES_TOTAL_512 2 54 #define SPD_DDR5_NBYTES_TOTAL_1024 3 55 #define SPD_DDR5_NBYTES_TOTAL_2048 4 56 #define SPD_DDR5_NBYTES_BETA(r) bitx8(r, 3, 0) 57 58 /* 59 * S8.1.2 SPD Revision for Base Configuration Parameters. This is the same as 60 * described in SPD_DDR4_SPD_REV as defined in spd_ddr4.h. 61 */ 62 #define SPD_DDR5_SPD_REV 0x001 63 #define SPD_DDR5_SPD_REV_ENC(r) bitx8(r, 7, 4) 64 #define SPD_DDR5_SPD_REV_ADD(r) bitx8(r, 3, 0) 65 #define SPD_DDR5_SPD_REV_V1 1 66 67 /* 68 * S8.1.3: Key Byte / DRAM Device Type. This field identifies the type of DDR 69 * device and is actually consistent across all SPD versions. Known values are 70 * in the spd_dram_type_t enumeration. 71 */ 72 #define SPD_DDR5_DRAM_TYPE 0x002 73 74 /* 75 * S8.1.4 Key Byte / Module Type 76 */ 77 #define SPD_DDR5_MOD_TYPE 0x003 78 #define SPD_DDR5_MOD_TYPE_ISHYBRID(r) bitx8(r, 7, 7) 79 #define SPD_DDR5_MOD_TYPE_HYBRID(r) bitx8(r, 6, 4) 80 #define SPD_DDR5_MOD_TYPE_HYBRID_NONE 0 81 #define SPD_DDR5_MOD_TYPE_HYBRID_NVDIMM_N 1 82 #define SPD_DDR5_MOD_TYPE_HYBRID_NVDIMM_P 2 83 #define SPD_DDR5_MOD_TYPE_TYPE(r) bitx8(r, 3, 0) 84 #define SPD_DDR5_MOD_TYPE_TYPE_RDIMM 1 85 #define SPD_DDR5_MOD_TYPE_TYPE_UDIMM 2 86 #define SPD_DDR5_MOD_TYPE_TYPE_SODIMM 3 87 #define SPD_DDR5_MOD_TYPE_TYPE_LRDIMM 4 88 #define SPD_DDR5_MOD_TYPE_TYPE_CUDIMM 5 89 #define SPD_DDR5_MOD_TYPE_TYPE_CSODIMM 6 90 #define SPD_DDR5_MOD_TYPE_TYPE_MRDIMM 7 91 #define SPD_DDR5_MOD_TYPE_TYPE_CAMM2 8 92 #define SPD_DDR5_MOD_TYPE_TYPE_SOCAMM2 9 93 #define SPD_DDR5_MOD_TYPE_TYPE_DDIMM 10 94 #define SPD_DDR5_MOD_TYPE_TYPE_SOLDER 11 95 96 /* 97 * S8.1.5 First SDRAM Density and Package 98 * S8.1.9 Second SDRAM Density and Package 99 */ 100 #define SPD_DDR5_DENPKG1 0x004 101 #define SPD_DDR5_DENPKG2 0x008 102 #define SPD_DDR5_DENPKG_DPP(r) bitx8(r, 7, 5) 103 #define SPD_DDR5_DENPKG_DPP_MONO 0 104 #define SPD_DDR5_DENPKG_DPP_DDP 1 105 #define SPD_DDR5_DENPKG_DPP_2H3DS 2 106 #define SPD_DDR5_DENPKG_DPP_4H3DS 3 107 #define SPD_DDR5_DENPKG_DPP_8H3DS 4 108 #define SPD_DDR5_DENPKG_DPP_16H3DS 5 109 #define SPD_DDR5_DENPKG_DPD(r) bitx8(r, 4, 0) 110 #define SPD_DDR5_DENPKG_DPD_4Gb 1 111 #define SPD_DDR5_DENPKG_DPD_8Gb 2 112 #define SPD_DDR5_DENPKG_DPD_12Gb 3 113 #define SPD_DDR5_DENPKG_DPD_16Gb 4 114 #define SPD_DDR5_DENPKG_DPD_24Gb 5 115 #define SPD_DDR5_DENPKG_DPD_32Gb 6 116 #define SPD_DDR5_DENPKG_DPD_48Gb 7 117 #define SPD_DDR5_DENPKG_DPD_64Gb 8 118 119 /* 120 * S8.1.6 First SDRAM Addressing 121 * S8.1.10 Second SDRAM Addressing 122 */ 123 #define SPD_DDR5_ADDR1 0x005 124 #define SPD_DDR5_ADDR2 0x009 125 #define SPD_DDR5_ADDR_NCOLS(r) bitx8(r, 7, 5) 126 #define SPD_DDR5_ADDR_NCOLS_BASE 10 127 #define SPD_DDR5_ADDR_NCOLS_MAX 11 128 #define SPD_DDR5_ADDR_NROWS(r) bitx8(r, 4, 0) 129 #define SPD_DDR5_ADDR_NROWS_BASE 16 130 #define SPD_DDR5_ADDR_NROWS_MAX 18 131 132 /* 133 * S8.1.7 First SDRAM I/O Width 134 * S8.1.11 Second SDRAM I/O Width 135 */ 136 #define SPD_DDR5_WIDTH1 0x006 137 #define SPD_DDR5_WIDTH2 0x00a 138 #define SPD_DDR5_WIDTH_WIDTH(r) bitx8(r, 7, 5) 139 #define SPD_DDR5_WIDTH_X4 0 140 #define SPD_DDR5_WIDTH_X8 1 141 #define SPD_DDR5_WIDTH_X16 2 142 #define SPD_DDR5_WIDTH_X32 3 143 144 /* 145 * S8.1.8 First SDRAM Bank Groups and Banks per Bank Group 146 * S8.1.8 Second SDRAM Bank Groups and Banks per Bank Group 147 * 148 * Both values here are in the number of bits that correspond to bank groups and 149 * banks per group. In other words, the total number is 1 << value. 150 */ 151 #define SPD_DDR5_BANKS1 0x007 152 #define SPD_DDR5_BANKS2 0x00b 153 #define SPD_DDR5_BANKS_NBG_BITS(r) bitx8(r, 7, 5) 154 #define SPD_DDR5_BANKS_NBG_BITS_MAX 3 155 #define SPD_DDR5_BANKS_NBA_BITS(r) bitx8(r, 2, 0) 156 #define SPD_DDR5_BANKS_NBA_BITS_MAX 2 157 158 /* 159 * S8.1.13 SDRAM BL32 and Post Package Repair 160 */ 161 #define SPD_DDR5_PPR 0x00c 162 #define SPD_DDR5_PPR_GRAN(r) bitx8(r, 7, 7) 163 #define SPD_DDR5_PPR_GRAN_BGRP 0 164 #define SPD_DDR5_PPR_GRAN_BANK 1 165 #define SPD_DDR5_PPR_LOCK_SUP(r) bitx8(r, 5, 5) 166 #define SPD_DDR5_PPR_BL32_SUP(r) bitx8(r, 4, 4) 167 #define SPD_DDR5_PPR_MPPR_SUP(r) bitx8(r, 1, 1) 168 169 /* 170 * S8.1.14 SDRAM Duty Cycle Adjustor and Partial Array Self Refresh 171 */ 172 #define SPD_DDR5_SDA 0x00d 173 #define SPD_DDR5_SPD_DCA_PASR(r) bitx8(r, 4, 4) 174 #define SPD_DDR5_SPD_DCA_TYPE(r) bitx8(r, 1, 0) 175 #define SPD_DDR5_SPD_DCA_TYPE_UNSUP 0 176 #define SPD_DDR5_SPD_DCA_TYPE_1_2P 1 177 #define SPD_DDR5_SPD_DCA_TYPE_4P 2 178 179 /* 180 * S8.1.15 SDRAM Fault Handling and Temperature Sense 181 */ 182 #define SPD_DDR5_FLT 0x00e 183 #define SPD_DDR5_FLT_PRAC_ABO(r) bitx8(r, 4, 4) 184 #define SPD_DDR5_FLT_WIDE_TS(r) bitx8(r, 3, 3) 185 #define SPD_DDR5_FLT_WBSUPR_SUP(r) bitx8(r, 2, 2) 186 #define SPD_DDR5_FLT_WBSUPR_SEL(r) bitx8(r, 1, 1) 187 #define SPD_DDR5_FLT_WBSUPR_SEL_MR9 0 188 #define SPD_DDR5_FLT_WBSUPR_SEL_MR15 1 189 #define SPD_DDR5_FLT_BFLT(r) bitx8(r, 0, 0) 190 191 /* 192 * S8.1.17 SDRAM Nominal Voltage, VDD 193 * S8.1.18 SDRAM Nominal Voltage, VDDQ 194 * S8.1.19 SDRAM Nominal Voltage, VDP 195 * 196 * These three share the same breakdown between nominal, operable, and endurant 197 * voltages. However, the actual values that they support are different. 198 */ 199 #define SPD_DDR5_DRAM_VDD 0x010 200 #define SPD_DDR5_DRAM_VDDQ 0x011 201 #define SPD_DDR5_DRAM_VPP 0x012 202 #define SPD_DDR5_DRAM_VOLT_NOM(r) bitx8(r, 7, 4) 203 #define SPD_DDR5_DRAM_VOLT_OPER(r) bitx8(r, 3, 2) 204 #define SPD_DDR5_DRAM_VOLT_END(r) bitx8(r, 1, 0) 205 #define SPD_DDR5_DRAM_VDD_V1P1 0 206 #define SPD_DDR5_DRAM_VDQ_V1P1 0 207 #define SPD_DDR5_DRAM_VPP_V1P8 0 208 209 /* 210 * S8.1.20 SDRAM Timing 211 */ 212 #define SPD_DDR5_TIME 0x013 213 #define SPD_DDR5_TIME_STD(r) bitx8(r, 0, 0) 214 #define SPD_DDR5_TIME_STD_STD 0 215 #define SPD_DDR5_TIME_STD_NON 1 216 217 /* 218 * Timing based parameters. DDR5 uses two timebase values, either 1ps or 1ns. 219 * This is different from DDR4 which had the MTB and FTB. For each parameter we 220 * note whether it is in picoseconds or nanosecond units. 221 */ 222 223 /* 224 * S8.1.21 SDRAM Minimum Cycle Time t~CKAVG~min (ps) 225 * S8.1.22 SDRAM Maximum Cycle Time t~CKAVG~max (ps) 226 */ 227 #define SPD_DDR5_TCKAVG_MIN_LSB 0x014 228 #define SPD_DDR5_TCKAVG_MIN_MSB 0x015 229 #define SPD_DDR5_TCKAVG_MAX_LSB 0x016 230 #define SPD_DDR5_TCKAVG_MAX_MSB 0x017 231 232 /* 233 * S8.1.23 CAS Latencies. These are 5 bytes which indicate which set o CAS 234 * latencies are supported. The LSB of the SPD_DDR5_CAS_SUP0 corresponds to 235 * CL20. Each subsequent bit is an additional 2 CL. So bit 4 is CL28. Byte 2 bit 236 * 6 is CL64. 237 */ 238 #define SPD_DDR5_CAS_SUP0 0x018 239 #define SPD_DDR5_CAS_SUP1 0x019 240 #define SPD_DDR5_CAS_SUP2 0x01a 241 #define SPD_DDR5_CAS_SUP3 0x01b 242 #define SPD_DDR5_CAS_SUP4 0x01c 243 244 /* 245 * S8.1.25 SDRAM Read Command to First Data (t~AA~) (ps) 246 * S8.1.26 SDRAM Activate to Read or Write Command Delay (t~RCD~) (ps) 247 * S8.1.27 SDRAM Row Precharge Time (t~RP~) (ps) 248 * S8.1.28 SDRAM Activate to Precharge Command Period (t~RAS~) (ps) 249 * S8.1.29 SDRAM Activate to to Activate or Refresh Command Period (t~RC~) (ps) 250 * S8.1.30 SDRAM Write Recovery Time (t~WR~) (ps) 251 * S8.1.31 SDRAM Normal Refresh Recovery Time (t~RFC1,tRFC1_slr~) (ns) 252 * S8.1.32 SDRAM Fine Granularity Refresh Recovery Time (t~RFC2,tRFC2_slr~) (ns) 253 * S8.1.33 SDRAM Same Bank Refresh Recovery Time (t~RFCsb,tRFCsb_slr~) (ns) 254 * S8.1.34 SDRAM Normal Refresh Recovery Time, 3DS Different Logical Rank 255 * (t~RFC1_dlr~) (ns) 256 * S8.1.35 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank 257 * (t~RFC2_dlr~) (ns) 258 * S8.1.36 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank 259 * (t~RFCsb_dlr~) (ns) 260 */ 261 #define SPD_DDR5_TAA_LSB 0x01e 262 #define SPD_DDR5_TAA_MSB 0x01f 263 #define SPD_DDR5_TRCD_LSB 0x020 264 #define SPD_DDR5_TRCD_MSB 0x021 265 #define SPD_DDR5_TRP_LSB 0x022 266 #define SPD_DDR5_TRP_MSB 0x023 267 #define SPD_DDR5_TRAS_LSB 0x024 268 #define SPD_DDR5_TRAS_MSB 0x025 269 #define SPD_DDR5_TRC_LSB 0x026 270 #define SPD_DDR5_TRC_MSB 0x027 271 #define SPD_DDR5_TWR_LSB 0x028 272 #define SPD_DDR5_TWR_MSB 0x029 273 #define SPD_DDR5_TRFC1_LSB 0x02a 274 #define SPD_DDR5_TRFC1_MSB 0x02b 275 #define SPD_DDR5_TRFC2_LSB 0x02c 276 #define SPD_DDR5_TRFC2_MSB 0x02d 277 #define SPD_DDR5_TRFCSB_LSB 0x02e 278 #define SPD_DDR5_TRFCSB_MSB 0x02f 279 #define SPD_DDR5_3DS_TRFC1_LSB 0x030 280 #define SPD_DDR5_3DS_TRFC1_MSB 0x031 281 #define SPD_DDR5_3DS_TRFC2_LSB 0x032 282 #define SPD_DDR5_3DS_TRFC2_MSB 0x033 283 #define SPD_DDR5_3DS_TRFCSB_LSB 0x034 284 #define SPD_DDR5_3DS_TRFCSB_MSB 0x035 285 286 /* 287 * S8.1.37 SDRAM Refresh Management First SDRAM 288 * S8.1.38 SDRAM Refresh Management Second SDRAM 289 * 290 * Refresh Management spans two bytes. 291 */ 292 #define SPD_DDR5_RFM0_SDRAM0 0x036 293 #define SPD_DDR5_RFM0_SDRAM1 0x038 294 #define SPD_DDR5_RFM0_RAAMMT_NORM(r) bitx8(r, 7, 5) 295 #define SPD_DDR5_RFM0_RAAMMT_NORM_MIN 3 296 #define SPD_DDR5_RFM0_RAAMMT_NORM_MAX 6 297 #define SPD_DDR5_RFM0_RAAMMT_NORM_MULT 1 298 #define SPD_DDR5_RFM0_RAAMMT_FGR(r) bitx8(r, 7, 5) 299 #define SPD_DDR5_RFM0_RAAMMT_FGR_MIN 6 300 #define SPD_DDR5_RFM0_RAAMMT_FGR_MAX 12 301 #define SPD_DDR5_RFM0_RAAMMT_FGR_MULT 2 302 #define SPD_DDR5_RFM0_RAAIMT_NORM(r) bitx8(r, 4, 1) 303 #define SPD_DDR5_RFM0_RAAIMT_NORM_MIN 32 304 #define SPD_DDR5_RFM0_RAAIMT_NORM_MAX 80 305 #define SPD_DDR5_RFM0_RAAIMT_NORM_MULT 8 306 #define SPD_DDR5_RFM0_RAAIMT_FGR(r) bitx8(r, 4, 1) 307 #define SPD_DDR5_RFM0_RAAIMT_FGR_MIN 16 308 #define SPD_DDR5_RFM0_RAAIMT_FGR_MAX 40 309 #define SPD_DDR5_RFM0_RAAIMT_FGR_MULT 4 310 #define SPD_DDR5_RFM0_RFM_REQ(r) bitx8(r, 0, 0) 311 #define SPD_DDR5_RFM1_SDRAM0 0x037 312 #define SPD_DDR5_RFM1_SDRAM1 0x039 313 #define SPD_DDR5_RFM1_CTR(r) bitx8(r, 7, 6) 314 #define SPD_DDR5_RFM1_CTR_1X 0 315 #define SPD_DDR5_RFM1_CTR_2X 1 316 #define SPD_DDR5_RFM1_BRC_SUP(r)bitx8(r, 3, 3) 317 #define SPD_DDR5_RFM1_BRC_SUP_234 0 318 #define SPD_DDR5_RFM1_BRC_SUP_2 1 319 #define SPD_DDR5_RFM1_BRC_CFG(r) bitx8(r, 2, 1) 320 #define SPD_DDR5_RFM1_BRC_CFG_BASE 2 321 #define SPD_DDR5_RFM1_BRC_CFG_MAX 4 322 #define SPD_DDR5_RFM1_DRFM_SUP(r) bitx8(r, 0, 0) 323 324 /* 325 * S8.1.39 SDRAM Adaptive Refresh Management. This is broken down so that there 326 * are three levels, A, B, and C. There are then two bytes per level. And there 327 * is one entry for the first DRAM and one for the second. With the exception of 328 * bit 0 of the low byte, which indicates whether or not this is supported, 329 * these two byte ranges all match the prior two bytes. 330 */ 331 #define SPD_DDR5_ARFM0_A_SDRAM0 0x03a 332 #define SPD_DDR5_ARFM1_A_SDRAM0 0x03b 333 #define SPD_DDR5_ARFM0_A_SDRAM1 0x03c 334 #define SPD_DDR5_ARFM1_A_SDRAM1 0x03d 335 #define SPD_DDR5_ARFM0_B_SDRAM0 0x03e 336 #define SPD_DDR5_ARFM1_B_SDRAM0 0x03f 337 #define SPD_DDR5_ARFM0_B_SDRAM1 0x040 338 #define SPD_DDR5_ARFM1_B_SDRAM1 0x041 339 #define SPD_DDR5_ARFM0_C_SDRAM0 0x042 340 #define SPD_DDR5_ARFM1_C_SDRAM0 0x043 341 #define SPD_DDR5_ARFM0_C_SDRAM1 0x044 342 #define SPD_DDR5_ARFM1_C_SDRAM1 0x045 343 #define SPD_DDR5_ARFM_SUP(r) bitx8(r, 0, 0) 344 345 /* 346 * S8.1.40 SDRAM Activate to Activate Command Delay for Same Bank Group 347 * (t~RRD_L~) 348 * S8.1.41 SDRAM Read to Read Command Delay for Same Bank Group (t~CDD_L~) 349 * S8.1.42 SDRAM Write to Write Command Delay for Same Bank Group (t~CDD_L_WR~) 350 * S8.1.43 SDRAM Write to Write Command Delay for Same Bank Group, Second Write 351 * not RMW (t~CDD_L_WR2~) 352 * S8.1.44 SDRAM Four Activate Window (t~FAW~) 353 * S8.1.45 SDRAM Write to Read Command Delay for Same Bank Group (t~CCD_L_WTR~) 354 * S8.1.46 SDRAM Write to Read Command Delay for Different Bank Group 355 * (t~CCD_S_WTR~) 356 * S8.1.47 SDRAM Read to Precharge Command Delay (t~RTP~,t~RTP_slr~) 357 * S8.1.48 (v1.2) SDRAM Read to Read Command Delay for Different Bank in Same 358 * Bank Group (t~CCD_M~) 359 * S8.1.49 (v1.2) SDRAM Write to Write Command Delay for Different Bank in Same 360 * Bank Group (t~CCD_M_WR~) 361 * S8.1.50 (v1.2) SDRAM Write to Read Command Delay for Different Bank in Same 362 * Bank Group (t~CCD_M_WTR~) 363 * 364 * These timing registers all consist of three bytes. The first two bytes are 365 * the LSB / MSB of the value in ps. The third bird defines the number of clock 366 * cycles required. 367 */ 368 #define SPD_DDR5_TRRD_L_LSB 0x046 369 #define SPD_DDR5_TRRD_L_MSB 0x047 370 #define SPD_DDR5_TRRD_L_NCK 0x048 371 #define SPD_DDR5_TCCD_L_LSB 0x049 372 #define SPD_DDR5_TCCD_L_MSB 0x04a 373 #define SPD_DDR5_TCCD_L_NCK 0x04b 374 #define SPD_DDR5_TCCD_L_WR_LSB 0x04c 375 #define SPD_DDR5_TCCD_L_WR_MSB 0x04d 376 #define SPD_DDR5_TCCD_L_WR_NCK 0x04e 377 #define SPD_DDR5_TCCD_L_WR2_LSB 0x04f 378 #define SPD_DDR5_TCCD_L_WR2_MSB 0x050 379 #define SPD_DDR5_TCCD_L_WR2_NCK 0x051 380 #define SPD_DDR5_TFAW_LSB 0x052 381 #define SPD_DDR5_TFAW_MSB 0x053 382 #define SPD_DDR5_TFAW_NCK 0x054 383 #define SPD_DDR5_TCCD_L_WTR_LSB 0x055 384 #define SPD_DDR5_TCCD_L_WTR_MSB 0x056 385 #define SPD_DDR5_TCCD_L_WTR_NCK 0x057 386 #define SPD_DDR5_TCCD_S_WTR_LSB 0x058 387 #define SPD_DDR5_TCCD_S_WTR_MSB 0x059 388 #define SPD_DDR5_TCCD_S_WTR_NCK 0x05a 389 #define SPD_DDR5_TRTP_LSB 0x05b 390 #define SPD_DDR5_TRTP_MSB 0x05c 391 #define SPD_DDR5_TRTP_NCK 0x05d 392 #define SPD_DDR5_TCCD_M_LSB 0x05e 393 #define SPD_DDR5_TCCD_M_MSB 0x05f 394 #define SPD_DDR5_TCCD_M_NCK 0x060 395 #define SPD_DDR5_TCCD_M_WR_LSB 0x061 396 #define SPD_DDR5_TCCD_M_WR_MSB 0x062 397 #define SPD_DDR5_TCCD_M_WR_NCK 0x063 398 #define SPD_DDR5_TCCD_M_WTR_LSB 0x064 399 #define SPD_DDR5_TCCD_M_WTR_MSB 0x065 400 #define SPD_DDR5_TCCD_M_WTR_NCK 0x066 401 402 /* 403 * The remaining bytes in this section are currently reserved. Next, we begin 404 * Annex A.0 which has common bytes that are shared between all module types. 405 */ 406 407 /* 408 * S11.1 Common: SPD Revision for Module Information. This is the equivalent of 409 * SPD_DDR5_SPD_REV, but covers all of the module-specific information, which 410 * includes both the common area and type-specific areas. 411 */ 412 #define SPD_DDR5_COM_REV 0x0c0 413 414 /* 415 * S11.2 Common: Hashing Sequence. This defines a possible hashing sequence that 416 * may be applied to a certificate related to device authentication per 417 * JEDS316-5. 418 */ 419 #define SPD_DDR5_COM_HASH 0x0c1 420 #define SPD_DDR5_COM_HASH_HASH(r) bitx8(r, 2, 0) 421 #define SPD_DDR5_COM_HASH_NONE 0 422 #define SPD_DDR5_COM_HASH_ALG1 1 423 424 /* 425 * S11.3 Common: Module Device Information. This contains a series of four 426 * registers for each of five possible items: the SPD, three PMICs (power 427 * management integrated circuit), and a temperature sensor. Before leveraging 428 * the MFG ID, one must consult the Device Type register to see if it is 429 * present. We start with generic definitions for each register type. Specifics 430 * to a register such as type values will follow. The revision is a BCD revision 431 * register. See DDR4 discussion. 432 */ 433 #define SPD_DDR5_COM_INFO_PRES(r) bitx8(r, 7, 7) 434 #define SPD_DDR5_COM_INFO_TYPE(r) bitx8(r, 3, 0) 435 436 #define SPD_DDR5_COM_MFG_ID0_SPD 0x0c2 437 #define SPD_DDR5_COM_MFG_ID1_SPD 0x0c3 438 #define SPD_DDR5_COM_INFO_SPD 0x0c4 439 #define SPD_DDR5_COM_INFO_TYPE_SPD5118 0 440 #define SPD_DDR5_COM_INFO_TYPE_ESPD5216 1 441 #define SPD_DDR5_COM_REV_SPD 0x0c5 442 443 #define SPD_DDR5_COM_MFG_ID0_PMIC0 0x0c6 444 #define SPD_DDR5_COM_MFG_ID1_PMIC0 0x0c7 445 #define SPD_DDR5_COM_INFO_PMIC0 0x0c8 446 #define SPD_DDR5_COM_INFO_TYPE_PMIC5000 0 447 #define SPD_DDR5_COM_INFO_TYPE_PMIC5010 1 448 #define SPD_DDR5_COM_INFO_TYPE_PMIC5100 2 449 #define SPD_DDR5_COM_INFO_TYPE_PMIC5020 3 450 #define SPD_DDR5_COM_INFO_TYPE_PMIC5120 4 451 #define SPD_DDR5_COM_INFO_TYPE_PMIC5200 5 452 #define SPD_DDR5_COM_INFO_TYPE_PMIC5030 6 453 #define SPD_DDR5_COM_REV_PMIC0 0x0c9 454 455 #define SPD_DDR5_COM_MFG_ID0_PMIC1 0x0ca 456 #define SPD_DDR5_COM_MFG_ID1_PMIC1 0x0cb 457 #define SPD_DDR5_COM_INFO_PMIC1 0x0cc 458 #define SPD_DDR5_COM_REV_PMIC1 0x0cd 459 460 #define SPD_DDR5_COM_MFG_ID0_PMIC2 0x0ce 461 #define SPD_DDR5_COM_MFG_ID1_PMIC2 0x0cf 462 #define SPD_DDR5_COM_INFO_PMIC2 0x0d0 463 #define SPD_DDR5_COM_REV_PMIC2 0x0d1 464 465 #define SPD_DDR5_COM_MFG_ID0_TS 0x0d2 466 #define SPD_DDR5_COM_MFG_ID1_TS 0x0d3 467 #define SPD_DDR5_COM_INFO_TS 0x0d4 468 #define SPD_DDR5_COM_INFO_TS1_PRES(r) bitx8(r, 6, 6) 469 #define SPD_DDR5_COM_INFO_TYPE_TS5111 0 470 #define SPD_DDR5_COM_INFO_TYPE_TS5110 1 471 #define SPD_DDR5_COM_INFO_TYPE_TS5211 2 472 #define SPD_DDR5_COM_INFO_TYPE_TS5210 3 473 #define SPD_DDR5_COM_REV_TS 0x0d5 474 475 /* 476 * S11.5 Common: Additional Support Devices. This was added in DDR5 1.3 and LP5 477 * 1.2. 478 */ 479 #define SPD_DDR5_COM_ADDDEV 0x0e5 480 #define SPD_DDR5_COM_ADDDEV_TVS_MGMT(r) bitx8(r, 2, 2) 481 #define SPD_DDR5_COM_ADDDEV_TVS_BULK(r) bitx8(r, 1, 1) 482 #define SPD_DDR5_COM_ADDDEV_FUSE_BULK(r) bitx8(r, 0, 0) 483 484 /* 485 * S11.6 Common: Module Nominal Height 486 */ 487 #define SPD_DDR5_COM_HEIGHT 0x0e6 488 #define SPD_DDR5_COM_HEIGHT_MM(r) bitx8(r, 4, 0) 489 #define SPD_DDR5_COM_HEIGHT_BASE 15 490 491 /* 492 * S11.7 Common: Module Maximum Thickness 493 */ 494 #define SPD_DDR5_COM_THICK 0x0e7 495 #define SPD_DDR5_COM_THICK_BACK(r) bitx8(r, 7, 4) 496 #define SPD_DDR5_COM_THICK_FRONT(r) bitx8(r, 3, 0) 497 #define SPD_DDR5_COM_THICK_BASE 1 498 499 /* 500 * S11.8 Common: Reference Raw Card Used 501 */ 502 #define SPD_DDR5_COM_REF 0x0e8 503 #define SPD_DDR5_COM_REF_REV(r) bitx8(r, 7, 5) 504 #define SPD_DDR5_COM_REF_REV_MAX 6 505 #define SPD_DDR5_COM_REF_CARD(r) bitx8(r, 4, 0) 506 507 /* 508 * S11.9 Common: DIMM Attributes 509 */ 510 #define SPD_DDR5_COM_ATTR 0x0e9 511 #define SPD_DDR5_COM_ATTR_OTR(r) bitx8(r, 7, 4) 512 #define SPD_DDR5_COM_ATTR_OTR_A1T 0 513 #define SPD_DDR5_COM_ATTR_OTR_A2T 1 514 #define SPD_DDR5_COM_ATTR_OTR_A3T 2 515 #define SPD_DDR5_COM_ATTR_OTR_IT 3 516 #define SPD_DDR5_COM_ATTR_OTR_ST 4 517 #define SPD_DDR5_COM_ATTR_OTR_ET 5 518 #define SPD_DDR5_COM_ATTR_OTR_RT 6 519 #define SPD_DDR5_COM_ATTR_OTR_NT 7 520 #define SPD_DDR5_COM_ATTR_OTR_XT 8 521 #define SPD_DDR5_COM_ATTR_SPREAD(r) bitx8(r, 2, 2) 522 #define SPD_DDR5_COM_ATTR_NROWS(r) bitx8(r, 1, 0) 523 #define SPD_DDR5_COM_ATTR_NROWS_UNDEF 0 524 #define SPD_DDR5_COM_ATTR_NROWS_1 1 525 #define SPD_DDR5_COM_ATTR_NROWS_2 2 526 #define SPD_DDR5_COM_ATTR_NROWS_4 3 527 #define SPD_DDR5_COM_ATTR_NROWS_3 4 528 529 /* 530 * S11.10 Common: Module Organization 531 */ 532 #define SPD_DDR5_COM_ORG 0x0ea 533 #define SPD_DDR5_COM_ORG_MIX(r) bitx8(r, 6, 6) 534 #define SPD_DDR5_COM_ORG_MIX_SYM 0 535 #define SPD_DDR5_COM_ORG_MIX_ASYM 1 536 #define SPD_DDR5_COM_ORG_NRANK(r) bitx8(r, 5, 3) 537 #define SPD_DDR5_COM_ORG_NRANK_BASE 1 538 539 /* 540 * S11.11 Common: Memory Channel Bus Width. Unlike DDR4, these widths are in 541 * terms of sub-channels. 542 */ 543 #define SPD_DDR5_COM_BUS_WIDTH 0x0eb 544 #define SPD_DDR5_COM_BUS_WIDTH_NSC(r) bitx8(r, 7, 5) 545 #define SPD_DDR5_COM_BUS_WIDTH_NSC_MAX 8 546 #define SPD_DDR5_COM_BUS_WIDTH_EXT(r) bitx8(r, 4, 3) 547 #define SPD_DDR5_COM_BUS_WIDTH_EXT_NONE 0 548 #define SPD_DDR5_COM_BUS_WIDTH_EXT_4b 1 549 #define SPD_DDR5_COM_BUS_WIDTH_EXT_8b 2 550 #define SPD_DDR5_COM_BUS_WIDTH_PRI(r) bitx8(r, 2, 0) 551 #define SPD_DDR5_COM_BUS_WIDTH_PRI_8b 0 552 #define SPD_DDR5_COM_BUS_WIDTH_PRI_16b 1 553 #define SPD_DDR5_COM_BUS_WIDTH_PRI_32b 2 554 #define SPD_DDR5_COM_BUS_WIDTH_PRI_64b 3 555 556 /* 557 * After this point, all remaining bytes are reserved and Annex specific 558 * information follows. Annex A.1 Module Specific Bytes for Solder Down is 559 * skipped because there are no bytes defined. The revisions for these all 560 * follow the common revision found at SPD_DDR5_COM_REV. 561 */ 562 563 /* 564 * Annex A.2 Module Specific Bytes for Buffered Memory Module Types. S13.1 565 * UDIMM: Module Specific Device Information. This follows the same pattern as 566 * the other device specific manufacturing information with a series of four 567 * bytes. See the discussion of S11.3. Revision 1.0 only defined the CLK 568 * information. Revision 1.1 added several additional pieces of data. 569 */ 570 #define SPD_DDR5_UDIMM_MFG_ID0_CLK 0x0f0 571 #define SPD_DDR5_UDIMM_MFG_ID1_CLK 0x0f1 572 #define SPD_DDR5_UDIMM_INFO_CLK 0x0f2 573 #define SPD_DDR5_UDIMM_INFO_TYPE_DDR5CK01 0 574 #define SPD_DDR5_UDIMM_REV_CLK 0x0f3 575 576 /* 577 * S13.2 UDIMM v1.1: CKD-RW00 CKD Configuration 578 */ 579 #define SPD_DDR5_UDIMM_CKD_CFG 0x0f4 580 #define SPD_DDR5_UDIMM_CKD_CFG_CHBQCK1(r) bitx8(r, 7, 7) 581 #define SPD_DDR5_UDIMM_CKD_CFG_CHBQCK0(r) bitx8(r, 6, 6) 582 #define SPD_DDR5_UDIMM_CKD_CFG_CHAQCK1(r) bitx8(r, 5, 5) 583 #define SPD_DDR5_UDIMM_CKD_CFG_CHAQCK0(r) bitx8(r, 4, 4) 584 585 /* 586 * S13.3 UDIMM v1.1: CKD-RW02 QCK Driver Characteristics 587 */ 588 #define SPD_DDR5_UDIMM_CKD_DRV 0x0f5 589 #define SPD_DDR5_UDIMM_CKD_DRV_CHBQCK1_DRIVE(r) bitx8(r, 7, 6) 590 #define SPD_DDR5_UDIMM_CKD_DRV_CHBQCK0_DRIVE(r) bitx8(r, 5, 4) 591 #define SPD_DDR5_UDIMM_CKD_DRV_CHAQCK1_DRIVE(r) bitx8(r, 3, 2) 592 #define SPD_DDR5_UDIMM_CKD_DRV_CHAQCK0_DRIVE(r) bitx8(r, 1, 0) 593 #define SPD_DDR5_UDIMM_CKD_DRV_LIGHT 0 594 #define SPD_DDR5_UDIMM_CKD_DRV_MODERATE 1 595 #define SPD_DDR5_UDIMM_CKD_DRV_STRONG 2 596 #define SPD_DDR5_UDIMM_CKD_DRV_WEAK 3 597 598 /* 599 * S13.4 UDIMM v1.1: CKD-RW03 QCK Output Differential Slew Rate 600 */ 601 #define SPD_DDR5_UDIMM_CKD_SLEW 0x0f6 602 #define SPD_DDR5_UDIMM_CKD_SLEW_CHBQCK_SLEW(r) bitx8(r, 5, 4) 603 #define SPD_DDR5_UDIMM_CKD_SLEW_CHAQCK_SLEW(r) bitx8(r, 1, 0) 604 #define SPD_DDR5_UDIMM_CKD_SLEW_SLEW_MODERATE 0 605 #define SPD_DDR5_UDIMM_CKD_SLEW_SLEW_FAST 1 606 607 /* 608 * Annex A.3: Module Specific Bytes for Registered (RDIMM) and Load Reduced 609 * (LRDIMM) Memory Module Types. 610 */ 611 612 /* 613 * S14.2 RDIMM: Module Specific Device Information. This covers the RCD and DB 614 * components. Only LRDIMMs will have the DB present and it will be left as zero 615 * for RDIMMs. 616 */ 617 #define SPD_DDR5_RDIMM_MFG_ID0_RCD 0x0f0 618 #define SPD_DDR5_RDIMM_MFG_ID1_RCD 0x0f1 619 #define SPD_DDR5_RDIMM_INFO_RCD 0x0f2 620 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD01 0 621 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD02 1 622 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD03 2 623 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD04 3 624 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD05 4 625 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD06 5 626 #define SPD_DDR5_RDIMM_REV_RCD 0x0f3 627 628 #define SPD_DDR5_RDIMM_MFG_ID0_DB 0x0f4 629 #define SPD_DDR5_RDIMM_MFG_ID1_DB 0x0f5 630 #define SPD_DDR5_RDIMM_INFO_DB 0x0f6 631 #define SPD_DDR5_RDIMM_INFO_TYPE_DB01 0 632 #define SPD_DDR5_RDIMM_INFO_TYPE_DB02 1 633 #define SPD_DDR5_RDIMM_REV_DB 0x0f7 634 635 /* 636 * S14.3 RDIMM: RCD-RW08 Clock Driver Enable 637 */ 638 #define SPD_DDR5_RDIMM_CLKEN 0x0f8 639 #define SPD_DDR5_RDIMM_CLKEN_BCK(r) bitx8(r, 5, 5) 640 #define SPD_DDR5_RDIMM_CLKEN_QDCK(r) bitx8(r, 3, 3) 641 #define SPD_DDR5_RDIMM_CLKEN_QCCK(r) bitx8(r, 2, 2) 642 #define SPD_DDR5_RDIMM_CLKEN_QBCK(r) bitx8(r, 1, 1) 643 #define SPD_DDR5_RDIMM_CLKEN_QACK(r) bitx8(r, 0, 0) 644 645 /* 646 * S14.4 RDIMM: RCD-RW09 Output Address and Control Enable 647 */ 648 #define SPD_DDR5_RDIMM_RW09 0x0f9 649 #define SPD_DDR5_RDIMM_RW09_QBCS(r) bitx8(r, 6, 6) 650 #define SPD_DDR5_RDIMM_RW09_QACS(r) bitx8(r, 5, 5) 651 #define SPD_DDR5_RDIMM_RW09_QXCA13(r) bitx8(r, 4, 4) 652 #define SPD_DDR5_RDIMM_RW09_BCS(r) bitx8(r, 3, 3) 653 #define SPD_DDR5_RDIMM_RW09_DCS(r) bitx8(r, 2, 2) 654 #define SPD_DDR5_RDIMM_RW09_QBCA(r) bitx8(r, 1, 1) 655 #define SPD_DDR5_RDIMM_RW09_QACA(r) bitx8(r, 0, 0) 656 657 /* 658 * S14.5 RDIMM: RCD-RW0A QCK Driver Characteristics 659 * S14.7 RDIMM: RCD-RW0C QxCA and QxCS_n Driver Characteristics 660 * S14.8 LRDIMM: RCD-RW0D Data Buffer Interface Driver Characteristics 661 * 662 * RDIMM 1.0 phrased these in terms of resistance values; however, RDIMM 1.1 663 * changed them into relative terms used elsewhere like light, moderate, and 664 * strong. 665 */ 666 #define SPD_DDR5_RDIMM_QCK_DRV 0x0fa 667 #define SPD_DDR5_RDIMM_QCK_DRV_QDCK(r) bitx8(r, 7, 6) 668 #define SPD_DDR5_RDIMM_QCK_DRV_QCCK(r) bitx8(r, 5, 4) 669 #define SPD_DDR5_RDIMM_QCK_DRV_QBCK(r) bitx8(r, 3, 2) 670 #define SPD_DDR5_RDIMM_QCK_DRV_QACK(r) bitx8(r, 1, 0) 671 #define SPD_DDR5_RDIMM_DRV_LIGHT 0 672 #define SPD_DDR5_RDIMM_DRV_MODERATE 1 673 #define SPD_DDR5_RDIMM_DRV_STRONG 2 674 675 #define SPD_DDR5_RDIMM_QCA_DRV 0x0fc 676 #define SPD_DDR5_RDIMM_QCA_DRV_CS(r) bitx8(r, 5, 4) 677 #define SPD_DDR5_RDIMM_QCA_DRV_CA(r) bitx8(r, 1, 0) 678 679 #define SPD_DDR5_LRDIMM_DB_DRV 0x0fd 680 #define SPD_DDR5_LRDIMM_DB_DRV_BCK(r) bitx8(r, 4, 3) 681 #define SPD_DDR5_LRDIMM_DB_DRV_BCOM(r) bitx8(r, 1, 0) 682 683 /* 684 * S14.9 RDIMM: RCD-RW0E QCK, QCA, and QCS Output Slew Rate 685 * S14.10 LRDIMM: RCD-RW0F BCK, BCOM, and BCS Output Slew Rate 686 * 687 * These all use the same rough definitions for slew rates, i.e. slow, moderate, 688 * and fast; however, they all have different voltage ranges. 689 */ 690 #define SPD_DDR5_RDIMM_QXX_SLEW 0x0fe 691 #define SPD_DDR5_RDIMM_QXX_SLEW_QCS(r) bitx8(r, 5, 4) 692 #define SPD_DDR5_RDIMM_SLEW_MODERTE 0 693 #define SPD_DDR5_RDIMM_SLEW_FAST 1 694 #define SPD_DDR5_RDIMM_SLEW_SLOW 2 695 #define SPD_DDR5_RDIMM_QXX_SLEW_QCA(r) bitx8(r, 3, 2) 696 #define SPD_DDR5_RDIMM_QXX_SLEW_QCK(r) bitx8(r, 1, 0) 697 698 #define SPD_DDR5_LRDIMM_BXX_SLEW 0x0ff 699 #define SPD_DDR5_LRDIMM_BXX_SLEW_BCK(r) bitx8(r, 3, 2) 700 #define SPD_DDR5_LRDIMM_BXX_SLEW_BCOM(r) bitx8(r, 1, 0) 701 702 /* 703 * S14.11 DB-RW86 DQS RTT Park Termination 704 */ 705 #define SPD_DDR5_LRDIMM_PARK 0x100 706 #define SPD_DDR5_LRDIMM_PARK_TERM(r) bitx8(r, 2, 0) 707 #define SPD_DDR5_LDRIMM_PARK_OFF 0 708 #define SPD_DDR5_LDRIMM_PARK_240R 1 709 #define SPD_DDR5_LDRIMM_PARK_120R 2 710 #define SPD_DDR5_LDRIMM_PARK_80R 3 711 #define SPD_DDR5_LDRIMM_PARK_60R 4 712 #define SPD_DDR5_LDRIMM_PARK_48R 5 713 #define SPD_DDR5_LDRIMM_PARK_40R 6 714 #define SPD_DDR5_LDRIMM_PARK_34R 7 715 716 /* 717 * Annex A.4: Module Specific Bytes for Multiplexed Rank (MRDIMM) Memory Module 718 * Types. Revision 1.0 only defined the type information. Revision 1.1 added 719 * several additional bytes of data that start after the MDB information. 720 */ 721 #define SPD_DDR5_MRDIMM_MFG_ID0_MRCD 0x0f0 722 #define SPD_DDR5_MRDIMM_MFG_ID1_MRCD 0x0f1 723 #define SPD_DDR5_MRDIMM_INFO_MRCD 0x0f2 724 #define SPD_DDR5_MRDIMM_INFO_TYPE_MRCD01 0 725 #define SPD_DDR5_MRDIMM_INFO_TYPE_MRCD02 1 726 #define SPD_DDR5_MRDIMM_INFO_TYPE_MRCD03 2 727 #define SPD_DDR5_MRDIMM_REV_MRCD 0x0f3 728 729 #define SPD_DDR5_MRDIMM_MFG_ID0_MDB 0x0f4 730 #define SPD_DDR5_MRDIMM_MFG_ID1_MDB 0x0f5 731 #define SPD_DDR5_MRDIMM_INFO_MDB 0x0f6 732 #define SPD_DDR5_MRDIMM_INFO_TYPE_MDB01 0 733 #define SPD_DDR5_MRDIMM_INFO_TYPE_MDB02 1 734 #define SPD_DDR5_MRDIMM_INFO_TYPE_MDB03 2 735 #define SPD_DDR5_MRDIMM_REV_MDB 0x0f7 736 737 /* 738 * S15.3 MRDIMM v1.1: MRCD-RW08 Clock Driver Enable 739 */ 740 #define SPD_DDR5_MRDIMM_CDEN 0x0f8 741 #define SPD_DDR5_MRDIMM_CDEN_BCK(r) bitx8(r, 5, 5) 742 #define SPD_DDR5_MRDIMM_CDEN_QDCK(r) bitx8(r, 3, 3) 743 #define SPD_DDR5_MRDIMM_CDEN_QCCK(r) bitx8(r, 2, 2) 744 #define SPD_DDR5_MRDIMM_CDEN_QBCK(r) bitx8(r, 1, 2) 745 #define SPD_DDR5_MRDIMM_CDEN_QACK(r) bitx8(r, 0, 0) 746 747 /* 748 * S15.3 MRDIMM v1.1: MRCD-RW09 Output Address and Control Enable 749 */ 750 #define SPD_DDR5_MRDIMM_OACEN 0x0f9 751 #define SPD_DDR5_MRDIMM_CDEN_DCS1(r) bitx8(r, 7, 7) 752 #define SPD_DDR5_MRDIMM_CDEN_QBCS(r) bitx8(r, 6, 6) 753 #define SPD_DDR5_MRDIMM_CDEN_QACS(r) bitx8(r, 5, 5) 754 #define SPD_DDR5_MRDIMM_CDEN_QCA13(r) bitx8(r, 4, 4) 755 #define SPD_DDR5_MRDIMM_CDEN_BCS(r) bitx8(r, 3, 3) 756 #define SPD_DDR5_MRDIMM_CDEN_QxCS1(r) bitx8(r, 2, 2) 757 #define SPD_DDR5_MRDIMM_CDEN_QBCA(r) bitx8(r, 1, 1) 758 #define SPD_DDR5_MRDIMM_CDEN_QACA(r) bitx8(r, 0, 0) 759 760 /* 761 * S15.4 MRDIMM v1.1: MRCD-RW0A QCK Driver Characteristics 762 * S15.6 MRDIMM v1.1: MRCD-RW0C QxCA and QxCS_n Driver Characteristics 763 * S15.7 MRDIMM v1.1: MRCD-RW0D Data Buffer Interface Driver Characteristics 764 * 765 * Similar to the RDIMM 1.1 version of these. These are all described in terms 766 * of relative rates. 767 */ 768 #define SPD_DDR5_MRDIMM_QCK_DRV 0x0fa 769 #define SPD_DDR5_MRDIMM_QCK_DRV_QDCK(r) bitx8(r, 7, 6) 770 #define SPD_DDR5_MRDIMM_QCK_DRV_QCCK(r) bitx8(r, 5, 4) 771 #define SPD_DDR5_MRDIMM_QCK_DRV_QBCK(r) bitx8(r, 3, 2) 772 #define SPD_DDR5_MRDIMM_QCK_DRV_QACK(r) bitx8(r, 1, 0) 773 #define SPD_DDR5_MRDIMM_DRV_LIGHT 0 774 #define SPD_DDR5_MRDIMM_DRV_MODERATE 1 775 #define SPD_DDR5_MRDIMM_DRV_STRONG 2 776 777 #define SPD_DDR5_MRDIMM_QCA_DRV 0x0fc 778 #define SPD_DDR5_MRDIMM_QCA_DRV_QCS1_OUT(r) bitx8(r, 7, 6) 779 #define SPD_DDR5_MRDIMM_QCA_DRV_QCS1_OUT_NORM 0 780 #define SPD_DDR5_MRDIMM_QCA_DRV_QCS1_OUT_DIS 1 781 #define SPD_DDR5_MRDIMM_QCA_DRV_QCS1_OUT_LOW 2 782 #define SPD_DDR5_MRDIMM_QCA_DRV_CS(r) bitx8(r, 5, 4) 783 #define SPD_DDR5_MRDIMM_QCA_DRV_CA(r) bitx8(r, 1, 0) 784 785 #define SPD_DDR5_MRDIMM_DB_DRV 0x0fd 786 #define SPD_DDR5_MRDIMM_DB_DRV_BCK(r) bitx8(r, 4, 3) 787 #define SPD_DDR5_MRDIMM_DB_DRV_BCOM(r) bitx8(r, 1, 0) 788 789 /* 790 * S15.8 MRDIMM v1.1: MRCD-RW0E QCK, QCA, and QCS Output Slew Rate 791 * S15.9 MRDIMM v1.1: MRCD-RW0F BCK, BCOM, and BCS Output Slew Rate 792 * 793 * Similar to the [LR]DIMM version. These use the same definitions for slew 794 * rates. 795 */ 796 #define SPD_DDR5_MRDIMM_QXX_SLEW 0x0fe 797 #define SPD_DDR5_MRDIMM_QXX_SLEW_QCS(r) bitx8(r, 5, 4) 798 #define SPD_DDR5_MRDIMM_SLEW_MODERTE 0 799 #define SPD_DDR5_MRDIMM_SLEW_FAST 1 800 #define SPD_DDR5_MRDIMM_SLEW_SLOW 2 801 #define SPD_DDR5_MRDIMM_QXX_SLEW_QCA(r) bitx8(r, 3, 2) 802 #define SPD_DDR5_MRDIMM_QXX_SLEW_QCK(r) bitx8(r, 1, 0) 803 804 #define SPD_DDR5_MRDIMM_BXX_SLEW 0x0ff 805 #define SPD_DDR5_MRDIMM_BXX_SLEW_BCK(r) bitx8(r, 3, 2) 806 #define SPD_DDR5_MRDIMM_BXX_SLEW_BCOM(r) bitx8(r, 1, 0) 807 808 /* 809 * S15.10 MRDIMM v1.1: MDB-PG[C]RWE0 Duty Cycle Adjuster Configuration 810 */ 811 #define SPD_DDR5_MRDIMM_DCA_CFG 0x100 812 #define SPD_DDR5_MRDIMM_DCA_CFG_CFG(r) bitx8(r, 0, 0) 813 814 /* 815 * S15.11 MRDIMM v1.1: MDB-PG[70]RWE1 DRAM Interface Receiver Type 816 */ 817 #define SPD_DDR5_MRDIMM_IRXTYPE 0x101 818 #define SPD_DDR5_MRDIMM_IRXTYPE_TYPE(r) bitx8(r, 0, 0) 819 #define SPD_DDR5_MRDIMM_IRXTYPE_TYPE_UNMATCHED 0 820 #define SPD_DDR5_MRDIMM_IRXTYPE_TYPE_MATCHED 1 821 822 /* 823 * Annex A.5: Module Specific Bytes for Differential Memory Module Types. Like 824 * UDIMMs and MRDIMMs, there is only a single section for Module Specific 825 * Device Information. 826 */ 827 #define SPD_DDR5_DDIMM_MFG_ID0_DMB 0x0f0 828 #define SPD_DDR5_DDIMM_MFG_ID1_DMB 0x0f1 829 #define SPD_DDR5_DDIMM_INFO_DMB 0x0f2 830 #define SPD_DDR5_DDIMM_INFO_TYPE_DMB501 0 831 #define SPD_DDR5_DDIMM_REV_DMB 0x0f3 832 833 /* 834 * Annex A.8: Module Specific Bytes for Compression Attached Memory Module Types 835 * (CAMM2). There are three revisions of this. The contents in revision 1.1 are 836 * specific to DDR5 and do not apply to LPDDR5/5X. 837 */ 838 #define SPD_DDR5_CAMM2_MFG_ID0_CKD0 0x0f0 839 #define SPD_DDR5_CAMM2_MFG_ID1_CKD0 0x0f1 840 #define SPD_DDR5_CAMM2_INFO_CKD0 0x0f2 841 #define SPD_DDR5_CAMM2_INFO_TYPE_CKD01 0 842 #define SPD_DDR5_CAMM2_INFO_REV_CKD0 0x0f3 843 #define SPD_DDR5_CAMM2_MFG_ID0_CKD1 0x0f4 844 #define SPD_DDR5_CAMM2_MFG_ID1_CKD1 0x0f5 845 #define SPD_DDR5_CAMM2_INFO_CKD1 0x0f6 846 #define SPD_DDR5_CAMM2_INFO_REV_CKD1 0x0f7 847 848 /* 849 * S19.3 CAMM2 v1.1: Clock Driver 0 RW00 CKD Configuration 850 * S19.6 CAMM2 v1.1: Clock Driver 1 RW00 CKD Configuration 851 */ 852 #define SPD_DDR5_CAMM2_CKD_CFG_CKD0 0x100 853 #define SPD_DDR5_CAMM2_CKD_CFG_CKD1 0x103 854 #define SPD_DDR5_CAMM2_CKD_CFG_CHBQCK1(r) bitx8(r, 7, 7) 855 #define SPD_DDR5_CAMM2_CKD_CFG_CHBQCK0(r) bitx8(r, 6, 6) 856 #define SPD_DDR5_CAMM2_CKD_CFG_CHAQCK1(r) bitx8(r, 5, 5) 857 #define SPD_DDR5_CAMM2_CKD_CFG_CHAQCK0(r) bitx8(r, 4, 4) 858 859 /* 860 * S19.4 CAMM2 v1.1: Clock Driver 0 RW02 QCK Driver Characteristics 861 * S19.7 CAMM2 v1.1: Clock Driver 1 RW02 QCK Driver Characteristics 862 */ 863 #define SPD_DDR5_CAMM2_CKD_DRV_CKD0 0x101 864 #define SPD_DDR5_CAMM2_CKD_DRV_CKD1 0x104 865 #define SPD_DDR5_CAMM2_CKD_DRV_CHBQCK1_DRIVE(r) bitx8(r, 7, 6) 866 #define SPD_DDR5_CAMM2_CKD_DRV_CHBQCK0_DRIVE(r) bitx8(r, 5, 4) 867 #define SPD_DDR5_CAMM2_CKD_DRV_CHAQCK1_DRIVE(r) bitx8(r, 3, 2) 868 #define SPD_DDR5_CAMM2_CKD_DRV_CHAQCK0_DRIVE(r) bitx8(r, 1, 0) 869 #define SPD_DDR5_CAMM2_CKD_DRV_LIGHT 0 870 #define SPD_DDR5_CAMM2_CKD_DRV_MODERATE 1 871 #define SPD_DDR5_CAMM2_CKD_DRV_STRONG 2 872 #define SPD_DDR5_CAMM2_CKD_DRV_WEAK 3 873 874 /* 875 * S19.6 CAMM2 v1.1: Clock Driver 0 RW03 QCK Output Differential Slew Rate 876 * S19.8 CAMM2 v1.1: Clock Driver 1 RW03 QCK Output Differential Slew Rate 877 */ 878 #define SPD_DDR5_CAMM2_CKD_SLEW_CKD0 0x102 879 #define SPD_DDR5_CAMM2_CKD_SLEW_CKD1 0x105 880 #define SPD_DDR5_CAMM2_CKD_SLEW_CHBQCK_SLEW(r) bitx8(r, 5, 4) 881 #define SPD_DDR5_CAMM2_CKD_SLEW_CHAQCK_SLEW(r) bitx8(r, 1, 0) 882 #define SPD_DDR5_CAMM2_CKD_SLEW_SLEW_MODERATE 0 883 #define SPD_DDR5_CAMM2_CKD_SLEW_SLEW_FAST 1 884 885 /* 886 * CAMM2 v1.2: Module Capacitance - VDDQ 887 * 888 * This is currently only defined in LPDDR5, but it applies to DDR5. 889 */ 890 #define SPD_DDR5_CAMM2_MOD_CAP_VDDQ 0x106 891 #define SPD_DDR5_CAMM2_MOD_CAP_VDDQ_NOM(r) bitx8(r, 4, 0) 892 #define SPD_DDR5_CAMM2_MOD_CAP_VDDQ_NOM_UNSPEC 0 893 #define SPD_DDR5_CAMM2_MOD_CAP_VDDQ_NOM_BASE 50 894 #define SPD_DDR5_CAMM2_MOD_CAP_VDDQ_NOM_STEP 25 895 #define SPD_DDR5_CAMM2_MOD_CAP_VDDQ_NOM_MAX 19 896 897 /* 898 * Annex A.9: Module Specific Bytes for Small Outline Compression Attached 899 * Memory Module Types (SOCAMM2). 900 */ 901 #define SPD_DDR5_SOCAMM2_MFG_ID0_VR0 0xf0 902 #define SPD_DDR5_SOCAMM2_MFG_ID1_VR0 0xf1 903 #define SPD_DDR5_SOCAMM2_SRC_VR0 0xf2 904 #define SPD_DDR5_SOCAMM2_REV_VR0 0xf3 905 #define SPD_DDR5_SOCAMM2_MFG_ID0_VR1 0xf4 906 #define SPD_DDR5_SOCAMM2_MFG_ID1_VR1 0xf5 907 #define SPD_DDR5_SOCAMM2_SRC_VR1 0xf6 908 #define SPD_DDR5_SOCAMM2_REV_VR1 0xf7 909 #define SPD_DDR5_SOCAMM2_MFG_ID0_VR2 0xf8 910 #define SPD_DDR5_SOCAMM2_MFG_ID1_VR2 0xf9 911 #define SPD_DDR5_SOCAMM2_SRC_VR2 0xfa 912 #define SPD_DDR5_SOCAMM2_REV_VR2 0xfb 913 #define SPD_DDR5_SOCAMM2_MFG_ID0_VR3 0xfc 914 #define SPD_DDR5_SOCAMM2_MFG_ID1_VR3 0xfd 915 #define SPD_DDR5_SOCAMM2_SRC_VR3 0xfe 916 #define SPD_DDR5_SOCAMM2_REV_VR3 0xff 917 918 #define SPD_DDR5_SOCAMM2_SRC_VR_PRES(r) bitx8(r, 7, 7) 919 #define SPD_DDR5_SOCAMM2_SRC_VR_VDDQ(r) bitx8(r, 4, 4) 920 #define SPD_DDR5_SOCAMM2_SRC_VR_VDD2(r) bitx8(r, 3, 3) 921 #define SPD_DDR5_SOCAMM2_SRC_VR_VDD2L(r) bitx8(r, 2, 2) 922 #define SPD_DDR5_SOCAMM2_SRC_VR_VDD2H(r) bitx8(r, 1, 1) 923 #define SPD_DDR5_SOCAMM2_SRC_VR_VDD1(r) bitx8(r, 0, 0) 924 925 /* 926 * S7.4 CRC. DDR5 modules have a single CRC calculation that covers bytes 0-509. 927 * Thus it covers everything prior to the manufacturing information. 928 */ 929 #define SPD_DDR5_CRC_LSB 0x1fe 930 #define SPD_DDR5_CRC_MSB 0x1ff 931 932 /* 933 * Manufacturing Information. 934 */ 935 936 /* 937 * S20.1 Module Manufacturer ID Code 938 * S20.7 DRAM Manufacturer ID Code 939 */ 940 #define SPD_DDR5_MOD_MFG_ID0 0x200 941 #define SPD_DDR5_MOD_MFG_ID1 0x201 942 #define SPD_DDR5_DRAM_MFG_ID0 0x228 943 #define SPD_DDR5_DRAM_MFG_ID1 0x229 944 945 /* 946 * S20.2 Module Manufacturing Location. This byte is manufacturer specific. 947 */ 948 #define SPD_DDR5_MOD_MFG_LOC 0x202 949 950 /* 951 * S20.3 module Manufacturing Date. Encoded as two BCD bytes for the year and 952 * week. 953 */ 954 #define SPD_DDR5_MOD_MFG_YEAR 0x203 955 #define SPD_DDR5_MOD_MFG_WEEK 0x204 956 957 /* 958 * S20.4 Module Serial Number. 959 * S20.5 Module Part Number 960 * S20.6 Module Revision Code 961 */ 962 #define SPD_DDR5_MOD_SN 0x205 963 #define SPD_DDR5_MOD_SN_LEN 4 964 #define SPD_DDR5_MOD_PN 0x209 965 #define SPD_DDR5_MOD_PN_LEN 30 966 #define SPD_DDR5_MOD_REV 0x227 967 968 /* 969 * S20.8 DRAM Stepping 970 */ 971 #define SPD_DDR5_DRAM_STEP 0x22a 972 973 /* 974 * Bytes 0x22b-0x27f are left for manufacturer specific data. 975 */ 976 977 #ifdef __cplusplus 978 } 979 #endif 980 981 #endif /* _SPD_DDR5_H */ 982