1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2023 Oxide Computer Company 14 */ 15 16 #ifndef _SPD_DDR5_H 17 #define _SPD_DDR5_H 18 19 /* 20 * Definitions for use in DDR5 Serial Presence Detect decoding based on JEDEC 21 * Standard JESD400-5a.01 DDR5 Serial Presence Detect (SPD) Contents. Release 22 * 1.1. This does not cover LPDDR5. 23 * 24 * DDR5 modules are organized into a few main regions: 25 * 26 * o Base Configuration and DRAM parameters (0x00-0x7f) 27 * o Common Module Parameters (0xc0-0xef) 28 * o Standard Module Parameters (0xf0-0x1bf) which vary on whether something 29 * is an RDIMM, UDIMM, etc. 30 * o A CRC check for the first 510 bytes (0x1fe-0x1ff) 31 * o Manufacturing Information (0x200-0x27f) 32 * o Optional end-user programmable regions (0x280-0x3ff) 33 * 34 * This covers all DDR5 variants other than NVDIMMs. LPDDR5 is a different beast 35 * entirely. 36 */ 37 38 #include <sys/bitext.h> 39 #include "spd_common.h" 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* 46 * S8.1.1 Number of Bytes in SPD Device and Beta Level 47 */ 48 #define SPD_DDR5_NBYTES 0x000 49 #define SPD_DDR5_NBYTES_BETAHI(r) bitx8(r, 7, 7) 50 #define SPD_DDR5_NBYTES_TOTAL(r) bitx8(r, 6, 4) 51 #define SPD_DDR5_NBYTES_TOTAL_UNDEF 0 52 #define SPD_DDR5_NBYTES_TOTAL_256 1 53 #define SPD_DDR5_NBYTES_TOTAL_512 2 54 #define SPD_DDR5_NBYTES_TOTAL_1024 3 55 #define SPD_DDR5_NBYTES_TOTAL_2048 4 56 #define SPD_DDR5_NBYTES_BETA(r) bitx8(r, 3, 0) 57 58 /* 59 * S8.1.2 SPD Revision for Base Configuration Parameters. This is the same as 60 * described in SPD_DDR4_SPD_REV as defined in spd_ddr4.h. 61 */ 62 #define SPD_DDR5_SPD_REV 0x001 63 #define SPD_DDR5_SPD_REV_ENC(r) bitx8(r, 7, 4) 64 #define SPD_DDR5_SPD_REV_ADD(r) bitx8(r, 3, 0) 65 #define SPD_DDR5_SPD_REV_V1 1 66 67 /* 68 * S8.1.3: Key Byte / DRAM Device Type. This field identifies the type of DDR 69 * device and is actually consistent across all SPD versions. Known values are 70 * in the spd_dram_type_t enumeration. 71 */ 72 #define SPD_DDR5_DRAM_TYPE 0x002 73 74 /* 75 * S8.1.4 Key Byte / Module Type 76 */ 77 #define SPD_DDR5_MOD_TYPE 0x003 78 #define SPD_DDR5_MOD_TYPE_ISHYBRID(r) bitx8(r, 7, 7) 79 #define SPD_DDR5_MOD_TYPE_HYBRID(r) bitx8(r, 6, 4) 80 #define SPD_DDR5_MOD_TYPE_HYBRID_NONE 0 81 #define SPD_DDR5_MOD_TYPE_HYBRID_NVDIMM_N 1 82 #define SPD_DDR5_MOD_TYPE_HYBRID_NVDIMM_P 2 83 #define SPD_DDR5_MOD_TYPE_TYPE(r) bitx8(r, 3, 0) 84 #define SPD_DDR5_MOD_TYPE_TYPE_RDIMM 1 85 #define SPD_DDR5_MOD_TYPE_TYPE_UDIMM 2 86 #define SPD_DDR5_MOD_TYPE_TYPE_SODIMM 3 87 #define SPD_DDR5_MOD_TYPE_TYPE_LRDIMM 4 88 #define SPD_DDR5_MOD_TYPE_TYPE_MRDIMM 7 89 #define SPD_DDR5_MOD_TYPE_TYPE_DDIMM 10 90 #define SPD_DDR5_MOD_TYPE_TYPE_SOLDER 11 91 92 /* 93 * S8.1.5 First SDRAM Density and Package 94 * S8.1.9 Second SDRAM Density and Package 95 */ 96 #define SPD_DDR5_DENPKG1 0x004 97 #define SPD_DDR5_DENPKG2 0x008 98 #define SPD_DDR5_DENPKG_DPP(r) bitx8(r, 7, 5) 99 #define SPD_DDR5_DENPKG_DPP_MONO 0 100 #define SPD_DDR5_DENPKG_DPP_DDP 1 101 #define SPD_DDR5_DENPKG_DPP_2H3DS 2 102 #define SPD_DDR5_DENPKG_DPP_4H3DS 3 103 #define SPD_DDR5_DENPKG_DPP_8H3DS 4 104 #define SPD_DDR5_DENPKG_DPP_16H3DS 5 105 #define SPD_DDR5_DENPKG_DPD(r) bitx8(r, 4, 0) 106 #define SPD_DDR5_DENPKG_DPD_4Gb 1 107 #define SPD_DDR5_DENPKG_DPD_8Gb 2 108 #define SPD_DDR5_DENPKG_DPD_12Gb 3 109 #define SPD_DDR5_DENPKG_DPD_16Gb 4 110 #define SPD_DDR5_DENPKG_DPD_24Gb 5 111 #define SPD_DDR5_DENPKG_DPD_32Gb 6 112 #define SPD_DDR5_DENPKG_DPD_48Gb 7 113 #define SPD_DDR5_DENPKG_DPD_64Gb 8 114 115 /* 116 * S8.1.6 First SDRAM Addressing 117 * S8.1.10 Second SDRAM Addressing 118 */ 119 #define SPD_DDR5_ADDR1 0x005 120 #define SPD_DDR5_ADDR2 0x009 121 #define SPD_DDR5_ADDR_NCOLS(r) bitx8(r, 7, 5) 122 #define SPD_DDR5_ADDR_NCOLS_BASE 10 123 #define SPD_DDR5_ADDR_NCOLS_MAX 11 124 #define SPD_DDR5_ADDR_NROWS(r) bitx8(r, 4, 0) 125 #define SPD_DDR5_ADDR_NROWS_BASE 16 126 #define SPD_DDR5_ADDR_NROWS_MAX 18 127 128 /* 129 * S8.1.7 First SDRAM I/O Width 130 * S8.1.11 Second SDRAM I/O Width 131 */ 132 #define SPD_DDR5_WIDTH1 0x006 133 #define SPD_DDR5_WIDTH2 0x00a 134 #define SPD_DDR5_WIDTH_WIDTH(r) bitx8(r, 7, 5) 135 #define SPD_DDR5_WIDTH_X4 0 136 #define SPD_DDR5_WIDTH_X8 1 137 #define SPD_DDR5_WIDTH_X16 2 138 #define SPD_DDR5_WIDTH_X32 3 139 140 /* 141 * S8.1.8 First SDRAM Bank Groups and Banks per Bank Group 142 * S8.1.8 Second SDRAM Bank Groups and Banks per Bank Group 143 * 144 * Both values here are in the number of bits that correspond to bank groups and 145 * banks per group. In other words, the total number is 1 << value. 146 */ 147 #define SPD_DDR5_BANKS1 0x007 148 #define SPD_DDR5_BANKS2 0x00b 149 #define SPD_DDR5_BANKS_NBG(r) bitx8(r, 7, 5) 150 #define SPD_DDR5_BANKS_NBG_MAX 8 151 #define SPD_DDR5_BANKS_NBA(r) bitx8(r, 2, 0) 152 #define SPD_DDR5_BANKS_NBA_MAX 4 153 154 /* 155 * S8.1.13 SDRAM BL32 and Post Package Repair 156 */ 157 #define SPD_DDR5_PPR 0x00c 158 #define SPD_DDR5_PPR_GRAN(r) bitx8(r, 7, 7) 159 #define SPD_DDR5_PPR_GRAN_BGRP 0 160 #define SPD_DDR5_PPR_GRAN_BANK 1 161 #define SPD_DDR5_PPR_LOCK_SUP(r) bitx8(r, 5, 5) 162 #define SPD_DDR5_PPR_BL32_SUP(r) bitx8(r, 4, 4) 163 #define SPD_DDR5_PPR_MPPR_SUP(r) bitx8(r, 1, 1) 164 165 /* 166 * S8.1.14 SDRAM Duty Cycle Adjustor and Partial Array Self Refresh 167 */ 168 #define SPD_DDR5_SDA 0x00d 169 #define SPD_DDR5_SPD_DCA_PASR(r) bitx8(r, 4, 4) 170 #define SPD_DDR5_SPD_DCA_TYPE(r) bitx8(r, 1, 0) 171 #define SPD_DDR5_SPD_DCA_TYPE_UNSUP 0 172 #define SPD_DDR5_SPD_DCA_TYPE_1_2P 1 173 #define SPD_DDR5_SPD_DCA_TYPE_4P 2 174 175 /* 176 * S8.1.15 SDRAM Fault Handling and Temperature Sense 177 */ 178 #define SPD_DDR5_FLT 0x00e 179 #define SPD_DDR5_FLT_WIDE_TS(r) bitx8(r, 3, 3) 180 #define SPD_DDR5_FLT_WBSUPR_SUP(r) bitx8(r, 2, 2) 181 #define SPD_DDR5_FLT_WBSUPR_SEL(r) bitx8(r, 1, 1) 182 #define SPD_DDR5_FLT_WBSUPR_SEL_MR9 0 183 #define SPD_DDR5_FLT_WBSUPR_SEL_MR15 1 184 #define SPD_DDR5_FLT_BFLT(r) bitx8(r, 0, 0) 185 186 /* 187 * S8.1.17 SDRAM Nominal Voltage, VDD 188 * S8.1.18 SDRAM Nominal Voltage, VDDQ 189 * S8.1.19 SDRAM Nominal Voltage, VDP 190 * 191 * These three share the same breakdown between nominal, operable, and endurant 192 * voltages. However, the actual values that they support are different. 193 */ 194 #define SPD_DDR5_DRAM_VDD 0x010 195 #define SPD_DDR5_DRAM_VDDQ 0x011 196 #define SPD_DDR5_DRAM_VPP 0x012 197 #define SPD_DDR5_DRAM_VOLT_NOM(r) bitx8(r, 7, 4) 198 #define SPD_DDR5_DRAM_VOLT_OPER(r) bitx8(r, 3, 2) 199 #define SPD_DDR5_DRAM_VOLT_END(r) bitx8(r, 1, 0) 200 #define SPD_DDR5_DRAM_VDD_V1P1 0 201 #define SPD_DDR5_DRAM_VDQ_V1P1 0 202 #define SPD_DDR5_DRAM_VPP_V1P8 0 203 204 /* 205 * S8.1.20 SDRAM Timing 206 */ 207 #define SPD_DDR5_TIME 0x013 208 #define SPD_DDR5_TIME_STD(r) bitx8(r, 0, 0) 209 #define SPD_DDR5_TIME_STD_STD 0 210 #define SPD_DDR5_TIME_STD_NON 1 211 212 /* 213 * Timing based parameters. DDR5 uses two timebase values, either 1ps or 1ns. 214 * This is different from DDR4 which had the MTB and FTB. For each parameter we 215 * note whether it is in picoseconds or nanosecond units. 216 */ 217 218 /* 219 * S8.4 SDRAM Minimum Cycle Time t~CKAVG~min (ps) 220 * S8.5 SDRAM Maximum Cycle Time t~CKAVG~max (ps) 221 */ 222 #define SPD_DDR5_TCKAVG_MIN_LSB 0x014 223 #define SPD_DDR5_TCKAVG_MIN_MSB 0x015 224 #define SPD_DDR5_TCKAVG_MAX_LSB 0x016 225 #define SPD_DDR5_TCKAVG_MAX_MSB 0x017 226 227 /* 228 * S8.6 CAS Latencies. These are 5 bytes which indicate which set o CAS 229 * latencies are supported. The LSB of the SPD_DDR5_CAS_SUP0 corresponds to 230 * CL20. Each subsequent bit is an additional 2 CL. So bit 4 is CL28. Byte 2 bit 231 * 6 is CL64. 232 */ 233 #define SPD_DDR5_CAS_SUP0 0x018 234 #define SPD_DDR5_CAS_SUP1 0x019 235 #define SPD_DDR5_CAS_SUP2 0x01a 236 #define SPD_DDR5_CAS_SUP3 0x01b 237 #define SPD_DDR5_CAS_SUP4 0x01c 238 239 /* 240 * S8.7 SDRAM Read Command to First Data (t~AA~) (ps) 241 * S8.8 SDRAM Activate to Read or Write Command Delay (t~RCD~) (ps) 242 * S8.9 SDRAM Row Precharge Time (t~RP~) (ps) 243 * S8.10 SDRAM Activate to Precharge Command Period (t~RAS~) (ps) 244 * S8.11 SDRAM Activate to to Activate or Refresh Command Period (t~RC~) (ps) 245 * S8.12 SDRAM Write Recovery Time (t~WR~) (ps) 246 * S8.13 SDRAM Normal Refresh Recovery Time (t~RFC1,tRFC1_slr~) (ns) 247 * S8.14 SDRAM Fine Granularity Refresh Recovery Time (t~RFC2,tRFC2_slr~) (ns) 248 * S8.15 SDRAM Same Bank Refresh Recovery Time (t~RFCsb,tRFCsb_slr~) (ns) 249 * S8.16 SDRAM Normal Refresh Recovery Time, 3DS Different Logical Rank 250 * (t~RFC1_dlr~) (ns) 251 * S8.17 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank 252 * (t~RFC2_dlr~) (ns) 253 * S8.18 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank 254 * (t~RFCsb_dlr~) (ns) 255 */ 256 #define SPD_DDR5_TAA_LSB 0x01e 257 #define SPD_DDR5_TAA_MSB 0x01f 258 #define SPD_DDR5_TRCD_LSB 0x020 259 #define SPD_DDR5_TRCD_MSB 0x021 260 #define SPD_DDR5_TRP_LSB 0x022 261 #define SPD_DDR5_TRP_MSB 0x023 262 #define SPD_DDR5_TRAS_LSB 0x024 263 #define SPD_DDR5_TRAS_MSB 0x025 264 #define SPD_DDR5_TRC_LSB 0x026 265 #define SPD_DDR5_TRC_MSB 0x027 266 #define SPD_DDR5_TWR_LSB 0x028 267 #define SPD_DDR5_TWR_MSB 0x029 268 #define SPD_DDR5_TRFC1_LSB 0x02a 269 #define SPD_DDR5_TRFC1_MSB 0x02b 270 #define SPD_DDR5_TRFC2_LSB 0x02c 271 #define SPD_DDR5_TRFC2_MSB 0x02d 272 #define SPD_DDR5_TRFCSB_LSB 0x02e 273 #define SPD_DDR5_TRFCSB_MSB 0x02f 274 #define SPD_DDR5_3DS_TRFC1_LSB 0x030 275 #define SPD_DDR5_3DS_TRFC1_MSB 0x031 276 #define SPD_DDR5_3DS_TRFC2_LSB 0x032 277 #define SPD_DDR5_3DS_TRFC2_MSB 0x033 278 #define SPD_DDR5_3DS_TRFCSB_LSB 0x034 279 #define SPD_DDR5_3DS_TRFCSB_MSB 0x035 280 281 /* 282 * S8.19 SDRAM Refresh Management First SDRAM 283 * S8.20 SDRAM Refresh Management Second SDRAM 284 * 285 * Refresh Management spans two bytes. 286 */ 287 #define SPD_DDR5_RFM0_SDRAM0 0x036 288 #define SPD_DDR5_RFM0_SDRAM1 0x038 289 #define SPD_DDR5_RFM0_RAAMMT_NORM(r) bitx8(r, 7, 5) 290 #define SPD_DDR5_RFM0_RAAMMT_NORM_MIN 3 291 #define SPD_DDR5_RFM0_RAAMMT_NORM_MAX 6 292 #define SPD_DDR5_RFM0_RAAMMT_NORM_MULT 1 293 #define SPD_DDR5_RFM0_RAAMMT_FGR(r) bitx8(r, 7, 5) 294 #define SPD_DDR5_RFM0_RAAMMT_FGR_MIN 6 295 #define SPD_DDR5_RFM0_RAAMMT_FGR_MAX 12 296 #define SPD_DDR5_RFM0_RAAMMT_FGR_MULT 2 297 #define SPD_DDR5_RFM0_RAAIMT_NORM(r) bitx8(r, 4, 1) 298 #define SPD_DDR5_RFM0_RAAIMT_NORM_MIN 32 299 #define SPD_DDR5_RFM0_RAAIMT_NORM_MAX 80 300 #define SPD_DDR5_RFM0_RAAIMT_NORM_MULT 8 301 #define SPD_DDR5_RFM0_RAAIMT_FGR(r) bitx8(r, 4, 1) 302 #define SPD_DDR5_RFM0_RAAIMT_FGR_MIN 16 303 #define SPD_DDR5_RFM0_RAAIMT_FGR_MAX 40 304 #define SPD_DDR5_RFM0_RAAIMT_FGR_MULT 4 305 #define SPD_DDR5_RFM0_RFM_REQ(r) bitx8(r, 0, 0) 306 #define SPD_DDR5_RFM1_SDRAM0 0x037 307 #define SPD_DDR5_RFM1_SDRAM1 0x039 308 #define SPD_DDR5_RFM1_CTR(r) bitx8(r, 7, 6) 309 #define SPD_DDR5_RFM1_CTR_1X 0 310 #define SPD_DDR5_RFM1_CTR_2X 1 311 #define SPD_DDR5_RFM1_BRC_SUP(r)bitx8(r, 3, 3) 312 #define SPD_DDR5_RFM1_BRC_SUP_234 0 313 #define SPD_DDR5_RFM1_BRC_SUP_2 1 314 #define SPD_DDR5_RFM1_BRC_CFG(r) bitx8(r, 2, 1) 315 #define SPD_DDR5_RFM1_BRC_CFG_BASE 2 316 #define SPD_DDR5_RFM1_BRC_CFG_MAX 4 317 #define SPD_DDR5_RFM1_DRFM_SUP(r) bitx8(r, 0, 0) 318 319 /* 320 * S8.21 SDRAM Adaptive Refresh Management. This is broken down so that there 321 * are three levels, A, B, and C. There are then two bytes per level. And there 322 * is one entry for the first DRAM and one for the second. With the exception of 323 * bit 0 of the low byte, which indicates whether or not this is supported, 324 * these two byte ranges all match the prior two bytes. 325 */ 326 #define SPD_DDR5_ARFM0_A_SDRAM0 0x03a 327 #define SPD_DDR5_ARFM1_A_SDRAM0 0x03b 328 #define SPD_DDR5_ARFM0_A_SDRAM1 0x03c 329 #define SPD_DDR5_ARFM1_A_SDRAM1 0x03d 330 #define SPD_DDR5_ARFM0_B_SDRAM0 0x03e 331 #define SPD_DDR5_ARFM1_B_SDRAM0 0x03f 332 #define SPD_DDR5_ARFM0_B_SDRAM1 0x040 333 #define SPD_DDR5_ARFM1_B_SDRAM1 0x041 334 #define SPD_DDR5_ARFM0_C_SDRAM0 0x042 335 #define SPD_DDR5_ARFM1_C_SDRAM0 0x043 336 #define SPD_DDR5_ARFM0_C_SDRAM1 0x044 337 #define SPD_DDR5_ARFM1_C_SDRAM1 0x045 338 #define SPD_DDR5_ARFM_SUP(r) bitx8(r, 0, 0) 339 340 /* 341 * S8.22 SDRAM Activate to Activate Command Delay for Same Bank Group (t~RRD_L~) 342 * S8.23 SDRAM Read to Read Command Delay for Same Bank Group (t~CDD_L~) 343 * S8.24 SDRAM Write to Write Command Delay for Same Bank Group (t~CDD_L_WR~) 344 * S8.25 SDRAM Write to Write Command Delay for Same Bank Group, Second Write 345 * not RMW (t~CDD_L_WR2~) 346 * S8.26 SDRAM Four Activate Window (t~FAW~) 347 * S8.27 SDRAM Write to Read Command Delay for Same Bank Group (t~CCD_L_WTR~) 348 * S8.28 SDRAM Write to Read Command Delay for Different Bank Group 349 * (t~CCD_S_WTR~) 350 * S8.29 SDRAM Read to Precharge Command Delay (t~RTP~,t~RTP_slr~) 351 * 352 * These timing registers all consist of three bytes. The first two bytes are 353 * the LSB / MSB of the value in ps. The third bird defines the number of clock 354 * cycles required. 355 */ 356 #define SPD_DDR5_TRRD_L_LSB 0x046 357 #define SPD_DDR5_TRRD_L_MSB 0x047 358 #define SPD_DDR5_TRRD_L_NCK 0x048 359 #define SPD_DDR5_TCCD_L_LSB 0x049 360 #define SPD_DDR5_TCCD_L_MSB 0x04a 361 #define SPD_DDR5_TCCD_L_NCK 0x04b 362 #define SPD_DDR5_TCCD_L_WR_LSB 0x04c 363 #define SPD_DDR5_TCCD_L_WR_MSB 0x04d 364 #define SPD_DDR5_TCCD_L_WR_NCK 0x04e 365 #define SPD_DDR5_TCCD_L_WR2_LSB 0x04f 366 #define SPD_DDR5_TCCD_L_WR2_MSB 0x050 367 #define SPD_DDR5_TCCD_L_WR2_NCK 0x051 368 #define SPD_DDR5_TFAW_LSB 0x052 369 #define SPD_DDR5_TFAW_MSB 0x053 370 #define SPD_DDR5_TFAW_NCK 0x054 371 #define SPD_DDR5_TCCD_L_WTR_LSB 0x055 372 #define SPD_DDR5_TCCD_L_WTR_MSB 0x056 373 #define SPD_DDR5_TCCD_L_WTR_NCK 0x057 374 #define SPD_DDR5_TCCD_S_WTR_LSB 0x058 375 #define SPD_DDR5_TCCD_S_WTR_MSB 0x059 376 #define SPD_DDR5_TCCD_S_WTR_NCK 0x05a 377 #define SPD_DDR5_TRTP_LSB 0x05b 378 #define SPD_DDR5_TRTP_MSB 0x05c 379 #define SPD_DDR5_TRTP_NCK 0x05d 380 381 /* 382 * The remaining bytes in this section are currently reserved. Next, we begin 383 * Annex A.0 which has common bytes that are shared between all module types. 384 */ 385 386 /* 387 * S11.1 Common: SPD Revision for Module Information. This is the equivalent of 388 * SPD_DDR5_SPD_REV, but covers all of the module-specific information, which 389 * includes both the common area and type-specific areas. 390 */ 391 #define SPD_DDR5_COM_REV 0x0c0 392 393 /* 394 * S11.2 Common: Hashing Sequence. This defines a possible hashing sequence that 395 * may be applied to a certificate related to device authentication per 396 * JEDS316-5. 397 */ 398 #define SPD_DDR5_COM_HASH 0x0c1 399 #define SPD_DDR5_COM_HASH_HASH(r) bitx8(r, 2, 0) 400 #define SPD_DDR5_COM_HASH_NONE 0 401 #define SPD_DDR5_COM_HASH_ALG1 1 402 403 /* 404 * S11.3 Common: Module Device Information. This contains a series of four 405 * registers for each of five possible items: the SPD, three PMICs (power 406 * management integrated circuit), and a temperature sensor. Before leveraging 407 * the MFG ID, one must consult the Device Type register to see if it is 408 * present. We start with generic definitions for each register type. Specifics 409 * to a register such as type values will follow. The revision is a BCD revision 410 * register. See DDR4 discussion. 411 */ 412 #define SPD_DDR5_COM_INFO_PRES(r) bitx8(r, 7, 7) 413 #define SPD_DDR5_COM_INFO_TYPE(r) bitx8(r, 3, 0) 414 415 #define SPD_DDR5_COM_MFG_ID0_SPD 0x0c2 416 #define SPD_DDR5_COM_MFG_ID1_SPD 0x0c3 417 #define SPD_DDR5_COM_INFO_SPD 0x0c4 418 #define SPD_DDR5_COM_INFO_TYPE_SPD5118 0 419 #define SPD_DDR5_COM_INFO_TYPE_ESPD5216 1 420 #define SPD_DDR5_COM_REV_SPD 0x0c5 421 422 #define SPD_DDR5_COM_MFG_ID0_PMIC0 0x0c6 423 #define SPD_DDR5_COM_MFG_ID1_PMIC0 0x0c7 424 #define SPD_DDR5_COM_INFO_PMIC0 0x0c8 425 #define SPD_DDR5_COM_INFO_TYPE_PMIC5000 0 426 #define SPD_DDR5_COM_INFO_TYPE_PMIC5010 1 427 #define SPD_DDR5_COM_INFO_TYPE_PMIC5100 2 428 #define SPD_DDR5_COM_REV_PMIC0 0x0c9 429 430 #define SPD_DDR5_COM_MFG_ID0_PMIC1 0x0ca 431 #define SPD_DDR5_COM_MFG_ID1_PMIC1 0x0cb 432 #define SPD_DDR5_COM_INFO_PMIC1 0x0cc 433 #define SPD_DDR5_COM_REV_PMIC1 0x0cd 434 435 #define SPD_DDR5_COM_MFG_ID0_PMIC2 0x0ce 436 #define SPD_DDR5_COM_MFG_ID1_PMIC2 0x0cf 437 #define SPD_DDR5_COM_INFO_PMIC2 0x0d0 438 #define SPD_DDR5_COM_REV_PMIC2 0x0d1 439 440 #define SPD_DDR5_COM_MFG_ID0_TS 0x0d2 441 #define SPD_DDR5_COM_MFG_ID1_TS 0x0d3 442 #define SPD_DDR5_COM_INFO_TS 0x0d4 443 #define SPD_DDR5_COM_INFO_TS1_PRES(r) bitx8(r, 6, 6) 444 #define SPD_DDR5_COM_INFO_TYPE_TS5111 0 445 #define SPD_DDR5_COM_INFO_TYPE_TS5110 1 446 #define SPD_DDR5_COM_REV_TS 0x0d5 447 448 /* 449 * S11.5 Common: Module Nominal Height 450 */ 451 #define SPD_DDR5_COM_HEIGHT 0x0e6 452 #define SPD_DDR5_COM_HEIGHT_MM(r) bitx8(r, 4, 0) 453 #define SPD_DDR5_COM_HEIGHT_BASE 15 454 455 /* 456 * S11.6 Common: Module Maximum Thickness 457 */ 458 #define SPD_DDR5_COM_THICK 0x0e7 459 #define SPD_DDR5_COM_THICK_BACK(r) bitx8(r, 7, 4) 460 #define SPD_DDR5_COM_THICK_FRONT(r) bitx8(r, 3, 0) 461 #define SPD_DDR5_COM_THICK_BASE 1 462 463 /* 464 * S11.7 Common: Reference Raw Card Used 465 */ 466 #define SPD_DDR5_COM_REF 0x0e8 467 #define SPD_DDR5_COM_REF_REV(r) bitx8(r, 7, 5) 468 #define SPD_DDR5_COM_REF_REV_MAX 6 469 #define SPD_DDR5_COM_REF_CARD(r) bitx8(r, 4, 0) 470 471 /* 472 * S11.8 Common: DIMM Attributes 473 */ 474 #define SPD_DDR5_COM_ATTR 0x0e9 475 #define SPD_DDR5_COM_ATTR_OTR(r) bitx8(r, 7, 4) 476 #define SPD_DDR5_COM_ATTR_OTR_A1T 0 477 #define SPD_DDR5_COM_ATTR_OTR_A2T 1 478 #define SPD_DDR5_COM_ATTR_OTR_A3T 2 479 #define SPD_DDR5_COM_ATTR_OTR_IT 3 480 #define SPD_DDR5_COM_ATTR_OTR_ST 4 481 #define SPD_DDR5_COM_ATTR_OTR_ET 5 482 #define SPD_DDR5_COM_ATTR_OTR_RT 6 483 #define SPD_DDR5_COM_ATTR_OTR_NT 7 484 #define SPD_DDR5_COM_ATTR_OTR_XT 8 485 #define SPD_DDR5_COM_ATTR_SPREAD(r) bitx8(r, 2, 2) 486 #define SPD_DDR5_COM_ATTR_NROWS(r) bitx8(r, 1, 0) 487 #define SPD_DDR5_COM_ATTR_NROWS_UNDEF 0 488 #define SPD_DDR5_COM_ATTR_NROWS_1 1 489 #define SPD_DDR5_COM_ATTR_NROWS_2 2 490 491 /* 492 * S11.9 Common: Module Organization 493 */ 494 #define SPD_DDR5_COM_ORG 0x0ea 495 #define SPD_DDR5_COM_ORG_MIX(r) bitx8(r, 6, 6) 496 #define SPD_DDR5_COM_ORG_MIX_SYM 0 497 #define SPD_DDR5_COM_ORG_MIX_ASYM 1 498 #define SPD_DDR5_COM_ORG_NRANK(r) bitx8(r, 5, 3) 499 #define SPD_DDR5_COM_ORG_NRANK_BASE 1 500 501 /* 502 * S11.10 Common: Memory Channel Bus Width. Unlike DDR4, these widths are in 503 * terms of sub-channels. 504 */ 505 #define SPD_DDR5_COM_BUS_WIDTH 0x0eb 506 #define SPD_DDR5_COM_BUS_WIDTH_NSC(r) bitx8(r, 6, 5) 507 #define SPD_DDR5_COM_BUS_WIDTH_NSC_BASE 1 508 #define SPD_DDR5_COM_BUS_WIDTH_NSC_MAX 2 509 #define SPD_DDR5_COM_BUS_WIDTH_EXT(r) bitx8(r, 4, 3) 510 #define SPD_DDR5_COM_BUS_WIDTH_EXT_NONE 0 511 #define SPD_DDR5_COM_BUS_WIDTH_EXT_4b 1 512 #define SPD_DDR5_COM_BUS_WIDTH_EXT_8b 2 513 #define SPD_DDR5_COM_BUS_WIDTH_PRI(r) bitx8(r, 2, 0) 514 #define SPD_DDR5_COM_BUS_WIDTH_PRI_8b 0 515 #define SPD_DDR5_COM_BUS_WIDTH_PRI_16b 1 516 #define SPD_DDR5_COM_BUS_WIDTH_PRI_32b 2 517 #define SPD_DDR5_COM_BUS_WIDTH_PRI_64b 3 518 519 /* 520 * After this point, all remaining bytes are reserved and Annex specific 521 * information follows. Annex A.1 Module Specific Bytes for Solder Down is 522 * skipped because there are no bytes defined. The revisions for these all 523 * follow the common revision found at SPD_DDR5_COM_REV. 524 */ 525 526 /* 527 * Annex A.2 Module Specific Bytes for Buffered Memory Module Types. S13.1 528 * UDIMM: Module Specific Device Information. This follows the same pattern as 529 * the other device specific manufacturing information with a series of four 530 * bytes. See the discussion of S11.3. This is the only defined entry in this 531 * annex right now. 532 */ 533 #define SPD_DDR5_UDIMM_MFG_ID0_CLK 0x0f0 534 #define SPD_DDR5_UDIMM_MFG_ID1_CLK 0x0f1 535 #define SPD_DDR5_UDIMM_INFO_CLK 0x0f2 536 #define SPD_DDR5_UDIMM_INFO_TYPE_DDR5CK01 0 537 #define SPD_DDR5_UDIMM_REV_CLK 0x0f3 538 539 /* 540 * Annex A.3: Module Specific Bytes for Registered (RDIMM) and Load Reduced 541 * (LRDIMM) Memory Module Types. 542 */ 543 544 /* 545 * S14.2 RDIMM: Module Specific Device Information. This covers the RCD and DB 546 * components. Only LRDIMMs will have the DB present and it will be left as zero 547 * for RDIMMs. 548 */ 549 #define SPD_DDR5_RDIMM_MFG_ID0_RCD 0x0f0 550 #define SPD_DDR5_RDIMM_MFG_ID1_RCD 0x0f1 551 #define SPD_DDR5_RDIMM_INFO_RCD 0x0f2 552 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD01 0 553 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD02 1 554 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD03 2 555 #define SPD_DDR5_RDIMM_REV_RCD 0x0f3 556 557 #define SPD_DDR5_RDIMM_MFG_ID0_DB 0x0f4 558 #define SPD_DDR5_RDIMM_MFG_ID1_DB 0x0f5 559 #define SPD_DDR5_RDIMM_INFO_DB 0x0f6 560 #define SPD_DDR5_RDIMM_INFO_TYPE_DB01 0 561 #define SPD_DDR5_RDIMM_INFO_TYPE_DB02 1 562 #define SPD_DDR5_RDIMM_REV_DB 0x0f7 563 564 /* 565 * S14.3 RDIMM: RCD-RW08 Clock Driver Enable 566 */ 567 #define SPD_DDR5_RDIMM_CLKEN 0x0f8 568 #define SPD_DDR5_RDIMM_CLKEN_BCK(r) bitx8(r, 5, 5) 569 #define SPD_DDR5_RDIMM_CLKEN_QDCK(r) bitx8(r, 3, 3) 570 #define SPD_DDR5_RDIMM_CLKEN_QCCK(r) bitx8(r, 2, 2) 571 #define SPD_DDR5_RDIMM_CLKEN_QBCK(r) bitx8(r, 1, 1) 572 #define SPD_DDR5_RDIMM_CLKEN_QACK(r) bitx8(r, 0, 0) 573 574 /* 575 * S14.4 RDIMM: RCD-RW09 Output Address and Control Enable 576 */ 577 #define SPD_DDR5_RDIMM_RW09 0x0f9 578 #define SPD_DDR5_RDIMM_RW09_QBCS(r) bitx8(r, 6, 6) 579 #define SPD_DDR5_RDIMM_RW09_QACS(r) bitx8(r, 5, 5) 580 #define SPD_DDR5_RDIMM_RW09_QXCA13(r) bitx8(r, 4, 4) 581 #define SPD_DDR5_RDIMM_RW09_BCS(r) bitx8(r, 3, 3) 582 #define SPD_DDR5_RDIMM_RW09_DCS(r) bitx8(r, 2, 2) 583 #define SPD_DDR5_RDIMM_RW09_QBCA(r) bitx8(r, 1, 1) 584 #define SPD_DDR5_RDIMM_RW09_QACA(r) bitx8(r, 0, 0) 585 586 /* 587 * S14.5 RDIMM: RCD-RW0A QCK Driver Characteristics 588 * S14.7 RDIMM: RCD-RW0C QxCA and QxCS_n Driver Characteristics 589 * S14.8 LRDIMM: RCD-RW0D Data Buffer Interface Driver Characteristics 590 * 591 * These share the same definitions for resistance values. One minor exception 592 * is that the LRDIMM BCOM does not support a 10R value. 593 */ 594 #define SPD_DDR5_RDIMM_QCK_DRV 0x0fa 595 #define SPD_DDR5_RDIMM_QCK_DRV_QDCK(r) bitx8(r, 7, 6) 596 #define SPD_DDR5_RDIMM_QCK_DRV_QCCK(r) bitx8(r, 5, 4) 597 #define SPD_DDR5_RDIMM_QCK_DRV_QBCK(r) bitx8(r, 3, 2) 598 #define SPD_DDR5_RDIMM_QCK_DRV_QACK(r) bitx8(r, 1, 0) 599 #define SPD_DDR5_RDIMM_DRV_20R 0 600 #define SPD_DDR5_RDIMM_DRV_14R 1 601 #define SPD_DDR5_RDIMM_DRV_10R 2 602 603 #define SPD_DDR5_RDIMM_QCA_DRV 0x0fc 604 #define SPD_DDR5_RDIMM_QCA_DRV_CS(r) bitx8(r, 5, 4) 605 #define SPD_DDR5_RDIMM_QCA_DRV_CA(r) bitx8(r, 1, 0) 606 607 #define SPD_DDR5_LRDIMM_DB_DRV 0x0fd 608 #define SPD_DDR5_LRDIMM_DB_DRV_BCK(r) bitx8(r, 4, 3) 609 #define SPD_DDR5_LRDIMM_DB_DRV_BCOM(r) bitx8(r, 1, 0) 610 611 /* 612 * S14.9 RDIMM: RCD-RW0E QCK, QCA, and QCS Output Slew Rate 613 * S14.10 LRDIMM: RCD-RW0F BCK, BCOM, and BCS Output Slew Rate 614 * 615 * These all use the same rough definitions for slew rates, i.e. slow, moderate, 616 * and fast; however, they all have different voltage ranges. 617 */ 618 #define SPD_DDR5_RDIMM_QXX_SLEW 0x0fe 619 #define SPD_DDR5_RDIMM_QXX_SLEW_QCS(r) bitx8(r, 5, 4) 620 #define SPD_DDR5_RDIMM_SLEW_MODERTE 0 621 #define SPD_DDR5_RDIMM_SLEW_FAST 1 622 #define SPD_DDR5_RDIMM_SLEW_SLOW 2 623 #define SPD_DDR5_RDIMM_QXX_SLEW_QCA(r) bitx8(r, 3, 2) 624 #define SPD_DDR5_RDIMM_QXX_SLEW_QCK(r) bitx8(r, 1, 0) 625 626 #define SPD_DDR5_LRDIMM_BXX_SLEW 0x0ff 627 #define SPD_DDR5_LRDIMM_BXX_SLEW_BCK(r) bitx8(r, 3, 2) 628 #define SPD_DDR5_LRDIMM_BXX_SLEW_BCOM(r) bitx8(r, 1, 0) 629 630 /* 631 * S14.11 DB-RW86 DQS RTT Park Termination 632 */ 633 #define SPD_DDR5_LRDIMM_PARK 0x100 634 #define SPD_DDR5_LRDIMM_PARK_TERM(r) bitx8(r, 2, 0) 635 #define SPD_DDR5_LDRIMM_PARK_OFF 0 636 #define SPD_DDR5_LDRIMM_PARK_240R 1 637 #define SPD_DDR5_LDRIMM_PARK_120R 2 638 #define SPD_DDR5_LDRIMM_PARK_80R 3 639 #define SPD_DDR5_LDRIMM_PARK_60R 4 640 #define SPD_DDR5_LDRIMM_PARK_48R 5 641 #define SPD_DDR5_LDRIMM_PARK_40R 6 642 #define SPD_DDR5_LDRIMM_PARK_34R 7 643 644 /* 645 * Annex A.4: Module Specific Bytes for Multiplexed Rank (MRDIMM) Memory Module 646 * Types. This only contains a single entry for S15.2 Module Specific Device 647 * Information. 648 */ 649 #define SPD_DDR5_MRDIMM_MFG_ID0_MRCD 0x0f0 650 #define SPD_DDR5_MRDIMM_MFG_ID1_MRCD 0x0f1 651 #define SPD_DDR5_MRDIMM_INFO_MRCD 0x0f2 652 #define SPD_DDR5_MRDIMM_INFO_TYPE_MRCD01 0 653 #define SPD_DDR5_MRDIMM_REV_MRCD 0x0f3 654 655 #define SPD_DDR5_MRDIMM_MFG_ID0_MDB 0x0f4 656 #define SPD_DDR5_MRDIMM_MFG_ID1_MDB 0x0f5 657 #define SPD_DDR5_MRDIMM_INFO_MDB 0x0f6 658 #define SPD_DDR5_MRDIMM_INFO_TYPE_MDB01 0 659 #define SPD_DDR5_MRDIMM_REV_MDB 0x0f7 660 661 /* 662 * Annex A.5: Module Specific Bytes for Differential Memory Module Types. Like 663 * UDIMMs and MRDIMMs, there is only a single section S16.2 for Module Specific 664 * Device Information. 665 */ 666 #define SPD_DDR5_DDIMM_MFG_ID0_DMB 0x0f0 667 #define SPD_DDR5_DDIMM_MFG_ID1_DMB 0x0f1 668 #define SPD_DDR5_DDIMM_INFO_DMB 0x0f2 669 #define SPD_DDR5_DDIMM_INFO_TYPE_DMB501 0 670 #define SPD_DDR5_DDIMM_REV_DMB 0x0f3 671 672 /* 673 * S7.4 CRC. DDR5 modules have a single CRC calculation that covers bytes 0-509. 674 * Thus it covers everything prior to the manufacturing information. 675 */ 676 #define SPD_DDR5_CRC_LSB 0x1fe 677 #define SPD_DDR5_CRC_MSB 0x1ff 678 679 /* 680 * Manufacturing Information. 681 */ 682 683 /* 684 * S19.1 Module Manufacturer ID Code 685 * S19.7 DRAM Manufacturer ID Code 686 */ 687 #define SPD_DDR5_MOD_MFG_ID0 0x200 688 #define SPD_DDR5_MOD_MFG_ID1 0x201 689 #define SPD_DDR5_DRAM_MFG_ID0 0x228 690 #define SPD_DDR5_DRAM_MFG_ID1 0x229 691 692 /* 693 * S19.2 Module Manufacturing Location. This byte is manufacturer specific. 694 */ 695 #define SPD_DDR5_MOD_MFG_LOC 0x202 696 697 /* 698 * S19.3 module Manufacturing Date. Encoded as two BCD bytes for the year and 699 * week. 700 */ 701 #define SPD_DDR5_MOD_MFG_YEAR 0x203 702 #define SPD_DDR5_MOD_MFG_WEEK 0x204 703 704 /* 705 * S19.4 Module Serial Number. 706 * S19.5 Module Part Number 707 * S19.6 Module Revision Code 708 */ 709 #define SPD_DDR5_MOD_SN 0x205 710 #define SPD_DDR5_MOD_SN_LEN 4 711 #define SPD_DDR5_MOD_PN 0x209 712 #define SPD_DDR5_MOD_PN_LEN 30 713 #define SPD_DDR5_MOD_REV 0x227 714 715 /* 716 * S19.8 DRAM Stepping 717 */ 718 #define SPD_DDR5_DRAM_STEP 0x22a 719 720 /* 721 * Bytes 0x22b-0x27f are left for manufacturer specific data. 722 */ 723 724 #ifdef __cplusplus 725 } 726 #endif 727 728 #endif /* _SPD_DDR5_H */ 729