1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2024 Oxide Computer Company 14 */ 15 16 #ifndef _SPD_DDR5_H 17 #define _SPD_DDR5_H 18 19 /* 20 * Definitions for use in DDR5 Serial Presence Detect decoding based on JEDEC 21 * Standard JESD400-5A.01 DDR5 Serial Presence Detect (SPD) Contents. Release 22 * 1.2. This does not cover LPDDR5. While the two are similar, there are enough 23 * differences that we maintain LPDDR5 in its own header (spd_lp5.h). 24 * 25 * DDR5 modules are organized into a few main regions: 26 * 27 * o Base Configuration and DRAM parameters (0x00-0x7f) 28 * o Common Module Parameters (0xc0-0xef) 29 * o Standard Module Parameters (0xf0-0x1bf) which vary on whether something 30 * is an RDIMM, UDIMM, etc. 31 * o A CRC check for the first 510 bytes (0x1fe-0x1ff) 32 * o Manufacturing Information (0x200-0x27f) 33 * o Optional end-user programmable regions (0x280-0x3ff) 34 * 35 * This covers all DDR5 variants other than NVDIMMs. 36 */ 37 38 #include <sys/bitext.h> 39 #include "spd_common.h" 40 41 #ifdef __cplusplus 42 extern "C" { 43 #endif 44 45 /* 46 * S8.1.1 Number of Bytes in SPD Device and Beta Level 47 */ 48 #define SPD_DDR5_NBYTES 0x000 49 #define SPD_DDR5_NBYTES_BETAHI(r) bitx8(r, 7, 7) 50 #define SPD_DDR5_NBYTES_TOTAL(r) bitx8(r, 6, 4) 51 #define SPD_DDR5_NBYTES_TOTAL_UNDEF 0 52 #define SPD_DDR5_NBYTES_TOTAL_256 1 53 #define SPD_DDR5_NBYTES_TOTAL_512 2 54 #define SPD_DDR5_NBYTES_TOTAL_1024 3 55 #define SPD_DDR5_NBYTES_TOTAL_2048 4 56 #define SPD_DDR5_NBYTES_BETA(r) bitx8(r, 3, 0) 57 58 /* 59 * S8.1.2 SPD Revision for Base Configuration Parameters. This is the same as 60 * described in SPD_DDR4_SPD_REV as defined in spd_ddr4.h. 61 */ 62 #define SPD_DDR5_SPD_REV 0x001 63 #define SPD_DDR5_SPD_REV_ENC(r) bitx8(r, 7, 4) 64 #define SPD_DDR5_SPD_REV_ADD(r) bitx8(r, 3, 0) 65 #define SPD_DDR5_SPD_REV_V1 1 66 67 /* 68 * S8.1.3: Key Byte / DRAM Device Type. This field identifies the type of DDR 69 * device and is actually consistent across all SPD versions. Known values are 70 * in the spd_dram_type_t enumeration. 71 */ 72 #define SPD_DDR5_DRAM_TYPE 0x002 73 74 /* 75 * S8.1.4 Key Byte / Module Type 76 */ 77 #define SPD_DDR5_MOD_TYPE 0x003 78 #define SPD_DDR5_MOD_TYPE_ISHYBRID(r) bitx8(r, 7, 7) 79 #define SPD_DDR5_MOD_TYPE_HYBRID(r) bitx8(r, 6, 4) 80 #define SPD_DDR5_MOD_TYPE_HYBRID_NONE 0 81 #define SPD_DDR5_MOD_TYPE_HYBRID_NVDIMM_N 1 82 #define SPD_DDR5_MOD_TYPE_HYBRID_NVDIMM_P 2 83 #define SPD_DDR5_MOD_TYPE_TYPE(r) bitx8(r, 3, 0) 84 #define SPD_DDR5_MOD_TYPE_TYPE_RDIMM 1 85 #define SPD_DDR5_MOD_TYPE_TYPE_UDIMM 2 86 #define SPD_DDR5_MOD_TYPE_TYPE_SODIMM 3 87 #define SPD_DDR5_MOD_TYPE_TYPE_LRDIMM 4 88 #define SPD_DDR5_MOD_TYPE_TYPE_CUDIMM 5 89 #define SPD_DDR5_MOD_TYPE_TYPE_CSODIMM 6 90 #define SPD_DDR5_MOD_TYPE_TYPE_MRDIMM 7 91 #define SPD_DDR5_MOD_TYPE_TYPE_CAMM2 8 92 #define SPD_DDR5_MOD_TYPE_TYPE_DDIMM 10 93 #define SPD_DDR5_MOD_TYPE_TYPE_SOLDER 11 94 95 /* 96 * S8.1.5 First SDRAM Density and Package 97 * S8.1.9 Second SDRAM Density and Package 98 */ 99 #define SPD_DDR5_DENPKG1 0x004 100 #define SPD_DDR5_DENPKG2 0x008 101 #define SPD_DDR5_DENPKG_DPP(r) bitx8(r, 7, 5) 102 #define SPD_DDR5_DENPKG_DPP_MONO 0 103 #define SPD_DDR5_DENPKG_DPP_DDP 1 104 #define SPD_DDR5_DENPKG_DPP_2H3DS 2 105 #define SPD_DDR5_DENPKG_DPP_4H3DS 3 106 #define SPD_DDR5_DENPKG_DPP_8H3DS 4 107 #define SPD_DDR5_DENPKG_DPP_16H3DS 5 108 #define SPD_DDR5_DENPKG_DPD(r) bitx8(r, 4, 0) 109 #define SPD_DDR5_DENPKG_DPD_4Gb 1 110 #define SPD_DDR5_DENPKG_DPD_8Gb 2 111 #define SPD_DDR5_DENPKG_DPD_12Gb 3 112 #define SPD_DDR5_DENPKG_DPD_16Gb 4 113 #define SPD_DDR5_DENPKG_DPD_24Gb 5 114 #define SPD_DDR5_DENPKG_DPD_32Gb 6 115 #define SPD_DDR5_DENPKG_DPD_48Gb 7 116 #define SPD_DDR5_DENPKG_DPD_64Gb 8 117 118 /* 119 * S8.1.6 First SDRAM Addressing 120 * S8.1.10 Second SDRAM Addressing 121 */ 122 #define SPD_DDR5_ADDR1 0x005 123 #define SPD_DDR5_ADDR2 0x009 124 #define SPD_DDR5_ADDR_NCOLS(r) bitx8(r, 7, 5) 125 #define SPD_DDR5_ADDR_NCOLS_BASE 10 126 #define SPD_DDR5_ADDR_NCOLS_MAX 11 127 #define SPD_DDR5_ADDR_NROWS(r) bitx8(r, 4, 0) 128 #define SPD_DDR5_ADDR_NROWS_BASE 16 129 #define SPD_DDR5_ADDR_NROWS_MAX 18 130 131 /* 132 * S8.1.7 First SDRAM I/O Width 133 * S8.1.11 Second SDRAM I/O Width 134 */ 135 #define SPD_DDR5_WIDTH1 0x006 136 #define SPD_DDR5_WIDTH2 0x00a 137 #define SPD_DDR5_WIDTH_WIDTH(r) bitx8(r, 7, 5) 138 #define SPD_DDR5_WIDTH_X4 0 139 #define SPD_DDR5_WIDTH_X8 1 140 #define SPD_DDR5_WIDTH_X16 2 141 #define SPD_DDR5_WIDTH_X32 3 142 143 /* 144 * S8.1.8 First SDRAM Bank Groups and Banks per Bank Group 145 * S8.1.8 Second SDRAM Bank Groups and Banks per Bank Group 146 * 147 * Both values here are in the number of bits that correspond to bank groups and 148 * banks per group. In other words, the total number is 1 << value. 149 */ 150 #define SPD_DDR5_BANKS1 0x007 151 #define SPD_DDR5_BANKS2 0x00b 152 #define SPD_DDR5_BANKS_NBG_BITS(r) bitx8(r, 7, 5) 153 #define SPD_DDR5_BANKS_NBG_BITS_MAX 3 154 #define SPD_DDR5_BANKS_NBA_BITS(r) bitx8(r, 2, 0) 155 #define SPD_DDR5_BANKS_NBA_BITS_MAX 2 156 157 /* 158 * S8.1.13 SDRAM BL32 and Post Package Repair 159 */ 160 #define SPD_DDR5_PPR 0x00c 161 #define SPD_DDR5_PPR_GRAN(r) bitx8(r, 7, 7) 162 #define SPD_DDR5_PPR_GRAN_BGRP 0 163 #define SPD_DDR5_PPR_GRAN_BANK 1 164 #define SPD_DDR5_PPR_LOCK_SUP(r) bitx8(r, 5, 5) 165 #define SPD_DDR5_PPR_BL32_SUP(r) bitx8(r, 4, 4) 166 #define SPD_DDR5_PPR_MPPR_SUP(r) bitx8(r, 1, 1) 167 168 /* 169 * S8.1.14 SDRAM Duty Cycle Adjustor and Partial Array Self Refresh 170 */ 171 #define SPD_DDR5_SDA 0x00d 172 #define SPD_DDR5_SPD_DCA_PASR(r) bitx8(r, 4, 4) 173 #define SPD_DDR5_SPD_DCA_TYPE(r) bitx8(r, 1, 0) 174 #define SPD_DDR5_SPD_DCA_TYPE_UNSUP 0 175 #define SPD_DDR5_SPD_DCA_TYPE_1_2P 1 176 #define SPD_DDR5_SPD_DCA_TYPE_4P 2 177 178 /* 179 * S8.1.15 SDRAM Fault Handling and Temperature Sense 180 */ 181 #define SPD_DDR5_FLT 0x00e 182 #define SPD_DDR5_FLT_WIDE_TS(r) bitx8(r, 3, 3) 183 #define SPD_DDR5_FLT_WBSUPR_SUP(r) bitx8(r, 2, 2) 184 #define SPD_DDR5_FLT_WBSUPR_SEL(r) bitx8(r, 1, 1) 185 #define SPD_DDR5_FLT_WBSUPR_SEL_MR9 0 186 #define SPD_DDR5_FLT_WBSUPR_SEL_MR15 1 187 #define SPD_DDR5_FLT_BFLT(r) bitx8(r, 0, 0) 188 189 /* 190 * S8.1.17 SDRAM Nominal Voltage, VDD 191 * S8.1.18 SDRAM Nominal Voltage, VDDQ 192 * S8.1.19 SDRAM Nominal Voltage, VDP 193 * 194 * These three share the same breakdown between nominal, operable, and endurant 195 * voltages. However, the actual values that they support are different. 196 */ 197 #define SPD_DDR5_DRAM_VDD 0x010 198 #define SPD_DDR5_DRAM_VDDQ 0x011 199 #define SPD_DDR5_DRAM_VPP 0x012 200 #define SPD_DDR5_DRAM_VOLT_NOM(r) bitx8(r, 7, 4) 201 #define SPD_DDR5_DRAM_VOLT_OPER(r) bitx8(r, 3, 2) 202 #define SPD_DDR5_DRAM_VOLT_END(r) bitx8(r, 1, 0) 203 #define SPD_DDR5_DRAM_VDD_V1P1 0 204 #define SPD_DDR5_DRAM_VDQ_V1P1 0 205 #define SPD_DDR5_DRAM_VPP_V1P8 0 206 207 /* 208 * S8.1.20 SDRAM Timing 209 */ 210 #define SPD_DDR5_TIME 0x013 211 #define SPD_DDR5_TIME_STD(r) bitx8(r, 0, 0) 212 #define SPD_DDR5_TIME_STD_STD 0 213 #define SPD_DDR5_TIME_STD_NON 1 214 215 /* 216 * Timing based parameters. DDR5 uses two timebase values, either 1ps or 1ns. 217 * This is different from DDR4 which had the MTB and FTB. For each parameter we 218 * note whether it is in picoseconds or nanosecond units. 219 */ 220 221 /* 222 * S8.1.21 SDRAM Minimum Cycle Time t~CKAVG~min (ps) 223 * S8.1.22 SDRAM Maximum Cycle Time t~CKAVG~max (ps) 224 */ 225 #define SPD_DDR5_TCKAVG_MIN_LSB 0x014 226 #define SPD_DDR5_TCKAVG_MIN_MSB 0x015 227 #define SPD_DDR5_TCKAVG_MAX_LSB 0x016 228 #define SPD_DDR5_TCKAVG_MAX_MSB 0x017 229 230 /* 231 * S8.1.23 CAS Latencies. These are 5 bytes which indicate which set o CAS 232 * latencies are supported. The LSB of the SPD_DDR5_CAS_SUP0 corresponds to 233 * CL20. Each subsequent bit is an additional 2 CL. So bit 4 is CL28. Byte 2 bit 234 * 6 is CL64. 235 */ 236 #define SPD_DDR5_CAS_SUP0 0x018 237 #define SPD_DDR5_CAS_SUP1 0x019 238 #define SPD_DDR5_CAS_SUP2 0x01a 239 #define SPD_DDR5_CAS_SUP3 0x01b 240 #define SPD_DDR5_CAS_SUP4 0x01c 241 242 /* 243 * S8.1.25 SDRAM Read Command to First Data (t~AA~) (ps) 244 * S8.1.26 SDRAM Activate to Read or Write Command Delay (t~RCD~) (ps) 245 * S8.1.27 SDRAM Row Precharge Time (t~RP~) (ps) 246 * S8.1.28 SDRAM Activate to Precharge Command Period (t~RAS~) (ps) 247 * S8.1.29 SDRAM Activate to to Activate or Refresh Command Period (t~RC~) (ps) 248 * S8.1.30 SDRAM Write Recovery Time (t~WR~) (ps) 249 * S8.1.31 SDRAM Normal Refresh Recovery Time (t~RFC1,tRFC1_slr~) (ns) 250 * S8.1.32 SDRAM Fine Granularity Refresh Recovery Time (t~RFC2,tRFC2_slr~) (ns) 251 * S8.1.33 SDRAM Same Bank Refresh Recovery Time (t~RFCsb,tRFCsb_slr~) (ns) 252 * S8.1.34 SDRAM Normal Refresh Recovery Time, 3DS Different Logical Rank 253 * (t~RFC1_dlr~) (ns) 254 * S8.1.35 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank 255 * (t~RFC2_dlr~) (ns) 256 * S8.1.36 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank 257 * (t~RFCsb_dlr~) (ns) 258 */ 259 #define SPD_DDR5_TAA_LSB 0x01e 260 #define SPD_DDR5_TAA_MSB 0x01f 261 #define SPD_DDR5_TRCD_LSB 0x020 262 #define SPD_DDR5_TRCD_MSB 0x021 263 #define SPD_DDR5_TRP_LSB 0x022 264 #define SPD_DDR5_TRP_MSB 0x023 265 #define SPD_DDR5_TRAS_LSB 0x024 266 #define SPD_DDR5_TRAS_MSB 0x025 267 #define SPD_DDR5_TRC_LSB 0x026 268 #define SPD_DDR5_TRC_MSB 0x027 269 #define SPD_DDR5_TWR_LSB 0x028 270 #define SPD_DDR5_TWR_MSB 0x029 271 #define SPD_DDR5_TRFC1_LSB 0x02a 272 #define SPD_DDR5_TRFC1_MSB 0x02b 273 #define SPD_DDR5_TRFC2_LSB 0x02c 274 #define SPD_DDR5_TRFC2_MSB 0x02d 275 #define SPD_DDR5_TRFCSB_LSB 0x02e 276 #define SPD_DDR5_TRFCSB_MSB 0x02f 277 #define SPD_DDR5_3DS_TRFC1_LSB 0x030 278 #define SPD_DDR5_3DS_TRFC1_MSB 0x031 279 #define SPD_DDR5_3DS_TRFC2_LSB 0x032 280 #define SPD_DDR5_3DS_TRFC2_MSB 0x033 281 #define SPD_DDR5_3DS_TRFCSB_LSB 0x034 282 #define SPD_DDR5_3DS_TRFCSB_MSB 0x035 283 284 /* 285 * S8.1.37 SDRAM Refresh Management First SDRAM 286 * S8.1.38 SDRAM Refresh Management Second SDRAM 287 * 288 * Refresh Management spans two bytes. 289 */ 290 #define SPD_DDR5_RFM0_SDRAM0 0x036 291 #define SPD_DDR5_RFM0_SDRAM1 0x038 292 #define SPD_DDR5_RFM0_RAAMMT_NORM(r) bitx8(r, 7, 5) 293 #define SPD_DDR5_RFM0_RAAMMT_NORM_MIN 3 294 #define SPD_DDR5_RFM0_RAAMMT_NORM_MAX 6 295 #define SPD_DDR5_RFM0_RAAMMT_NORM_MULT 1 296 #define SPD_DDR5_RFM0_RAAMMT_FGR(r) bitx8(r, 7, 5) 297 #define SPD_DDR5_RFM0_RAAMMT_FGR_MIN 6 298 #define SPD_DDR5_RFM0_RAAMMT_FGR_MAX 12 299 #define SPD_DDR5_RFM0_RAAMMT_FGR_MULT 2 300 #define SPD_DDR5_RFM0_RAAIMT_NORM(r) bitx8(r, 4, 1) 301 #define SPD_DDR5_RFM0_RAAIMT_NORM_MIN 32 302 #define SPD_DDR5_RFM0_RAAIMT_NORM_MAX 80 303 #define SPD_DDR5_RFM0_RAAIMT_NORM_MULT 8 304 #define SPD_DDR5_RFM0_RAAIMT_FGR(r) bitx8(r, 4, 1) 305 #define SPD_DDR5_RFM0_RAAIMT_FGR_MIN 16 306 #define SPD_DDR5_RFM0_RAAIMT_FGR_MAX 40 307 #define SPD_DDR5_RFM0_RAAIMT_FGR_MULT 4 308 #define SPD_DDR5_RFM0_RFM_REQ(r) bitx8(r, 0, 0) 309 #define SPD_DDR5_RFM1_SDRAM0 0x037 310 #define SPD_DDR5_RFM1_SDRAM1 0x039 311 #define SPD_DDR5_RFM1_CTR(r) bitx8(r, 7, 6) 312 #define SPD_DDR5_RFM1_CTR_1X 0 313 #define SPD_DDR5_RFM1_CTR_2X 1 314 #define SPD_DDR5_RFM1_BRC_SUP(r)bitx8(r, 3, 3) 315 #define SPD_DDR5_RFM1_BRC_SUP_234 0 316 #define SPD_DDR5_RFM1_BRC_SUP_2 1 317 #define SPD_DDR5_RFM1_BRC_CFG(r) bitx8(r, 2, 1) 318 #define SPD_DDR5_RFM1_BRC_CFG_BASE 2 319 #define SPD_DDR5_RFM1_BRC_CFG_MAX 4 320 #define SPD_DDR5_RFM1_DRFM_SUP(r) bitx8(r, 0, 0) 321 322 /* 323 * S8.1.39 SDRAM Adaptive Refresh Management. This is broken down so that there 324 * are three levels, A, B, and C. There are then two bytes per level. And there 325 * is one entry for the first DRAM and one for the second. With the exception of 326 * bit 0 of the low byte, which indicates whether or not this is supported, 327 * these two byte ranges all match the prior two bytes. 328 */ 329 #define SPD_DDR5_ARFM0_A_SDRAM0 0x03a 330 #define SPD_DDR5_ARFM1_A_SDRAM0 0x03b 331 #define SPD_DDR5_ARFM0_A_SDRAM1 0x03c 332 #define SPD_DDR5_ARFM1_A_SDRAM1 0x03d 333 #define SPD_DDR5_ARFM0_B_SDRAM0 0x03e 334 #define SPD_DDR5_ARFM1_B_SDRAM0 0x03f 335 #define SPD_DDR5_ARFM0_B_SDRAM1 0x040 336 #define SPD_DDR5_ARFM1_B_SDRAM1 0x041 337 #define SPD_DDR5_ARFM0_C_SDRAM0 0x042 338 #define SPD_DDR5_ARFM1_C_SDRAM0 0x043 339 #define SPD_DDR5_ARFM0_C_SDRAM1 0x044 340 #define SPD_DDR5_ARFM1_C_SDRAM1 0x045 341 #define SPD_DDR5_ARFM_SUP(r) bitx8(r, 0, 0) 342 343 /* 344 * S8.1.40 SDRAM Activate to Activate Command Delay for Same Bank Group 345 * (t~RRD_L~) 346 * S8.1.41 SDRAM Read to Read Command Delay for Same Bank Group (t~CDD_L~) 347 * S8.1.42 SDRAM Write to Write Command Delay for Same Bank Group (t~CDD_L_WR~) 348 * S8.1.43 SDRAM Write to Write Command Delay for Same Bank Group, Second Write 349 * not RMW (t~CDD_L_WR2~) 350 * S8.1.44 SDRAM Four Activate Window (t~FAW~) 351 * S8.1.45 SDRAM Write to Read Command Delay for Same Bank Group (t~CCD_L_WTR~) 352 * S8.1.46 SDRAM Write to Read Command Delay for Different Bank Group 353 * (t~CCD_S_WTR~) 354 * S8.1.47 SDRAM Read to Precharge Command Delay (t~RTP~,t~RTP_slr~) 355 * S8.1.48 (v1.2) SDRAM Read to Read Command Delay for Different Bank in Same 356 * Bank Group (t~CCD_M~) 357 * S8.1.49 (v1.2) SDRAM Write to Write Command Delay for Different Bank in Same 358 * Bank Group (t~CCD_M_WR~) 359 * S8.1.50 (v1.2) SDRAM Write to Read Command Delay for Different Bank in Same 360 * Bank Group (t~CCD_M_WTR~) 361 * 362 * These timing registers all consist of three bytes. The first two bytes are 363 * the LSB / MSB of the value in ps. The third bird defines the number of clock 364 * cycles required. 365 */ 366 #define SPD_DDR5_TRRD_L_LSB 0x046 367 #define SPD_DDR5_TRRD_L_MSB 0x047 368 #define SPD_DDR5_TRRD_L_NCK 0x048 369 #define SPD_DDR5_TCCD_L_LSB 0x049 370 #define SPD_DDR5_TCCD_L_MSB 0x04a 371 #define SPD_DDR5_TCCD_L_NCK 0x04b 372 #define SPD_DDR5_TCCD_L_WR_LSB 0x04c 373 #define SPD_DDR5_TCCD_L_WR_MSB 0x04d 374 #define SPD_DDR5_TCCD_L_WR_NCK 0x04e 375 #define SPD_DDR5_TCCD_L_WR2_LSB 0x04f 376 #define SPD_DDR5_TCCD_L_WR2_MSB 0x050 377 #define SPD_DDR5_TCCD_L_WR2_NCK 0x051 378 #define SPD_DDR5_TFAW_LSB 0x052 379 #define SPD_DDR5_TFAW_MSB 0x053 380 #define SPD_DDR5_TFAW_NCK 0x054 381 #define SPD_DDR5_TCCD_L_WTR_LSB 0x055 382 #define SPD_DDR5_TCCD_L_WTR_MSB 0x056 383 #define SPD_DDR5_TCCD_L_WTR_NCK 0x057 384 #define SPD_DDR5_TCCD_S_WTR_LSB 0x058 385 #define SPD_DDR5_TCCD_S_WTR_MSB 0x059 386 #define SPD_DDR5_TCCD_S_WTR_NCK 0x05a 387 #define SPD_DDR5_TRTP_LSB 0x05b 388 #define SPD_DDR5_TRTP_MSB 0x05c 389 #define SPD_DDR5_TRTP_NCK 0x05d 390 #define SPD_DDR5_TCCD_M_LSB 0x05e 391 #define SPD_DDR5_TCCD_M_MSB 0x05f 392 #define SPD_DDR5_TCCD_M_NCK 0x060 393 #define SPD_DDR5_TCCD_M_WR_LSB 0x061 394 #define SPD_DDR5_TCCD_M_WR_MSB 0x062 395 #define SPD_DDR5_TCCD_M_WR_NCK 0x063 396 #define SPD_DDR5_TCCD_M_WTR_LSB 0x064 397 #define SPD_DDR5_TCCD_M_WTR_MSB 0x065 398 #define SPD_DDR5_TCCD_M_WTR_NCK 0x066 399 400 /* 401 * The remaining bytes in this section are currently reserved. Next, we begin 402 * Annex A.0 which has common bytes that are shared between all module types. 403 */ 404 405 /* 406 * S11.1 Common: SPD Revision for Module Information. This is the equivalent of 407 * SPD_DDR5_SPD_REV, but covers all of the module-specific information, which 408 * includes both the common area and type-specific areas. 409 */ 410 #define SPD_DDR5_COM_REV 0x0c0 411 412 /* 413 * S11.2 Common: Hashing Sequence. This defines a possible hashing sequence that 414 * may be applied to a certificate related to device authentication per 415 * JEDS316-5. 416 */ 417 #define SPD_DDR5_COM_HASH 0x0c1 418 #define SPD_DDR5_COM_HASH_HASH(r) bitx8(r, 2, 0) 419 #define SPD_DDR5_COM_HASH_NONE 0 420 #define SPD_DDR5_COM_HASH_ALG1 1 421 422 /* 423 * S11.3 Common: Module Device Information. This contains a series of four 424 * registers for each of five possible items: the SPD, three PMICs (power 425 * management integrated circuit), and a temperature sensor. Before leveraging 426 * the MFG ID, one must consult the Device Type register to see if it is 427 * present. We start with generic definitions for each register type. Specifics 428 * to a register such as type values will follow. The revision is a BCD revision 429 * register. See DDR4 discussion. 430 */ 431 #define SPD_DDR5_COM_INFO_PRES(r) bitx8(r, 7, 7) 432 #define SPD_DDR5_COM_INFO_TYPE(r) bitx8(r, 3, 0) 433 434 #define SPD_DDR5_COM_MFG_ID0_SPD 0x0c2 435 #define SPD_DDR5_COM_MFG_ID1_SPD 0x0c3 436 #define SPD_DDR5_COM_INFO_SPD 0x0c4 437 #define SPD_DDR5_COM_INFO_TYPE_SPD5118 0 438 #define SPD_DDR5_COM_INFO_TYPE_ESPD5216 1 439 #define SPD_DDR5_COM_REV_SPD 0x0c5 440 441 #define SPD_DDR5_COM_MFG_ID0_PMIC0 0x0c6 442 #define SPD_DDR5_COM_MFG_ID1_PMIC0 0x0c7 443 #define SPD_DDR5_COM_INFO_PMIC0 0x0c8 444 #define SPD_DDR5_COM_INFO_TYPE_PMIC5000 0 445 #define SPD_DDR5_COM_INFO_TYPE_PMIC5010 1 446 #define SPD_DDR5_COM_INFO_TYPE_PMIC5100 2 447 #define SPD_DDR5_COM_INFO_TYPE_PMIC5020 3 448 #define SPD_DDR5_COM_INFO_TYPE_PMIC5120 4 449 #define SPD_DDR5_COM_INFO_TYPE_PMIC5200 5 450 #define SPD_DDR5_COM_INFO_TYPE_PMIC5030 6 451 #define SPD_DDR5_COM_REV_PMIC0 0x0c9 452 453 #define SPD_DDR5_COM_MFG_ID0_PMIC1 0x0ca 454 #define SPD_DDR5_COM_MFG_ID1_PMIC1 0x0cb 455 #define SPD_DDR5_COM_INFO_PMIC1 0x0cc 456 #define SPD_DDR5_COM_REV_PMIC1 0x0cd 457 458 #define SPD_DDR5_COM_MFG_ID0_PMIC2 0x0ce 459 #define SPD_DDR5_COM_MFG_ID1_PMIC2 0x0cf 460 #define SPD_DDR5_COM_INFO_PMIC2 0x0d0 461 #define SPD_DDR5_COM_REV_PMIC2 0x0d1 462 463 #define SPD_DDR5_COM_MFG_ID0_TS 0x0d2 464 #define SPD_DDR5_COM_MFG_ID1_TS 0x0d3 465 #define SPD_DDR5_COM_INFO_TS 0x0d4 466 #define SPD_DDR5_COM_INFO_TS1_PRES(r) bitx8(r, 6, 6) 467 #define SPD_DDR5_COM_INFO_TYPE_TS5111 0 468 #define SPD_DDR5_COM_INFO_TYPE_TS5110 1 469 #define SPD_DDR5_COM_INFO_TYPE_TS5211 2 470 #define SPD_DDR5_COM_INFO_TYPE_TS5210 3 471 #define SPD_DDR5_COM_REV_TS 0x0d5 472 473 /* 474 * S11.5 Common: Module Nominal Height 475 */ 476 #define SPD_DDR5_COM_HEIGHT 0x0e6 477 #define SPD_DDR5_COM_HEIGHT_MM(r) bitx8(r, 4, 0) 478 #define SPD_DDR5_COM_HEIGHT_BASE 15 479 480 /* 481 * S11.6 Common: Module Maximum Thickness 482 */ 483 #define SPD_DDR5_COM_THICK 0x0e7 484 #define SPD_DDR5_COM_THICK_BACK(r) bitx8(r, 7, 4) 485 #define SPD_DDR5_COM_THICK_FRONT(r) bitx8(r, 3, 0) 486 #define SPD_DDR5_COM_THICK_BASE 1 487 488 /* 489 * S11.7 Common: Reference Raw Card Used 490 */ 491 #define SPD_DDR5_COM_REF 0x0e8 492 #define SPD_DDR5_COM_REF_REV(r) bitx8(r, 7, 5) 493 #define SPD_DDR5_COM_REF_REV_MAX 6 494 #define SPD_DDR5_COM_REF_CARD(r) bitx8(r, 4, 0) 495 496 /* 497 * S11.8 Common: DIMM Attributes 498 */ 499 #define SPD_DDR5_COM_ATTR 0x0e9 500 #define SPD_DDR5_COM_ATTR_OTR(r) bitx8(r, 7, 4) 501 #define SPD_DDR5_COM_ATTR_OTR_A1T 0 502 #define SPD_DDR5_COM_ATTR_OTR_A2T 1 503 #define SPD_DDR5_COM_ATTR_OTR_A3T 2 504 #define SPD_DDR5_COM_ATTR_OTR_IT 3 505 #define SPD_DDR5_COM_ATTR_OTR_ST 4 506 #define SPD_DDR5_COM_ATTR_OTR_ET 5 507 #define SPD_DDR5_COM_ATTR_OTR_RT 6 508 #define SPD_DDR5_COM_ATTR_OTR_NT 7 509 #define SPD_DDR5_COM_ATTR_OTR_XT 8 510 #define SPD_DDR5_COM_ATTR_SPREAD(r) bitx8(r, 2, 2) 511 #define SPD_DDR5_COM_ATTR_NROWS(r) bitx8(r, 1, 0) 512 #define SPD_DDR5_COM_ATTR_NROWS_UNDEF 0 513 #define SPD_DDR5_COM_ATTR_NROWS_1 1 514 #define SPD_DDR5_COM_ATTR_NROWS_2 2 515 516 /* 517 * S11.9 Common: Module Organization 518 */ 519 #define SPD_DDR5_COM_ORG 0x0ea 520 #define SPD_DDR5_COM_ORG_MIX(r) bitx8(r, 6, 6) 521 #define SPD_DDR5_COM_ORG_MIX_SYM 0 522 #define SPD_DDR5_COM_ORG_MIX_ASYM 1 523 #define SPD_DDR5_COM_ORG_NRANK(r) bitx8(r, 5, 3) 524 #define SPD_DDR5_COM_ORG_NRANK_BASE 1 525 526 /* 527 * S11.10 Common: Memory Channel Bus Width. Unlike DDR4, these widths are in 528 * terms of sub-channels. 529 */ 530 #define SPD_DDR5_COM_BUS_WIDTH 0x0eb 531 #define SPD_DDR5_COM_BUS_WIDTH_NSC(r) bitx8(r, 7, 5) 532 #define SPD_DDR5_COM_BUS_WIDTH_NSC_MAX 8 533 #define SPD_DDR5_COM_BUS_WIDTH_EXT(r) bitx8(r, 4, 3) 534 #define SPD_DDR5_COM_BUS_WIDTH_EXT_NONE 0 535 #define SPD_DDR5_COM_BUS_WIDTH_EXT_4b 1 536 #define SPD_DDR5_COM_BUS_WIDTH_EXT_8b 2 537 #define SPD_DDR5_COM_BUS_WIDTH_PRI(r) bitx8(r, 2, 0) 538 #define SPD_DDR5_COM_BUS_WIDTH_PRI_8b 0 539 #define SPD_DDR5_COM_BUS_WIDTH_PRI_16b 1 540 #define SPD_DDR5_COM_BUS_WIDTH_PRI_32b 2 541 #define SPD_DDR5_COM_BUS_WIDTH_PRI_64b 3 542 543 /* 544 * After this point, all remaining bytes are reserved and Annex specific 545 * information follows. Annex A.1 Module Specific Bytes for Solder Down is 546 * skipped because there are no bytes defined. The revisions for these all 547 * follow the common revision found at SPD_DDR5_COM_REV. 548 */ 549 550 /* 551 * Annex A.2 Module Specific Bytes for Buffered Memory Module Types. S13.1 552 * UDIMM: Module Specific Device Information. This follows the same pattern as 553 * the other device specific manufacturing information with a series of four 554 * bytes. See the discussion of S11.3. Revision 1.0 only defined the CLK 555 * information. Revision 1.1 added several additional pieces of data. 556 */ 557 #define SPD_DDR5_UDIMM_MFG_ID0_CLK 0x0f0 558 #define SPD_DDR5_UDIMM_MFG_ID1_CLK 0x0f1 559 #define SPD_DDR5_UDIMM_INFO_CLK 0x0f2 560 #define SPD_DDR5_UDIMM_INFO_TYPE_DDR5CK01 0 561 #define SPD_DDR5_UDIMM_REV_CLK 0x0f3 562 563 /* 564 * S13.2 UDIMM v1.1: CKD-RW00 CKD Configuration 565 */ 566 #define SPD_DDR5_UDIMM_CKD_CFG 0x0f4 567 #define SPD_DDR5_UDIMM_CKD_CFG_CHBQCK1(r) bitx8(r, 7, 7) 568 #define SPD_DDR5_UDIMM_CKD_CFG_CHBQCK0(r) bitx8(r, 6, 6) 569 #define SPD_DDR5_UDIMM_CKD_CFG_CHAQCK1(r) bitx8(r, 5, 5) 570 #define SPD_DDR5_UDIMM_CKD_CFG_CHAQCK0(r) bitx8(r, 4, 4) 571 572 /* 573 * S13.3 UDIMM v1.1: CKD-RW02 QCK Driver Characteristics 574 */ 575 #define SPD_DDR5_UDIMM_CKD_DRV 0x0f5 576 #define SPD_DDR5_UDIMM_CKD_DRV_CHBQCK1_DRIVE(r) bitx8(r, 7, 6) 577 #define SPD_DDR5_UDIMM_CKD_DRV_CHBQCK0_DRIVE(r) bitx8(r, 5, 4) 578 #define SPD_DDR5_UDIMM_CKD_DRV_CHAQCK1_DRIVE(r) bitx8(r, 3, 2) 579 #define SPD_DDR5_UDIMM_CKD_DRV_CHAQCK0_DRIVE(r) bitx8(r, 1, 0) 580 #define SPD_DDR5_UDIMM_CKD_DRV_LIGHT 0 581 #define SPD_DDR5_UDIMM_CKD_DRV_MODERATE 1 582 #define SPD_DDR5_UDIMM_CKD_DRV_STRONG 2 583 #define SPD_DDR5_UDIMM_CKD_DRV_WEAK 3 584 585 /* 586 * S13.4 UDIMM v1.1: CKD-RW03 QCK Output Differential Slew Rate 587 */ 588 #define SPD_DDR5_UDIMM_CKD_SLEW 0x0f6 589 #define SPD_DDR5_UDIMM_CKD_SLEW_CHBQCK_SLEW(r) bitx8(r, 5, 4) 590 #define SPD_DDR5_UDIMM_CKD_SLEW_CHAQCK_SLEW(r) bitx8(r, 1, 0) 591 #define SPD_DDR5_UDIMM_CKD_SLEW_SLEW_MODERATE 0 592 #define SPD_DDR5_UDIMM_CKD_SLEW_SLEW_FAST 1 593 594 /* 595 * Annex A.3: Module Specific Bytes for Registered (RDIMM) and Load Reduced 596 * (LRDIMM) Memory Module Types. 597 */ 598 599 /* 600 * S14.2 RDIMM: Module Specific Device Information. This covers the RCD and DB 601 * components. Only LRDIMMs will have the DB present and it will be left as zero 602 * for RDIMMs. 603 */ 604 #define SPD_DDR5_RDIMM_MFG_ID0_RCD 0x0f0 605 #define SPD_DDR5_RDIMM_MFG_ID1_RCD 0x0f1 606 #define SPD_DDR5_RDIMM_INFO_RCD 0x0f2 607 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD01 0 608 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD02 1 609 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD03 2 610 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD04 3 611 #define SPD_DDR5_RDIMM_INFO_TYPE_RCD05 4 612 #define SPD_DDR5_RDIMM_REV_RCD 0x0f3 613 614 #define SPD_DDR5_RDIMM_MFG_ID0_DB 0x0f4 615 #define SPD_DDR5_RDIMM_MFG_ID1_DB 0x0f5 616 #define SPD_DDR5_RDIMM_INFO_DB 0x0f6 617 #define SPD_DDR5_RDIMM_INFO_TYPE_DB01 0 618 #define SPD_DDR5_RDIMM_INFO_TYPE_DB02 1 619 #define SPD_DDR5_RDIMM_REV_DB 0x0f7 620 621 /* 622 * S14.3 RDIMM: RCD-RW08 Clock Driver Enable 623 */ 624 #define SPD_DDR5_RDIMM_CLKEN 0x0f8 625 #define SPD_DDR5_RDIMM_CLKEN_BCK(r) bitx8(r, 5, 5) 626 #define SPD_DDR5_RDIMM_CLKEN_QDCK(r) bitx8(r, 3, 3) 627 #define SPD_DDR5_RDIMM_CLKEN_QCCK(r) bitx8(r, 2, 2) 628 #define SPD_DDR5_RDIMM_CLKEN_QBCK(r) bitx8(r, 1, 1) 629 #define SPD_DDR5_RDIMM_CLKEN_QACK(r) bitx8(r, 0, 0) 630 631 /* 632 * S14.4 RDIMM: RCD-RW09 Output Address and Control Enable 633 */ 634 #define SPD_DDR5_RDIMM_RW09 0x0f9 635 #define SPD_DDR5_RDIMM_RW09_QBCS(r) bitx8(r, 6, 6) 636 #define SPD_DDR5_RDIMM_RW09_QACS(r) bitx8(r, 5, 5) 637 #define SPD_DDR5_RDIMM_RW09_QXCA13(r) bitx8(r, 4, 4) 638 #define SPD_DDR5_RDIMM_RW09_BCS(r) bitx8(r, 3, 3) 639 #define SPD_DDR5_RDIMM_RW09_DCS(r) bitx8(r, 2, 2) 640 #define SPD_DDR5_RDIMM_RW09_QBCA(r) bitx8(r, 1, 1) 641 #define SPD_DDR5_RDIMM_RW09_QACA(r) bitx8(r, 0, 0) 642 643 /* 644 * S14.5 RDIMM: RCD-RW0A QCK Driver Characteristics 645 * S14.7 RDIMM: RCD-RW0C QxCA and QxCS_n Driver Characteristics 646 * S14.8 LRDIMM: RCD-RW0D Data Buffer Interface Driver Characteristics 647 * 648 * RDIMM 1.0 phrased these in terms of resistance values; however, RDIMM 1.1 649 * changed them into relative terms used elsewhere like light, moderate, and 650 * strong. 651 */ 652 #define SPD_DDR5_RDIMM_QCK_DRV 0x0fa 653 #define SPD_DDR5_RDIMM_QCK_DRV_QDCK(r) bitx8(r, 7, 6) 654 #define SPD_DDR5_RDIMM_QCK_DRV_QCCK(r) bitx8(r, 5, 4) 655 #define SPD_DDR5_RDIMM_QCK_DRV_QBCK(r) bitx8(r, 3, 2) 656 #define SPD_DDR5_RDIMM_QCK_DRV_QACK(r) bitx8(r, 1, 0) 657 #define SPD_DDR5_RDIMM_DRV_LIGHT 0 658 #define SPD_DDR5_RDIMM_DRV_MODERATE 1 659 #define SPD_DDR5_RDIMM_DRV_STRONG 2 660 661 #define SPD_DDR5_RDIMM_QCA_DRV 0x0fc 662 #define SPD_DDR5_RDIMM_QCA_DRV_CS(r) bitx8(r, 5, 4) 663 #define SPD_DDR5_RDIMM_QCA_DRV_CA(r) bitx8(r, 1, 0) 664 665 #define SPD_DDR5_LRDIMM_DB_DRV 0x0fd 666 #define SPD_DDR5_LRDIMM_DB_DRV_BCK(r) bitx8(r, 4, 3) 667 #define SPD_DDR5_LRDIMM_DB_DRV_BCOM(r) bitx8(r, 1, 0) 668 669 /* 670 * S14.9 RDIMM: RCD-RW0E QCK, QCA, and QCS Output Slew Rate 671 * S14.10 LRDIMM: RCD-RW0F BCK, BCOM, and BCS Output Slew Rate 672 * 673 * These all use the same rough definitions for slew rates, i.e. slow, moderate, 674 * and fast; however, they all have different voltage ranges. 675 */ 676 #define SPD_DDR5_RDIMM_QXX_SLEW 0x0fe 677 #define SPD_DDR5_RDIMM_QXX_SLEW_QCS(r) bitx8(r, 5, 4) 678 #define SPD_DDR5_RDIMM_SLEW_MODERTE 0 679 #define SPD_DDR5_RDIMM_SLEW_FAST 1 680 #define SPD_DDR5_RDIMM_SLEW_SLOW 2 681 #define SPD_DDR5_RDIMM_QXX_SLEW_QCA(r) bitx8(r, 3, 2) 682 #define SPD_DDR5_RDIMM_QXX_SLEW_QCK(r) bitx8(r, 1, 0) 683 684 #define SPD_DDR5_LRDIMM_BXX_SLEW 0x0ff 685 #define SPD_DDR5_LRDIMM_BXX_SLEW_BCK(r) bitx8(r, 3, 2) 686 #define SPD_DDR5_LRDIMM_BXX_SLEW_BCOM(r) bitx8(r, 1, 0) 687 688 /* 689 * S14.11 DB-RW86 DQS RTT Park Termination 690 */ 691 #define SPD_DDR5_LRDIMM_PARK 0x100 692 #define SPD_DDR5_LRDIMM_PARK_TERM(r) bitx8(r, 2, 0) 693 #define SPD_DDR5_LDRIMM_PARK_OFF 0 694 #define SPD_DDR5_LDRIMM_PARK_240R 1 695 #define SPD_DDR5_LDRIMM_PARK_120R 2 696 #define SPD_DDR5_LDRIMM_PARK_80R 3 697 #define SPD_DDR5_LDRIMM_PARK_60R 4 698 #define SPD_DDR5_LDRIMM_PARK_48R 5 699 #define SPD_DDR5_LDRIMM_PARK_40R 6 700 #define SPD_DDR5_LDRIMM_PARK_34R 7 701 702 /* 703 * Annex A.4: Module Specific Bytes for Multiplexed Rank (MRDIMM) Memory Module 704 * Types. Revision 1.0 only defined the type information. Revision 1.1 added 705 * several additional bytes of data that start after the MDB information. 706 */ 707 #define SPD_DDR5_MRDIMM_MFG_ID0_MRCD 0x0f0 708 #define SPD_DDR5_MRDIMM_MFG_ID1_MRCD 0x0f1 709 #define SPD_DDR5_MRDIMM_INFO_MRCD 0x0f2 710 #define SPD_DDR5_MRDIMM_INFO_TYPE_MRCD01 0 711 #define SPD_DDR5_MRDIMM_INFO_TYPE_MRCD02 1 712 #define SPD_DDR5_MRDIMM_REV_MRCD 0x0f3 713 714 #define SPD_DDR5_MRDIMM_MFG_ID0_MDB 0x0f4 715 #define SPD_DDR5_MRDIMM_MFG_ID1_MDB 0x0f5 716 #define SPD_DDR5_MRDIMM_INFO_MDB 0x0f6 717 #define SPD_DDR5_MRDIMM_INFO_TYPE_MDB01 0 718 #define SPD_DDR5_MRDIMM_INFO_TYPE_MDB02 1 719 #define SPD_DDR5_MRDIMM_REV_MDB 0x0f7 720 721 /* 722 * S15.3 MRDIMM v1.1: MRCD-RW08 Clock Driver Enable 723 */ 724 #define SPD_DDR5_MRDIMM_CDEN 0x0f8 725 #define SPD_DDR5_MRDIMM_CDEN_BCK(r) bitx8(r, 5, 5) 726 #define SPD_DDR5_MRDIMM_CDEN_QDCK(r) bitx8(r, 3, 3) 727 #define SPD_DDR5_MRDIMM_CDEN_QCCK(r) bitx8(r, 2, 2) 728 #define SPD_DDR5_MRDIMM_CDEN_QBCK(r) bitx8(r, 1, 2) 729 #define SPD_DDR5_MRDIMM_CDEN_QACK(r) bitx8(r, 0, 0) 730 731 /* 732 * S15.3 MRDIMM v1.1: MRCD-RW09 Output Address and Control Enable 733 */ 734 #define SPD_DDR5_MRDIMM_OACEN 0x0f9 735 #define SPD_DDR5_MRDIMM_CDEN_DCS1(r) bitx8(r, 7, 7) 736 #define SPD_DDR5_MRDIMM_CDEN_QBCS(r) bitx8(r, 6, 6) 737 #define SPD_DDR5_MRDIMM_CDEN_QACS(r) bitx8(r, 5, 5) 738 #define SPD_DDR5_MRDIMM_CDEN_QCA13(r) bitx8(r, 4, 4) 739 #define SPD_DDR5_MRDIMM_CDEN_BCS(r) bitx8(r, 3, 3) 740 #define SPD_DDR5_MRDIMM_CDEN_QxCS1(r) bitx8(r, 2, 2) 741 #define SPD_DDR5_MRDIMM_CDEN_QBCA(r) bitx8(r, 1, 1) 742 #define SPD_DDR5_MRDIMM_CDEN_QACA(r) bitx8(r, 0, 0) 743 744 /* 745 * S15.4 MRDIMM v1.1: MRCD-RW0A QCK Driver Characteristics 746 * S15.6 MRDIMM v1.1: MRCD-RW0C QxCA and QxCS_n Driver Characteristics 747 * S15.7 MRDIMM v1.1: MRCD-RW0D Data Buffer Interface Driver Characteristics 748 * 749 * Similar to the RDIMM 1.1 version of these. These are all described in terms 750 * of relative rates. 751 */ 752 #define SPD_DDR5_MRDIMM_QCK_DRV 0x0fa 753 #define SPD_DDR5_MRDIMM_QCK_DRV_QDCK(r) bitx8(r, 7, 6) 754 #define SPD_DDR5_MRDIMM_QCK_DRV_QCCK(r) bitx8(r, 5, 4) 755 #define SPD_DDR5_MRDIMM_QCK_DRV_QBCK(r) bitx8(r, 3, 2) 756 #define SPD_DDR5_MRDIMM_QCK_DRV_QACK(r) bitx8(r, 1, 0) 757 #define SPD_DDR5_MRDIMM_DRV_LIGHT 0 758 #define SPD_DDR5_MRDIMM_DRV_MODERATE 1 759 #define SPD_DDR5_MRDIMM_DRV_STRONG 2 760 761 #define SPD_DDR5_MRDIMM_QCA_DRV 0x0fc 762 #define SPD_DDR5_MRDIMM_QCA_DRV_QCS1_OUT(r) bitx8(r, 7, 6) 763 #define SPD_DDR5_MRDIMM_QCA_DRV_QCS1_OUT_NORM 0 764 #define SPD_DDR5_MRDIMM_QCA_DRV_QCS1_OUT_DIS 1 765 #define SPD_DDR5_MRDIMM_QCA_DRV_QCS1_OUT_LOW 2 766 #define SPD_DDR5_MRDIMM_QCA_DRV_CS(r) bitx8(r, 5, 4) 767 #define SPD_DDR5_MRDIMM_QCA_DRV_CA(r) bitx8(r, 1, 0) 768 769 #define SPD_DDR5_MRDIMM_DB_DRV 0x0fd 770 #define SPD_DDR5_MRDIMM_DB_DRV_BCK(r) bitx8(r, 4, 3) 771 #define SPD_DDR5_MRDIMM_DB_DRV_BCOM(r) bitx8(r, 1, 0) 772 773 /* 774 * S15.8 MRDIMM v1.1: MRCD-RW0E QCK, QCA, and QCS Output Slew Rate 775 * S15.9 MRDIMM v1.1: MRCD-RW0F BCK, BCOM, and BCS Output Slew Rate 776 * 777 * Similar to the [LR]DIMM version. These use the same definitions for slew 778 * rates. 779 */ 780 #define SPD_DDR5_MRDIMM_QXX_SLEW 0x0fe 781 #define SPD_DDR5_MRDIMM_QXX_SLEW_QCS(r) bitx8(r, 5, 4) 782 #define SPD_DDR5_MRDIMM_SLEW_MODERTE 0 783 #define SPD_DDR5_MRDIMM_SLEW_FAST 1 784 #define SPD_DDR5_MRDIMM_SLEW_SLOW 2 785 #define SPD_DDR5_MRDIMM_QXX_SLEW_QCA(r) bitx8(r, 3, 2) 786 #define SPD_DDR5_MRDIMM_QXX_SLEW_QCK(r) bitx8(r, 1, 0) 787 788 #define SPD_DDR5_MRDIMM_BXX_SLEW 0x0ff 789 #define SPD_DDR5_MRDIMM_BXX_SLEW_BCK(r) bitx8(r, 3, 2) 790 #define SPD_DDR5_MRDIMM_BXX_SLEW_BCOM(r) bitx8(r, 1, 0) 791 792 /* 793 * S15.10 MRDIMM v1.1: MDB-PG[C]RWE0 Duty Cycle Adjuster Configuration 794 */ 795 #define SPD_DDR5_MRDIMM_DCA_CFG 0x100 796 #define SPD_DDR5_MRDIMM_DCA_CFG_CFG(r) bitx8(r, 0, 0) 797 798 /* 799 * S15.11 MRDIMM v1.1: MDB-PG[70]RWE1 DRAM Interface Receiver Type 800 */ 801 #define SPD_DDR5_MRDIMM_IRXTYPE 0x101 802 #define SPD_DDR5_MRDIMM_IRXTYPE_TYPE(r) bitx8(r, 0, 0) 803 #define SPD_DDR5_MRDIMM_IRXTYPE_TYPE_UNMATCHED 0 804 #define SPD_DDR5_MRDIMM_IRXTYPE_TYPE_MATCHED 1 805 806 /* 807 * Annex A.5: Module Specific Bytes for Differential Memory Module Types. Like 808 * UDIMMs and MRDIMMs, there is only a single section for Module Specific 809 * Device Information. 810 */ 811 #define SPD_DDR5_DDIMM_MFG_ID0_DMB 0x0f0 812 #define SPD_DDR5_DDIMM_MFG_ID1_DMB 0x0f1 813 #define SPD_DDR5_DDIMM_INFO_DMB 0x0f2 814 #define SPD_DDR5_DDIMM_INFO_TYPE_DMB501 0 815 #define SPD_DDR5_DDIMM_REV_DMB 0x0f3 816 817 /* 818 * Annex A.8: Module Specific Bytes for Compression Attached Memory Module Types 819 * (CAMM2). 820 */ 821 #define SPD_DDR5_CAMM2_MFG_ID0_CKD0 0x0f0 822 #define SPD_DDR5_CAMM2_MFG_ID1_CKD0 0x0f1 823 #define SPD_DDR5_CAMM2_INFO_CKD0 0x0f2 824 #define SPD_DDR5_CAMM2_INFO_TYPE_CKD01 0 825 #define SPD_DDR5_CAMM2_INFO_REV_CKD0 0x0f3 826 #define SPD_DDR5_CAMM2_MFG_ID0_CKD1 0x0f4 827 #define SPD_DDR5_CAMM2_MFG_ID1_CKD1 0x0f5 828 #define SPD_DDR5_CAMM2_INFO_CKD1 0x0f6 829 #define SPD_DDR5_CAMM2_INFO_REV_CKD1 0x0f7 830 831 /* 832 * S7.4 CRC. DDR5 modules have a single CRC calculation that covers bytes 0-509. 833 * Thus it covers everything prior to the manufacturing information. 834 */ 835 #define SPD_DDR5_CRC_LSB 0x1fe 836 #define SPD_DDR5_CRC_MSB 0x1ff 837 838 /* 839 * Manufacturing Information. 840 */ 841 842 /* 843 * S20.1 Module Manufacturer ID Code 844 * S20.7 DRAM Manufacturer ID Code 845 */ 846 #define SPD_DDR5_MOD_MFG_ID0 0x200 847 #define SPD_DDR5_MOD_MFG_ID1 0x201 848 #define SPD_DDR5_DRAM_MFG_ID0 0x228 849 #define SPD_DDR5_DRAM_MFG_ID1 0x229 850 851 /* 852 * S20.2 Module Manufacturing Location. This byte is manufacturer specific. 853 */ 854 #define SPD_DDR5_MOD_MFG_LOC 0x202 855 856 /* 857 * S20.3 module Manufacturing Date. Encoded as two BCD bytes for the year and 858 * week. 859 */ 860 #define SPD_DDR5_MOD_MFG_YEAR 0x203 861 #define SPD_DDR5_MOD_MFG_WEEK 0x204 862 863 /* 864 * S20.4 Module Serial Number. 865 * S20.5 Module Part Number 866 * S20.6 Module Revision Code 867 */ 868 #define SPD_DDR5_MOD_SN 0x205 869 #define SPD_DDR5_MOD_SN_LEN 4 870 #define SPD_DDR5_MOD_PN 0x209 871 #define SPD_DDR5_MOD_PN_LEN 30 872 #define SPD_DDR5_MOD_REV 0x227 873 874 /* 875 * S20.8 DRAM Stepping 876 */ 877 #define SPD_DDR5_DRAM_STEP 0x22a 878 879 /* 880 * Bytes 0x22b-0x27f are left for manufacturer specific data. 881 */ 882 883 #ifdef __cplusplus 884 } 885 #endif 886 887 #endif /* _SPD_DDR5_H */ 888