1*fe82ebb0SRobert Mustacchi /* 2*fe82ebb0SRobert Mustacchi * This file and its contents are supplied under the terms of the 3*fe82ebb0SRobert Mustacchi * Common Development and Distribution License ("CDDL"), version 1.0. 4*fe82ebb0SRobert Mustacchi * You may only use this file in accordance with the terms of version 5*fe82ebb0SRobert Mustacchi * 1.0 of the CDDL. 6*fe82ebb0SRobert Mustacchi * 7*fe82ebb0SRobert Mustacchi * A full copy of the text of the CDDL should have accompanied this 8*fe82ebb0SRobert Mustacchi * source. A copy of the CDDL is also available via the Internet at 9*fe82ebb0SRobert Mustacchi * http://www.illumos.org/license/CDDL. 10*fe82ebb0SRobert Mustacchi */ 11*fe82ebb0SRobert Mustacchi 12*fe82ebb0SRobert Mustacchi /* 13*fe82ebb0SRobert Mustacchi * Copyright 2023 Oxide Computer Company 14*fe82ebb0SRobert Mustacchi */ 15*fe82ebb0SRobert Mustacchi 16*fe82ebb0SRobert Mustacchi #ifndef _SPD_DDR5_H 17*fe82ebb0SRobert Mustacchi #define _SPD_DDR5_H 18*fe82ebb0SRobert Mustacchi 19*fe82ebb0SRobert Mustacchi /* 20*fe82ebb0SRobert Mustacchi * Definitions for use in DDR5 Serial Presence Detect decoding based on JEDEC 21*fe82ebb0SRobert Mustacchi * Standard JESD400-5a.01 DDR5 Serial Presence Detect (SPD) Contents. Release 22*fe82ebb0SRobert Mustacchi * 1.1. This does not cover LPDDR5. 23*fe82ebb0SRobert Mustacchi * 24*fe82ebb0SRobert Mustacchi * DDR5 modules are organized into a few main regions: 25*fe82ebb0SRobert Mustacchi * 26*fe82ebb0SRobert Mustacchi * o Base Configuration and DRAM parameters (0x00-0x7f) 27*fe82ebb0SRobert Mustacchi * o Common Module Parameters (0xc0-0xef) 28*fe82ebb0SRobert Mustacchi * o Standard Module Parameters (0xf0-0x1bf) which vary on whether something 29*fe82ebb0SRobert Mustacchi * is an RDIMM, UDIMM, etc. 30*fe82ebb0SRobert Mustacchi * o A CRC check for the first 510 bytes (0x1fe-0x1ff) 31*fe82ebb0SRobert Mustacchi * o Manufacturing Information (0x200-0x27f) 32*fe82ebb0SRobert Mustacchi * o Optional end-user programmable regions (0x280-0x3ff) 33*fe82ebb0SRobert Mustacchi * 34*fe82ebb0SRobert Mustacchi * This covers all DDR5 variants other than NVDIMMs. LPDDR5 is a different beast 35*fe82ebb0SRobert Mustacchi * entirely. 36*fe82ebb0SRobert Mustacchi */ 37*fe82ebb0SRobert Mustacchi 38*fe82ebb0SRobert Mustacchi #include <sys/bitext.h> 39*fe82ebb0SRobert Mustacchi #include "spd_common.h" 40*fe82ebb0SRobert Mustacchi 41*fe82ebb0SRobert Mustacchi #ifdef __cplusplus 42*fe82ebb0SRobert Mustacchi extern "C" { 43*fe82ebb0SRobert Mustacchi #endif 44*fe82ebb0SRobert Mustacchi 45*fe82ebb0SRobert Mustacchi /* 46*fe82ebb0SRobert Mustacchi * S8.1.1 Number of Bytes in SPD Device and Beta Level 47*fe82ebb0SRobert Mustacchi */ 48*fe82ebb0SRobert Mustacchi #define SPD_DDR5_NBYTES 0x000 49*fe82ebb0SRobert Mustacchi #define SPD_DDR5_NBYTES_BETAHI(r) bitx8(r, 7, 7) 50*fe82ebb0SRobert Mustacchi #define SPD_DDR5_NBYTES_TOTAL(r) bitx8(r, 6, 4) 51*fe82ebb0SRobert Mustacchi #define SPD_DDR5_NBYTES_TOTAL_UNDEF 0 52*fe82ebb0SRobert Mustacchi #define SPD_DDR5_NBYTES_TOTAL_256 1 53*fe82ebb0SRobert Mustacchi #define SPD_DDR5_NBYTES_TOTAL_512 2 54*fe82ebb0SRobert Mustacchi #define SPD_DDR5_NBYTES_TOTAL_1024 3 55*fe82ebb0SRobert Mustacchi #define SPD_DDR5_NBYTES_TOTAL_2048 4 56*fe82ebb0SRobert Mustacchi #define SPD_DDR5_NBYTES_BETA(r) bitx8(r, 3, 0) 57*fe82ebb0SRobert Mustacchi 58*fe82ebb0SRobert Mustacchi /* 59*fe82ebb0SRobert Mustacchi * S8.1.2 SPD Revision for Base Configuration Parameters. This is the same as 60*fe82ebb0SRobert Mustacchi * described in SPD_DDR4_SPD_REV as defined in spd_ddr4.h. 61*fe82ebb0SRobert Mustacchi */ 62*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SPD_REV 0x001 63*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SPD_REV_ENC(r) bitx8(r, 7, 4) 64*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SPD_REV_ADD(r) bitx8(r, 3, 0) 65*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SPD_REV_V1 1 66*fe82ebb0SRobert Mustacchi 67*fe82ebb0SRobert Mustacchi /* 68*fe82ebb0SRobert Mustacchi * S8.1.3: Key Byte / DRAM Device Type. This field identifies the type of DDR 69*fe82ebb0SRobert Mustacchi * device and is actually consistent across all SPD versions. Known values are 70*fe82ebb0SRobert Mustacchi * in the spd_dram_type_t enumeration. 71*fe82ebb0SRobert Mustacchi */ 72*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_TYPE 0x002 73*fe82ebb0SRobert Mustacchi 74*fe82ebb0SRobert Mustacchi /* 75*fe82ebb0SRobert Mustacchi * S8.1.4 Key Byte / Module Type 76*fe82ebb0SRobert Mustacchi */ 77*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE 0x003 78*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_ISHYBRID(r) bitx8(r, 7, 7) 79*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_HYBRID(r) bitx8(r, 6, 4) 80*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_HYBRID_NONE 0 81*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_HYBRID_NVDIMM_N 1 82*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_HYBRID_NVDIMM_P 2 83*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_TYPE(r) bitx8(r, 3, 0) 84*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_TYPE_RDIMM 1 85*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_TYPE_UDIMM 2 86*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_TYPE_SODIMM 3 87*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_TYPE_LRDIMM 4 88*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_TYPE_MRDIMM 7 89*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_TYPE_DDIMM 10 90*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_TYPE_TYPE_SOLDER 11 91*fe82ebb0SRobert Mustacchi 92*fe82ebb0SRobert Mustacchi /* 93*fe82ebb0SRobert Mustacchi * S8.1.5 First SDRAM Density and Package 94*fe82ebb0SRobert Mustacchi * S8.1.9 Second SDRAM Density and Package 95*fe82ebb0SRobert Mustacchi */ 96*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG1 0x004 97*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG2 0x008 98*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPP(r) bitx8(r, 7, 5) 99*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPP_MONO 0 100*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPP_DDP 1 101*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPP_2H3DS 2 102*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPP_4H3DS 3 103*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPP_8H3DS 4 104*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPP_16H3DS 5 105*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPD(r) bitx8(r, 4, 0) 106*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPD_4Gb 1 107*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPD_8Gb 2 108*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPD_12Gb 3 109*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPD_16Gb 4 110*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPD_24Gb 5 111*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPD_32Gb 6 112*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPD_48Gb 7 113*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DENPKG_DPD_64Gb 8 114*fe82ebb0SRobert Mustacchi 115*fe82ebb0SRobert Mustacchi /* 116*fe82ebb0SRobert Mustacchi * S8.1.6 First SDRAM Addressing 117*fe82ebb0SRobert Mustacchi * S8.1.10 Second SDRAM Addressing 118*fe82ebb0SRobert Mustacchi */ 119*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ADDR1 0x005 120*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ADDR2 0x009 121*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ADDR_NCOLS(r) bitx8(r, 7, 5) 122*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ADDR_NCOLS_BASE 10 123*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ADDR_NCOLS_MAX 11 124*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ADDR_NROWS(r) bitx8(r, 4, 0) 125*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ADDR_NROWS_BASE 16 126*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ADDR_NROWS_MAX 18 127*fe82ebb0SRobert Mustacchi 128*fe82ebb0SRobert Mustacchi /* 129*fe82ebb0SRobert Mustacchi * S8.1.7 First SDRAM I/O Width 130*fe82ebb0SRobert Mustacchi * S8.1.11 Second SDRAM I/O Width 131*fe82ebb0SRobert Mustacchi */ 132*fe82ebb0SRobert Mustacchi #define SPD_DDR5_WIDTH1 0x006 133*fe82ebb0SRobert Mustacchi #define SPD_DDR5_WIDTH2 0x00a 134*fe82ebb0SRobert Mustacchi #define SPD_DDR5_WIDTH_WIDTH(r) bitx8(r, 7, 5) 135*fe82ebb0SRobert Mustacchi #define SPD_DDR5_WIDTH_X4 0 136*fe82ebb0SRobert Mustacchi #define SPD_DDR5_WIDTH_X8 1 137*fe82ebb0SRobert Mustacchi #define SPD_DDR5_WIDTH_X16 2 138*fe82ebb0SRobert Mustacchi #define SPD_DDR5_WIDTH_X32 3 139*fe82ebb0SRobert Mustacchi 140*fe82ebb0SRobert Mustacchi /* 141*fe82ebb0SRobert Mustacchi * S8.1.8 First SDRAM Bank Groups and Banks per Bank Group 142*fe82ebb0SRobert Mustacchi * S8.1.8 Second SDRAM Bank Groups and Banks per Bank Group 143*fe82ebb0SRobert Mustacchi * 144*fe82ebb0SRobert Mustacchi * Both values here are in the number of bits that correspond to bank groups and 145*fe82ebb0SRobert Mustacchi * banks per group. In other words, the total number is 1 << value. 146*fe82ebb0SRobert Mustacchi */ 147*fe82ebb0SRobert Mustacchi #define SPD_DDR5_BANKS1 0x007 148*fe82ebb0SRobert Mustacchi #define SPD_DDR5_BANKS2 0x00b 149*fe82ebb0SRobert Mustacchi #define SPD_DDR5_BANKS_NBG(r) bitx8(r, 7, 5) 150*fe82ebb0SRobert Mustacchi #define SPD_DDR5_BANKS_NBG_MAX 8 151*fe82ebb0SRobert Mustacchi #define SPD_DDR5_BANKS_NBA(r) bitx8(r, 2, 0) 152*fe82ebb0SRobert Mustacchi #define SPD_DDR5_BANKS_NBA_MAX 4 153*fe82ebb0SRobert Mustacchi 154*fe82ebb0SRobert Mustacchi /* 155*fe82ebb0SRobert Mustacchi * S8.1.13 SDRAM BL32 and Post Package Repair 156*fe82ebb0SRobert Mustacchi */ 157*fe82ebb0SRobert Mustacchi #define SPD_DDR5_PPR 0x00c 158*fe82ebb0SRobert Mustacchi #define SPD_DDR5_PPR_GRAN(r) bitx8(r, 7, 7) 159*fe82ebb0SRobert Mustacchi #define SPD_DDR5_PPR_GRAN_BGRP 0 160*fe82ebb0SRobert Mustacchi #define SPD_DDR5_PPR_GRAN_BANK 1 161*fe82ebb0SRobert Mustacchi #define SPD_DDR5_PPR_LOCK_SUP(r) bitx8(r, 5, 5) 162*fe82ebb0SRobert Mustacchi #define SPD_DDR5_PPR_BL32_SUP(r) bitx8(r, 4, 4) 163*fe82ebb0SRobert Mustacchi #define SPD_DDR5_PPR_MPPR_SUP(r) bitx8(r, 1, 1) 164*fe82ebb0SRobert Mustacchi 165*fe82ebb0SRobert Mustacchi /* 166*fe82ebb0SRobert Mustacchi * S8.1.14 SDRAM Duty Cycle Adjustor and Partial Array Self Refresh 167*fe82ebb0SRobert Mustacchi */ 168*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SDA 0x00d 169*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SPD_DCA_PASR(r) bitx8(r, 4, 4) 170*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SPD_DCA_TYPE(r) bitx8(r, 1, 0) 171*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SPD_DCA_TYPE_UNSUP 0 172*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SPD_DCA_TYPE_1_2P 1 173*fe82ebb0SRobert Mustacchi #define SPD_DDR5_SPD_DCA_TYPE_4P 2 174*fe82ebb0SRobert Mustacchi 175*fe82ebb0SRobert Mustacchi /* 176*fe82ebb0SRobert Mustacchi * S8.1.15 SDRAM Fault Handling and Temperature Sense 177*fe82ebb0SRobert Mustacchi */ 178*fe82ebb0SRobert Mustacchi #define SPD_DDR5_FLT 0x00e 179*fe82ebb0SRobert Mustacchi #define SPD_DDR5_FLT_WIDE_TS(r) bitx8(r, 3, 3) 180*fe82ebb0SRobert Mustacchi #define SPD_DDR5_FLT_WBSUPR_SUP(r) bitx8(r, 2, 2) 181*fe82ebb0SRobert Mustacchi #define SPD_DDR5_FLT_WBSUPR_SEL(r) bitx8(r, 1, 1) 182*fe82ebb0SRobert Mustacchi #define SPD_DDR5_FLT_WBSUPR_SEL_MR9 0 183*fe82ebb0SRobert Mustacchi #define SPD_DDR5_FLT_WBSUPR_SEL_MR15 1 184*fe82ebb0SRobert Mustacchi #define SPD_DDR5_FLT_BFLT(r) bitx8(r, 0, 0) 185*fe82ebb0SRobert Mustacchi 186*fe82ebb0SRobert Mustacchi /* 187*fe82ebb0SRobert Mustacchi * S8.1.17 SDRAM Nominal Voltage, VDD 188*fe82ebb0SRobert Mustacchi * S8.1.18 SDRAM Nominal Voltage, VDDQ 189*fe82ebb0SRobert Mustacchi * S8.1.19 SDRAM Nominal Voltage, VDP 190*fe82ebb0SRobert Mustacchi * 191*fe82ebb0SRobert Mustacchi * These three share the same breakdown between nominal, operable, and endurant 192*fe82ebb0SRobert Mustacchi * voltages. However, the actual values that they support are different. 193*fe82ebb0SRobert Mustacchi */ 194*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_VDD 0x010 195*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_VDDQ 0x011 196*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_VPP 0x012 197*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_VOLT_NOM(r) bitx8(r, 7, 4) 198*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_VOLT_OPER(r) bitx8(r, 3, 2) 199*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_VOLT_END(r) bitx8(r, 1, 0) 200*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_VDD_V1P1 0 201*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_VDQ_V1P1 0 202*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_VPP_V1P8 0 203*fe82ebb0SRobert Mustacchi 204*fe82ebb0SRobert Mustacchi /* 205*fe82ebb0SRobert Mustacchi * S8.1.20 SDRAM Timing 206*fe82ebb0SRobert Mustacchi */ 207*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TIME 0x013 208*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TIME_STD(r) bitx8(r, 0, 0) 209*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TIME_STD_STD 0 210*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TIME_STD_NON 1 211*fe82ebb0SRobert Mustacchi 212*fe82ebb0SRobert Mustacchi /* 213*fe82ebb0SRobert Mustacchi * Timing based parameters. DDR5 uses two timebase values, either 1ps or 1ns. 214*fe82ebb0SRobert Mustacchi * This is different from DDR4 which had the MTB and FTB. For each parameter we 215*fe82ebb0SRobert Mustacchi * note whether it is in picoseconds or nanosecond units. 216*fe82ebb0SRobert Mustacchi */ 217*fe82ebb0SRobert Mustacchi 218*fe82ebb0SRobert Mustacchi /* 219*fe82ebb0SRobert Mustacchi * S8.4 SDRAM Minimum Cycle Time t~CKAVG~min (ps) 220*fe82ebb0SRobert Mustacchi * S8.5 SDRAM Maximum Cycle Time t~CKAVG~max (ps) 221*fe82ebb0SRobert Mustacchi */ 222*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCKAVG_MIN_LSB 0x014 223*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCKAVG_MIN_MSB 0x015 224*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCKAVG_MAX_LSB 0x016 225*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCKAVG_MAX_MSB 0x017 226*fe82ebb0SRobert Mustacchi 227*fe82ebb0SRobert Mustacchi /* 228*fe82ebb0SRobert Mustacchi * S8.6 CAS Latencies. These are 5 bytes which indicate which set o CAS 229*fe82ebb0SRobert Mustacchi * latencies are supported. The LSB of the SPD_DDR5_CAS_SUP0 corresponds to 230*fe82ebb0SRobert Mustacchi * CL20. Each subsequent bit is an additional 2 CL. So bit 4 is CL28. Byte 2 bit 231*fe82ebb0SRobert Mustacchi * 6 is CL64. 232*fe82ebb0SRobert Mustacchi */ 233*fe82ebb0SRobert Mustacchi #define SPD_DDR5_CAS_SUP0 0x018 234*fe82ebb0SRobert Mustacchi #define SPD_DDR5_CAS_SUP1 0x019 235*fe82ebb0SRobert Mustacchi #define SPD_DDR5_CAS_SUP2 0x01a 236*fe82ebb0SRobert Mustacchi #define SPD_DDR5_CAS_SUP3 0x01b 237*fe82ebb0SRobert Mustacchi #define SPD_DDR5_CAS_SUP4 0x01c 238*fe82ebb0SRobert Mustacchi 239*fe82ebb0SRobert Mustacchi /* 240*fe82ebb0SRobert Mustacchi * S8.7 SDRAM Read Command to First Data (t~AA~) (ps) 241*fe82ebb0SRobert Mustacchi * S8.8 SDRAM Activate to Read or Write Command Delay (t~RCD~) (ps) 242*fe82ebb0SRobert Mustacchi * S8.9 SDRAM Row Precharge Time (t~RP~) (ps) 243*fe82ebb0SRobert Mustacchi * S8.10 SDRAM Activate to Precharge Command Period (t~RAS~) (ps) 244*fe82ebb0SRobert Mustacchi * S8.11 SDRAM Activate to to Activate or Refresh Command Period (t~RC~) (ps) 245*fe82ebb0SRobert Mustacchi * S8.12 SDRAM Write Recovery Time (t~WR~) (ps) 246*fe82ebb0SRobert Mustacchi * S8.13 SDRAM Normal Refresh Recovery Time (t~RFC1,tRFC1_slr~) (ns) 247*fe82ebb0SRobert Mustacchi * S8.14 SDRAM Fine Granularity Refresh Recovery Time (t~RFC2,tRFC2_slr~) (ns) 248*fe82ebb0SRobert Mustacchi * S8.15 SDRAM Same Bank Refresh Recovery Time (t~RFCsb,tRFCsb_slr~) (ns) 249*fe82ebb0SRobert Mustacchi * S8.16 SDRAM Normal Refresh Recovery Time, 3DS Different Logical Rank 250*fe82ebb0SRobert Mustacchi * (t~RFC1_dlr~) (ns) 251*fe82ebb0SRobert Mustacchi * S8.17 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank 252*fe82ebb0SRobert Mustacchi * (t~RFC2_dlr~) (ns) 253*fe82ebb0SRobert Mustacchi * S8.18 SDRAM Fine Granularity Recovery Time, 3DS Different Logical Rank 254*fe82ebb0SRobert Mustacchi * (t~RFCsb_dlr~) (ns) 255*fe82ebb0SRobert Mustacchi */ 256*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TAA_LSB 0x01e 257*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TAA_MSB 0x01f 258*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRCD_LSB 0x020 259*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRCD_MSB 0x021 260*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRP_LSB 0x022 261*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRP_MSB 0x023 262*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRAS_LSB 0x024 263*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRAS_MSB 0x025 264*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRC_LSB 0x026 265*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRC_MSB 0x027 266*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TWR_LSB 0x028 267*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TWR_MSB 0x029 268*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRFC1_LSB 0x02a 269*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRFC1_MSB 0x02b 270*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRFC2_LSB 0x02c 271*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRFC2_MSB 0x02d 272*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRFCSB_LSB 0x02e 273*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRFCSB_MSB 0x02f 274*fe82ebb0SRobert Mustacchi #define SPD_DDR5_3DS_TRFC1_LSB 0x030 275*fe82ebb0SRobert Mustacchi #define SPD_DDR5_3DS_TRFC1_MSB 0x031 276*fe82ebb0SRobert Mustacchi #define SPD_DDR5_3DS_TRFC2_LSB 0x032 277*fe82ebb0SRobert Mustacchi #define SPD_DDR5_3DS_TRFC2_MSB 0x033 278*fe82ebb0SRobert Mustacchi #define SPD_DDR5_3DS_TRFCSB_LSB 0x034 279*fe82ebb0SRobert Mustacchi #define SPD_DDR5_3DS_TRFCSB_MSB 0x035 280*fe82ebb0SRobert Mustacchi 281*fe82ebb0SRobert Mustacchi /* 282*fe82ebb0SRobert Mustacchi * S8.19 SDRAM Refresh Management First SDRAM 283*fe82ebb0SRobert Mustacchi * S8.20 SDRAM Refresh Management Second SDRAM 284*fe82ebb0SRobert Mustacchi * 285*fe82ebb0SRobert Mustacchi * Refresh Management spans two bytes. 286*fe82ebb0SRobert Mustacchi */ 287*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_SDRAM0 0x036 288*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_SDRAM1 0x038 289*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAMMT_NORM(r) bitx8(r, 7, 5) 290*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAMMT_NORM_MIN 3 291*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAMMT_NORM_MAX 6 292*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAMMT_NORM_MULT 1 293*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAMMT_FGR(r) bitx8(r, 7, 5) 294*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAMMT_FGR_MIN 6 295*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAMMT_FGR_MAX 12 296*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAMMT_FGR_MULT 2 297*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAIMT_NORM(r) bitx8(r, 4, 1) 298*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAIMT_NORM_MIN 32 299*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAIMT_NORM_MAX 80 300*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAIMT_NORM_MULT 8 301*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAIMT_FGR(r) bitx8(r, 4, 1) 302*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAIMT_FGR_MIN 16 303*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAIMT_FGR_MAX 40 304*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RAAIMT_FGR_MULT 4 305*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM0_RFM_REQ(r) bitx8(r, 0, 0) 306*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_SDRAM0 0x037 307*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_SDRAM1 0x039 308*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_CTR(r) bitx8(r, 7, 6) 309*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_CTR_1X 0 310*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_CTR_2X 1 311*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_BRC_SUP(r)bitx8(r, 3, 3) 312*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_BRC_SUP_234 0 313*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_BRC_SUP_2 1 314*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_BRC_CFG(r) bitx8(r, 2, 1) 315*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_BRC_CFG_BASE 2 316*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_BRC_CFG_MAX 4 317*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RFM1_DRFM_SUP(r) bitx8(r, 0, 0) 318*fe82ebb0SRobert Mustacchi 319*fe82ebb0SRobert Mustacchi /* 320*fe82ebb0SRobert Mustacchi * S8.21 SDRAM Adaptive Refresh Management. This is broken down so that there 321*fe82ebb0SRobert Mustacchi * are three levels, A, B, and C. There are then two bytes per level. And there 322*fe82ebb0SRobert Mustacchi * is one entry for the first DRAM and one for the second. With the exception of 323*fe82ebb0SRobert Mustacchi * bit 0 of the low byte, which indicates whether or not this is supported, 324*fe82ebb0SRobert Mustacchi * these two byte ranges all match the prior two bytes. 325*fe82ebb0SRobert Mustacchi */ 326*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM0_A_SDRAM0 0x03a 327*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM1_A_SDRAM0 0x03b 328*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM0_A_SDRAM1 0x03c 329*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM1_A_SDRAM1 0x03d 330*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM0_B_SDRAM0 0x03e 331*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM1_B_SDRAM0 0x03f 332*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM0_B_SDRAM1 0x040 333*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM1_B_SDRAM1 0x041 334*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM0_C_SDRAM0 0x042 335*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM1_C_SDRAM0 0x043 336*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM0_C_SDRAM1 0x044 337*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM1_C_SDRAM1 0x045 338*fe82ebb0SRobert Mustacchi #define SPD_DDR5_ARFM_SUP(r) bitx8(r, 0, 0) 339*fe82ebb0SRobert Mustacchi 340*fe82ebb0SRobert Mustacchi /* 341*fe82ebb0SRobert Mustacchi * S8.22 SDRAM Activate to Activate Command Delay for Same Bank Group (t~RRD_L~) 342*fe82ebb0SRobert Mustacchi * S8.23 SDRAM Read to Read Command Delay for Same Bank Group (t~CDD_L~) 343*fe82ebb0SRobert Mustacchi * S8.24 SDRAM Write to Write Command Delay for Same Bank Group (t~CDD_L_WR~) 344*fe82ebb0SRobert Mustacchi * S8.25 SDRAM Write to Write Command Delay for Same Bank Group, Second Write 345*fe82ebb0SRobert Mustacchi * not RMW (t~CDD_L_WR2~) 346*fe82ebb0SRobert Mustacchi * S8.26 SDRAM Four Activate Window (t~FAW~) 347*fe82ebb0SRobert Mustacchi * S8.27 SDRAM Write to Read Command Delay for Same Bank Group (t~CCD_L_WTR~) 348*fe82ebb0SRobert Mustacchi * S8.28 SDRAM Write to Read Command Delay for Different Bank Group 349*fe82ebb0SRobert Mustacchi * (t~CCD_S_WTR~) 350*fe82ebb0SRobert Mustacchi * S8.29 SDRAM Read to Precharge Command Delay (t~RTP~,t~RTP_slr~) 351*fe82ebb0SRobert Mustacchi * 352*fe82ebb0SRobert Mustacchi * These timing registers all consist of three bytes. The first two bytes are 353*fe82ebb0SRobert Mustacchi * the LSB / MSB of the value in ps. The third bird defines the number of clock 354*fe82ebb0SRobert Mustacchi * cycles required. 355*fe82ebb0SRobert Mustacchi */ 356*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRRD_L_LSB 0x046 357*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRRD_L_MSB 0x047 358*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRRD_L_NCK 0x048 359*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_LSB 0x049 360*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_MSB 0x04a 361*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_NCK 0x04b 362*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_WR_LSB 0x04c 363*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_WR_MSB 0x04d 364*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_WR_NCK 0x04e 365*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_WR2_LSB 0x04f 366*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_WR2_MSB 0x050 367*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_WR2_NCK 0x051 368*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TFAW_LSB 0x052 369*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TFAW_MSB 0x053 370*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TFAW_NCK 0x054 371*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_WTR_LSB 0x055 372*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_WTR_MSB 0x056 373*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_L_WTR_NCK 0x057 374*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_S_WTR_LSB 0x058 375*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_S_WTR_MSB 0x059 376*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TCCD_S_WTR_NCK 0x05a 377*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRTP_LSB 0x05b 378*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRTP_MSB 0x05c 379*fe82ebb0SRobert Mustacchi #define SPD_DDR5_TRTP_NCK 0x05d 380*fe82ebb0SRobert Mustacchi 381*fe82ebb0SRobert Mustacchi /* 382*fe82ebb0SRobert Mustacchi * The remaining bytes in this section are currently reserved. Next, we begin 383*fe82ebb0SRobert Mustacchi * Annex A.0 which has common bytes that are shared between all module types. 384*fe82ebb0SRobert Mustacchi */ 385*fe82ebb0SRobert Mustacchi 386*fe82ebb0SRobert Mustacchi /* 387*fe82ebb0SRobert Mustacchi * S11.1 Common: SPD Revision for Module Information. This is the equivalent of 388*fe82ebb0SRobert Mustacchi * SPD_DDR5_SPD_REV, but covers all of the module-specific information, which 389*fe82ebb0SRobert Mustacchi * includes both the common area and type-specific areas. 390*fe82ebb0SRobert Mustacchi */ 391*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REV 0x0c0 392*fe82ebb0SRobert Mustacchi 393*fe82ebb0SRobert Mustacchi /* 394*fe82ebb0SRobert Mustacchi * S11.2 Common: Hashing Sequence. This defines a possible hashing sequence that 395*fe82ebb0SRobert Mustacchi * may be applied to a certificate related to device authentication per 396*fe82ebb0SRobert Mustacchi * JEDS316-5. 397*fe82ebb0SRobert Mustacchi */ 398*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_HASH 0x0c1 399*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_HASH_HASH(r) bitx8(r, 2, 0) 400*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_HASH_NONE 0 401*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_HASH_ALG1 1 402*fe82ebb0SRobert Mustacchi 403*fe82ebb0SRobert Mustacchi /* 404*fe82ebb0SRobert Mustacchi * S11.3 Common: Module Device Information. This contains a series of four 405*fe82ebb0SRobert Mustacchi * registers for each of five possible items: the SPD, three PMICs (power 406*fe82ebb0SRobert Mustacchi * management integrated circuit), and a temperature sensor. Before leveraging 407*fe82ebb0SRobert Mustacchi * the MFG ID, one must consult the Device Type register to see if it is 408*fe82ebb0SRobert Mustacchi * present. We start with generic definitions for each register type. Specifics 409*fe82ebb0SRobert Mustacchi * to a register such as type values will follow. The revision is a BCD revision 410*fe82ebb0SRobert Mustacchi * register. See DDR4 discussion. 411*fe82ebb0SRobert Mustacchi */ 412*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_PRES(r) bitx8(r, 7, 7) 413*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TYPE(r) bitx8(r, 3, 0) 414*fe82ebb0SRobert Mustacchi 415*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID0_SPD 0x0c2 416*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID1_SPD 0x0c3 417*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_SPD 0x0c4 418*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TYPE_SPD5118 0 419*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TYPE_ESPD5216 1 420*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REV_SPD 0x0c5 421*fe82ebb0SRobert Mustacchi 422*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID0_PMIC0 0x0c6 423*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID1_PMIC0 0x0c7 424*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_PMIC0 0x0c8 425*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TYPE_PMIC5000 0 426*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TYPE_PMIC5010 1 427*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TYPE_PMIC5100 2 428*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REV_PMIC0 0x0c9 429*fe82ebb0SRobert Mustacchi 430*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID0_PMIC1 0x0ca 431*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID1_PMIC1 0x0cb 432*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_PMIC1 0x0cc 433*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REV_PMIC1 0x0cd 434*fe82ebb0SRobert Mustacchi 435*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID0_PMIC2 0x0ce 436*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID1_PMIC2 0x0cf 437*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_PMIC2 0x0d0 438*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REV_PMIC2 0x0d1 439*fe82ebb0SRobert Mustacchi 440*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID0_TS 0x0d2 441*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_MFG_ID1_TS 0x0d3 442*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TS 0x0d4 443*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TS1_PRES(r) bitx8(r, 6, 6) 444*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TYPE_TS5111 0 445*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_INFO_TYPE_TS5110 1 446*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REV_TS 0x0d5 447*fe82ebb0SRobert Mustacchi 448*fe82ebb0SRobert Mustacchi /* 449*fe82ebb0SRobert Mustacchi * S11.5 Common: Module Nominal Height 450*fe82ebb0SRobert Mustacchi */ 451*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_HEIGHT 0x0e6 452*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_HEIGHT_MM(r) bitx8(r, 4, 0) 453*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_HEIGHT_BASE 15 454*fe82ebb0SRobert Mustacchi 455*fe82ebb0SRobert Mustacchi /* 456*fe82ebb0SRobert Mustacchi * S11.6 Common: Module Maximum Thickness 457*fe82ebb0SRobert Mustacchi */ 458*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_THICK 0x0e7 459*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_THICK_BACK(r) bitx8(r, 7, 4) 460*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_THICK_FRONT(r) bitx8(r, 3, 0) 461*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_THICK_BASE 1 462*fe82ebb0SRobert Mustacchi 463*fe82ebb0SRobert Mustacchi /* 464*fe82ebb0SRobert Mustacchi * S11.7 Common: Reference Raw Card Used 465*fe82ebb0SRobert Mustacchi */ 466*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REF 0x0e8 467*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REF_REV(r) bitx8(r, 7, 5) 468*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REF_REV_MAX 6 469*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_REF_CARD(r) bitx8(r, 4, 0) 470*fe82ebb0SRobert Mustacchi 471*fe82ebb0SRobert Mustacchi /* 472*fe82ebb0SRobert Mustacchi * S11.8 Common: DIMM Attributes 473*fe82ebb0SRobert Mustacchi */ 474*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR 0x0e9 475*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR(r) bitx8(r, 7, 4) 476*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR_A1T 0 477*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR_A2T 1 478*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR_A3T 2 479*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR_IT 3 480*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR_ST 4 481*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR_ET 5 482*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR_RT 6 483*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR_NT 7 484*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_OTR_XT 8 485*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_SPREAD(r) bitx8(r, 2, 2) 486*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_NROWS(r) bitx8(r, 1, 0) 487*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_NROWS_UNDEF 0 488*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_NROWS_1 1 489*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ATTR_NROWS_2 2 490*fe82ebb0SRobert Mustacchi 491*fe82ebb0SRobert Mustacchi /* 492*fe82ebb0SRobert Mustacchi * S11.9 Common: Module Organization 493*fe82ebb0SRobert Mustacchi */ 494*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ORG 0x0ea 495*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ORG_MIX(r) bitx8(r, 6, 6) 496*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ORG_MIX_SYM 0 497*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ORG_MIX_ASYM 1 498*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ORG_NRANK(r) bitx8(r, 5, 3) 499*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_ORG_NRANK_BASE 1 500*fe82ebb0SRobert Mustacchi 501*fe82ebb0SRobert Mustacchi /* 502*fe82ebb0SRobert Mustacchi * S11.10 Common: Memory Channel Bus Width. Unlike DDR4, these widths are in 503*fe82ebb0SRobert Mustacchi * terms of sub-channels. 504*fe82ebb0SRobert Mustacchi */ 505*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH 0x0eb 506*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_NSC(r) bitx8(r, 6, 5) 507*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_NSC_BASE 1 508*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_NSC_MAX 2 509*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_EXT(r) bitx8(r, 4, 3) 510*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_EXT_NONE 0 511*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_EXT_4b 1 512*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_EXT_8b 2 513*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_PRI(r) bitx8(r, 2, 0) 514*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_PRI_8b 0 515*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_PRI_16b 1 516*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_PRI_32b 2 517*fe82ebb0SRobert Mustacchi #define SPD_DDR5_COM_BUS_WIDTH_PRI_64b 3 518*fe82ebb0SRobert Mustacchi 519*fe82ebb0SRobert Mustacchi /* 520*fe82ebb0SRobert Mustacchi * After this point, all remaining bytes are reserved and Annex specific 521*fe82ebb0SRobert Mustacchi * information follows. Annex A.1 Module Specific Bytes for Solder Down is 522*fe82ebb0SRobert Mustacchi * skipped because there are no bytes defined. The revisions for these all 523*fe82ebb0SRobert Mustacchi * follow the common revision found at SPD_DDR5_COM_REV. 524*fe82ebb0SRobert Mustacchi */ 525*fe82ebb0SRobert Mustacchi 526*fe82ebb0SRobert Mustacchi /* 527*fe82ebb0SRobert Mustacchi * Annex A.2 Module Specific Bytes for Buffered Memory Module Types. S13.1 528*fe82ebb0SRobert Mustacchi * UDIMM: Module Specific Device Information. This follows the same pattern as 529*fe82ebb0SRobert Mustacchi * the other device specific manufacturing information with a series of four 530*fe82ebb0SRobert Mustacchi * bytes. See the discussion of S11.3. This is the only defined entry in this 531*fe82ebb0SRobert Mustacchi * annex right now. 532*fe82ebb0SRobert Mustacchi */ 533*fe82ebb0SRobert Mustacchi #define SPD_DDR5_UDIMM_MFG_ID0_CLK 0x0f0 534*fe82ebb0SRobert Mustacchi #define SPD_DDR5_UDIMM_MFG_ID1_CLK 0x0f1 535*fe82ebb0SRobert Mustacchi #define SPD_DDR5_UDIMM_INFO_CLK 0x0f2 536*fe82ebb0SRobert Mustacchi #define SPD_DDR5_UDIMM_INFO_TYPE_DDR5CK01 0 537*fe82ebb0SRobert Mustacchi #define SPD_DDR5_UDIMM_REV_CLK 0x0f3 538*fe82ebb0SRobert Mustacchi 539*fe82ebb0SRobert Mustacchi /* 540*fe82ebb0SRobert Mustacchi * Annex A.3: Module Specific Bytes for Registered (RDIMM) and Load Reduced 541*fe82ebb0SRobert Mustacchi * (LRDIMM) Memory Module Types. 542*fe82ebb0SRobert Mustacchi */ 543*fe82ebb0SRobert Mustacchi 544*fe82ebb0SRobert Mustacchi /* 545*fe82ebb0SRobert Mustacchi * S14.2 RDIMM: Module Specific Device Information. This covers the RCD and DB 546*fe82ebb0SRobert Mustacchi * components. Only LRDIMMs will have the DB present and it will be left as zero 547*fe82ebb0SRobert Mustacchi * for RDIMMs. 548*fe82ebb0SRobert Mustacchi */ 549*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_MFG_ID0_RCD 0x0f0 550*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_MFG_ID1_RCD 0x0f1 551*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_INFO_RCD 0x0f2 552*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_INFO_TYPE_RCD01 0 553*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_INFO_TYPE_RCD02 1 554*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_INFO_TYPE_RCD03 2 555*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_REV_RCD 0x0f3 556*fe82ebb0SRobert Mustacchi 557*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_MFG_ID0_DB 0x0f4 558*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_MFG_ID1_DB 0x0f5 559*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_INFO_DB 0x0f6 560*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_INFO_TYPE_DB01 0 561*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_INFO_TYPE_DB02 1 562*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_REV_DB 0x0f7 563*fe82ebb0SRobert Mustacchi 564*fe82ebb0SRobert Mustacchi /* 565*fe82ebb0SRobert Mustacchi * S14.3 RDIMM: RCD-RW08 Clock Driver Enable 566*fe82ebb0SRobert Mustacchi */ 567*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_CLKEN 0x0f8 568*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_CLKEN_BCK(r) bitx8(r, 5, 5) 569*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_CLKEN_QDCK(r) bitx8(r, 3, 3) 570*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_CLKEN_QCCK(r) bitx8(r, 2, 2) 571*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_CLKEN_QBCK(r) bitx8(r, 1, 1) 572*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_CLKEN_QACK(r) bitx8(r, 0, 0) 573*fe82ebb0SRobert Mustacchi 574*fe82ebb0SRobert Mustacchi /* 575*fe82ebb0SRobert Mustacchi * S14.4 RDIMM: RCD-RW09 Output Address and Control Enable 576*fe82ebb0SRobert Mustacchi */ 577*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_RW09 0x0f9 578*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_RW09_QBCS(r) bitx8(r, 6, 6) 579*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_RW09_QACS(r) bitx8(r, 5, 5) 580*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_RW09_QXCA13(r) bitx8(r, 4, 4) 581*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_RW09_BCS(r) bitx8(r, 3, 3) 582*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_RW09_DCS(r) bitx8(r, 2, 2) 583*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_RW09_QBCA(r) bitx8(r, 1, 1) 584*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_RW09_QACA(r) bitx8(r, 0, 0) 585*fe82ebb0SRobert Mustacchi 586*fe82ebb0SRobert Mustacchi /* 587*fe82ebb0SRobert Mustacchi * S14.5 RDIMM: RCD-RW0A QCK Driver Characteristics 588*fe82ebb0SRobert Mustacchi * S14.7 RDIMM: RCD-RW0C QxCA and QxCS_n Driver Characteristics 589*fe82ebb0SRobert Mustacchi * S14.8 LRDIMM: RCD-RW0D Data Buffer Interface Driver Characteristics 590*fe82ebb0SRobert Mustacchi * 591*fe82ebb0SRobert Mustacchi * These share the same definitions for resistance values. One minor exception 592*fe82ebb0SRobert Mustacchi * is that the LRDIMM BCOM does not support a 10R value. 593*fe82ebb0SRobert Mustacchi */ 594*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QCK_DRV 0x0fa 595*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QCK_DRV_QDCK(r) bitx8(r, 7, 6) 596*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QCK_DRV_QCCK(r) bitx8(r, 5, 4) 597*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QCK_DRV_QBCK(r) bitx8(r, 3, 2) 598*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QCK_DRV_QACK(r) bitx8(r, 1, 0) 599*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_DRV_20R 0 600*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_DRV_14R 1 601*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_DRV_10R 2 602*fe82ebb0SRobert Mustacchi 603*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QCA_DRV 0x0fc 604*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QCA_DRV_CS(r) bitx8(r, 5, 4) 605*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QCA_DRV_CA(r) bitx8(r, 1, 0) 606*fe82ebb0SRobert Mustacchi 607*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LRDIMM_DB_DRV 0x0fd 608*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LRDIMM_DB_DRV_BCK(r) bitx8(r, 4, 3) 609*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LRDIMM_DB_DRV_BCOM(r) bitx8(r, 1, 0) 610*fe82ebb0SRobert Mustacchi 611*fe82ebb0SRobert Mustacchi /* 612*fe82ebb0SRobert Mustacchi * S14.9 RDIMM: RCD-RW0E QCK, QCA, and QCS Output Slew Rate 613*fe82ebb0SRobert Mustacchi * S14.10 LRDIMM: RCD-RW0F BCK, BCOM, and BCS Output Slew Rate 614*fe82ebb0SRobert Mustacchi * 615*fe82ebb0SRobert Mustacchi * These all use the same rough definitions for slew rates, i.e. slow, moderate, 616*fe82ebb0SRobert Mustacchi * and fast; however, they all have different voltage ranges. 617*fe82ebb0SRobert Mustacchi */ 618*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QXX_SLEW 0x0fe 619*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QXX_SLEW_QCS(r) bitx8(r, 5, 4) 620*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_SLEW_MODERTE 0 621*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_SLEW_FAST 1 622*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_SLEW_SLOW 2 623*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QXX_SLEW_QCA(r) bitx8(r, 3, 2) 624*fe82ebb0SRobert Mustacchi #define SPD_DDR5_RDIMM_QXX_SLEW_QCK(r) bitx8(r, 1, 0) 625*fe82ebb0SRobert Mustacchi 626*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LRDIMM_BXX_SLEW 0x0ff 627*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LRDIMM_BXX_SLEW_BCK(r) bitx8(r, 3, 2) 628*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LRDIMM_BXX_SLEW_BCOM(r) bitx8(r, 1, 0) 629*fe82ebb0SRobert Mustacchi 630*fe82ebb0SRobert Mustacchi /* 631*fe82ebb0SRobert Mustacchi * S14.11 DB-RW86 DQS RTT Park Termination 632*fe82ebb0SRobert Mustacchi */ 633*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LRDIMM_PARK 0x100 634*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LRDIMM_PARK_TERM(r) bitx8(r, 2, 0) 635*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LDRIMM_PARK_OFF 0 636*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LDRIMM_PARK_240R 1 637*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LDRIMM_PARK_120R 2 638*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LDRIMM_PARK_80R 3 639*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LDRIMM_PARK_60R 4 640*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LDRIMM_PARK_48R 5 641*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LDRIMM_PARK_40R 6 642*fe82ebb0SRobert Mustacchi #define SPD_DDR5_LDRIMM_PARK_34R 7 643*fe82ebb0SRobert Mustacchi 644*fe82ebb0SRobert Mustacchi /* 645*fe82ebb0SRobert Mustacchi * Annex A.4: Module Specific Bytes for Multiplexed Rank (MRDIMM) Memory Module 646*fe82ebb0SRobert Mustacchi * Types. This only contains a single entry for S15.2 Module Specific Device 647*fe82ebb0SRobert Mustacchi * Information. 648*fe82ebb0SRobert Mustacchi */ 649*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_MFG_ID0_MRCD 0x0f0 650*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_MFG_ID1_MRCD 0x0f1 651*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_INFO_MRCD 0x0f2 652*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_INFO_TYPE_MRCD01 0 653*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_REV_MRCD 0x0f3 654*fe82ebb0SRobert Mustacchi 655*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_MFG_ID0_MDB 0x0f4 656*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_MFG_ID1_MDB 0x0f5 657*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_INFO_MDB 0x0f6 658*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_INFO_TYPE_MDB01 0 659*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MRDIMM_REV_MDB 0x0f7 660*fe82ebb0SRobert Mustacchi 661*fe82ebb0SRobert Mustacchi /* 662*fe82ebb0SRobert Mustacchi * Annex A.5: Module Specific Bytes for Differential Memory Module Types. Like 663*fe82ebb0SRobert Mustacchi * UDIMMs and MRDIMMs, there is only a single section S16.2 for Module Specific 664*fe82ebb0SRobert Mustacchi * Device Information. 665*fe82ebb0SRobert Mustacchi */ 666*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DDIMM_MFG_ID0_DMB 0x0f0 667*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DDIMM_MFG_ID1_DMB 0x0f1 668*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DDIMM_INFO_DMB 0x0f2 669*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DDIMM_INFO_TYPE_DMB501 0 670*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DDIMM_REV_DMB 0x0f3 671*fe82ebb0SRobert Mustacchi 672*fe82ebb0SRobert Mustacchi /* 673*fe82ebb0SRobert Mustacchi * S7.4 CRC. DDR5 modules have a single CRC calculation that covers bytes 0-509. 674*fe82ebb0SRobert Mustacchi * Thus it covers everything prior to the manufacturing information. 675*fe82ebb0SRobert Mustacchi */ 676*fe82ebb0SRobert Mustacchi #define SPD_DDR5_CRC_LSB 0x1fe 677*fe82ebb0SRobert Mustacchi #define SPD_DDR5_CRC_MSB 0x1ff 678*fe82ebb0SRobert Mustacchi 679*fe82ebb0SRobert Mustacchi /* 680*fe82ebb0SRobert Mustacchi * Manufacturing Information. 681*fe82ebb0SRobert Mustacchi */ 682*fe82ebb0SRobert Mustacchi 683*fe82ebb0SRobert Mustacchi /* 684*fe82ebb0SRobert Mustacchi * S19.1 Module Manufacturer ID Code 685*fe82ebb0SRobert Mustacchi * S19.7 DRAM Manufacturer ID Code 686*fe82ebb0SRobert Mustacchi */ 687*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_MFG_ID0 0x200 688*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_MFG_ID1 0x201 689*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_MFG_ID0 0x228 690*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_MFG_ID1 0x229 691*fe82ebb0SRobert Mustacchi 692*fe82ebb0SRobert Mustacchi /* 693*fe82ebb0SRobert Mustacchi * S19.2 Module Manufacturing Location. This byte is manufacturer specific. 694*fe82ebb0SRobert Mustacchi */ 695*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_MFG_LOC 0x202 696*fe82ebb0SRobert Mustacchi 697*fe82ebb0SRobert Mustacchi /* 698*fe82ebb0SRobert Mustacchi * S19.3 module Manufacturing Date. Encoded as two BCD bytes for the year and 699*fe82ebb0SRobert Mustacchi * week. 700*fe82ebb0SRobert Mustacchi */ 701*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_MFG_YEAR 0x203 702*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_MFG_WEEK 0x204 703*fe82ebb0SRobert Mustacchi 704*fe82ebb0SRobert Mustacchi /* 705*fe82ebb0SRobert Mustacchi * S19.4 Module Serial Number. 706*fe82ebb0SRobert Mustacchi * S19.5 Module Part Number 707*fe82ebb0SRobert Mustacchi * S19.6 Module Revision Code 708*fe82ebb0SRobert Mustacchi */ 709*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_SN 0x205 710*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_SN_LEN 4 711*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_PN 0x209 712*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_PN_LEN 30 713*fe82ebb0SRobert Mustacchi #define SPD_DDR5_MOD_REV 0x227 714*fe82ebb0SRobert Mustacchi 715*fe82ebb0SRobert Mustacchi /* 716*fe82ebb0SRobert Mustacchi * S19.8 DRAM Stepping 717*fe82ebb0SRobert Mustacchi */ 718*fe82ebb0SRobert Mustacchi #define SPD_DDR5_DRAM_STEP 0x22a 719*fe82ebb0SRobert Mustacchi 720*fe82ebb0SRobert Mustacchi /* 721*fe82ebb0SRobert Mustacchi * Bytes 0x22b-0x27f are left for manufacturer specific data. 722*fe82ebb0SRobert Mustacchi */ 723*fe82ebb0SRobert Mustacchi 724*fe82ebb0SRobert Mustacchi #ifdef __cplusplus 725*fe82ebb0SRobert Mustacchi } 726*fe82ebb0SRobert Mustacchi #endif 727*fe82ebb0SRobert Mustacchi 728*fe82ebb0SRobert Mustacchi #endif /* _SPD_DDR5_H */ 729