xref: /illumos-gate/usr/src/lib/libjedec/common/spd_ddr4.h (revision 8119dad84d6416f13557b0ba8e2aaf9064cbcfd3)
1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source.  A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * Copyright 2024 Oxide Computer Company
14  */
15 
16 #ifndef _SPD_DDR4_H
17 #define	_SPD_DDR4_H
18 
19 /*
20  * Definitions for use in DDR4 Serial Presence Detect decoding based on JEDEC
21  * Standard 21-C Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules
22  * Release 6.
23  *
24  * DDR4 modules are organized into a few main regions:
25  *
26  *   o Base Configuration and DRAM parameters (bytes 0x00-0x7f)
27  *   o Standard Module Parameters (bytes 0x80-0xbf) these vary on whether
28  *     something is considered an RDIMM, UDIMM, LRDIMM, etc.
29  *   o Hybrid Module Parameters (bytes 0xc0-0xff)
30  *   o Hybrid Module Extended Parameters (bytes 0x100-0x13f).
31  *   o Manufacturing Information (bytes 0x140-0x17f)
32  *   o End User Programmable data (0x180-0x1ff).
33  *
34  * This does not currently provide definitions for DDR4 NVDIMMs.
35  */
36 
37 #include <sys/bitext.h>
38 #include "spd_common.h"
39 
40 #ifdef __cplusplus
41 extern "C" {
42 #endif
43 
44 /*
45  * S8.1.1 Number of Bytes Used / Number of Bytes in SPD Device.
46  */
47 #define	SPD_DDR4_NBYTES	0x000
48 #define	SPD_DDR4_NBYTES_TOTAL(r)	bitx8(r, 6, 4)
49 #define	SPD_DDR4_NBYTES_TOTAL_UNDEF	0
50 #define	SPD_DDR4_NBYTES_TOTAL_256	1
51 #define	SPD_DDR4_NBYTES_TOTAL_512	2
52 #define	SPD_DDR4_NBYTES_USED(r)		bitx8(r, 3, 0)
53 #define	SPD_DDR4_NBYTES_USED_UNDEF	0
54 #define	SPD_DDR4_NBYTES_USED_128	1
55 #define	SPD_DDR4_NBYTES_USED_256	2
56 #define	SPD_DDR4_NBYTES_USED_384	3
57 #define	SPD_DDR4_NBYTES_USED_512	4
58 
59 /*
60  * S8.1.2: SPD Revision. The SPD revision is split into two 4-bit fields. There
61  * is an encoding level and an additions level. This can be somewhat thought of
62  * like a major and minor version. The upper 4-bit encoding level tells us
63  * whether or not we can parse it. The additions level just says what's been
64  * added, but it doesn't reset across major versions.
65  *
66  * Currently all DDR4 devices are at encoding revision 1. The additions level
67  * varies based on the type of DDR4 device (RDIMM, UDIMM, etc.).
68  */
69 #define	SPD_DDR4_SPD_REV	0x001
70 #define	SPD_DDR4_SPD_REV_ENC(r)	bitx8(r, 7, 4)
71 #define	SPD_DDR4_SPD_REV_ADD(r)	bitx8(r, 3, 0)
72 #define	SPD_DDR4_SPD_REV_V1	1
73 
74 /*
75  * S8.1.3: Key Byte / DRAM Device Type. This field identifies the type of DDR
76  * device and is actually consistent across all SPD versions. Known values are
77  * in the spd_dram_type_t enumeration.
78  */
79 #define	SPD_DDR4_DRAM_TYPE	0x002
80 
81 /*
82  * S8.1.4: Key Byte / Module type. This is used to describe what kind of DDR
83  * module it is, which tell us what the module-specific section contents are.
84  * These bits, unlike the one above are device specific.
85  */
86 #define	SPD_DDR4_MOD_TYPE	0x003
87 #define	SPD_DDR4_MOD_TYPE_ISHYBRID(r)	bitx8(r, 7, 7)
88 #define	SPD_DDR4_MOD_TYPE_HYBRID(r)	bitx8(r, 6, 4)
89 #define	SPD_DDR4_MOD_TYPE_HYBRID_NONE		0
90 #define	SPD_DDR4_MOD_TYPE_HYBRID_NVDIMM_NF	1
91 #define	SPD_DDR4_MOD_TYPE_HYBRID_NVDIMM_P	2
92 #define	SPD_DDR4_MOD_TYPE_HYBRID_NVDIMM_H	3
93 #define	SPD_DDR4_MOD_TYPE_TYPE(r)	bitx8(r, 3, 0)
94 #define	SPD_DDR4_MOD_TYPE_TYPE_EXT		0
95 #define	SPD_DDR4_MOD_TYPE_TYPE_RDIMM		1
96 #define	SPD_DDR4_MOD_TYPE_TYPE_UDIMM		2
97 #define	SPD_DDR4_MOD_TYPE_TYPE_SODIMM		3
98 #define	SPD_DDR4_MOD_TYPE_TYPE_LRDIMM		4
99 #define	SPD_DDR4_MOD_TYPE_TYPE_MINI_RDIMM	5
100 #define	SPD_DDR4_MOD_TYPE_TYPE_MINI_UDIMM	6
101 #define	SPD_DDR4_MOD_TYPE_TYPE_72b_SORDIMM	8
102 #define	SPD_DDR4_MOD_TYPE_TYPE_72b_SOUDIMM	9
103 #define	SPD_DDR4_MOD_TYPE_TYPE_16b_SODIMM	12
104 #define	SPD_DDR4_MOD_TYPE_TYPE_32b_SODIMM	13
105 
106 /*
107  * S8.1.5 SDRAM Density and Banks.
108  */
109 #define	SPD_DDR4_DENSITY	0x004
110 #define	SPD_DDR4_DENSITY_NBG_BITS(r)	bitx8(r, 7, 6)
111 #define	SPD_DDR4_DENSITY_NBG_BITS_MAX	2
112 #define	SPD_DDR4_DENSITY_NBA_BITS(r)	bitx8(r, 5, 4)
113 #define	SPD_DDR4_DENSITY_NBA_BITS_BASE	2
114 #define	SPD_DDR4_DENSITY_NBA_BITS_MAX	3
115 #define	SPD_DDR4_DENSITY_DENSITY(r)	bitx8(r, 3, 0)
116 #define	SPD_DDR4_DENSITY_DENSITY_256Mb	0
117 #define	SPD_DDR4_DENSITY_DENSITY_512Mb	1
118 #define	SPD_DDR4_DENSITY_DENSITY_1Gb	2
119 #define	SPD_DDR4_DENSITY_DENSITY_2Gb	3
120 #define	SPD_DDR4_DENSITY_DENSITY_4Gb	4
121 #define	SPD_DDR4_DENSITY_DENSITY_8Gb	5
122 #define	SPD_DDR4_DENSITY_DENSITY_16Gb	6
123 #define	SPD_DDR4_DENSITY_DENSITY_32Gb	7
124 #define	SPD_DDR4_DENSITY_DENSITY_12Gb	8
125 #define	SPD_DDR4_DENSITY_DENSITY_24Gb	9
126 
127 /*
128  * S8.1.6 SDRAM Addressing.
129  */
130 #define	SPD_DDR4_ADDR	0x005
131 #define	SPD_DDR4_ADDR_NROWS(r)	bitx8(r, 5, 3)
132 #define	SPD_DDR4_ADDR_NROWS_BASE	12
133 #define	SPD_DDR4_ADDR_NROWS_MAX		18
134 #define	SPD_DDR4_ADDR_NCOLS(r)	bitx8(r, 2, 0)
135 #define	SPD_DDR4_ADDR_NCOLS_BASE	9
136 #define	SPD_DDR4_ADDR_NCOLS_MAX		12
137 
138 /*
139  * S8.1.7 Primary SDRAM Package Type
140  * S8.1.11 Secondary SDRAM Package Type
141  *
142  * This contains information about the package types that are present. The
143  * secondary is only used when asymmetrical SDRAM types are present. These are
144  * generally the same bits and meanings, with the one exception that the bits
145  * 3:2 must be 0 in the primary. As such, we try to reuse definitions. In the
146  * ratio macros, the 1S and 2S refer to the fact that they are 1 and 2 module
147  * densities smaller.
148  */
149 #define	SPD_DDR4_PRI_PKG	0x006
150 #define	SPD_DDR4_SEC_PKG	0x00a
151 #define	SPD_DDR4_PKG_TYPE(r)	bitx8(r, 7, 7)
152 #define	SPD_DDR4_PKG_TYPE_MONO	0
153 #define	SPD_DDR4_PKG_TYPE_NOT	1
154 #define	SPD_DDR4_PKG_DIE_CNT(r)	bitx8(r, 6, 4)
155 #define	SPD_DDR4_PKG_DIE_CNT_BASE	1
156 #define	SPD_DDR4_SEC_PKG_RATIO(r)	bitx8(r, 3, 2)
157 #define	SPD_DDR4_SEC_PKG_RATIO_EQ	0
158 #define	SPD_DDR4_SEC_PKG_RATIO_1S	1
159 #define	SPD_DDR4_SEC_PKG_RATIO_2S	2
160 #define	SPD_DDR4_PKG_SIG_LOAD(r)	bitx8(r, 1, 0)
161 #define	SPD_DDR4_PKG_SIG_LOAD_UNSPEC	0
162 #define	SPD_DDR4_PKG_SIG_LOAD_MULTI	1
163 #define	SPD_DDR4_PKG_SIG_LOAD_SINGLE	2
164 
165 /*
166  * S8.1.8 SDRAM Optional Features.
167  */
168 #define	SPD_DDR4_OPT_FEAT	0x007
169 #define	SPD_DDR4_OPT_FEAT_MAW(r)	bitx8(r, 5, 4)
170 #define	SPD_DDR4_OPT_FEAT_MAW_8192X	0
171 #define	SPD_DDR4_OPT_FEAT_MAW_4096X	1
172 #define	SPD_DDR4_OPT_FEAT_MAW_2048X	2
173 #define	SPD_DDR4_OPT_FEAT_MAC(r)	bitx8(r, 3, 0)
174 #define	SPD_DDR4_OPT_FEAT_MAC_UNTESTED	0
175 #define	SPD_DDR4_OPT_FEAT_MAC_700K	1
176 #define	SPD_DDR4_OPT_FEAT_MAC_600K	2
177 #define	SPD_DDR4_OPT_FEAT_MAC_500K	3
178 #define	SPD_DDR4_OPT_FEAT_MAC_400K	4
179 #define	SPD_DDR4_OPT_FEAT_MAC_300K	5
180 #define	SPD_DDR4_OPT_FEAT_MAC_200K	6
181 #define	SPD_DDR4_OPT_FEAT_MAC_UNLIMITED	8
182 
183 /*
184  * S8.1.9 SDRAM Thermal and Refresh Options. This in theory is supposed to have
185  * additional information from a data sheet; however, this field is noted as
186  * reserved as zero. Therefore we entirely ignore this byte.
187  */
188 
189 /*
190  * S8.1.10 Other SDRAM Optional Features. These are even more that aren't in the
191  * first set of optional features.
192  */
193 #define	SPD_DDR4_OPT_FEAT2	0x009
194 #define	SPD_DDR4_OPT_FEAT2_PPR(r)	bitx8(r, 7, 6)
195 #define	SPD_DDR4_OPT_FEAT2_PPR_NOTSUP	0
196 #define	SPD_DDR4_OPT_FEAT2_PPR_1RPBG	1
197 #define	SPD_DDR4_OPT_FEAT2_SOFT_PPR(r)	bitx8(r, 5, 5)
198 #define	SPD_DDR4_OPT_FEAT2_MBIST_PPR(r)	bitx8(r, 4, 4)
199 
200 /*
201  * S8.1.12 Module Nominal Voltage, VDD.
202  */
203 #define	SPD_DDR4_VOLT	0x00b
204 #define	SPD_DDR4_VOLT_V1P2_ENDUR(r)	bitx8(r, 1, 1)
205 #define	SPD_DDR4_VOLT_V1P2_OPER(r)	bitx8(r, 0, 0)
206 
207 /*
208  * S8.1.13 Module Organization
209  */
210 #define	SPD_DDR4_MOD_ORG	0x00c
211 #define	SPD_DDR4_MOD_ORG_RANK_MIX(r)	bitx8(r, 6, 6)
212 #define	SPD_DDR4_MOD_ORG_RANK_MIX_SYM	0
213 #define	SPD_DDR4_MOD_ORG_RANK_MIX_ASYM	1
214 #define	SPD_DDR4_MOD_ORG_NPKG_RANK(r)	bitx8(r, 5, 3)
215 #define	SPD_DDR4_MOD_ORG_NPKG_RANK_BASE	1
216 #define	SPD_DDR4_MOD_ORG_WIDTH(r)	bitx8(r, 2, 0)
217 #define	SPD_DDR4_MOD_ORG_WIDTH_4b	0
218 #define	SPD_DDR4_MOD_ORG_WIDTH_8b	1
219 #define	SPD_DDR4_MOD_ORG_WIDTH_16b	2
220 #define	SPD_DDR4_MOD_ORG_WIDTH_32b	3
221 
222 /*
223  * S8.1.14 Module Memory Bus Width. The extensions here are generally used for
224  * ECC.
225  */
226 #define	SPD_DDR4_MOD_BUS_WIDTH	0x00d
227 #define	SPD_DDR4_MOD_BUS_WIDTH_EXT(r)	bitx8(r, 4, 3)
228 #define	SPD_DDR4_MOD_BUS_WIDTH_EXT_NONE	0
229 #define	SPD_DDR4_MOD_BUS_WIDTH_EXT_8b	1
230 #define	SPD_DDR4_MOD_BUS_WIDTH_PRI(r)	bitx8(r, 2, 0)
231 #define	SPD_DDR4_MOD_BUS_WIDTH_PRI_8b	0
232 #define	SPD_DDR4_MOD_BUS_WIDTH_PRI_16b	1
233 #define	SPD_DDR4_MOD_BUS_WIDTH_PRI_32b	2
234 #define	SPD_DDR4_MOD_BUS_WIDTH_PRI_64b	3
235 
236 /*
237  * S8.1.15 Module Thermal Sensor.
238  */
239 #define	SPD_DDR4_MOD_THERM	0x00e
240 #define	SPD_DDR4_MOD_THERM_PRES(r)	bitx8(r, 7, 7)
241 
242 /*
243  * S8.1.16 Extended Module Type. This contains a 4-bit extended module type;
244  * however, none are defined for DDR4. We do not bother with a definition for
245  * it. S8.1.17 Byte 16 is just reserved as must be zero.
246  */
247 
248 /*
249  * S8.1.18 Timebases. These values are used throughout all other calculations to
250  * describe various values that are present throughout many of the subsequent
251  * bytes. There are two defined entities: the Median Time Base (MTB) and the
252  * Fine Time Base (FTB). There is only one MTB and FTB defined for DDR4. These
253  * are 125ps and 1ps respectively.
254  *
255  * Many of the timing values are split into two registers. One which contains a
256  * value in MTB and one which has an adjustment in FTB. This is used when there
257  * would otherwise be a fractional value that could not be rounded up to an even
258  * number of MTB. We represent the FTB values by appending '_FINE' to them.
259  */
260 #define	SPD_DDR4_TIMEBASE	0x011
261 #define	SPD_DDR4_TIMEBASE_MTB(r)	bitx8(r, 3, 2)
262 #define	SPD_DDR4_TIMEBASE_MTB_125ps	0
263 #define	SPD_DDR4_TIMEBASE_FTB(r)	bitx8(r, 1, 0)
264 #define	SPD_DDR4_TIMEBASE_FTB_1ps	0
265 #define	SPD_DDR4_MTB_PS		125
266 #define	SPD_DDR4_FTB_PS		1
267 
268 /*
269  * S8.1.19 SDRAM Minimum Cycle Time t~ckavg~min.
270  * S8.1.52 Fine Offset for ^
271  * S8.1.20 SDRAM Maximum Cycle Time t~ckavg~max.
272  * S8.1.51 Fine Offset for ^
273  */
274 #define	SPD_DDR4_TCKAVG_MIN		0x012
275 #define	SPD_DDR4_TCKAVG_MIN_FINE	0x07d
276 #define	SPD_DDR4_TCKAVG_MAX		0x013
277 #define	SPD_DDR4_TCKAVG_MAX_FINE	0x07c
278 
279 /*
280  * S8.1.21 CAS Latencies. There are four bytes that are used to get at this and
281  * show what is supported. These either start at CL7 or CL23 depending on the
282  * top bit of the last CAS byte.
283  */
284 #define	SPD_DDR4_CAS_SUP0	0x014
285 #define	SPD_DDR4_CAS_SUP1	0x015
286 #define	SPD_DDR4_CAS_SUP2	0x016
287 #define	SPD_DDR4_CAS_SUP3	0x017
288 #define	SPD_DDR4_CAS_SUP3_RANGE(r)	bitx8(r, 7, 7)
289 #define	SPD_DDR4_CAS_SUP3_RANGE_7	0
290 #define	SPD_DDR4_CAS_SUP3_RANGE_23	1
291 
292 /*
293  * S8.1.22 Minimum CAS Latency Time t~AA~min. This uses the MTB.
294  * S8.1.50 Fine Offset for ^
295  */
296 #define	SPD_DDR4_TAA_MIN	0x018
297 #define	SPD_DDR4_TAA_MIN_FINE	0x07b
298 
299 /*
300  * S8.1.23 Minimum RAS to CAS Delay Time t~RCD~min.
301  * S8.1.49 Fine Offset for ^
302  */
303 #define	SPD_DDR4_TRCD_MIN	0x019
304 #define	SPD_DDR4_TRCD_MIN_FINE	0x07a
305 
306 /*
307  * S8.1.24 Minimum Row Precharge Delay Time t~RP~min.
308  * S8.1.48 Fine Offset for ^
309  */
310 #define	SPD_DDR4_TRP_MIN	0x01a
311 #define	SPD_DDR4_TRP_MIN_FINE	0x079
312 
313 /*
314  * S8.1.25 Upper Nibbles for t~RAS~min and t~RC~min. These are bits 11:9 of
315  * these values. The lower byte is in subsequent values.
316  * S8.1.26 Minimum Active to Precharge Delay Time t~RAS~min.
317  * S8.1.27 Minimum Active to Active/Refresh Delay Time t~RC~min.
318  * S8.1.47 Fine Offset for ^
319  */
320 #define	SPD_DDR4_RAS_RC_UPPER	0x01b
321 #define	SPD_DDR4_RAS_RC_UPPER_RC(r)	bitx8(r, 7, 4)
322 #define	SPD_DDR4_RAS_RC_UPPER_RAS(r)	bitx8(r, 3, 0)
323 #define	SPD_DDR4_TRAS_MIN	0x01c
324 #define	SPD_DDR4_TRC_MIN	0x01d
325 #define	SPD_DDR4_TRC_MIN_FINE	0x078
326 
327 /*
328  * S8.1.28: Minimum Refresh Recovery Delay Time t~RFC1~min.
329  * S8.1.29: Minimum Refresh Recovery Delay Time t~RFC2~min.
330  * S8.1.30: Minimum Refresh Recovery Delay Time t~RFC4~min.
331  *
332  * These are all different minimum refresh times. They are all two byte values
333  * in units of MTB.
334  */
335 #define	SPD_DDR4_TRFC1_MIN_LSB	0x01e
336 #define	SPD_DDR4_TRFC1_MIN_MSB	0x01f
337 #define	SPD_DDR4_TRFC2_MIN_LSB	0x020
338 #define	SPD_DDR4_TRFC2_MIN_MSB	0x021
339 #define	SPD_DDR4_TRFC4_MIN_LSB	0x022
340 #define	SPD_DDR4_TRFC4_MIN_MSB	0x023
341 
342 /*
343  * S8.1.31 Upper nibble for t~FAW~
344  * S8.1.32 Minimum Four Activate Window Delay t~FAW~min.
345  *
346  * This is another 12-bit MTB-unit field.
347  */
348 #define	SPD_DDR4_TFAW_UPPER	0x024
349 #define	SPD_DDR4_TFAW_UPPER_FAW(r)	bitx8(r, 3, 0)
350 #define	SPD_DDR4_TFAW		0x025
351 
352 /*
353  * S8.1.33 Minimum Activate to Activate Delay Time t~RRD_S~min, different bank
354  * group.
355  * S8.1.46 Fine Offset for ^
356  *
357  * S8.1.34 Minimum Activate to Activate Delay Time t~RRD_L~min, same bank group.
358  * S8.1.45 Fine Offset for ^
359  *
360  * S8.1.35 Minimum CAS to CAS Delay Time t~CCD_L~min, same bank group.
361  * S8.1.44 Fine Offset for ^
362  * group.
363  */
364 #define	SPD_DDR4_TRRDS_MIN	0x026
365 #define	SPD_DDR4_TRRDS_MIN_FINE	0x077
366 #define	SPD_DDR4_TRRDL_MIN	0x027
367 #define	SPD_DDR4_TRRDL_MIN_FINE	0x076
368 #define	SPD_DDR4_TCCDL_MIN	0x028
369 #define	SPD_DDR4_TCCDL_MIN_FINE	0x075
370 
371 /*
372  * S8.1.36 Upper Nibble for t~WR~min.
373  * S8.1.37 Minimum Write Recovery Time t~WR~min.
374  */
375 #define	SPD_DDR4_TWR_MIN_UPPER	0x029
376 #define	SPD_DDR4_TWR_MIN_UPPER_TWR(r)	bitx8(r, 3, 0)
377 #define	SPD_DDR4_TWR_MIN	0x02a
378 
379 /*
380  * S 8.1.38 Upper Nibbles for t~WTR~min
381  * S8.1.39 Minimum Write to Read Time t~WTR_S~min, different bank group.
382  * S8.1.40 Minimum Write to Read Time t~WTR_L~min, same bank group.
383  *
384  * Note, the referenced version of the spec has a typo here and refers to this
385  * as byte 0x29, but that already exists with a different meaning.
386  */
387 #define	SPD_DDR4_TWRT_UPPER	0x02b
388 #define	SPD_DDR4_TWRT_UPPER_TWRL(r)	bitx8(r, 7, 4)
389 #define	SPD_DDR4_TWRT_UPPER_TWRS(r)	bitx8(r, 3, 0)
390 #define	SPD_DDR4_TWTRS_MIN	0x02c
391 #define	SPD_DDR4_TWTRL_MIN	0x02d
392 
393 /*
394  * Bytes 0x2e to 0x3b are all reserved.
395  */
396 
397 /*
398  * S8.1.42 Connector to SDRAM bit mapping. Each of the bytes defines a different
399  * set of pins here. These all have a fairly standard set of transformations
400  * that can be applied. These include a package rank map which only has a single
401  * identity transformation applied and a separate nibble map encoding.
402  */
403 #define	SPD_DDR4_MAP_DQ0	0x03c
404 #define	SPD_DDR4_MAP_DQ4	0x03d
405 #define	SPD_DDR4_MAP_DQ8	0x03e
406 #define	SPD_DDR4_MAP_DQ12	0x03f
407 #define	SPD_DDR4_MAP_DQ16	0x040
408 #define	SPD_DDR4_MAP_DQ20	0x041
409 #define	SPD_DDR4_MAP_DQ24	0x042
410 #define	SPD_DDR4_MAP_DQ28	0x043
411 #define	SPD_DDR4_MAP_CB0	0x044
412 #define	SPD_DDR4_MAP_CB4	0x045
413 #define	SPD_DDR4_MAP_DQ32	0x046
414 #define	SPD_DDR4_MAP_DQ36	0x047
415 #define	SPD_DDR4_MAP_DQ40	0x048
416 #define	SPD_DDR4_MAP_DQ44	0x049
417 #define	SPD_DDR4_MAP_DQ48	0x04a
418 #define	SPD_DDR4_MAP_DQ52	0x04b
419 #define	SPD_DDR4_MAP_DQ56	0x04c
420 #define	SPD_DDR4_MAP_DQ60	0x04d
421 #define	SPD_DDR4_MAP_PKG(r)	bitx8(r, 7, 6)
422 #define	SPD_DDR4_MAP_PKG_FLIP	0
423 #define	SPD_DDR4_MAP_NIBBLE(r)	bitx8(r, 5, 5)
424 #define	SPD_DDR4_MAP_IDX(r)	bitx8(r, 4, 0)
425 #define	SPD_DDR4_MAP_IDX_UNSPEC	0
426 
427 /*
428  * Bytes 0x4e-0x74 are reserved. Bytes 75-7D are fine offsets that are laid out
429  * with their base counterparts.
430  */
431 
432 /*
433  * S8.1.53 CRC For Base Configuration Section. This is a CRC that covers bytes
434  * 0x00 to 0x7D using a specific CRC16.
435  */
436 #define	SPD_DDR4_CRC_LSB	0x07e
437 #define	SPD_DDR4_CRC_MSB	0x07f
438 
439 /*
440  * We jump ahead to another common region which contains the common
441  * manufacturing information which is shared across all module types.
442  */
443 
444 /*
445  * S8.5.1 Module Manufacturer ID Code. This is a two byte JEP-108 style MFG ID.
446  * S8.5.7 DRAM Manufacturer ID code.
447  */
448 #define	SPD_DDR4_MOD_MFG_ID0	0x140
449 #define	SPD_DDR4_MOD_MFG_ID1	0x141
450 #define	SPD_DDR4_DRAM_MFG_ID0	0x15e
451 #define	SPD_DDR4_DRAM_MFG_ID1	0x15f
452 
453 /*
454  * S8.5.2 Module Manufacturing Location. This byte is manufacturer specific.
455  */
456 #define	SPD_DDR4_MOD_MFG_LOC	0x142
457 
458 /*
459  * S8.5.3 Module Manufacturing Date. Encoded as two BCD bytes for the year and
460  * week.
461  */
462 #define	SPD_DDR4_MOD_MFG_YEAR	0x143
463 #define	SPD_DDR4_MOD_MFG_WEEK	0x144
464 
465 /*
466  * S8.5.4 Module Serial Number.
467  * S8.5.5 Module Part Number
468  * S8.5.6 Module Revision Code
469  */
470 #define	SPD_DDR4_MOD_SN		0x145
471 #define	SPD_DDR4_MOD_SN_LEN	4
472 #define	SPD_DDR4_MOD_PN		0x149
473 #define	SPD_DDR4_MOD_PN_LEN	20
474 #define	SPD_DDR4_MOD_REV	0x15d
475 
476 /*
477  * S8.5.8 DRAM Stepping
478  */
479 #define	SPD_DDR4_DRAM_STEP	0x160
480 
481 /*
482  * Bytes 0x161-0x17d are left for Manufacturer specific data while bytes
483  * 0x17e-0x17f are reserved.
484  */
485 
486 /*
487  * The next region of bytes in the range 0x80-0xbf. We have specific definitions
488  * for RDIMMs, LRDIMMs, and UDIMMs. While these often are very similar, they are
489  * subtlety different.
490  */
491 
492 /*
493  * S9.2.1 RDIMM: Raw Card Extension, Module Nominal Height. Bits 7-5 here have a
494  * raw card revision. The revision extension, bits 7:5, are only valid when the
495  * value of the normal reference card used in byte 0x82 is set to 0b11 (3).
496  */
497 #define	SPD_DDR4_RDIMM_HEIGHT	0x080
498 #define	SPD_DDR4_RDIMM_HEIGHT_REV(r)	bitx8(r, 7, 5)
499 #define	SPD_DDR4_RDIMM_HEIGHT_MM(r)	bitx8(r, 4, 0)
500 #define	SPD_DDR4_RDIMM_HEIGHT_LT15MM	0
501 #define	SPD_DDR4_RDIMM_HEIGHT_BASE	15
502 
503 /*
504  * S9.2.2 RDIMM: Module Maximum Thickness. These measure thicknesses in mm, with
505  * zero value meaning less than or equal to 1mm.
506  */
507 #define	SPD_DDR4_RDIMM_THICK	0x081
508 #define	SPD_DDR4_RDIMM_THICK_BACK(r)	bitx8(r, 7, 4)
509 #define	SPD_DDR4_RDIMM_THICK_FRONT(r)	bitx8(r, 3, 0)
510 #define	SPD_DDR4_RDIMM_THICK_BASE	1
511 
512 /*
513  * S9.2.3 RDIMM: Reference Raw Card Used. Bit 7 is used as basically another bit
514  * for bits 4-0. We do not define each meaning of these bit combinations in this
515  * header, that is left for tables in the library. When bits 6:5 are 0b11 (3)
516  * then we must add in the reference card value in byte 0x80 to bits 6:5.
517  */
518 #define	SPD_DDR4_RDIMM_REF	0x082
519 #define	SPD_DDR4_RDIMM_REF_EXT(r)	bitx8(r, 7, 7)
520 #define	SPD_DDR4_RDIMM_REF_REV(r)	bitx8(r, 6, 5)
521 #define	SPD_DDR4_RDIMM_REV_USE_HEIGHT	3
522 #define	SPD_DDR4_RDIMM_REF_CARD(r)	bitx8(r, 4, 0)
523 
524 /*
525  * S9.2.4 RDIMM: DIMM Attributes.
526  */
527 #define	SPD_DDR4_RDIMM_ATTR	0x083
528 #define	SPD_DDR4_RDIMM_ATTR_TYPE(r)	bitx8(r, 7, 4)
529 #define	SPD_DDR4_RDIMM_ATTR_TYPE_RCD01	0
530 #define	SPD_DDR4_RDIMM_ATTR_TYPE_RCD02	1
531 #define	SPD_DDR4_RDIMM_ATTR_NROWS(r)	bitx8(r, 3, 2)
532 #define	SPD_DDR4_RDIMM_ATTR_NREGS(r)	bitx8(r, 1, 0)
533 
534 /*
535  * S9.2.5 RDIMM: Thermal Heat Spreader Solution
536  */
537 #define	SPD_DDR4_RDIMM_THERM	0x084
538 #define	SPD_DDR4_RDIMM_THERM_IMPL(r)	bitx8(r, 7, 7)
539 
540 /*
541  * S9.2.6 RDIMM: Register Manufacturer JEDEC ID. This contains the JEDEC ID for
542  * the manufacturer encoded as the number of continuation bytes and then the
543  * actual code. This works with libjedec_vendor_string.
544  */
545 #define	SPD_DDR4_RDIMM_REG_MFG_ID0	0x085
546 #define	SPD_DDR4_RDIMM_REG_MFG_ID1	0x086
547 
548 /*
549  * S9.2.7 RDIMM: Register Revision Number. This value is just a straight up hex
550  * encoded value. It's a bit arbitrary. For example, they say 0x31 can be rev
551  * 3.1, while 0x01 is just revision 1, and 0xB1 is revision B1.
552  */
553 #define	SPD_DDR4_RDIMM_REV	0x087
554 #define	SPD_DDR4_RDIMM_REV_UNDEF	0xff
555 
556 /*
557  * S9.2.8 RDIMM: Address Mapping from Register to DRAM. This covers how the
558  * register maps ranks 1 and 3 between the register and the actual modules.
559  * Ranks 0/2 are always standard.
560  */
561 #define	SPD_DDR4_RDIMM_MAP	0x88
562 #define	SPD_DDR4_RDIMM_MAP_R1(r)	bitx8(r, 0, 0)
563 #define	SPD_DDR4_RDIMM_MAP_R1_STD	0
564 #define	SPD_DDR4_RDIMM_MAP_R1_MIRROR	1
565 
566 /*
567  * S9.2.9 RDIMM: Register Output Drive Strength for Control and Command/Address
568  * S9.2.10 RDIMM: Register Output Drive Strength for Clock
569  */
570 #define	SPD_DDR4_RDIMM_ODS0	0x89
571 #define	SPD_DDR4_RDIMM_ODS0_CS(r)	bitx8(r, 7, 6)
572 #define	SPD_DDR4_RDIMM_ODS0_CA(r)	bitx8(r, 5, 4)
573 #define	SPD_DDR4_RDIMM_ODS0_ODT(r)	bitx8(r, 3, 2)
574 #define	SPD_DDR4_RDIMM_ODS0_CKE(r)	bitx8(r, 1, 0)
575 #define	SPD_DDR4_RDIMM_ODS0_LIGHT	0
576 #define	SPD_DDR4_RDIMM_ODS0_MODERATE	1
577 #define	SPD_DDR4_RDIMM_ODS0_STRONG	2
578 #define	SPD_DDR4_RDIMM_ODS0_VERY_STRONG	3
579 #define	SPD_DDR4_RDIMM_ODS1	0x8a
580 #define	SPD_DDR4_RDIMM_ODS1_SLEW_SUP(r)	bitx8(r, 6, 6)
581 #define	SPD_DDR4_RDIMM_ODS1_Y1(r)	bitx8(r, 3, 2)
582 #define	SPD_DDR4_RDIMM_ODS1_Y0(r)	bitx8(r, 1, 0)
583 
584 /*
585  * S9.2.12 CRC for SPD Block 1.
586  */
587 #define	SPD_DDR4_BLK1_CRC_START	0x80
588 #define	SPD_DDR4_BLK1_CRC_LSB	0xfe
589 #define	SPD_DDR4_BLK1_CRC_MSB	0xff
590 
591 /*
592  * S9.1.1 UDIMM: Raw Card Extension, Module Nominal Height.
593  * S9.1.2 UDIMM: Module Maximum Thickness.
594  * S9.1.3 UDIMM: Reference Raw Card Used.
595  *
596  * These definitions are the same as for RDIMMs.
597  */
598 #define	SPD_DDR4_UDIMM_HEIGHT	0x080
599 #define	SPD_DDR4_UDIMM_THICK	0x081
600 #define	SPD_DDR4_UDIMM_REF	0x082
601 
602 /*
603  * S9.1.4 UDIMM: Address Mapping from Edge Connector to DRAM. This is similar to
604  * SPD_DDR4_RDIMM_MAP; however it doesn't take into account the register.
605  */
606 #define	SPD_DDR4_UDIMM_MAP	0x83
607 
608 /*
609  * Everything else in UDIMMs is reserved, aside from the CRC, which is the same
610  * as RDIMMs.
611  */
612 
613 /*
614  * S9.3.1 LRDIMM: Raw Card Extension, Module Nominal Height
615  * S9.3.2 LRDIMM: Module Maximum Thickness
616  * S9.3.3 LRDIMM: Reference Raw Card Used
617  *
618  * These are the same as the corresponding UDIMM / RDIMM values.
619  */
620 #define	SPD_DDR4_LRDIMM_HEIGHT	0x080
621 #define	SPD_DDR4_LRDIMM_THICK	0x081
622 #define	SPD_DDR4_LRDIMM_REF	0x082
623 
624 /*
625  * S9.3.4 LRDIMM: DIMM Attributes.
626  */
627 #define	SPD_DDR4_LRDIMM_ATTR	0x083
628 #define	SPD_DDR4_LRDIMM_ATTR_TYPE(r)	bitx8(r, 7, 4)
629 #define	SPD_DDR4_LRDIMM_ATTR_TYPE_RCD01_DB01	0
630 #define	SPD_DDR4_LRDIMM_ATTR_TYPE_RCD02_DB02	1
631 #define	SPD_DDR4_LRDIMM_ATTR_NROWS(r)	bitx8(r, 3, 2)
632 #define	SPD_DDR4_LRDIMM_ATTR_NREGS(r)	bitx8(r, 1, 0)
633 
634 /*
635  * S9.3.5 LRDIMM: Thermal Heat Spreader. See RDIMM version.
636  */
637 #define	SPD_DDR4_LRDIMM_THERM	0x084
638 
639 /*
640  * S9.3.6 LRDIMM: Register and Data Buffer Manufacturer. See RDIMM version.
641  */
642 #define	SPD_DDR4_LRDIMM_REG_MFG_ID0	0x085
643 #define	SPD_DDR4_LRDIMM_REG_MFG_ID1	0x086
644 
645 /*
646  * S9.3.7 LRDIMM: Register Revision Number. See RDIMM for more info.
647  */
648 #define	SPD_DDR4_LRDIMM_REV	0x087
649 
650 /*
651  * S9.3.8 LRDIMM: Address Mapping from Register to DRAM. See RDIMM.
652  */
653 #define	SPD_DDR4_LRDIMM_MAP	0x88
654 
655 /*
656  * S9.3.9 LRDIMM: Register Output Drive Strength for Control and
657  * Command/Address.
658  * S9.3.10: LRDIMM: Register Output Drive Strength for Clock and Data Buffer
659  * Control.
660  * See RDIMM for valid drive strength values and ODS0.
661  */
662 #define	SPD_DDR4_LRDIMM_ODS0	0x89
663 #define	SPD_DDR4_LRDIMM_ODS1	0x8a
664 #define	SPD_DDR4_LRDIMM_ODS1_OSRC_SUP(r)	bitx8(r, 6, 6)
665 #define	SPD_DDR4_LRDIMM_ODS1_BCK(r)	bitx8(r, 5, 5)
666 #define	SPD_DDR4_LRDIMM_ODS1_BCOM(r)	bitx8(r, 4, 4)
667 #define	SPD_DDR4_LRDIMM_ODS1_MODERATE	0
668 #define	SPD_DDR4_LRDIMM_ODS1_STRONG	1
669 /*
670  * The above two bit ranges use a single bit drive strength while the following
671  * two use the same two-bit version as RDIMMs.
672  */
673 #define	SPD_DDR4_RDIMM_ODS1_Y1(r)	bitx8(r, 3, 2)
674 #define	SPD_DDR4_RDIMM_ODS1_Y0(r)	bitx8(r, 1, 0)
675 
676 /*
677  * S9.3.7 LRDIMM: Data Buffer Revision Number.
678  */
679 #define	SPD_DDR4_LRDIMM_DB_REV	0x08b
680 
681 /*
682  * S9.3.12 LRDIMM: DRAM VrefDQ for Package Rank 0
683  * S9.3.13 LRDIMM: DRAM VrefDQ for Package Rank 1
684  * S9.3.14 LRDIMM: DRAM VrefDQ for Package Rank 2
685  * S9.3.15 LRDIMM: DRAM VrefDQ for Package Rank 3
686  *
687  * These are all encoded with a value from MR6 in JESD79-4 apparently.
688  */
689 #define	SPD_DDR4_LRDIMM_VREFDQ0	0x08c
690 #define	SPD_DDR4_LRDIMM_VREFDQ1	0x08d
691 #define	SPD_DDR4_LRDIMM_VREFDQ2	0x08e
692 #define	SPD_DDR4_LRDIMM_VREFDQ3	0x08f
693 #define	SPD_DDR4_LRDIMM_VREFDQ_V(r)	bitx8(r, 5, 0)
694 
695 /*
696  * S9.3.16 LRDIMM: Data Buffer VrefDQ for DRAM Interface. The entire byte is
697  * used to match the encoding from the DDR4DB01 spec.
698  */
699 #define	SPD_DDR4_LRDIMM_VREFDQ_DB	0x090
700 
701 /*
702  * S9.3.17 LRDIMM: Data Buffer MDQ Drive Strength and RTT for data rate <= 1866
703  * S9.3.18 LRDIMM: Data Buffer MDQ Drive Strength and RTT for 1866 < data rate
704  * <= 2400
705  * S9.3.19 LRDIMM: Data Buffer MDQ Drive Strength and RTT for 2400 < data rate
706  * <= 3200
707  *
708  * These three registers all share the same bit values and register extraction.
709  */
710 #define	SPD_DDR4_LRDIMM_MDQ_1866	0x091
711 #define	SPD_DDR4_LRDIMM_MDQ_2400	0x092
712 #define	SPD_DDR4_LRDIMM_MDQ_3200	0x093
713 #define	SPD_DDR4_LRDIMM_MDQ_DS(r)	bitx8(r, 6, 4)
714 #define	SPD_DDR4_LRDIMM_MDQ_DS_40R	0
715 #define	SPD_DDR4_LRDIMM_MDQ_DS_34R	1
716 #define	SPD_DDR4_LRDIMM_MDQ_DS_48R	2
717 #define	SPD_DDR4_LRDIMM_MDQ_DS_60R	5
718 #define	SPD_DDR4_LRDIMM_MDQ_RTT(r)	bitx8(r, 2, 0)
719 #define	SPD_DDR4_LRDIMM_MDQ_RTT_DIS	0
720 #define	SPD_DDR4_LRDIMM_MDQ_RTT_60R	1
721 #define	SPD_DDR4_LRDIMM_MDQ_RTT_120R	2
722 #define	SPD_DDR4_LRDIMM_MDQ_RTT_40R	3
723 #define	SPD_DDR4_LRDIMM_MDQ_RTT_240R	4
724 #define	SPD_DDR4_LRDIMM_MDQ_RTT_48R	5
725 #define	SPD_DDR4_LRDIMM_MDQ_RTT_80R	6
726 #define	SPD_DDR4_LRDIMM_MDQ_RTT_34R	7
727 
728 /*
729  * S9.3.20: LRDIMM: DRAM Drive Strength. One byte covers all data rates, which
730  * share the same resistance values.
731  */
732 #define	SPD_DDR4_LRDIMM_DRAM_DS	0x094
733 #define	SPD_DDR4_LRDIMM_DRAM_DS_3200(r)	bitx8(r, 5, 4)
734 #define	SPD_DDR4_LRDIMM_DRAM_DS_2400(r)	bitx8(r, 3, 2)
735 #define	SPD_DDR4_LRDIMM_DRAM_DS_1866(r)	bitx8(r, 1, 0)
736 #define	SPD_DDR4_LRDIMM_DRAM_DS_34R	0
737 #define	SPD_DDR4_LRDIMM_DRAM_DS_48R	1
738 
739 /*
740  * S9.3.21 LRDIMM: DRAM ODT (RTT_WR and RTT_NOM) for data rate <= 1866
741  * S9.3.22 LRDIMM: DRAM ODT (RTT_WR and RTT_NOM) for 1866 < data rate <= 2400
742  * S9.3.23 LRDIMM: DRAM ODT (RTT_WR and RTT_NOM) for 2400 < data rate <= 3200
743  */
744 #define	SPD_DDR4_LRDIMM_ODT_1866	0x095
745 #define	SPD_DDR4_LRDIMM_ODT_2400	0x096
746 #define	SPD_DDR4_LRDIMM_ODT_3200	0x097
747 #define	SPD_DDR4_LRDIMM_ODT_WR(r)	bitx8(r, 5, 3)
748 #define	SPD_DDR4_LRDIMM_ODT_WR_DYN_OFF	0
749 #define	SPD_DDR4_LRDIMM_ODT_WR_120R	1
750 #define	SPD_DDR4_LRDIMM_ODT_WR_240R	2
751 #define	SPD_DDR4_LRDIMM_ODT_WR_HIZ	3
752 #define	SPD_DDR4_LRDIMM_ODT_WR_80R	4
753 #define	SPD_DDR4_LRDIMM_ODT_NOM(r)	bitx8(r, 2, 0)
754 #define	SPD_DDR4_LRDIMM_ODT_NOM_DIS	0
755 #define	SPD_DDR4_LRDIMM_ODT_NOM_60R	1
756 #define	SPD_DDR4_LRDIMM_ODT_NOM_120R	2
757 #define	SPD_DDR4_LRDIMM_ODT_NOM_40R	3
758 #define	SPD_DDR4_LRDIMM_ODT_NOM_240R	4
759 #define	SPD_DDR4_LRDIMM_ODT_NOM_48R	5
760 #define	SPD_DDR4_LRDIMM_ODT_NOM_80R	6
761 #define	SPD_DDR4_LRDIMM_ODT_NOM_34R	7
762 
763 /*
764  * S9.3.24 LRDIMM: DRAM ODT (RTT_PARK) for data rate <= 1866
765  * S9.3.25 LRDIMM: DRAM ODT (RTT_PARK) for 1866 < data rate <= 2400
766  * S9.3.26 LRDIMM: DRAM ODT (RTT_PARK) for 2400 < data rate <= 3200
767  */
768 #define	SPD_DDR4_LRDIMM_PARK_1866	0x098
769 #define	SPD_DDR4_LRDIMM_PARK_2400	0x099
770 #define	SPD_DDR4_LRDIMM_PARK_3200	0x09a
771 #define	SPD_DDR4_LRDIMM_PARK_R23(r)	bitx8(r, 5, 3)
772 #define	SPD_DDR4_LRDIMM_PARK_R01(r)	bitx8(r, 2, 0)
773 #define	SPD_DDR4_LRDIMM_PARK_DIS	0
774 #define	SPD_DDR4_LRDIMM_PARK_60R	1
775 #define	SPD_DDR4_LRDIMM_PARK_120R	2
776 #define	SPD_DDR4_LRDIMM_PARK_40R	3
777 #define	SPD_DDR4_LRDIMM_PARK_240R	4
778 #define	SPD_DDR4_LRDIMM_PARK_48R	5
779 #define	SPD_DDR4_LRDIMM_PARK_80R	6
780 #define	SPD_DDR4_LRDIMM_PARK_34R	7
781 
782 /*
783  * S9.3.27: Data Buffer VrefDQ for DRAM Interface Range.
784  */
785 #define	SPD_DDR4_LRDIMM_VREFDQ_RNG	0x09b
786 #define	SPD_DDR4_LRDIMM_VREFDQ_RNG_DB(r)	bitx8(r, 4, 4)
787 #define	SPD_DDR4_LRDIMM_VREFDQ_RNG_R3(r)	bitx8(r, 3, 3)
788 #define	SPD_DDR4_LRDIMM_VREFDQ_RNG_R2(r)	bitx8(r, 2, 2)
789 #define	SPD_DDR4_LRDIMM_VREFDQ_RNG_R1(r)	bitx8(r, 1, 1)
790 #define	SPD_DDR4_LRDIMM_VREFDQ_RNG_R0(r)	bitx8(r, 0, 0)
791 #define	SPD_DDR4_LRDIMM_VERFDQ_RNG_1	0
792 #define	SPD_DDR4_LRDIMM_VERFDQ_RNG_2	1
793 
794 /*
795  * S9.3.28: Data Buffer DQ Decision Feedback Equalization
796  */
797 #define	SPD_DDR4_LRDIMM_EQ	0x09c
798 #define	SPD_DDR4_LRDIMM_EQ_DFE_SUP(r)	bitx8(r, 1, 1)
799 #define	SPD_DDR4_LRDIMM_EQ_GA_SUP(r)	bitx8(r, 0, 0)
800 
801 #ifdef __cplusplus
802 }
803 #endif
804 
805 #endif /* _SPD_DDR4_H */
806