1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright (c) 2018, Joyent, Inc. 14 * Copyright 2026 Oxide Computer Company 15 */ 16 17 #ifndef _LIBJEDEC_H 18 #define _LIBJEDEC_H 19 20 /* 21 * Library routines that support various JEDEC standards: 22 * 23 * o JEDEC JEP-106 vendor data 24 * o Temperature range and Measurement Standards for Components and Modules 25 * (JESD402-1) 26 * o DDR3 Serial Presence Detect (SPD) decoding 27 * o DDR4 Serial Presence Detect (SPD) decoding 28 * o LPDDR3/4/4x Serial Presence Detect (SPD) decoding 29 * o DDR5 Serial Presence Detect (SPD) decoding 30 * o LPDDR5/x Serial Presence Detect (SPD) decoding 31 */ 32 33 #include <sys/types.h> 34 #include <stdint.h> 35 #include <libnvpair.h> 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /* 42 * Decode a JEDEC continuation ID (without parity) and a group ID. 43 */ 44 extern const char *libjedec_vendor_string(uint_t, uint_t); 45 46 /* 47 * JEDEC operating temperature ranges. These are defined in JESD402-1B 48 * (September 2024). 49 */ 50 typedef enum { 51 /* 52 * Operating Case Temperature Ranges 53 */ 54 JEDEC_TEMP_CASE_A1T, 55 JEDEC_TEMP_CASE_A2T, 56 JEDEC_TEMP_CASE_A3T, 57 JEDEC_TEMP_CASE_IT, 58 JEDEC_TEMP_CASE_ET, 59 JEDEC_TEMP_CASE_ST, 60 JEDEC_TEMP_CASE_XT, 61 JEDEC_TEMP_CASE_NT, 62 JEDEC_TEMP_CASE_RT, 63 /* 64 * Operating Ambient Temperature Ranges 65 */ 66 JEDEC_TEMP_AMB_CT, 67 JEDEC_TEMP_AMB_IOT, 68 JEDEC_TEMP_AMB_IPT, 69 JEDEC_TEMP_AMB_IXT, 70 JEDEC_TEMP_AMB_AO3T, 71 JEDEC_TEMP_AMB_AO2T, 72 JEDEC_TEMP_AMB_AO1T, 73 /* 74 * Storage Temperature Ranges 75 */ 76 JEDEC_TEMP_STOR_2, 77 JEDEC_TEMP_STOR_1B, 78 JEDEC_TEMP_STOR_1A, 79 JEDEC_TEMP_STOR_ST, 80 /* 81 * Operating Junction Temperature Ranges 82 */ 83 JEDEC_TEMP_JNCT_A135, 84 JEDEC_TEMP_JNCT_A130, 85 JEDEC_TEMP_JNCT_A1T, 86 JEDEC_TEMP_JNCT_A120, 87 JEDEC_TEMP_JNCT_A115, 88 JEDEC_TEMP_JNCT_A110, 89 JEDEC_TEMP_JNCT_A2T, 90 JEDEC_TEMP_JNCT_A100, 91 JEDEC_TEMP_JNCT_A95, 92 JEDEC_TEMP_JNCT_A90, 93 JEDEC_TEMP_JNCT_A3T, 94 JEDEC_TEMP_JNCT_LT135, 95 JEDEC_TEMP_JNCT_LT130, 96 JEDEC_TEMP_JNCT_LT125, 97 JEDEC_TEMP_JNCT_LT120, 98 JEDEC_TEMP_JNCT_LT115, 99 JEDEC_TEMP_JNCT_LT110, 100 JEDEC_TEMP_JNCT_LT105, 101 JEDEC_TEMP_JNCT_LT100, 102 JEDEC_TEMP_JNCT_IT, 103 JEDEC_TEMP_JNCT_LT90, 104 JEDEC_TEMP_JNCT_LT85, 105 JEDEC_TEMP_JNCT_ET120, 106 JEDEC_TEMP_JNCT_ET115, 107 JEDEC_TEMP_JNCT_ET110, 108 JEDEC_TEMP_JNCT_ET, 109 JEDEC_TEMP_JNCT_ET100, 110 JEDEC_TEMP_JNCT_ET95, 111 JEDEC_TEMP_JNCT_ET90, 112 JEDEC_TEMP_JNCT_ST, 113 JEDEC_TEMP_JNCT_120, 114 JEDEC_TEMP_JNCT_115, 115 JEDEC_TEMP_JNCT_110, 116 JEDEC_TEMP_JNCT_105, 117 JEDEC_TEMP_JNCT_100, 118 JEDEC_TEMP_JNCT_XT, 119 JEDEC_TEMP_JNCT_90, 120 JEDEC_TEMP_JNCT_NT 121 } libjedec_temp_range_t; 122 extern boolean_t libjedec_temp_range(libjedec_temp_range_t, int32_t *, 123 int32_t *); 124 125 /* 126 * This is a series of error codes that libjedec may produce while trying to 127 * parse the overall SPD data structure. These represent a top-level failure and 128 * have meaning when no nvlist_t is returned. 129 */ 130 typedef enum { 131 /* 132 * Indicates that we didn't encounter a fatal error; however, we may 133 * have a specific parsing error that relates to a key in the nvlist. 134 */ 135 LIBJEDEC_SPD_OK = 0, 136 /* 137 * Indicates that we did not have enough memory while trying to 138 * construct the generated nvlist_t. 139 */ 140 LIBJEDEC_SPD_NOMEM, 141 /* 142 * Indicates that the data that we found was insufficient to 143 * successfully parse basic information. The required size varies per 144 * SPD key byte type. 145 */ 146 LIBJEDEC_SPD_TOOSHORT, 147 /* 148 * Indicates that we found an unsupported type of SPD data and therefore 149 * cannot parse this. 150 */ 151 LIBJEDEC_SPD_UNSUP_TYPE, 152 /* 153 * Indicates that while we found a supported type of SPD data, we do not 154 * understand its revision. 155 */ 156 LIBJEDEC_SPD_UNSUP_REV 157 } spd_error_t; 158 159 /* 160 * Decode a binary payload of SPD data, if possible. The returned nvlist is made 161 * up of a series of keys described below. Parsing errors are broken into two 162 * categories. Fatal errors set a value in the spd_error_t below. Non-fatal 163 * errors, such as encountering a value which we don't have a translation for, 164 * are in a nested errors nvlist_t indexed by key. 165 * 166 * The keys are all dot delineated to create a few different top-level 167 * namespaces. These include: 168 * 169 * "meta" -- Which includes information about the SPD, encoding, and things like 170 * the type of module. 171 * 172 * "dram" -- Parameters that are specific to the SDRAM dies present. What one 173 * thinks of as a stick of DRAM consists of several different SDRAM dies on the 174 * PCB. This includes things like the row and columns bits and timing 175 * information. 176 * 177 * "channel" -- Parameters that are tied to an implementation of a channel. DDR4 178 * has a single channel where as DDR5 and LPDDR[345] have some number of 179 * sub-channels. 180 * 181 * "ddr4", "ddr5" -- These include information which is specific to the general 182 * DDR standard. While we have tried to consolidate information between them 183 * where applicable, some things are specific to the standard. 184 * 185 * "lp" -- These are parameters that are currently specific to one of the 186 * low-power DDR specifications such as LPDDR5. 187 * 188 * "module" -- Parameters that are specific to the broader module and PCB 189 * itself. This includes information like the height or devices present. 190 * 191 * "ddr4.rdimm", "ddr4.lrdimm", "ddr5.rdimm", etc. -- These are parameter that 192 * are specific to a module being both the combination of a specific DDR 193 * standard and a specific type of module. Common parameters are often in the 194 * "module" section. 195 * 196 * "ddr3.mb", "ddr4.rcd", etc. -- These are generation-specific parameters that 197 * refer to a specific component like the rcd found on RDIMMs and LRDIMMs or the 198 * mb on LRDIMMs. 199 * 200 * "mfg" -- Manufacturing related information. 201 * 202 * "errors" -- The key for the errors nvlist_t. See the spd_error_kind_t 203 * definition later on. Each error has both a numeric code and a string message. 204 */ 205 extern nvlist_t *libjedec_spd(const uint8_t *, size_t, spd_error_t *); 206 207 /* 208 * The following are keys in the metadata nvlist_t. The SPD_KEY_NBYTES_TOTAL is 209 * present in DDR4 and DDR5. The SPD_KEY_NBYTES_USED is only present on DDR4 210 * right now. All supported SPD encodings have the raw revision information. If 211 * the values for the total bytes or used bytes are set to undefined, then they 212 * will not be present. 213 * 214 * DDR5 introduces an idea of a public beta level that gets reset between 215 * external releases. It theoretically modifies every scion. DDR5 also 216 * introduces a second revision that is for the module information. This will 217 * not be present on systems prior to DDR5. 218 */ 219 #define SPD_KEY_NBYTES_TOTAL "meta.total-bytes" /* uint32_t */ 220 #define SPD_KEY_NBYTES_USED "meta.used-bytes" /* uint32_t */ 221 #define SPD_KEY_REV_ENC "meta.revision-encoding" /* uint32_t */ 222 #define SPD_KEY_REV_ADD "meta.revision-additions" /* uint32_t */ 223 #define SPD_KEY_BETA "meta.beta-version" /* uint32_t */ 224 #define SPD_KEY_MOD_REV_ENC "meta.module-revision-encoding" /* uint32_t */ 225 #define SPD_KEY_MOD_REV_ADD "meta.module-revision-additions" /* uint32_t */ 226 227 /* 228 * DRAM Type information. This indicates the standard that the device conforms 229 * to. This enumeration's values match the JEDEC specification's values. This is 230 * present for everything. 231 */ 232 typedef enum { 233 SPD_DT_FAST_PAGE_MODE = 0x01, 234 SPD_DT_EDO = 0x02, 235 SPD_DT_PIPE_NIBBLE = 0x03, 236 SPD_DT_SDRAM = 0x04, 237 SPD_DT_ROM = 0x05, 238 SPD_DT_DDR_SGRAM = 0x06, 239 SPD_DT_DDR_SDRAM = 0x07, 240 SPD_DT_DDR2_SDRAM = 0x08, 241 SPD_DT_DDR2_SDRAM_FBDIMM = 0x09, 242 SPD_DT_DDR2_SDRAM_FDIMM_P = 0x0a, 243 SPD_DT_DDR3_SDRAM = 0x0b, 244 SPD_DT_DDR4_SDRAM = 0x0c, 245 SPD_DT_DDR4E_SDRAM = 0x0e, 246 SPD_DT_LPDDR3_SDRAM = 0x0f, 247 SPD_DT_LPDDR4_SDRAM = 0x10, 248 SPD_DT_LPDDR4X_SDRAM = 0x11, 249 SPD_DT_DDR5_SDRAM = 0x12, 250 SPD_DT_LPDDR5_SDRAM = 0x13, 251 SPD_DT_DDR5_NVDIMM_P = 0x14, 252 SPD_DT_LPDDR5X_SDRAM = 0x15 253 } spd_dram_type_t; 254 #define SPD_KEY_DRAM_TYPE "meta.dram-type" /* uint32_t (enum) */ 255 256 typedef enum { 257 SPD_MOD_TYPE_RDIMM, 258 SPD_MOD_TYPE_UDIMM, 259 SPD_MOD_TYPE_SODIMM, 260 SPD_MOD_TYPE_LRDIMM, 261 SPD_MOD_TYPE_MRDIMM, 262 SPD_MOD_TYPE_DDIMM, 263 SPD_MOD_TYPE_SOLDER, 264 SPD_MOD_TYPE_MINI_RDIMM, 265 SPD_MOD_TYPE_MINI_UDIMM, 266 SPD_MOD_TYPE_MINI_CDIMM, 267 SPD_MOD_TYPE_72b_SO_RDIMM, 268 SPD_MOD_TYPE_72b_SO_UDIMM, 269 SPD_MOD_TYPE_72b_SO_CDIMM, 270 SPD_MOD_TYPE_16b_SO_DIMM, 271 SPD_MOD_TYPE_32b_SO_DIMM, 272 SPD_MOD_TYPE_CUDIMM, 273 SPD_MOD_TYPE_CSODIMM, 274 SPD_MOD_TYPE_CAMM2, 275 SPD_MOD_TYPE_LPDIMM, 276 SPD_MOD_TYPE_MICRO_DIMM, 277 SPD_MOD_TYPE_SOCAMM2 278 } spd_module_type_t; 279 #define SPD_KEY_MOD_TYPE "meta.module-type" /* uint32_t (enum) */ 280 typedef enum { 281 SPD_MOD_NOT_HYBRID, 282 SPD_MOD_HYBRID_NVDIMMM 283 } spd_module_hybrid_t; 284 #define SPD_KEY_MOD_HYBRID_TYPE "meta.hybrid-type" /* uint32_t */ 285 286 typedef enum { 287 SPD_MOD_TYPE_NVDIMM_N, 288 SPD_MOD_TYPE_NVDIMM_P, 289 SPD_MOD_TYPE_NVDIMM_H 290 } spd_module_nvdimm_type_t; 291 #define SPD_KEY_MOD_NVDIMM_TYPE "meta.nvdimm-type" /* uint32_t */ 292 293 /* 294 * Different SPD standards have different integrity rules. The regions covered 295 * by the CRCs also vary. We end up with per-spec keys. All data types for these 296 * are uint32_t's so that way we can record the expected CRC. We use a uint32_t 297 * for consistency even though the data only fits in a uint16_t. Note, callers 298 * must check to see if these exist. If there are keys with these names in the 299 * errors object, then the rest of the data should be considered suspect, but we 300 * will have attempted to parse everything we can. The DDR4 values are shared 301 * across LPDDR3/4/4X. The DDR5 values are shared across LPDDR5/5X. 302 */ 303 #define SPD_KEY_CRC_DDR3 "meta.crc-ddr3" /* uint32_t */ 304 #define SPD_KEY_CRC_DDR3_LEN "meta.crc-ddr3-len" /* uint32_t */ 305 #define SPD_KEY_CRC_DDR4_BASE "meta.crc-ddr4-base" /* uint32_t */ 306 #define SPD_KEY_CRC_DDR4_BLK1 "meta.crc-ddr4-block1" /* uint32_t */ 307 #define SPD_KEY_CRC_DDR5 "meta.crc-ddr5" /* uint32_t */ 308 309 /* 310 * DDR5 adds a field in the SPD to describe how data should be hashed to compute 311 * and compare to an attribute certification to authenticate modules. This is 312 * only present in DDR5. We only add a value here if this is actually supported. 313 */ 314 typedef enum { 315 SPD_HASH_SEQ_ALG_1 316 } spd_hash_seq_alg_t; 317 #define SPD_KEY_HASH_SEQ "meta.hash-sequence-algorithm" /* uint32_t */ 318 319 /* 320 * This section contains information related to DRAM technology. 321 */ 322 323 /* 324 * Bank, bank group, row, and column bits. These are all present in both DDR4 325 * and DDR5. DDR4 allows cases where there are no bank groups. If no bits are 326 * used, then this item is empty. 327 */ 328 #define SPD_KEY_NROW_BITS "dram.num-row-bits" /* uint32_t */ 329 #define SPD_KEY_NCOL_BITS "dram.num-column-bits" /* uint32_t */ 330 #define SPD_KEY_NBANK_BITS "dram.num-bank-bits" /* uint32_t */ 331 #define SPD_KEY_NBGRP_BITS "dram.num-bank-group-bits" /* uint32_t */ 332 #define SPD_KEY_SEC_NROW_BITS "dram.sec-num-row-bits" /* uint32_t */ 333 #define SPD_KEY_SEC_NCOL_BITS "dram.sec-num-column-bits" /* uint32_t */ 334 #define SPD_KEY_SEC_NBANK_BITS "dram.sec-num-bank-bits" /* uint32_t */ 335 #define SPD_KEY_SEC_NBGRP_BITS "dram.sec-num-bank-group-bits" /* uint32_t */ 336 337 /* 338 * Die Density. This is the capacity that each die contains in bits. 339 */ 340 #define SPD_KEY_DIE_SIZE "dram.die-bit-size" /* uint64_t */ 341 #define SPD_KEY_SEC_DIE_SIZE "dram.sec-die-bit-size" /* uint64_t */ 342 343 /* 344 * Package information. DRAM may be made up of a monolithic package type or 345 * several different types. There is a boolean property present to indicate that 346 * it is not monolithic. For these there is a die count and then a separate 347 * notion of what the signal loading type is. If the property is present then we 348 * will also have the die count and loading type for the secondary. Note, these 349 * loading parameters are considered at the device balls as opposed to specific 350 * signals. 351 */ 352 #define SPD_KEY_PKG_NOT_MONO "meta.non-monolithic-package" /* key only */ 353 #define SPD_KEY_PKG_NDIE "dram.package-die-count" /* uint32_t */ 354 #define SPD_KEY_SEC_PKG_NDIE "dram.sec-package-die-count" /* uint32_t */ 355 typedef enum { 356 SPD_SL_UNSPECIFIED, 357 SPD_SL_MUTLI_STACK, 358 SPD_SL_3DS 359 } spd_signal_loading_t; 360 #define SPD_KEY_PKG_SL "dram.package-sig-loading" /* uint32_t */ 361 #define SPD_KEY_SEC_PKG_SL "dram.sec-package-sig-loading" /* uint32_t */ 362 363 /* 364 * Post-package Repair. PPR is supported in DDR4, DDR5. LPDDR4, and LPDDR5. PPR 365 * support is indicated by the presence of the spd_ppr_flags_t structure. If it 366 * is not supported, then there will be no PPR related keys present. In some 367 * cases the PPR granularity may not be known, in which case it is not present. 368 */ 369 typedef enum { 370 SPD_PPR_F_HARD_PPR = 1 << 0, 371 SPD_PPR_F_SOFT_PPR = 1 << 1, 372 SPD_PPR_F_MBIST_PPR = 1 << 2, 373 SPD_PPR_F_PPR_UNDO = 1 << 3 374 } spd_ppr_flags_t; 375 376 typedef enum { 377 SPD_PPR_GRAN_BANK_GROUP, 378 SPD_PPR_GRAN_BANK 379 } spd_ppr_gran_t; 380 #define SPD_KEY_PPR "dram.ppr-flags" /* uint32_t (enum) */ 381 #define SPD_KEY_PPR_GRAN "dram.ppr-gran" /* uint32_t (enum) */ 382 383 /* 384 * Voltages in mV. This is an array of nominal voltages that are supported. DDR3 385 * defines multiple voltages, but DDR4 and DDR5 only have a single voltage 386 * (specific to the supply). DDR3 and DDR4 only defined V~DD~ in SPD. While 387 * V~DQ~ and V~PP~ are defined in DDR5. 388 */ 389 #define SPD_KEY_NOM_VDD "dram.nominal-vdd" /* uint32_t[] */ 390 #define SPD_KEY_NOM_VDDQ "dram.nominal-vddq" /* uint32_t[] */ 391 #define SPD_KEY_NOM_VPP "dram.nominal-vpp" /* uint32_t[] */ 392 393 /* 394 * DRAM module organization. 395 * 396 * This describes the number of ranks that exist on a per-channel basis. In 397 * DDR4, there is only one channel and so this effectively covers the entire 398 * module. In DDR5 and LPDDR there are multiple channels or sub-channels. The 399 * rank mix may be symmetrical or asymmetrical. A key will be set if that's the 400 * case. 401 */ 402 #define SPD_KEY_RANK_ASYM "dram.asymmetrical-ranks" /* key */ 403 #define SPD_KEY_NRANKS "channel.num-ranks" /* uint32_t */ 404 405 /* 406 * DRAM and Module/Channel widths. 407 * 408 * A 'channel' refers to the entire interface between a memory 409 * controller and memory. In DDR4 there is only a single channel that covers the 410 * entire 72-bit (64-bit data, 8-bit ECC) bus. In DDR5 and LPDDR5 this is made 411 * up of a pair of sub-channels. In LPDDR3/4 the device exposed a number of 412 * channels, that are effecitvely similar in spirit to the DDR5 sub-channel. The 413 * channel keys below cover whatever the smallest defined unit is. For DDR4 (and 414 * earlier) this is the entire channel. For LPDDR3/4 these are the independent 415 * channels in the SPD spec and for DDR5 and LPDDR5 these are sub-channels. The 416 * channel width is split between a primary data and ECC size. 417 * 418 * In LPDDR3/4 a given DRAM die may support a varying number of channels. That 419 * is stored in the num-channels calculation and otherwise set to 1 for all 420 * other types of memory. 421 * 422 * Separately the individual DRAM dies themselves have a width which is 423 * SPD_KEY_DRAM_WIDTH. This is the portion of each die that contributes to the 424 * given channel. 425 */ 426 #define SPD_KEY_DRAM_WIDTH "dram.width" /* uint32_t */ 427 #define SPD_KEY_SEC_DRAM_WIDTH "dram.sec-width" /* uint32_t */ 428 #define SPD_KEY_DRAM_NCHAN "dram.num-channels" /* uint32_t */ 429 #define SPD_KEY_NSUBCHAN "module.num-subchan" /* uint32_t */ 430 #define SPD_KEY_DATA_WIDTH "channel.data-width" /* uint32_t */ 431 #define SPD_KEY_ECC_WIDTH "channel.ecc-width" /* uint32_t */ 432 433 /* 434 * LPDDR offers a notion of a 'byte mode' where half of the I/Os can be shared 435 * between multiple dies. This key is set when tihs is true. 436 */ 437 #define SPD_KEY_LP_BYTE_MODE "lp.byte-mode" /* key */ 438 439 /* 440 * LPDDR3-5 have a signal loading matrix that indicates the amount of load that 441 * is on different groups of signals. All values are a uint32_t of the count of 442 * loads. 443 */ 444 #define SPD_KEY_LP_LOAD_DSM "lp.load-data-strobe-mask" 445 #define SPD_KEY_LP_LOAD_CAC "lp.load-command-address-clock" 446 #define SPD_KEY_LP_LOAD_CS "lp.load-chip-select" 447 448 /* 449 * DDR3, DDR4, and LPDDR3-5/x specify specific timebases in the SPD data. DDR5 450 * just requires a specific timebase and therefore does not define these keys. 451 * This like all other time values is explicitly in ps. 452 */ 453 #define SPD_KEY_MTB "dram.median-time-base" /* uint32_t */ 454 #define SPD_KEY_FTB "dram.fine-time-base" /* uint32_t */ 455 456 /* 457 * Supported CAS Latencies. This is an array of integers to indicate which index 458 * CAS latencies are possible. 459 */ 460 #define SPD_KEY_CAS "dram.cas-latencies" /* uint32_t [] */ 461 462 /* 463 * Time parameters. These are all in picoseconds. All values are uint64_t. 464 */ 465 #define SPD_KEY_TCKAVG_MIN "dram.t~CKAVG~min" 466 #define SPD_KEY_TCKAVG_MAX "dram.t~CKAVG~max" 467 #define SPD_KEY_TAA_MIN "dram.t~AA~min" 468 #define SPD_KEY_TRCD_MIN "dram.t~RCD~min" 469 #define SPD_KEY_TRP_MIN "dram.t~RP~min" 470 #define SPD_KEY_TRAS_MIN "dram.t~RAS~min" 471 #define SPD_KEY_TRC_MIN "dram.t~RC~min" 472 #define SPD_KEY_TRFC1_MIN "dram.t~RFC1~min" 473 #define SPD_KEY_TRFC2_MIN "dram.t~RFC2~min" 474 #define SPD_KEY_TFAW "dram.t~FAW~" 475 #define SPD_KEY_TRRD_L_MIN "dram.t~RRD_L~min" 476 #define SPD_KEY_TCCD_L_MIN "dram.t~CCD_S~min" 477 #define SPD_KEY_TWR_MIN "dram.t~WR~min" 478 479 /* 480 * The following time are only used in DDR4. While some of the DDR4 and DDR5 481 * write to read or write to write parameters are similar, because they use 482 * different names for times, we distinguish them as different values. 483 */ 484 #define SPD_KEY_TRFC4_MIN "dram.t~RFC4~min" 485 #define SPD_KEY_TRRD_S_MIN "dram.t~RRD_S~min" 486 #define SPD_KEY_TWTRS_MIN "dram.t~WTR_S~min" 487 #define SPD_KEY_TWTRL_MIN "dram.t~WTR_L~min" 488 489 /* 490 * The following times are specific to DDR5. t~CCD_L_WTR~ in DDR5 is the 491 * equivalent to t~WTRS_L~min, same with t~CCD_S_WTR~. 492 */ 493 #define SPD_KEY_TCCDLWR "dram.t~CCD_L_WR" 494 #define SPD_KEY_TCCDLWR2 "dram.t~CCD_L_WR2" 495 #define SPD_KEY_TCCDLWTR "dram.t~CCD_L_WTR" 496 #define SPD_KEY_TCCDSWTR "dram.t~CCD_S_WTR" 497 #define SPD_KEY_TRTP "dram.t~RTP~" 498 #define SPD_KEY_TCCDM "dram.t~CCD_M~" 499 #define SPD_KEY_TCCDMWR "dram.t~CCD_M_WR~" 500 #define SPD_KEY_TCCDMWTR "dram.t~CCD_M_WTR~" 501 502 /* 503 * While prior DDR standards did have minimum clock times for certain 504 * activities, these were first added to the SPD data in DDR5. All values for 505 * these are uint32_t's and are in clock cycles. 506 */ 507 #define SPD_KEY_TRRD_L_NCK "dram.t~RRD_L~nCK" 508 #define SPD_KEY_TCCD_L_NCK "dram.t~CCD_L~nCK" 509 #define SPD_KEY_TCCDLWR_NCK "dram.t~CCD_L_WR~nCK" 510 #define SPD_KEY_TCCDLWR2_NCK "dram.t~CCD_L_WR2~nCK" 511 #define SPD_KEY_TFAW_NCK "dram.t~FAW~nCK" 512 #define SPD_KEY_TCCDLWTR_NCK "dram.t~CCD_L_WTR~nCK" 513 #define SPD_KEY_TCCDSWTR_NCK "dram.t~CCD_S_WTR~nCK" 514 #define SPD_KEY_TRTP_NCK "dram.t~RTP~nCK" 515 #define SPD_KEY_TCCDM_NCK "dram.t~CCD_M~nCK" 516 #define SPD_KEY_TCCDMWR_NCK "dram.t~CCD_M_WR~nCK" 517 #define SPD_KEY_TCCDMWTR_NCK "dram.t~CCD_M_WTR~nCK" 518 519 /* 520 * The following times are only used in DDR5. The RFCx_dlr values are for 3DS 521 * RDIMMs. 522 */ 523 #define SPD_KEY_TRFCSB "dram.t~RFCsb~" 524 #define SPD_KEY_TRFC1_DLR "dram.3ds-t~RFC1_dlr~" 525 #define SPD_KEY_TRFC2_DLR "dram.3ds-t~RFC2_dlr~" 526 #define SPD_KEY_TRFCSB_DLR "dram.3ds-t~RFCsb_dlr~" 527 528 /* 529 * The following times are only used by LPDDR3-5, but like other variable timing 530 * entries, we still use the "dram" prefix. These are per-bank and all bank row 531 * precharges and minimum refresh recovery times. 532 */ 533 #define SPD_KEY_TRPAB_MIN "dram.t~RPab~" 534 #define SPD_KEY_TRPPB_MIN "dram.t~RPpb~" 535 #define SPD_KEY_TRFCAB_MIN "dram.t~RFCab~" 536 #define SPD_KEY_TRFCPB_MIN "dram.t~RFCpb~" 537 538 /* 539 * These refer to the maximum activate window and the maximum activate count. In 540 * cases where the MAC is unknown no key will be present. This was present in 541 * DDR and LPDDR 3 and 4. It is no longer present in DDR and LPDDR4 5 and 542 * therefore will not be present for those. 543 */ 544 #define SPD_KEY_MAW "dram.maw" /* uint32_t */ 545 #define SPD_KEY_MAC "dram.mac" /* uint32_t */ 546 #define SPD_KEY_MAC_UNLIMITED UINT32_MAX 547 548 /* 549 * LPDDR3/4/4X have specific latency sets. The following enum, stored as a u32 550 * contains these options. 551 */ 552 typedef enum { 553 SPD_LP_RWLAT_WRITE_A = 1 << 0, 554 SPD_LP_RWLAT_WRITE_B = 1 << 1, 555 SPD_LP_RWLAT_DBIRD_EN = 1 << 2 556 } spd_lp_rwlat_t; 557 #define SPD_KEY_LP_RWLAT "lp.read-write-latency" /* uint32_t */ 558 559 /* 560 * Partial Automatic self-refresh (PASR) was introduced in DDR3 and continued in 561 * DDR5. Automatic self-refresh (ASR) was only in DDR3. We treat it as a part of 562 * the other DDR3 assorted features. The last DDR3 specific thing is the 563 * extended temperature fresh rate. 564 */ 565 #define SPD_KEY_DDR_PASR "dram.pasr" /* key */ 566 typedef enum { 567 SPD_DDR3_FEAT_ASR = 1 << 0, 568 SPD_DDR3_FEAT_DLL_OFF = 1 << 1, 569 SPD_DDR3_FEAT_RZQ_7 = 1 << 2, 570 SPD_DDR3_FEAT_RZQ_6 = 1 << 3 571 } spd_ddr3_feat_t; 572 #define SPD_KEY_DDR3_FEAT "ddr3.asr" /* uint32_t */ 573 #define SPD_KEY_DDR3_XTRR "ddr3.xt-refresh-rate" /* uint32_t */ 574 575 /* 576 * The following are DDR5 specific properties. BL32 indicates whether burst 577 * length 32 mode is supported, which is a key. Along with the partial array 578 * self refresh. The Duty Cycle Adjuster is an enumeration because there are 579 * multiple modes. The wide temperature sensing is another DDR5 bit represented 580 * as a key as well as an enum of fault handling. 581 */ 582 #define SPD_KEY_DDR5_BL32 "ddr5.bl32" /* key */ 583 typedef enum { 584 SPD_DCA_UNSPPORTED, 585 SPD_DCA_1_OR_2_PHASE, 586 SPD_DCA_4_PHASE 587 } spd_dca_t; 588 #define SPD_KEY_DDR5_DCA "ddr5.dca" /* uint32_t */ 589 #define SPD_KEY_DDR5_WIDE_TS "ddr5.wide-temp-sense" /* key */ 590 typedef enum { 591 SPD_FLT_BOUNDED = 1 << 0, 592 SPD_FLT_WRSUP_MR9 = 1 << 1, 593 SPD_FLT_WRSUP_MR15 = 1 << 2 594 } spd_fault_t; 595 #define SPD_KEY_DDR5_FLT "ddr5.fault-handling" /* uint32_t */ 596 #define SPD_KEY_DDR5_PRAC "ddr5.per-row-act-count" /* key */ 597 598 /* 599 * DDR5 allows for non-standard core timing options. This is indicated by a 600 * single key that acts as a flag. 601 */ 602 #define SPD_KEY_DDR5_NONSTD_TIME "ddr5.non-standard-timing" /* key */ 603 604 /* 605 * DDR5 adds information about refresh management. This is split into 606 * information about general refresh management and then optional adaptive 607 * refresh management. There are three levels of adaptive refresh management 608 * titled A, B, and C. Both the general refresh management and the adaptive 609 * refresh management exist for both the primary and secondary types in 610 * asymmetrical modules. Information about the RAAIMT and RAAMMT is only present 611 * if refresh management is required. Similarly, BRC information is only present 612 * if DRFM is supported. All values here are uint32_t's. 613 */ 614 typedef enum { 615 SPD_RFM_F_REQUIRED = 1 << 0, 616 SPD_RFM_F_DRFM_SUP = 1 << 1, 617 } spd_rfm_flags_t; 618 #define SPD_KEY_DDR5_RFM_FLAGS_PRI "ddr5.rfm.flags" 619 #define SPD_KEY_DDR5_RFM_RAAIMT_PRI "ddr5.rfm.raaimt" 620 #define SPD_KEY_DDR5_RFM_RAAIMT_FGR_PRI "ddr5.rfm.raaimt-fgr" 621 #define SPD_KEY_DDR5_RFM_RAAMMT_PRI "ddr5.rfm.raammt" 622 #define SPD_KEY_DDR5_RFM_RAAMMT_FGR_PRI "ddr5.rfm.raammt-fgr" 623 #define SPD_KEY_DDR5_RFM_BRC_CFG_PRI "ddr5.rfm.brc-config" 624 625 typedef enum { 626 SPD_BRC_F_LVL_2 = 1 << 0, 627 SPD_BRC_F_LVL_3 = 1 << 1, 628 SPD_BRC_F_LVL_4 = 1 << 2 629 } spd_brc_flags_t; 630 #define SPD_KEY_DDR5_RFM_BRC_SUP_PRI "ddr5.rfm.brc-level" 631 #define SPD_KEY_DDR5_RFM_RAA_DEC_PRI "ddr5.rfm.raa-dec" 632 #define SPD_KEY_DDR5_RFM_FLAGS_SEC "ddr5.rfm.sec-flags" 633 #define SPD_KEY_DDR5_RFM_RAAIMT_SEC "ddr5.rfm.sec-raaimt" 634 #define SPD_KEY_DDR5_RFM_RAAIMT_FGR_SEC "ddr5.rfm.sec-raaimt-fgr" 635 #define SPD_KEY_DDR5_RFM_RAAMMT_SEC "ddr5.rfm.sec-raammt" 636 #define SPD_KEY_DDR5_RFM_RAAMMT_FGR_SEC "ddr5.rfm.sec-raammt-fgr" 637 #define SPD_KEY_DDR5_RFM_BRC_CFG_SEC "ddr5.rfm.sec-brc-config" 638 #define SPD_KEY_DDR5_RFM_BRC_SUP_SEC "ddr5.rfm.sec-brc-level" 639 #define SPD_KEY_DDR5_RFM_RAA_DEC_SEC "ddr5.rfm.sec-raa-dec" 640 641 #define SPD_KEY_DDR5_ARFMA_FLAGS_PRI "ddr5.arfm-a.flags" 642 #define SPD_KEY_DDR5_ARFMA_RAAIMT_PRI "ddr5.arfm-a.raaimt" 643 #define SPD_KEY_DDR5_ARFMA_RAAIMT_FGR_PRI "ddr5.arfm-a.raaimt-fgr" 644 #define SPD_KEY_DDR5_ARFMA_RAAMMT_PRI "ddr5.arfm-a.raammt" 645 #define SPD_KEY_DDR5_ARFMA_RAAMMT_FGR_PRI "ddr5.arfm-a.raammt-fgr" 646 #define SPD_KEY_DDR5_ARFMA_BRC_CFG_PRI "ddr5.arfm-a.brc-config" 647 #define SPD_KEY_DDR5_ARFMA_BRC_SUP_PRI "ddr5.arfm-a.brc-level" 648 #define SPD_KEY_DDR5_ARFMA_RAA_DEC_PRI "ddr5.arfm-a.raa-dec" 649 #define SPD_KEY_DDR5_ARFMA_FLAGS_SEC "ddr5.arfm-a.sec-flags" 650 #define SPD_KEY_DDR5_ARFMA_RAAIMT_SEC "ddr5.arfm-a.sec-raaimt" 651 #define SPD_KEY_DDR5_ARFMA_RAAIMT_FGR_SEC "ddr5.arfm-a.sec-raaimt-fgr" 652 #define SPD_KEY_DDR5_ARFMA_RAAMMT_SEC "ddr5.arfm-a.sec-raammt" 653 #define SPD_KEY_DDR5_ARFMA_RAAMMT_FGR_SEC "ddr5.arfm-a.sec-raammt-fgr" 654 #define SPD_KEY_DDR5_ARFMA_BRC_CFG_SEC "ddr5.arfm-a.sec-brc-config" 655 #define SPD_KEY_DDR5_ARFMA_BRC_SUP_SEC "ddr5.arfm-a.sec-brc-level" 656 #define SPD_KEY_DDR5_ARFMA_RAA_DEC_SEC "ddr5.arfm-a.sec-raa-dec" 657 658 #define SPD_KEY_DDR5_ARFMB_FLAGS_PRI "ddr5.arfm-b.flags" 659 #define SPD_KEY_DDR5_ARFMB_RAAIMT_PRI "ddr5.arfm-b.raaimt" 660 #define SPD_KEY_DDR5_ARFMB_RAAIMT_FGR_PRI "ddr5.arfm-b.raaimt-fgr" 661 #define SPD_KEY_DDR5_ARFMB_RAAMMT_PRI "ddr5.arfm-b.raammt" 662 #define SPD_KEY_DDR5_ARFMB_RAAMMT_FGR_PRI "ddr5.arfm-b.raammt-fgr" 663 #define SPD_KEY_DDR5_ARFMB_BRC_CFG_PRI "ddr5.arfm-b.brc-config" 664 #define SPD_KEY_DDR5_ARFMB_BRC_SUP_PRI "ddr5.arfm-b.brc-level" 665 #define SPD_KEY_DDR5_ARFMB_RAA_DEC_PRI "ddr5.arfm-b.raa-dec" 666 #define SPD_KEY_DDR5_ARFMB_FLAGS_SEC "ddr5.arfm-b.sec-flags" 667 #define SPD_KEY_DDR5_ARFMB_RAAIMT_SEC "ddr5.arfm-b.sec-raaimt" 668 #define SPD_KEY_DDR5_ARFMB_RAAIMT_FGR_SEC "ddr5.arfm-b.sec-raaimt-fgr" 669 #define SPD_KEY_DDR5_ARFMB_RAAMMT_SEC "ddr5.arfm-b.sec-raammt" 670 #define SPD_KEY_DDR5_ARFMB_RAAMMT_FGR_SEC "ddr5.arfm-b.sec-raammt-fgr" 671 #define SPD_KEY_DDR5_ARFMB_BRC_CFG_SEC "ddr5.arfm-b.sec-brc-config" 672 #define SPD_KEY_DDR5_ARFMB_BRC_SUP_SEC "ddr5.arfm-b.sec-brc-level" 673 #define SPD_KEY_DDR5_ARFMB_RAA_DEC_SEC "ddr5.arfm-b.sec-raa-dec" 674 675 #define SPD_KEY_DDR5_ARFMC_FLAGS_PRI "ddr5.arfm-c.flags" 676 #define SPD_KEY_DDR5_ARFMC_RAAIMT_PRI "ddr5.arfm-c.raaimt" 677 #define SPD_KEY_DDR5_ARFMC_RAAIMT_FGR_PRI "ddr5.arfm-c.raaimt-fgr" 678 #define SPD_KEY_DDR5_ARFMC_RAAMMT_PRI "ddr5.arfm-c.raammt" 679 #define SPD_KEY_DDR5_ARFMC_RAAMMT_FGR_PRI "ddr5.arfm-c.raammt-fgr" 680 #define SPD_KEY_DDR5_ARFMC_BRC_CFG_PRI "ddr5.arfm-c.brc-config" 681 #define SPD_KEY_DDR5_ARFMC_BRC_SUP_PRI "ddr5.arfm-c.brc-level" 682 #define SPD_KEY_DDR5_ARFMC_RAA_DEC_PRI "ddr5.arfm-c.raa-dec" 683 #define SPD_KEY_DDR5_ARFMC_FLAGS_SEC "ddr5.arfm-c.sec-flags" 684 #define SPD_KEY_DDR5_ARFMC_RAAIMT_SEC "ddr5.arfm-c.sec-raaimt" 685 #define SPD_KEY_DDR5_ARFMC_RAAIMT_FGR_SEC "ddr5.arfm-c.sec-raaimt-fgr" 686 #define SPD_KEY_DDR5_ARFMC_RAAMMT_SEC "ddr5.arfm-c.sec-raammt" 687 #define SPD_KEY_DDR5_ARFMC_RAAMMT_FGR_SEC "ddr5.arfm-c.sec-raammt-fgr" 688 #define SPD_KEY_DDR5_ARFMC_BRC_CFG_SEC "ddr5.arfm-c.sec-brc-config" 689 #define SPD_KEY_DDR5_ARFMC_BRC_SUP_SEC "ddr5.arfm-c.sec-brc-level" 690 #define SPD_KEY_DDR5_ARFMC_RAA_DEC_SEC "ddr5.arfm-c.sec-raa-dec" 691 /* 692 * Module-type specific keys and values. These are often the intersection of 693 * both the DDR standard and the module type. That is, a DDR4 and DDR5 RDIMM 694 * expose some information that isn't quite the same. These often contain things 695 * that are drive strengths and slew rates. These kinds of items fall into two 696 * categories. Ones where there is a fixed resistance and one where there is a 697 * qualitative range that depends on things like the specific parts present. 698 */ 699 typedef enum { 700 SPD_DRIVE_LIGHT, 701 SPD_DRIVE_MODERATE, 702 SPD_DRIVE_STRONG, 703 SPD_DRIVE_VERY_STRONG, 704 SPD_DRIVE_WEAK 705 } spd_drive_t; 706 707 typedef enum { 708 SPD_SLEW_SLOW, 709 SPD_SLEW_MODERATE, 710 SPD_SLEW_FAST 711 } spd_slew_t; 712 713 /* 714 * DDR4 RDIMM and LRDIMM drive strengths. These all use the spd_drive_t. These 715 * are all on the RCD. There is also a key for whether or not slew-control is 716 * supported. 717 * 718 * DDR3 has similar, but not identical drive strengths. Rather than trying to 719 * combine them awkwardly, we just have a separate set of definitions. These may 720 * be made more uniform in the future. In DDR3 the LRDIMM does not incorporate a 721 * register like in DDR4, therefore the MB has overlapping drive strength keys. 722 */ 723 #define SPD_KEY_DDR3_RCD_DS_CAA "ddr3.rcd.ca-a-drive-strength" 724 #define SPD_KEY_DDR3_RCD_DS_CAB "ddr3.rcd.ca-b-drive-strength" 725 #define SPD_KEY_DDR3_RCD_DS_CTLA "ddr3.rcd.cs-a-drive-strength" 726 #define SPD_KEY_DDR3_RCD_DS_CTLB "ddr3.rcd.cs-b-drive-strength" 727 #define SPD_KEY_DDR3_RCD_DS_Y0 "ddr3.rcd.y0-drive-strength" 728 #define SPD_KEY_DDR3_RCD_DS_Y1 "ddr3.rcd.y1-drive-strength" 729 730 #define SPD_KEY_DDR3_MB_DS_Y0 "ddr3.mb.y0-drive-strength" 731 #define SPD_KEY_DDR3_MB_DS_Y1 "ddr3.mb.y1-drive-strength" 732 #define SPD_KEY_DDR3_MB_DS_CKE "ddr3.mb.cke-drive-strength" 733 #define SPD_KEY_DDR3_MB_DS_ODT "ddr3.mb.cke-drive-strength" 734 #define SPD_KEY_DDR3_MB_DS_CS "ddr3.mb.cs-drive-strength" 735 #define SPD_KEY_DDR3_MB_DS_CA "ddr3.mb.ca-drive-strength" 736 737 #define SPD_KEY_DDR4_RCD_SLEW "ddr4.rcd.rcd-slew-control" /* key */ 738 #define SPD_KEY_DDR4_RCD_DS_CKE "ddr4.rcd.cke-drive-strength" 739 #define SPD_KEY_DDR4_RCD_DS_ODT "ddr4.rcd.odt-drive-strength" 740 #define SPD_KEY_DDR4_RCD_DS_CA "ddr4.rcd.ca-drive-strength" 741 #define SPD_KEY_DDR4_RCD_DS_CS "ddr4.rcd.cs-drive-strength" 742 #define SPD_KEY_DDR4_RCD_DS_Y0 "ddr4.rcd.y0-drive-strength" 743 #define SPD_KEY_DDR4_RCD_DS_Y1 "ddr4.rcd.y1-drive-strength" 744 #define SPD_KEY_DDR4_RCD_DS_BCOM "ddr4.rcd.bcom-drive-strength" 745 #define SPD_KEY_DDR4_RCD_DS_BCK "ddr4.rcd.bck-drive-strength" 746 747 /* 748 * DDR3 LRDIMMs have the ability to specify the orientation of the memory 749 * buffer. These describe the physical orientation relative to the edge 750 * connector. 751 */ 752 typedef enum { 753 SPD_ORNT_HORIZONTAL, 754 SPD_ORNT_VERTICAL 755 } spd_orientation_t; 756 #define SPD_KEY_DDR3_MB_ORIENT "ddr3.mb.orientation" /* uint32_t */ 757 758 /* 759 * DDR3 LRDIMMs have various extended and additive clock delays for various 760 * signals. The extended delay is x/128 * tCK while the additive delay is x/32 * 761 * tCK. We store these all as uint32_t keys where the value is the value of x 762 * above. If there is no delay or the delay is not enabled, then the key will 763 * not exist. 764 */ 765 #define SPD_KEY_DDR3_MB_EXTD_Y "ddr4.mb.y-extended-delay" 766 #define SPD_KEY_DDR3_MB_EXTD_CS "ddr4.mb.cs-extended-delay" 767 #define SPD_KEY_DDR3_MB_EXTD_ODT "ddr4.mb.odt-extended-delay" 768 #define SPD_KEY_DDR3_MB_EXTD_CKE "ddr4.mb.cke-extended-delay" 769 #define SPD_KEY_DDR3_MB_ADDD_Y "ddr4.mb.y-additive-delay" 770 #define SPD_KEY_DDR3_MB_ADDD_CS "ddr4.mb.cs-additive-delay" 771 #define SPD_KEY_DDR3_MB_ADDD_ODT "ddr4.mb.odt-additive-delay" 772 #define SPD_KEY_DDR3_MB_ADDD_CKE "ddr4.mb.cke-additive-delay" 773 774 /* 775 * DDR3 LRDIMMs have the ability to control whether or not QxODT[1:0] is 776 * asserted during reads or writes on each rank. There is a value for each of 777 * the three primary speed buckets in DDR3: 800/1066, 1333/1600, and 778 * 1866/2133. This is organized as a series of boolean_t[3] entries where each 779 * entry corresponds to one of the three speeds. 780 */ 781 #define SPD_KEY_DDR3_MB_R0_ODT0_RD "ddr3.mb.r0-qxodt0-read-assert" 782 #define SPD_KEY_DDR3_MB_R0_ODT1_RD "ddr3.mb.r0-qxodt1-read-assert" 783 #define SPD_KEY_DDR3_MB_R0_ODT0_WR "ddr3.mb.r0-qxodt0-write-assert" 784 #define SPD_KEY_DDR3_MB_R0_ODT1_WR "ddr3.mb.r0-qxodt1-write-assert" 785 #define SPD_KEY_DDR3_MB_R1_ODT0_RD "ddr3.mb.r1-qxodt0-read-assert" 786 #define SPD_KEY_DDR3_MB_R1_ODT1_RD "ddr3.mb.r1-qxodt1-read-assert" 787 #define SPD_KEY_DDR3_MB_R1_ODT0_WR "ddr3.mb.r1-qxodt0-write-assert" 788 #define SPD_KEY_DDR3_MB_R1_ODT1_WR "ddr3.mb.r1-qxodt1-write-assert" 789 #define SPD_KEY_DDR3_MB_R2_ODT0_RD "ddr3.mb.r2-qxodt0-read-assert" 790 #define SPD_KEY_DDR3_MB_R2_ODT1_RD "ddr3.mb.r2-qxodt1-read-assert" 791 #define SPD_KEY_DDR3_MB_R2_ODT0_WR "ddr3.mb.r2-qxodt0-write-assert" 792 #define SPD_KEY_DDR3_MB_R2_ODT1_WR "ddr3.mb.r2-qxodt1-write-assert" 793 #define SPD_KEY_DDR3_MB_R3_ODT0_RD "ddr3.mb.r3-qxodt0-read-assert" 794 #define SPD_KEY_DDR3_MB_R3_ODT1_RD "ddr3.mb.r3-qxodt1-read-assert" 795 #define SPD_KEY_DDR3_MB_R3_ODT0_WR "ddr3.mb.r3-qxodt0-write-assert" 796 #define SPD_KEY_DDR3_MB_R3_ODT1_WR "ddr3.mb.r3-qxodt1-write-assert" 797 #define SPD_KEY_DDR3_MB_R4_ODT0_RD "ddr3.mb.r4-qxodt0-read-assert" 798 #define SPD_KEY_DDR3_MB_R4_ODT1_RD "ddr3.mb.r4-qxodt1-read-assert" 799 #define SPD_KEY_DDR3_MB_R4_ODT0_WR "ddr3.mb.r4-qxodt0-write-assert" 800 #define SPD_KEY_DDR3_MB_R4_ODT1_WR "ddr3.mb.r4-qxodt1-write-assert" 801 #define SPD_KEY_DDR3_MB_R5_ODT0_RD "ddr3.mb.r5-qxodt0-read-assert" 802 #define SPD_KEY_DDR3_MB_R5_ODT1_RD "ddr3.mb.r5-qxodt1-read-assert" 803 #define SPD_KEY_DDR3_MB_R5_ODT0_WR "ddr3.mb.r5-qxodt0-write-assert" 804 #define SPD_KEY_DDR3_MB_R5_ODT1_WR "ddr3.mb.r5-qxodt1-write-assert" 805 #define SPD_KEY_DDR3_MB_R6_ODT0_RD "ddr3.mb.r6-qxodt0-read-assert" 806 #define SPD_KEY_DDR3_MB_R6_ODT1_RD "ddr3.mb.r6-qxodt1-read-assert" 807 #define SPD_KEY_DDR3_MB_R6_ODT0_WR "ddr3.mb.r6-qxodt0-write-assert" 808 #define SPD_KEY_DDR3_MB_R6_ODT1_WR "ddr3.mb.r6-qxodt1-write-assert" 809 #define SPD_KEY_DDR3_MB_R7_ODT0_RD "ddr3.mb.r7-qxodt0-read-assert" 810 #define SPD_KEY_DDR3_MB_R7_ODT1_RD "ddr3.mb.r7-qxodt1-read-assert" 811 #define SPD_KEY_DDR3_MB_R7_ODT0_WR "ddr3.mb.r7-qxodt0-write-assert" 812 #define SPD_KEY_DDR3_MB_R7_ODT1_WR "ddr3.mb.r7-qxodt1-write-assert" 813 814 /* 815 * DDR4 LRDIMMs specify the VrefDQ for each package rank. These are communicated 816 * in terms of the DDR4 spec which specifies them as a percentage of the actual 817 * voltage. This is always phrased in the spec as AB.CD%, so for example 60.25%. 818 * We treat this percentage as a four digit unsigned value rather than trying to 819 * play games with whether or not the value can be represented in floating 820 * point. Divide the value by 100 to get the percentage. That is, 47.60% will be 821 * encoded as 4760. All of these values are a uint32_t. 822 */ 823 #define SPD_KEY_DDR4_VREFDQ_R0 "ddr4.lrdimm.VrefDQ-rank0" 824 #define SPD_KEY_DDR4_VREFDQ_R1 "ddr4.lrdimm.VrefDQ-rank1" 825 #define SPD_KEY_DDR4_VREFDQ_R2 "ddr4.lrdimm.VrefDQ-rank2" 826 #define SPD_KEY_DDR4_VREFDQ_R3 "ddr4.lrdimm.VrefDQ-rank3" 827 #define SPD_KEY_DDR4_VREFDQ_DB "ddr4.lrdimm.VrefDQ-db" 828 829 /* 830 * DDR4 LRDIMMs define the data buffer drive strength and termination in terms 831 * of various data rate ranges. Specifically (0, 1866], (1866, 2400], and (2400, 832 * 3200]. All of these values are measured in terms of Ohms. As such, all of 833 * these values are an array of three uint32_t's whose values correspond to each 834 * of those ranges. We define a few additional values for these to represent 835 * cases where they are disabled or high-impedance. 836 * 837 * DDR3 LRDIMMs are similar, but their groups are 800/1066, 1333/1600, and 838 * 1866/2133. 839 */ 840 #define SPD_TERM_DISABLED 0 841 #define SPD_TERM_HIZ UINT32_MAX 842 #define SPD_KEY_DDR4_MDQ_RTT "ddr4.lrdimm.mdq-read-termination" 843 #define SPD_KEY_DDR4_MDQ_DS "ddr4.lrdimm.mdq-drive-strength" 844 #define SPD_KEY_DDR4_DRAM_DS "ddr4.lrdimm.dram-drive-strength" 845 #define SPD_KEY_DDR4_RTT_WR "ddr4.lrdimm.odt-read-termination-wr" 846 #define SPD_KEY_DDR4_RTT_NOM "ddr4.lrdimm.odt-read-termination-nom" 847 #define SPD_KEY_DDR4_RTT_PARK_R0 "ddr4.lrdimm.odt-r0_1-rtt-park" 848 #define SPD_KEY_DDR4_RTT_PARK_R2 "ddr4.lrdimm.odt-r2_3-rtt-park" 849 850 #define SPD_KEY_DDR3_MDQ_DS "ddr3.lrdimm.mdq-drive-strength" 851 #define SPD_KEY_DDR3_MDQ_ODT "ddr3.lrdimm.mdq-odt-strength" 852 #define SPD_KEY_DDR3_RTT_WRT "ddr3.lrdimm.mdq-odt-read-termination-wr" 853 #define SPD_KEY_DDR3_RTT_NOM "ddr3.lrdimm.mdq-odt-read-termination-nom" 854 #define SPD_KEY_DDR3_DRAM_DS "ddr3.lrdimm.dram-drive-strength" 855 856 /* 857 * DDR3 LRDIMMs specify a minimum and maximum delay for the various supported 858 * voltage types. These are stored as two uint64_t[3] arrays ordered as 1.25, 859 * 1.35, and 1.5V. These are times in ps. 860 */ 861 #define SPD_KEY_DDR3_MOD_MIN_DELAY "ddr3.lrdimm.minimum-module-delay" 862 #define SPD_KEY_DDR3_MOD_MAX_DELAY "ddr3.lrdimm.maximum-module-delay" 863 864 /* 865 * DDR3 LRDIMMs also have personality bytes that are loaded directly into the 866 * memory buffer control words. We pass these through as a uint8_t[15]. 867 */ 868 #define SPD_KEY_DDR3_MB_PERS "ddr3.lrdimm.personality" 869 870 /* 871 * The last DDR4 LRDIMM specific component is whether or not the data buffer's 872 * gain and decision feedback equalization are supported. These both are keys. 873 */ 874 #define SPD_KEY_DDR4_DB_GAIN "ddr4.lrdimm.db-gain-adjustment" 875 #define SPD_KEY_DDR4_DB_DFE "ddr4.lrdimm.decision-feedback-eq" 876 877 /* 878 * DDR5 RDIMMs and LRDIMMs have specific enables for groups of pins. There are 879 * then drive strength values which are encoded as a spd_drive_t. Note, prior to 880 * DDR5 RDIMMs v1.1, these were differential impedance values measured in Ohms. 881 * These have been normalized to the general drive strength enums. Separately 882 * there are slew rates, those use the spd_slew_t. Because these use different 883 * units between DDR4 and DDR5, we treat them as different keys. 884 */ 885 #define SPD_KEY_DDR5_RCD_QACK_EN "ddr5.rcd.qack-enabled" 886 #define SPD_KEY_DDR5_RCD_QBCK_EN "ddr5.rcd.qbck-enabled" 887 #define SPD_KEY_DDR5_RCD_QCCK_EN "ddr5.rcd.qcck-enabled" 888 #define SPD_KEY_DDR5_RCD_QDCK_EN "ddr5.rcd.qdck-enabled" 889 #define SPD_KEY_DDR5_RCD_BCK_EN "ddr5.rcd.bck-enabled" 890 #define SPD_KEY_DDR5_RCD_QACA_EN "ddr5.rcd.qaca-enabled" 891 #define SPD_KEY_DDR5_RCD_QBCA_EN "ddr5.rcd.qbca-enabled" 892 #define SPD_KEY_DDR5_RCD_QxCS_EN "ddr5.rcd.qxcs-enabled" 893 #define SPD_KEY_DDR5_RCD_QxCA13_EN "ddr5.rcd.qxca13-enabled" 894 #define SPD_KEY_DDR5_RCD_QACS_EN "ddr5.rcd.qacs-enabled" 895 #define SPD_KEY_DDR5_RCD_QBCS_EN "ddr5.rcd.qbcs-enabled" 896 897 /* Drive strengths use the spd_drive_t encoded as a uint32_t */ 898 #define SPD_KEY_DDR5_RCD_QACK_DS "ddr5.rcd.qack-drive-strength" 899 #define SPD_KEY_DDR5_RCD_QBCK_DS "ddr5.rcd.qbck-drive-strength" 900 #define SPD_KEY_DDR5_RCD_QCCK_DS "ddr5.rcd.qcck-drive-strength" 901 #define SPD_KEY_DDR5_RCD_QDCK_DS "ddr5.rcd.qdck-drive-strength" 902 #define SPD_KEY_DDR5_RCD_QxCS_DS "ddr5.rcd.qxcs-drive-strength" 903 #define SPD_KEY_DDR5_RCD_CA_DS "ddr5.rcd.ca-drive-strength" 904 905 /* Slew rates use the spd_rate_t encoded as a uint32_t */ 906 #define SPD_KEY_DDR5_RCD_QCK_SLEW "ddr5.rcd.qck-slew" 907 #define SPD_KEY_DDR5_RCD_QCA_SLEW "ddr5.rcd.qca-slew" 908 #define SPD_KEY_DDR5_RCD_QCS_SLEW "ddr5.rcd.qcs-slew" 909 910 /* 911 * These are all specific to DDR5 LRDIMMs. The values are the same as above. The 912 * RTT value is a value in Ohms. If RTT termination is disabled then the key 913 * will not be present. 914 */ 915 #define SPD_KEY_DDR5_RCD_BCS_EN "ddr5.rcd.bcs-enabled" /* key */ 916 #define SPD_KEY_DDR5_RCD_BCOM_DS "ddr5.rcd.bcom-drive-strength" 917 #define SPD_KEY_DDR5_RCD_BCK_DS "ddr5.rcd.bck-drive-strength" 918 #define SPD_KEY_DDR5_RCD_RTT_TERM "ddr5.rcd.dqs-rtt" 919 #define SPD_KEY_DDR5_RCD_BCOM_SLEW "ddr5.rcd.bcom-slew" 920 #define SPD_KEY_DDR5_RCD_BCK_SLEW "ddr5.rcd.bck-slew" 921 922 /* 923 * DDR5 UDIMM specific values. Note, these are only present in UDIMM v1.1 and 924 * therefore may be missing in older revisions. 925 */ 926 927 /* 928 * Unbuffered clock configuration, drivers, and slew rates. The various -enabled 929 * values are keys. The drive strengths and slew rates use the spd_drive_t and 930 * spd_slew_t respectively encoded as uint32_t values. 931 */ 932 #define SPD_KEY_DDR5_CKD_CHAQCK0_EN "ddr5.ckd.cha-qck0_A-enabled" 933 #define SPD_KEY_DDR5_CKD_CHAQCK1_EN "ddr5.ckd.cha-qck1_A-enabled" 934 #define SPD_KEY_DDR5_CKD_CHBQCK0_EN "ddr5.ckd.chb-qck0_B-enabled" 935 #define SPD_KEY_DDR5_CKD_CHBQCK1_EN "ddr5.ckd.chb-qck1_B-enabled" 936 #define SPD_KEY_DDR5_CKD_CHAQCK0_DS "ddr5.ckd.cha-qck0_A-drive-strength" 937 #define SPD_KEY_DDR5_CKD_CHAQCK1_DS "ddr5.ckd.cha-qck1_A-drive-strength" 938 #define SPD_KEY_DDR5_CKD_CHBQCK0_DS "ddr5.ckd.chb-qck0_B-drive-strength" 939 #define SPD_KEY_DDR5_CKD_CHBQCK1_DS "ddr5.ckd.chb-qck1_B-drive-strength" 940 #define SPD_KEY_DDR5_CKD_CHAQCK_SLEW "ddr5.ckd.cha-qck_slew" 941 #define SPD_KEY_DDR5_CKD_CHBQCK_SLEW "ddr5.ckd.chb-qck_slew" 942 943 /* 944 * DDR5/LPDDR5 CAMM2 specific values. There are two groups of additions for 945 * CAMM2. For DDR5 devices, CAMM2 v1.1 adds the same set of clock output devices 946 * that UDIMMs with clocks add. There are two clock drivers present so it uses 947 * the existing values for ckd0 and then a new set for ckd1 to minimize parsing 948 * differences. In CAMM2 Annex version 1.2 the nominal capacitance is defined 949 * for both DDR5 and LPDDR5. 950 */ 951 #define SPD_KEY_DDR5_CKD1_CHAQCK0_EN "ddr5.ckd1.cha-qck0_A-enabled" 952 #define SPD_KEY_DDR5_CKD1_CHAQCK1_EN "ddr5.ckd1.cha-qck1_A-enabled" 953 #define SPD_KEY_DDR5_CKD1_CHBQCK0_EN "ddr5.ckd1.chb-qck0_B-enabled" 954 #define SPD_KEY_DDR5_CKD1_CHBQCK1_EN "ddr5.ckd1.chb-qck1_B-enabled" 955 #define SPD_KEY_DDR5_CKD1_CHAQCK0_DS "ddr5.ckd1.cha-qck0_A-drive-strength" 956 #define SPD_KEY_DDR5_CKD1_CHAQCK1_DS "ddr5.ckd1.cha-qck1_A-drive-strength" 957 #define SPD_KEY_DDR5_CKD1_CHBQCK0_DS "ddr5.ckd1.chb-qck0_B-drive-strength" 958 #define SPD_KEY_DDR5_CKD1_CHBQCK1_DS "ddr5.ckd1.chb-qck1_B-drive-strength" 959 #define SPD_KEY_DDR5_CKD1_CHAQCK_SLEW "ddr5.ckd1.cha-qck_slew" 960 #define SPD_KEY_DDR5_CKD1_CHBQCK_SLEW "ddr5.ckd1.chb-qck_slew" 961 962 /* 963 * The module capacitance covers the VDDQ rail. We include the upper bound here. 964 * e.g. a value of 125 usually is that the nominal capacitance is (100, 125]. 965 * This is a uint32_t value in uF. 966 */ 967 #define SPD_KEY_DDR5_CAMM2_MOD_CAP "ddr5.camm2.module-vddq-nom-cap" 968 969 /* 970 * DDR5 MRDIMM specific values. Note, these are only present in MRDIMM v1.1 and 971 * therefore may be missing in older revisions. While these values are really 972 * similar to the RDIMM variants, because they are taken from the MRCD instead 973 * of the RCD specification, we define different keys. 974 */ 975 #define SPD_KEY_DDR5_MRCD_QACK_EN "ddr5.mrcd.qack-enabled" 976 #define SPD_KEY_DDR5_MRCD_QBCK_EN "ddr5.mrcd.qbck-enabled" 977 #define SPD_KEY_DDR5_MRCD_QCCK_EN "ddr5.mrcd.qcck-enabled" 978 #define SPD_KEY_DDR5_MRCD_QDCK_EN "ddr5.mrcd.qdck-enabled" 979 #define SPD_KEY_DDR5_MRCD_BCK_EN "ddr5.mrcd.bck-enabled" 980 #define SPD_KEY_DDR5_MRCD_QACA_EN "ddr5.mrcd.qaca-enabled" 981 #define SPD_KEY_DDR5_MRCD_QBCA_EN "ddr5.mrcd.qbca-enabled" 982 #define SPD_KEY_DDR5_MRCD_BCS_EN "ddr5.mrcd.bcs-enabled" 983 #define SPD_KEY_DDR5_MRCD_QxCS_EN "ddr5.mrcd.qxcs-enabled" 984 #define SPD_KEY_DDR5_MRCD_QxCA13_EN "ddr5.mrcd.qxca13-enabled" 985 #define SPD_KEY_DDR5_MRCD_QACS_EN "ddr5.mrcd.qacs-enabled" 986 #define SPD_KEY_DDR5_MRCD_QBCS_EN "ddr5.mrcd.qbcs-enabled" 987 #define SPD_KEY_DDR5_MRCD_DCS1_EN "ddr5.mrcd.dcs1-enabled" 988 989 /* Drive strengths use the spd_drive_t encoded as a uint32_t */ 990 #define SPD_KEY_DDR5_MRCD_QACK_DS "ddr5.mrcd.qack-drive-strength" 991 #define SPD_KEY_DDR5_MRCD_QBCK_DS "ddr5.mrcd.qbck-drive-strength" 992 #define SPD_KEY_DDR5_MRCD_QCCK_DS "ddr5.mrcd.qcck-drive-strength" 993 #define SPD_KEY_DDR5_MRCD_QDCK_DS "ddr5.mrcd.qdck-drive-strength" 994 #define SPD_KEY_DDR5_MRCD_QxCS_DS "ddr5.mrcd.qxcs-drive-strength" 995 #define SPD_KEY_DDR5_MRCD_CA_DS "ddr5.mrcd.ca-drive-strength" 996 #define SPD_KEY_DDR5_MRCD_BCOM_DS "ddr5.mrcd.bcom-drive-strength" 997 #define SPD_KEY_DDR5_MRCD_BCK_DS "ddr5.mrcd.bck-drive-strength" 998 999 /* Slew rates use the spd_rate_t encoded as a uint32_t */ 1000 #define SPD_KEY_DDR5_MRCD_QCK_SLEW "ddr5.mrcd.qck-slew" 1001 #define SPD_KEY_DDR5_MRCD_QCA_SLEW "ddr5.mrcd.qca-slew" 1002 #define SPD_KEY_DDR5_MRCD_QCS_SLEW "ddr5.mrcd.qcs-slew" 1003 #define SPD_KEY_DDR5_MRCD_BCOM_SLEW "ddr5.mrcd.bcom-slew" 1004 #define SPD_KEY_DDR5_MRCD_BCK_SLEW "ddr5.mrcd.bck-slew" 1005 1006 typedef enum { 1007 SPD_MRCD_OUT_NORMAL, 1008 SPD_MRCD_OUT_DISABLED, 1009 SPD_MRCD_OUT_LOW 1010 } spd_mrcd_output_ctrl_t; 1011 #define SPD_KEY_DDR5_MRCD_QxCS_OUT "ddr5.mrcd.qxcs-output-control" 1012 1013 typedef enum { 1014 SPD_MRCD_DCA_CFG_0, 1015 SPD_MRCD_DCA_CFG_1 1016 } spd_mrcd_dca_cfg_t; 1017 #define SPD_KEY_DDR5_MRCD_DCA_CFG "ddr5.mrcd.dca-configuration" 1018 1019 typedef enum { 1020 SPD_MRDIMM_IRXT_UNMATCHED, 1021 SPD_MRDIMM_IRXT_MATCHED 1022 } spd_mrdimm_irxt_t; 1023 #define SPD_KEY_DDR5_MRDIMM_IRXT "ddr5.mrdimm.interface-rx-type" 1024 1025 /* 1026 * Module Properties. These are items that generally relate to the module as a 1027 * whole. 1028 */ 1029 1030 /* 1031 * Connection Mapping. In DDR4 there is the ability to remap groups of pins from 1032 * the connector to the various package SDRAMs. Every 4 bits can be remapped to 1033 * either another upper or lower nibble in a package. Separately bits can also 1034 * be flipped between packages. These exist for all 64-bits of DQ and 8 bits of 1035 * CBs. If mirroring is set, then a key will be added for that pin group. For 1036 * each pin group, the mapping to a specific type of rewriting will be done. We 1037 * conventionally use 0, 1, 2, and 3 as the lower nibble and 4, 5, 6, 7 as the 1038 * upper nibble, though the actual pins will vary based on where they are. 1039 */ 1040 #define SPD_KEY_DDR4_MAP_DQ0 "module.dq0-map" /* uint32_t [4] */ 1041 #define SPD_KEY_DDR4_MAP_DQ4 "module.dq4-map" /* uint32_t [4] */ 1042 #define SPD_KEY_DDR4_MAP_DQ8 "module.dq8-map" /* uint32_t [4] */ 1043 #define SPD_KEY_DDR4_MAP_DQ12 "module.dq12-map" /* uint32_t [4] */ 1044 #define SPD_KEY_DDR4_MAP_DQ16 "module.dq16-map" /* uint32_t [4] */ 1045 #define SPD_KEY_DDR4_MAP_DQ20 "module.dq20-map" /* uint32_t [4] */ 1046 #define SPD_KEY_DDR4_MAP_DQ24 "module.dq24-map" /* uint32_t [4] */ 1047 #define SPD_KEY_DDR4_MAP_DQ28 "module.dq28-map" /* uint32_t [4] */ 1048 #define SPD_KEY_DDR4_MAP_DQ32 "module.dq32-map" /* uint32_t [4] */ 1049 #define SPD_KEY_DDR4_MAP_DQ36 "module.dq36-map" /* uint36_t [4] */ 1050 #define SPD_KEY_DDR4_MAP_DQ40 "module.dq40-map" /* uint32_t [4] */ 1051 #define SPD_KEY_DDR4_MAP_DQ44 "module.dq44-map" /* uint32_t [4] */ 1052 #define SPD_KEY_DDR4_MAP_DQ48 "module.dq48-map" /* uint32_t [4] */ 1053 #define SPD_KEY_DDR4_MAP_DQ52 "module.dq52-map" /* uint32_t [4] */ 1054 #define SPD_KEY_DDR4_MAP_DQ56 "module.dq56-map" /* uint32_t [4] */ 1055 #define SPD_KEY_DDR4_MAP_DQ60 "module.dq60-map" /* uint32_t [4] */ 1056 #define SPD_KEY_DDR4_MAP_CB0 "module.cb0-map" /* uint32_t [4] */ 1057 #define SPD_KEY_DDR4_MAP_CB4 "module.cb4-map" /* uint32_t [4] */ 1058 1059 /* 1060 * In addition, there is module level mapping in DDR3/DDR4 that is used to 1061 * indicate that odd ranks are mirrored. This is between the edge connector and 1062 * the DRAM itself. We only add a key when it is mirrored. 1063 */ 1064 #define SPD_KEY_MOD_EDGE_MIRROR "module.edge-odd-mirror" /* key */ 1065 1066 /* 1067 * Present devices. Modules often have multiple additional types of devices 1068 * present like temperature sensors, voltage regulators, registers, etc. The 1069 * following key indicates what all is present on this DIMM. Depending on the 1070 * DDR revision, we will then have additional keys with its ID, revision, name, 1071 * and compliant type. In a few cases we will define the type and presence based 1072 * on information. For example, DDR4 only allows a single type of temperature 1073 * sensor or SPD device. Even though we don't know the manufacturer, we will 1074 * still note this. 1075 * 1076 * Each of these items will have four keys. One for the manufacturer ID, one for 1077 * their string name, one for the device type, and one for the revision. Note, 1078 * while TS1 and TS2 are both flags in DDR5, they share common manufacturer 1079 * information, which is why there is only one entry here. 1080 * 1081 * For each device type there is a separate enum with supported types of devices 1082 * that can be present for these. 1083 */ 1084 typedef enum { 1085 SPD_DEVICE_TEMP_1 = 1 << 0, 1086 SPD_DEVICE_TEMP_2 = 1 << 1, 1087 SPD_DEVICE_HS = 1 << 2, 1088 SPD_DEVICE_PMIC_0 = 1 << 3, 1089 SPD_DEVICE_PMIC_1 = 1 << 4, 1090 SPD_DEVICE_PMIC_2 = 1 << 5, 1091 SPD_DEVICE_CD_0 = 1 << 6, 1092 SPD_DEVICE_CD_1 = 1 << 7, 1093 SPD_DEVICE_RCD = 1 << 8, 1094 SPD_DEVICE_DB = 1 << 9, 1095 SPD_DEVICE_MRCD = 1 << 10, 1096 SPD_DEVICE_MDB = 1 << 11, 1097 SPD_DEVICE_DMB = 1 << 12, 1098 SPD_DEVICE_SPD = 1 << 13, 1099 SPD_DEVICE_VR_0 = 1 << 14, 1100 SPD_DEVICE_VR_1 = 1 << 15, 1101 SPD_DEVICE_VR_2 = 1 << 16, 1102 SPD_DEVICE_VR_3 = 1 << 17 1103 } spd_device_t; 1104 #define SPD_KEY_DEVS "module.devices" /* uint32_t */ 1105 1106 typedef enum { 1107 /* DDR3 */ 1108 SPD_TEMP_T_TSE2002, 1109 /* DDR4 and LPDDR4 */ 1110 SPD_TEMP_T_TSE2004av, 1111 /* DDR5 */ 1112 SPD_TEMP_T_TS5111, 1113 SPD_TEMP_T_TS5110, 1114 SPD_TEMP_T_TS5211, 1115 SPD_TEMP_T_TS5210 1116 } spd_temp_type_t; 1117 1118 typedef enum { 1119 /* DDR5 */ 1120 SPD_PMIC_T_PMIC5000, 1121 SPD_PMIC_T_PMIC5010, 1122 SPD_PMIC_T_PMIC5100, 1123 SPD_PMIC_T_PMIC5020, 1124 SPD_PMIC_T_PMIC5120, 1125 SPD_PMIC_T_PMIC5200, 1126 SPD_PMIC_T_PMIC5030 1127 } spd_pmic_type_t; 1128 1129 typedef enum { 1130 /* DDR5 */ 1131 SPD_CD_T_DDR5CK01 1132 } spd_cd_type_t; 1133 1134 typedef enum { 1135 /* DDR3 */ 1136 SPD_RCD_T_SSTE32882, 1137 /* DDR4 */ 1138 SPD_RCD_T_DDR4RCD01, 1139 SPD_RCD_T_DDR4RCD02, 1140 /* DDR5 */ 1141 SPD_RCD_T_DDR5RCD01, 1142 SPD_RCD_T_DDR5RCD02, 1143 SPD_RCD_T_DDR5RCD03, 1144 SPD_RCD_T_DDR5RCD04, 1145 SPD_RCD_T_DDR5RCD05, 1146 SPD_RCD_T_DDR5RCD06 1147 } spd_rcd_type_t; 1148 1149 typedef enum { 1150 /* DDR4 */ 1151 SPD_DB_T_DDR4DB01, 1152 SPD_DB_T_DDR4DB02, 1153 /* DDR5 */ 1154 SPD_DB_T_DDR5DB01, 1155 SPD_DB_T_DDR5DB02, 1156 /* 1157 * DDR3 LRDIMMs had a memory buffer that did not have a full 1158 * designation. We count them here. 1159 */ 1160 SPD_DB_T_DDR3MB 1161 } spd_db_type_t; 1162 1163 typedef enum { 1164 /* DDR5 */ 1165 SPD_MRCD_T_DDR5MRCD01, 1166 SPD_MRCD_T_DDR5MRCD02, 1167 SPD_MRCD_T_DDR5MRCD03 1168 } spd_mrcd_type_t; 1169 1170 typedef enum { 1171 /* DDR5 */ 1172 SPD_MDB_T_DDR5MDB01, 1173 SPD_MDB_T_DDR5MDB02, 1174 SPD_MDB_T_DDR5MDB03 1175 } spd_mdb_type_t; 1176 1177 typedef enum { 1178 /* DDR5 */ 1179 SPD_DMB_T_DMB5011 1180 } spd_dmb_type_t; 1181 1182 typedef enum { 1183 /* DDR4 */ 1184 SPD_SPD_T_EE1004, 1185 /* DDR5 */ 1186 SPD_SPD_T_SPD5118, 1187 SPD_SPD_T_ESPD5216, 1188 /* DDR3 */ 1189 SPD_SPD_T_EE1002 1190 } spd_spd_type_t; 1191 1192 #define SPD_KEY_DEV_TEMP_MFG "module.temp.mfg-id" /* uint32_t [2] */ 1193 #define SPD_KEY_DEV_TEMP_MFG_NAME "module.temp.mfg-name" /* string */ 1194 #define SPD_KEY_DEV_TEMP_TYPE "module.temp.type" /* uint32_t */ 1195 #define SPD_KEY_DEV_TEMP_REV "module.temp.revision" /* string */ 1196 1197 #define SPD_KEY_DEV_PMIC0_MFG "module.pmic0.mfg-id" /* uint32_t [2] */ 1198 #define SPD_KEY_DEV_PMIC0_MFG_NAME "module.pmic0.mfg-name" /* string */ 1199 #define SPD_KEY_DEV_PMIC0_TYPE "module.pmic0.type" /* uint32_t */ 1200 #define SPD_KEY_DEV_PMIC0_REV "module.pmic0.revision" /* string */ 1201 #define SPD_KEY_DEV_PMIC1_MFG "module.pmic1.mfg-id" /* uint32_t [2] */ 1202 #define SPD_KEY_DEV_PMIC1_MFG_NAME "module.pmic1.mfg-name" /* string */ 1203 #define SPD_KEY_DEV_PMIC1_TYPE "module.pmic1.type" /* uint32_t */ 1204 #define SPD_KEY_DEV_PMIC1_REV "module.pmic1.revision" /* string */ 1205 #define SPD_KEY_DEV_PMIC2_MFG "module.pmic2.mfg-id" /* uint32_t [2] */ 1206 #define SPD_KEY_DEV_PMIC2_MFG_NAME "module.pmic2.mfg-name" /* string */ 1207 #define SPD_KEY_DEV_PMIC2_TYPE "module.pmic2.type" /* uint32_t */ 1208 #define SPD_KEY_DEV_PMIC2_REV "module.pmic2.revision" /* string */ 1209 1210 #define SPD_KEY_DEV_CD0_MFG "module.cd0.mfg-id" /* uint32_t [2] */ 1211 #define SPD_KEY_DEV_CD0_MFG_NAME "module.cd0.mfg-name" /* string */ 1212 #define SPD_KEY_DEV_CD0_TYPE "module.cd0.type" /* uint32_t */ 1213 #define SPD_KEY_DEV_CD0_REV "module.cd0.revision" /* string */ 1214 #define SPD_KEY_DEV_CD1_MFG "module.cd1.mfg-id" /* uint32_t [2] */ 1215 #define SPD_KEY_DEV_CD1_MFG_NAME "module.cd1.mfg-name" /* string */ 1216 #define SPD_KEY_DEV_CD1_TYPE "module.cd1.type" /* uint32_t */ 1217 #define SPD_KEY_DEV_CD1_REV "module.cd1.revision" /* string */ 1218 1219 #define SPD_KEY_DEV_RCD_MFG "module.rcd.mfg-id" /* uint32_t [2] */ 1220 #define SPD_KEY_DEV_RCD_MFG_NAME "module.rcd.mfg-name" /* string */ 1221 #define SPD_KEY_DEV_RCD_TYPE "module.rcd.type" /* uint32_t */ 1222 #define SPD_KEY_DEV_RCD_REV "module.rcd.revision" /* string */ 1223 1224 #define SPD_KEY_DEV_DB_MFG "module.db.mfg-id" /* uint32_t [2] */ 1225 #define SPD_KEY_DEV_DB_MFG_NAME "module.db.mfg-name" /* string */ 1226 #define SPD_KEY_DEV_DB_TYPE "module.db.type" /* uint32_t */ 1227 #define SPD_KEY_DEV_DB_REV "module.db.revision" /* string */ 1228 1229 #define SPD_KEY_DEV_MRCD_MFG "module.mrcd.mfg-id" /* uint32_t [2] */ 1230 #define SPD_KEY_DEV_MRCD_MFG_NAME "module.mrcd.mfg-name" /* string */ 1231 #define SPD_KEY_DEV_MRCD_TYPE "module.mrcd.type" /* uint32_t */ 1232 #define SPD_KEY_DEV_MRCD_REV "module.mrcd.revision" /* string */ 1233 1234 #define SPD_KEY_DEV_MDB_MFG "module.mdb.mfg-id" /* uint32_t [2] */ 1235 #define SPD_KEY_DEV_MDB_MFG_NAME "module.mdb.mfg-name" /* string */ 1236 #define SPD_KEY_DEV_MDB_TYPE "module.mdb.type" /* uint32_t */ 1237 #define SPD_KEY_DEV_MDB_REV "module.mdb.revision" /* string */ 1238 1239 #define SPD_KEY_DEV_DMB_MFG "module.dmb.mfg-id" /* uint32_t [2] */ 1240 #define SPD_KEY_DEV_DMB_MFG_NAME "module.dmb.mfg-name" /* string */ 1241 #define SPD_KEY_DEV_DMB_TYPE "module.dmb.type" /* uint32_t */ 1242 #define SPD_KEY_DEV_DMB_REV "module.dmb.revision" /* string */ 1243 1244 #define SPD_KEY_DEV_SPD_MFG "module.spd.mfg-id" /* uint32_t [2] */ 1245 #define SPD_KEY_DEV_SPD_MFG_NAME "module.spd.mfg-name" /* string */ 1246 #define SPD_KEY_DEV_SPD_TYPE "module.spd.type" /* uint32_t */ 1247 #define SPD_KEY_DEV_SPD_REV "module.spd.revision" /* string */ 1248 1249 /* 1250 * Voltage regulators, present on SOCAMM2 devices, do not have a type. However, 1251 * they do have a set of rails that they provide for, which the spec calls a 1252 * source. 1253 */ 1254 typedef enum { 1255 SPD_VR_SRC_VDD1 = 1 << 0, 1256 SPD_VR_SRC_VDD2H = 1 << 1, 1257 SPD_VR_SRC_VDD2L = 1 << 2, 1258 SPD_VR_SRC_VDD2 = 1 << 3, 1259 SPD_VR_SRC_VDDQ = 1 << 4 1260 } spd_vr_rail_source_t; 1261 1262 #define SPD_KEY_DEV_VR0_MFG "module.vr0.mfg-id" /* uint32_t [2] */ 1263 #define SPD_KEY_DEV_VR0_MFG_NAME "module.vr0.mfg-nam3" /* string */ 1264 #define SPD_KEY_DEV_VR0_REV "module.vr0.revision" /* string */ 1265 #define SPD_KEY_DEV_VR0_SRC "module.vr0.source" /* uint32_t */ 1266 1267 #define SPD_KEY_DEV_VR1_MFG "module.vr1.mfg-id" /* uint32_t [2] */ 1268 #define SPD_KEY_DEV_VR1_MFG_NAME "module.vr1.mfg-nam3" /* string */ 1269 #define SPD_KEY_DEV_VR1_REV "module.vr1.revision" /* string */ 1270 #define SPD_KEY_DEV_VR1_SRC "module.vr1.source" /* uint32_t */ 1271 1272 #define SPD_KEY_DEV_VR2_MFG "module.vr2.mfg-id" /* uint32_t [2] */ 1273 #define SPD_KEY_DEV_VR2_MFG_NAME "module.vr2.mfg-nam3" /* string */ 1274 #define SPD_KEY_DEV_VR2_REV "module.vr2.revision" /* string */ 1275 #define SPD_KEY_DEV_VR2_SRC "module.vr2.source" /* uint32_t */ 1276 1277 #define SPD_KEY_DEV_VR3_MFG "module.vr3.mfg-id" /* uint32_t [2] */ 1278 #define SPD_KEY_DEV_VR3_MFG_NAME "module.vr3.mfg-nam3" /* string */ 1279 #define SPD_KEY_DEV_VR3_REV "module.vr3.revision" /* string */ 1280 #define SPD_KEY_DEV_VR3_SRC "module.vr3.source" /* uint32_t */ 1281 1282 /* 1283 * In addition to the primary devices, there is a notion of devices which are 1284 * used for support of the device such as fuses or transient voltage 1285 * suppression. We use a single enum for each class of such devices where the 1286 * enum gives specifics about what it applies to. This was only added in DDR5 1287 * SPD version 1.3 and LPDDR version 1.2 so these may not be present. 1288 */ 1289 typedef enum { 1290 SPD_FUSE_VIN_BULK = 1 << 0 1291 } spd_fuse_t; 1292 #define SPD_KEY_DEV_FUSE "module.fuse" /* uint32_t */ 1293 1294 typedef enum { 1295 SPD_TVS_VIN_BULK = 1 << 0, 1296 SPD_TVS_VIN_MGMT = 1 << 1 1297 } spd_tvs_t; 1298 #define SPD_KEY_DEV_TVS "module.tvs" /* uint32_t */ 1299 1300 /* 1301 * Module physical dimensions. DRAM modules provide information about their 1302 * height and their front and back thicknesses. All values are in millimeters. 1303 * In general, values are defined as 1 mm ranges in the form such as 18mm < 1304 * height <= 19mm or 2mm < thickness <= 3mm. As such in all these ranges we 1305 * encode it as the less than or equal to side of the thickness or height. 1306 * 1307 * However, at the extremes of thickness and height, it can be arbitrary. The 1308 * minimum height can be any value <= 15mm and the maximum is just > 45mm. 1309 * Similarly the maximum thickness is just any value greater than 15mm. For 1310 * these values, we define aliases that can be used to indicate we're in these 1311 * conditions for the height and thickness, allowing this to otherwise be the 1312 * common well understood value. 1313 */ 1314 #define SPD_MOD_HEIGHT_LT15MM 15 1315 #define SPD_MOD_HEIGHT_GT45MM 46 1316 #define SPD_KEY_MOD_HEIGHT "module.height" /* uint32_t */ 1317 #define SPD_MOD_THICK_GT15MM 16 1318 #define SPD_KEY_MOD_FRONT_THICK "module.front-thickness" /* uint32_t */ 1319 #define SPD_KEY_MOD_BACK_THICK "module.back-thickness" /* uint32_t */ 1320 1321 /* 1322 * This is the number of rows of DRAM dies on the module. In addition, DDR3 and 1323 * DDR4 provides the number of registers present on the device. This is not 1324 * present in DDR5. 1325 */ 1326 #define SPD_KEY_MOD_NROWS "module.dram-die-rows" /* uint32_t */ 1327 #define SPD_KEY_MOD_NREGS "module.total-registers" /* uint32_t */ 1328 1329 /* 1330 * Operating temperature ranges. These ranges are defined by JEDEC. The code can 1331 * be translated with libjedec_temp_range() to transform it into a pair of 1332 * values. 1333 */ 1334 #define SPD_KEY_MOD_OPER_TEMP "module.operating-temperature" /* uint32_t */ 1335 1336 /* 1337 * Module reference card and design revision. JEDEC provides various reference 1338 * designs for modules and revisions of those. 1339 */ 1340 #define SPD_KEY_MOD_REF_DESIGN "module.reference-design" /* string */ 1341 #define SPD_KEY_MOD_DESIGN_REV "module.design-revision" /* uint32_t */ 1342 1343 /* 1344 * Manufacturing Section. These keys are present if manufacturing related 1345 * information is made available. This space is not DIMM-revision specific. All 1346 * fields are defined in DDR4 and DDR5. Note, the SPD_KEY_MFG_DRAM_STEP is 1347 * optional and therefore an invalid value will result in this not being 1348 * present. 1349 */ 1350 #define SPD_KEY_MFG_MOD_MFG_ID "mfg.module-mfg-id" /* uint32[2] */ 1351 #define SPD_KEY_MFG_MOD_MFG_NAME "mfg.module-mfg-name" /* string */ 1352 #define SPD_KEY_MFG_DRAM_MFG_ID "mfg.dram-mfg-id" /* uint32[2] */ 1353 #define SPD_KEY_MFG_DRAM_MFG_NAME "mfg.dram-mfg-name" /* string */ 1354 #define SPD_KEY_MFG_MOD_LOC_ID "mfg.module-loc-id" /* uint32 */ 1355 #define SPD_KEY_MFG_MOD_YEAR "mfg.module-year" /* string */ 1356 #define SPD_KEY_MFG_MOD_WEEK "mfg.module-week" /* string */ 1357 #define SPD_KEY_MFG_MOD_PN "mfg.module-pn" /* string */ 1358 #define SPD_KEY_MFG_MOD_SN "mfg.module-sn" /* string */ 1359 #define SPD_KEY_MFG_MOD_REV "mfg.module-rev" /* string */ 1360 #define SPD_KEY_MFG_DRAM_STEP "mfg.dram-step" /* string */ 1361 1362 /* 1363 * The errors nvlist_t is designed such that it is a nested nvlist_t in the 1364 * returned data. Each key in that nvlist_t corresponds to a key that we would 1365 * otherwise produce. Each key is an nvlist_t that has two keys, a 'code' and a 1366 * 'message'. 1367 * 1368 * There is currently an additional top-level special key. This is the 1369 * 'incomplete' key. When data is too short to process an entry, rather than 1370 * flag every possible missing key (as most times the consumer will know the 1371 * amount of data they have), for the time being we will insert a single 1372 * incomplete key with a uint32_t whose value indicates the starting offset of 1373 * the key that we could not process. Note, this may not be the first byte that 1374 * was missing (if we had 100 bytes and a 20 byte key at offset 90, we would 1375 * insert 90). 1376 */ 1377 typedef enum { 1378 /* 1379 * Indicates that the error occurred because we could not translate a 1380 * given piece of information. For example, a value that we didn't know 1381 * or a failure to look up something in a string table. 1382 */ 1383 SPD_ERROR_NO_XLATE, 1384 /* 1385 * This indicates that we encountered an non-ASCII or unprintable 1386 * character in an SPD string which should not be allowed per se. 1387 */ 1388 SPD_ERROR_UNPRINT, 1389 /* 1390 * This indicates that there was no data for a given key. For example, a 1391 * string that was all padded spaces. 1392 */ 1393 SPD_ERROR_NO_DATA, 1394 /* 1395 * Indicates that some kind of internal error occurred. 1396 */ 1397 SPD_ERROR_INTERNAL, 1398 /* 1399 * This indicates that there's something suspicious or weird to us about 1400 * the data in question. The most common case is a bad CRC. 1401 */ 1402 SPD_ERROR_BAD_DATA 1403 } spd_error_kind_t; 1404 #define SPD_KEY_INCOMPLETE "incomplete" /* uint32_t */ 1405 #define SPD_KEY_ERRS "errors" /* nvlist_t */ 1406 #define SPD_KEY_ERRS_CODE "code" /* uint32_t */ 1407 #define SPD_KEY_ERRS_MSG "message" /* string */ 1408 1409 #ifdef __cplusplus 1410 } 1411 #endif 1412 1413 #endif /* _LIBJEDEC_H */ 1414