1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Copyright (c) 2009, Intel Corporation 29 * All rights reserved. 30 */ 31 32/* 33 * Portions Copyright 2009 Advanced Micro Devices, Inc. 34 */ 35 36/* 37 * Assembler support routines to getcpuid information used to set 38 * cache size information. Cache information used by memset, strcpy, etc.. 39 */ 40 41#include <sys/asm_linkage.h> 42#include "proc64_id.h" 43 44 .global .memops_method 45 .global .amd64cache1, .amd64cache1half, .amd64cache2, .amd64cache2half 46 .global .largest_level_cache_size 47 48 49/* 50 * Defaults for Core 2 Duo and AMD's SledgeHammer 51 */ 52 .data 53 .balign 8 54.memops_method: 55 .int NO_SSE 56 57 .balign 8 58.amd64cache1: .quad AMD_DFLT_L1_CACHE_SIZE 59.amd64cache1half: .quad AMD_DFLT_L1_CACHE_SIZE/2 60.amd64cache2: .quad AMD_DFLT_L2_CACHE_SIZE 61.amd64cache2half: .quad AMD_DFLT_L2_CACHE_SIZE/2 62.largest_level_cache_size: 63 .int AMD_DFLT_L2_CACHE_SIZE 64 65/* 66 * Get cpuid data. 67 * (void)__libc_get_cpuid(int cpuid_function, void *out_reg, int cache_index ) 68 */ 69 .text 70 71 ENTRY(__libc_get_cpuid) 72 # rdi = cpuid function, rsi = out_reg addr, rdx = cache index(fn 4) 73 push %rbx 74 mov %edx,%ecx 75 mov %edi,%eax 76 cpuid 77 mov %eax,(%rsi) 78 mov %ebx,0x4(%rsi) 79 mov %ecx,0x8(%rsi) 80 mov %edx,0xc(%rsi) 81 pop %rbx 82 ret 83 SET_SIZE(__libc_get_cpuid) 84 85/* 86 * Set memops SSE level to use. 87 * void __intel_set_memops_method(long sse_level); 88 */ 89 ENTRY(__intel_set_memops_method) 90 mov %edi,.memops_method(%rip) 91 ret 92 SET_SIZE(__intel_set_memops_method) 93 94/* 95 * Set cache info global variables used by various libc primitives. 96 * __set_cache_sizes(long l1_cache_size, long l2_cache_size, 97 * long largest_level_cache); 98 */ 99 ENTRY(__set_cache_sizes) 100 # rdi = l1_cache_size, rsi = l2_cache_size, rdx = largest_level_cache 101 102 mov %rdi,.amd64cache1(%rip) 103 shr $1, %rdi 104 mov %rdi,.amd64cache1half(%rip) 105 106 mov %rsi,.amd64cache2(%rip) 107 shr $1, %rsi 108 mov %rsi,.amd64cache2half(%rip) 109 110 mov %rdx,.largest_level_cache_size(%rip) 111 ret 112 SET_SIZE(__set_cache_sizes) 113