1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _TOPO_HC_H 28 #define _TOPO_HC_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * Allowable hardware component names for hc FMRIs 38 */ 39 #define BAY "bay" 40 #define BRANCH "branch" 41 #define CMP "CMP" 42 #define CENTERPLANE "centerplane" 43 #define CHASSIS "chassis" 44 #define CHIP "chip" 45 #define CHIP_SELECT "chip-select" 46 #define CPU "cpu" 47 #define CPUBOARD "cpuboard" 48 #define DIMM "dimm" 49 #define DISK "disk" 50 #define DRAMCHANNEL "dram-channel" 51 #define FAN "fan" 52 #define FANMODULE "fanmodule" 53 #define HOSTBRIDGE "hostbridge" 54 #define INTERCONNECT "interconnect" 55 #define IOBOARD "ioboard" 56 #define MEMBOARD "memboard" 57 #define MEMORYCONTROL "memory-controller" 58 #define MOTHERBOARD "motherboard" 59 #define NIU "niu" 60 #define NIUFN "niufn" 61 #define PCI_BUS "pcibus" 62 #define PCI_DEVICE "pcidev" 63 #define PCI_FUNCTION "pcifn" 64 #define PCIEX_BUS "pciexbus" 65 #define PCIEX_DEVICE "pciexdev" 66 #define PCIEX_FUNCTION "pciexfn" 67 #define PCIEX_ROOT "pciexrc" 68 #define PCIEX_SWUP "pciexswu" 69 #define PCIEX_SWDWN "pciexswd" 70 #define POWERMODULE "powermodule" 71 #define PSU "psu" 72 #define RANK "rank" 73 #define SYSTEMBOARD "systemboard" 74 #define XAUI "xaui" 75 #define XFP "xfp" 76 77 /* 78 * Allowable hc node property group and property names 79 */ 80 #define TOPO_PGROUP_IO "io" 81 #define TOPO_IO_DEVTYPE "devtype" 82 #define TOPO_IO_DRIVER "driver" 83 #define TOPO_IO_MODULE "module" 84 #define TOPO_IO_DEV "dev" 85 #define TOPO_IO_DEVID "devid" 86 #define TOPO_IO_DEV_PATH "devfs-path" 87 #define TOPO_IO_AP_PATH "ap-path" 88 #define TOPO_IO_PHYS_PATH "phys-path" 89 90 #define TOPO_PGROUP_PCI "pci" 91 #define TOPO_PCI_VENDID "vendor-id" 92 #define TOPO_PCI_DEVID "device-id" 93 #define TOPO_PCI_EXCAP "extended-capabilities" 94 #define TOPO_PCI_BDF "BDF" 95 #define TOPO_PCI_CLASS "class-code" 96 #define TOPO_PCI_AADDR "assigned-addresses" 97 98 #ifdef __cplusplus 99 } 100 #endif 101 102 #endif /* _TOPO_HC_H */ 103