xref: /illumos-gate/usr/src/grub/grub-0.97/netboot/tlan.c (revision 1b8adde7ba7d5e04395c141c5400dc2cffd7d809)
1 #define EB51
2 
3 #ifdef EB50
4 #define __unused __attribute__((unused))
5 #endif
6 
7 /**************************************************************************
8 *
9 *    tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
10 *    Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
11 *
12 *    This program is free software; you can redistribute it and/or modify
13 *    it under the terms of the GNU General Public License as published by
14 *    the Free Software Foundation; either version 2 of the License, or
15 *    (at your option) any later version.
16 *
17 *    This program is distributed in the hope that it will be useful,
18 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
19 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
20 *    GNU General Public License for more details.
21 *
22 *    You should have received a copy of the GNU General Public License
23 *    along with this program; if not, write to the Free Software
24 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 *
26 *    Portions of this code based on:
27 *	lan.c: Linux ThunderLan Driver:
28 *
29 *	by James Banks
30 *
31 *  	(C) 1997-1998 Caldera, Inc.
32 *	(C) 1998 James Banks
33 *	(C) 1999-2001 Torben Mathiasen
34 *	(C) 2002 Samuel Chessman
35 *
36 *    REVISION HISTORY:
37 *    ================
38 *    v1.0	07-08-2003	timlegge	Initial not quite working version
39 *    v1.1	07-27-2003	timlegge	Sync 5.0 and 5.1 versions
40 *    v1.2	08-19-2003	timlegge	Implement Multicast Support
41 *    v1.3	08-23-2003	timlegge	Fix the transmit Function
42 *    v1.4	01-17-2004	timlegge	Initial driver output cleanup
43 *
44 *    Indent Options: indent -kr -i8
45 ***************************************************************************/
46 
47 /* to get some global routines like printf */
48 #include "etherboot.h"
49 /* to get the interface to the body of the program */
50 #include "nic.h"
51 /* to get the PCI support functions, if this is a PCI NIC */
52 #include "pci.h"
53 #include "timer.h"
54 #include "tlan.h"
55 
56 #define drv_version "v1.4"
57 #define drv_date "01-17-2004"
58 
59 /* NIC specific static variables go here */
60 #define HZ 100
61 #define TX_TIME_OUT	  (6*HZ)
62 
63 #ifdef EB50
64 #define	cpu_to_le32(val) (val)
65 #define	le32_to_cpu(val) (val)
66 #define	virt_to_bus(x) ((unsigned long) x)
67 #define	bus_to_virt(x) ((unsigned long) x)
68 #endif
69 
70 /* Condensed operations for readability. */
71 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
72 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
73 
74 
75 static void TLan_ResetLists(struct nic *nic __unused);
76 static void TLan_ResetAdapter(struct nic *nic __unused);
77 static void TLan_FinishReset(struct nic *nic __unused);
78 
79 static void TLan_EeSendStart(u16);
80 static int TLan_EeSendByte(u16, u8, int);
81 static void TLan_EeReceiveByte(u16, u8 *, int);
82 static int TLan_EeReadByte(u16 io_base, u8, u8 *);
83 
84 static void TLan_PhyDetect(struct nic *nic);
85 static void TLan_PhyPowerDown(struct nic *nic);
86 static void TLan_PhyPowerUp(struct nic *nic);
87 
88 
89 static void TLan_SetMac(struct nic *nic __unused, int areg, char *mac);
90 
91 static void TLan_PhyReset(struct nic *nic);
92 static void TLan_PhyStartLink(struct nic *nic);
93 static void TLan_PhyFinishAutoNeg(struct nic *nic);
94 
95 #ifdef MONITOR
96 static void TLan_PhyMonitor(struct nic *nic);
97 #endif
98 
99 
100 static void refill_rx(struct nic *nic __unused);
101 
102 static int TLan_MiiReadReg(struct nic *nic __unused, u16, u16, u16 *);
103 static void TLan_MiiSendData(u16, u32, unsigned);
104 static void TLan_MiiSync(u16);
105 static void TLan_MiiWriteReg(struct nic *nic __unused, u16, u16, u16);
106 
107 
108 const char *media[] = {
109 	"10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ",
110 	"100baseTx-FD", "100baseT4", 0
111 };
112 
113 /* This much match tlan_pci_tbl[]!  */
114 enum tlan_nics {
115 	NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B =
116 	    4, NETEL100PI = 5,
117 	NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 =
118 	    10, NETELLIGENT_10_100_WS_5100 = 11,
119 	NETELLIGENT_10_T2 = 12
120 };
121 
122 struct pci_id_info {
123 	const char *name;
124 	int nic_id;
125 	struct match_info {
126 		u32 pci, pci_mask, subsystem, subsystem_mask;
127 		u32 revision, revision_mask;	/* Only 8 bits. */
128 	} id;
129 	u32 flags;
130 	u16 addrOfs;		/* Address Offset */
131 };
132 
133 static struct pci_id_info tlan_pci_tbl[] = {
134 	{"Compaq Netelligent 10 T PCI UTP", NETEL10,
135 	 {0xae340e11, 0xffffffff, 0, 0, 0, 0},
136 	 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
137 	{"Compaq Netelligent 10/100 TX PCI UTP", NETEL100,
138 	 {0xae320e11, 0xffffffff, 0, 0, 0, 0},
139 	 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
140 	{"Compaq Integrated NetFlex-3/P", NETFLEX3I,
141 	 {0xae350e11, 0xffffffff, 0, 0, 0, 0},
142 	 TLAN_ADAPTER_NONE, 0x83},
143 	{"Compaq NetFlex-3/P", THUNDER,
144 	 {0xf1300e11, 0xffffffff, 0, 0, 0, 0},
145 	 TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
146 	{"Compaq NetFlex-3/P", NETFLEX3B,
147 	 {0xf1500e11, 0xffffffff, 0, 0, 0, 0},
148 	 TLAN_ADAPTER_NONE, 0x83},
149 	{"Compaq Netelligent Integrated 10/100 TX UTP", NETEL100PI,
150 	 {0xae430e11, 0xffffffff, 0, 0, 0, 0},
151 	 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
152 	{"Compaq Netelligent Dual 10/100 TX PCI UTP", NETEL100D,
153 	 {0xae400e11, 0xffffffff, 0, 0, 0, 0},
154 	 TLAN_ADAPTER_NONE, 0x83},
155 	{"Compaq Netelligent 10/100 TX Embedded UTP", NETEL100I,
156 	 {0xb0110e11, 0xffffffff, 0, 0, 0, 0},
157 	 TLAN_ADAPTER_NONE, 0x83},
158 	{"Olicom OC-2183/2185", OC2183,
159 	 {0x0013108d, 0xffffffff, 0, 0, 0, 0},
160 	 TLAN_ADAPTER_USE_INTERN_10, 0x83},
161 	{"Olicom OC-2325", OC2325,
162 	 {0x0012108d, 0xffffffff, 0, 0, 0, 0},
163 	 TLAN_ADAPTER_UNMANAGED_PHY, 0xF8},
164 	{"Olicom OC-2326", OC2326,
165 	 {0x0014108d, 0xffffffff, 0, 0, 0, 0},
166 	 TLAN_ADAPTER_USE_INTERN_10, 0xF8},
167 	{"Compaq Netelligent 10/100 TX UTP", NETELLIGENT_10_100_WS_5100,
168 	 {0xb0300e11, 0xffffffff, 0, 0, 0, 0},
169 	 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
170 	{"Compaq Netelligent 10 T/2 PCI UTP/Coax", NETELLIGENT_10_T2,
171 	 {0xb0120e11, 0xffffffff, 0, 0, 0, 0},
172 	 TLAN_ADAPTER_NONE, 0x83},
173 	{"Compaq NetFlex-3/E", 0,	/* EISA card */
174 	 {0, 0, 0, 0, 0, 0},
175 	 TLAN_ADAPTER_ACTIVITY_LED | TLAN_ADAPTER_UNMANAGED_PHY |
176 	 TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
177 	{"Compaq NetFlex-3/E", 0,	/* EISA card */
178 	 {0, 0, 0, 0, 0, 0},
179 	 TLAN_ADAPTER_ACTIVITY_LED, 0x83},
180 	{0, 0,
181 	 {0, 0, 0, 0, 0, 0},
182 	 0, 0},
183 };
184 
185 
186 struct TLanList {
187 	u32 forward;
188 	u16 cStat;
189 	u16 frameSize;
190 	struct {
191 		u32 count;
192 		u32 address;
193 	} buffer[TLAN_BUFFERS_PER_LIST];
194 };
195 
196 
197 
198 struct TLanList tx_ring[TLAN_NUM_TX_LISTS];
199 static unsigned char txb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_TX_LISTS];
200 
201 struct TLanList rx_ring[TLAN_NUM_RX_LISTS];
202 static unsigned char rxb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_RX_LISTS];
203 
204 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
205 
206 
207 int chip_idx;
208 
209 
210 /*****************************************************************
211 * TLAN Private Information Structure
212 *
213 ****************************************************************/
214 struct tlan_private {
215 	unsigned short vendor_id;	/* PCI Vendor code */
216 	unsigned short dev_id;	/* PCI Device code */
217 	const char *nic_name;
218 	u8 *padBuffer;
219 	u8 *rxBuffer;
220 	struct TLanList *rx_head_desc;
221 	u32 rxHead;
222 	u32 rxTail;
223 	u32 rxEocCount;
224 	unsigned int cur_rx, dirty_rx;	/* Producer/consumer ring indicies */
225 	unsigned int cur_tx, dirty_tx;
226 	unsigned rx_buf_sz;	/* Based on mtu + Slack */
227 	struct TLanList *txList;
228 	struct TLanList *rxList;
229 	u8 *txBuffer;
230 	u32 txHead;
231 	u32 txInProgress;
232 	u32 txTail;
233 	int eoc;
234 	u32 txBusyCount;
235 	u32 phyOnline;
236 	u32 timerSetAt;
237 	u32 timerType;
238 	u32 adapterRev;
239 	u32 aui;
240 	u32 debug;
241 	u32 duplex;
242 	u32 phy[2];
243 	u32 phyNum;
244 	u32 speed;
245 	u8 tlanRev;
246 	u8 tlanFullDuplex;
247 	char devName[8];
248 	u8 link;
249 	u8 is_eisa;
250 	u8 neg_be_verbose;
251 } TLanPrivateInfo;
252 
253 static struct tlan_private *priv;
254 
255 u32 BASE;
256 
257 
258 
259 /***************************************************************
260 *	TLan_ResetLists
261 *
262 *	Returns:
263 *		Nothing
264 *	Parms:
265 *		dev	The device structure with the list
266 *			stuctures to be reset.
267 *
268 *	This routine sets the variables associated with managing
269 *	the TLAN lists to their initial values.
270 *
271 **************************************************************/
272 
TLan_ResetLists(struct nic * nic __unused)273 void TLan_ResetLists(struct nic *nic __unused)
274 {
275 
276 	int i;
277 	struct TLanList *list;
278 	priv->txHead = 0;
279 	priv->txTail = 0;
280 
281 	for (i = 0; i < TLAN_NUM_TX_LISTS; i++) {
282 		list = &tx_ring[i];
283 		list->cStat = TLAN_CSTAT_UNUSED;
284 /*		list->buffer[0].address = 0; */
285 		list->buffer[0].address = virt_to_bus(txb +
286 				(i * TLAN_MAX_FRAME_SIZE));
287 		list->buffer[2].count = 0;
288 		list->buffer[2].address = 0;
289 		list->buffer[9].address = 0;
290 /*		list->forward = 0; */
291 	}
292 
293 	priv->cur_rx = 0;
294 	priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE);
295 	priv->rx_head_desc = &rx_ring[0];
296 
297 	/* Initialize all the Rx descriptors */
298 	for (i = 0; i < TLAN_NUM_RX_LISTS; i++) {
299 		rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]);
300 		rx_ring[i].cStat = TLAN_CSTAT_READY;
301 		rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE;
302 		rx_ring[i].buffer[0].count =
303 		    TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
304 		rx_ring[i].buffer[0].address =
305 		    virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]);
306 		rx_ring[i].buffer[1].count = 0;
307 		rx_ring[i].buffer[1].address = 0;
308 	}
309 
310 	/* Mark the last entry as wrapping the ring */
311 	rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]);
312 	priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS);
313 
314 } /* TLan_ResetLists */
315 
316 /***************************************************************
317 *	TLan_Reset
318 *
319 *	Returns:
320 *		0
321 *	Parms:
322 *		dev	Pointer to device structure of adapter
323 *			to be reset.
324 *
325 *	This function resets the adapter and it's physical
326 *	device.  See Chap. 3, pp. 9-10 of the "ThunderLAN
327 *	Programmer's Guide" for details.  The routine tries to
328 *	implement what is detailed there, though adjustments
329 *	have been made.
330 *
331 **************************************************************/
332 
TLan_ResetAdapter(struct nic * nic __unused)333 void TLan_ResetAdapter(struct nic *nic __unused)
334 {
335 	int i;
336 	u32 addr;
337 	u32 data;
338 	u8 data8;
339 
340 	priv->tlanFullDuplex = FALSE;
341 	priv->phyOnline = 0;
342 /*  1.	Assert reset bit. */
343 
344 	data = inl(BASE + TLAN_HOST_CMD);
345 	data |= TLAN_HC_AD_RST;
346 	outl(data, BASE + TLAN_HOST_CMD);
347 
348 	udelay(1000);
349 
350 /*  2.	Turn off interrupts. ( Probably isn't necessary ) */
351 
352 	data = inl(BASE + TLAN_HOST_CMD);
353 	data |= TLAN_HC_INT_OFF;
354 	outl(data, BASE + TLAN_HOST_CMD);
355 /*  3.	Clear AREGs and HASHs. */
356 
357 	for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) {
358 		TLan_DioWrite32(BASE, (u16) i, 0);
359 	}
360 
361 /*  4.	Setup NetConfig register. */
362 
363 	data =
364 	    TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
365 	TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
366 
367 /*  5.	Load Ld_Tmr and Ld_Thr in HOST_CMD. */
368 
369 	outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
370 	outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
371 
372 /*  6.	Unreset the MII by setting NMRST (in NetSio) to 1. */
373 
374 	outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
375 	addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
376 	TLan_SetBit(TLAN_NET_SIO_NMRST, addr);
377 
378 /*  7.	Setup the remaining registers. */
379 
380 	if (priv->tlanRev >= 0x30) {
381 		data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
382 		TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
383 	}
384 	TLan_PhyDetect(nic);
385 	data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
386 
387 	if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) {
388 		data |= TLAN_NET_CFG_BIT;
389 		if (priv->aui == 1) {
390 			TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
391 		} else if (priv->duplex == TLAN_DUPLEX_FULL) {
392 			TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
393 			priv->tlanFullDuplex = TRUE;
394 		} else {
395 			TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
396 		}
397 	}
398 
399 	if (priv->phyNum == 0) {
400 		data |= TLAN_NET_CFG_PHY_EN;
401 	}
402 	TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
403 
404 	if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
405 		TLan_FinishReset(nic);
406 	} else {
407 		TLan_PhyPowerDown(nic);
408 	}
409 
410 }	/* TLan_ResetAdapter */
411 
TLan_FinishReset(struct nic * nic)412 void TLan_FinishReset(struct nic *nic)
413 {
414 
415 	u8 data;
416 	u32 phy;
417 	u8 sio;
418 	u16 status;
419 	u16 partner;
420 	u16 tlphy_ctl;
421 	u16 tlphy_par;
422 	u16 tlphy_id1, tlphy_id2;
423 	int i;
424 
425 	phy = priv->phy[priv->phyNum];
426 
427 	data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
428 	if (priv->tlanFullDuplex) {
429 		data |= TLAN_NET_CMD_DUPLEX;
430 	}
431 	TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
432 	data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
433 	if (priv->phyNum == 0) {
434 		data |= TLAN_NET_MASK_MASK7;
435 	}
436 	TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
437 	TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
438 	TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &tlphy_id1);
439 	TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &tlphy_id2);
440 
441 	if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY)
442 	    || (priv->aui)) {
443 		status = MII_GS_LINK;
444 		printf("TLAN:  %s: Link forced.\n", priv->nic_name);
445 	} else {
446 		TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
447 		udelay(1000);
448 		TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
449 		if ((status & MII_GS_LINK) &&	/* We only support link info on Nat.Sem. PHY's */
450 		    (tlphy_id1 == NAT_SEM_ID1)
451 		    && (tlphy_id2 == NAT_SEM_ID2)) {
452 			TLan_MiiReadReg(nic, phy, MII_AN_LPA, &partner);
453 			TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR,
454 					&tlphy_par);
455 
456 			printf("TLAN: %s: Link active with ",
457 			       priv->nic_name);
458 			if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
459 				printf("forced 10%sMbps %s-Duplex\n",
460 				       tlphy_par & TLAN_PHY_SPEED_100 ? ""
461 				       : "0",
462 				       tlphy_par & TLAN_PHY_DUPLEX_FULL ?
463 				       "Full" : "Half");
464 			} else {
465 				printf
466 				    ("AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
467 				     tlphy_par & TLAN_PHY_SPEED_100 ? "" :
468 				     "0",
469 				     tlphy_par & TLAN_PHY_DUPLEX_FULL ?
470 				     "Full" : "Half");
471 				printf("TLAN: Partner capability: ");
472 				for (i = 5; i <= 10; i++)
473 					if (partner & (1 << i))
474 						printf("%s", media[i - 5]);
475 				printf("\n");
476 			}
477 
478 			TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
479 #ifdef MONITOR
480 			/* We have link beat..for now anyway */
481 			priv->link = 1;
482 			/*Enabling link beat monitoring */
483 			/* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_LINK_BEAT ); */
484 			mdelay(10000);
485 			TLan_PhyMonitor(nic);
486 #endif
487 		} else if (status & MII_GS_LINK) {
488 			printf("TLAN: %s: Link active\n", priv->nic_name);
489 			TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
490 		}
491 	}
492 
493 	if (priv->phyNum == 0) {
494 		TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl);
495 		tlphy_ctl |= TLAN_TC_INTEN;
496 		TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl);
497 		sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
498 		sio |= TLAN_NET_SIO_MINTEN;
499 		TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
500 	}
501 
502 	if (status & MII_GS_LINK) {
503 		TLan_SetMac(nic, 0, nic->node_addr);
504 		priv->phyOnline = 1;
505 		outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
506 /*		if ( debug >= 1 && debug != TLAN_DEBUG_PROBE ) {
507 			outb( ( TLAN_HC_REQ_INT >> 8 ), BASE + TLAN_HOST_CMD + 1 );
508 		}
509 
510 		*/
511 		outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
512 		outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);
513 	} else {
514 		printf
515 		    ("TLAN: %s: Link inactive, will retry in 10 secs...\n",
516 		     priv->nic_name);
517 		/* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_FINISH_RESET ); */
518 		mdelay(10000);
519 		TLan_FinishReset(nic);
520 		return;
521 
522 	}
523 
524 }	/* TLan_FinishReset */
525 
526 /**************************************************************************
527 POLL - Wait for a frame
528 ***************************************************************************/
tlan_poll(struct nic * nic,int retrieve)529 static int tlan_poll(struct nic *nic, int retrieve)
530 {
531 	/* return true if there's an ethernet packet ready to read */
532 	/* nic->packet should contain data on return */
533 	/* nic->packetlen should contain length of data */
534 	u32 framesize;
535 	u32 host_cmd = 0;
536 	u32 ack = 1;
537 	int eoc = 0;
538 	int entry = priv->cur_rx % TLAN_NUM_RX_LISTS;
539 	u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat);
540 	u16 host_int = inw(BASE + TLAN_HOST_INT);
541 
542 	if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve)
543 	  return 1;
544 
545 	outw(host_int, BASE + TLAN_HOST_INT);
546 
547 	if (!(tmpCStat & TLAN_CSTAT_FRM_CMP))
548 		return 0;
549 
550 	/* printf("PI-1: 0x%hX\n", host_int); */
551 	if (tmpCStat & TLAN_CSTAT_EOC)
552 		eoc = 1;
553 
554 	framesize = rx_ring[entry].frameSize;
555 
556 	nic->packetlen = framesize;
557 
558 #ifdef EBDEBUG
559      printf(".%d.", framesize);
560 #endif
561 
562 	memcpy(nic->packet, rxb +
563 	       (priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen);
564 
565 	rx_ring[entry].cStat = 0;
566 #ifdef EBDEBUG
567 	hex_dump(nic->packet, nic->packetlen);
568 	printf("%d", entry);
569 #endif
570 	entry = (entry + 1) % TLAN_NUM_RX_LISTS;
571 	priv->cur_rx = entry;
572 	if (eoc) {
573 		if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) ==
574 		    TLAN_CSTAT_READY) {
575 			ack |= TLAN_HC_GO | TLAN_HC_RT;
576 			host_cmd = TLAN_HC_ACK | ack | 0x001C0000;
577 			outl(host_cmd, BASE + TLAN_HOST_CMD);
578 		}
579 	} else {
580 		host_cmd = TLAN_HC_ACK | ack | (0x000C0000);
581 		outl(host_cmd, BASE + TLAN_HOST_CMD);
582 #ifdef EBDEBUG
583 		printf("AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM));
584 		host_int = inw(BASE + TLAN_HOST_INT);
585 		printf("PI-2: 0x%hX\n", host_int);
586 #endif
587 	}
588 	refill_rx(nic);
589 	return (1);		/* initially as this is called to flush the input */
590 }
591 
refill_rx(struct nic * nic __unused)592 static void refill_rx(struct nic *nic __unused)
593 {
594 	int entry = 0;
595 
596 	for (;
597 	     (priv->cur_rx - priv->dirty_rx +
598 	      TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0;
599 	     priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) {
600 		entry = priv->dirty_rx % TLAN_NUM_TX_LISTS;
601 		rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE;
602 		rx_ring[entry].cStat = TLAN_CSTAT_READY;
603 	}
604 
605 }
606 
607 /* #define EBDEBUG */
608 /**************************************************************************
609 TRANSMIT - Transmit a frame
610 ***************************************************************************/
tlan_transmit(struct nic * nic,const char * d,unsigned int t,unsigned int s,const char * p)611 static void tlan_transmit(struct nic *nic, const char *d,	/* Destination */
612 			  unsigned int t,	/* Type */
613 			  unsigned int s,	/* size */
614 			  const char *p)
615 {				/* Packet */
616 	u16 nstype;
617 	u32 to;
618 	struct TLanList *tail_list;
619 	struct TLanList *head_list;
620 	u8 *tail_buffer;
621 	u32 ack = 0;
622 	u32 host_cmd;
623 	int eoc = 0;
624 	u16 tmpCStat;
625 #ifdef EBDEBUG
626 	u16 host_int = inw(BASE + TLAN_HOST_INT);
627 #endif
628 	int entry = 0;
629 
630 #ifdef EBDEBUG
631 	printf("INT0-0x%hX\n", host_int);
632 #endif
633 
634 	if (!priv->phyOnline) {
635 		printf("TRANSMIT:  %s PHY is not ready\n", priv->nic_name);
636 		return;
637 	}
638 
639 	tail_list = priv->txList + priv->txTail;
640 
641 	if (tail_list->cStat != TLAN_CSTAT_UNUSED) {
642 		printf("TRANSMIT: %s is busy (Head=%d Tail=%d)\n",
643 		       priv->nic_name, priv->txList, priv->txTail);
644 		tx_ring[entry].cStat = TLAN_CSTAT_UNUSED;
645 		priv->txBusyCount++;
646 		return;
647 	}
648 
649 	tail_list->forward = 0;
650 
651 	tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE);
652 
653 	/* send the packet to destination */
654 	memcpy(tail_buffer, d, ETH_ALEN);
655 	memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN);
656 	nstype = htons((u16) t);
657 	memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2);
658 	memcpy(tail_buffer + ETH_HLEN, p, s);
659 
660 	s += ETH_HLEN;
661 	s &= 0x0FFF;
662 	while (s < ETH_ZLEN)
663 		tail_buffer[s++] = '\0';
664 
665 	/*=====================================================*/
666 	/* Receive
667 	 * 0000 0000 0001 1100
668 	 * 0000 0000 0000 1100
669 	 * 0000 0000 0000 0011 = 0x0003
670 	 *
671 	 * 0000 0000 0000 0000 0000 0000 0000 0011
672 	 * 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000
673 	 *
674 	 * Transmit
675 	 * 0000 0000 0001 1100
676 	 * 0000 0000 0000 0100
677 	 * 0000 0000 0000 0001 = 0x0001
678 	 *
679 	 * 0000 0000 0000 0000 0000 0000 0000 0001
680 	 * 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000
681 	 * */
682 
683 	/* Setup the transmit descriptor */
684 	tail_list->frameSize = (u16) s;
685 	tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) s;
686 	tail_list->buffer[1].count = 0;
687 	tail_list->buffer[1].address = 0;
688 
689 	tail_list->cStat = TLAN_CSTAT_READY;
690 
691 #ifdef EBDEBUG
692 	host_int = inw(BASE + TLAN_HOST_INT);
693 	printf("INT1-0x%hX\n", host_int);
694 #endif
695 
696 	if (!priv->txInProgress) {
697 		priv->txInProgress = 1;
698 		outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
699 		outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
700 	} else {
701 		if (priv->txTail == 0) {
702 #ifdef EBDEBUG
703 			printf("Out buffer\n");
704 #endif
705 			(priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward =
706 			    virt_to_le32desc(tail_list);
707 		} else {
708 #ifdef EBDEBUG
709 			printf("Fix this \n");
710 #endif
711 			(priv->txList + (priv->txTail - 1))->forward =
712 			    virt_to_le32desc(tail_list);
713 		}
714 	}
715 
716 	CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS);
717 
718 #ifdef EBDEBUG
719 	host_int = inw(BASE + TLAN_HOST_INT);
720 	printf("INT2-0x%hX\n", host_int);
721 #endif
722 
723 	to = currticks() + TX_TIME_OUT;
724 	while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to);
725 
726 	head_list = priv->txList + priv->txHead;
727 	while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP)
728 			&& (ack < 255)) {
729 		ack++;
730 		if(tmpCStat & TLAN_CSTAT_EOC)
731 			eoc =1;
732 		head_list->cStat = TLAN_CSTAT_UNUSED;
733 		CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS);
734 		head_list = priv->txList + priv->txHead;
735 
736 	}
737 	if(!ack)
738 		printf("Incomplete TX Frame\n");
739 
740 	if(eoc) {
741 		head_list = priv->txList + priv->txHead;
742 		if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
743 			outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
744 			ack |= TLAN_HC_GO;
745 		} else {
746 			priv->txInProgress = 0;
747 		}
748 	}
749 	if(ack) {
750 		host_cmd = TLAN_HC_ACK | ack;
751 		outl(host_cmd, BASE + TLAN_HOST_CMD);
752 	}
753 
754 	if(priv->tlanRev < 0x30 ) {
755 		ack = 1;
756 		head_list = priv->txList + priv->txHead;
757 		if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
758 			outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
759 			ack |= TLAN_HC_GO;
760 		} else {
761 			priv->txInProgress = 0;
762 		}
763 		host_cmd = TLAN_HC_ACK | ack | 0x00140000;
764 		outl(host_cmd, BASE + TLAN_HOST_CMD);
765 
766 	}
767 
768 	if (currticks() >= to) {
769 		printf("TX Time Out");
770 	}
771 }
772 
773 /**************************************************************************
774 DISABLE - Turn off ethernet interface
775 ***************************************************************************/
776 #ifdef EB51
tlan_disable(struct dev * dev __unused)777 static void tlan_disable(struct dev *dev __unused)
778 #else
779 static void tlan_disable(struct nic *nic __unused)
780 #endif
781 {
782 	/* put the card in its initial state */
783 	/* This function serves 3 purposes.
784 	 * This disables DMA and interrupts so we don't receive
785 	 *  unexpected packets or interrupts from the card after
786 	 *  etherboot has finished.
787 	 * This frees resources so etherboot may use
788 	 *  this driver on another interface
789 	 * This allows etherboot to reinitialize the interface
790 	 *  if something is something goes wrong.
791 	 *
792 	 */
793 	outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
794 }
795 
796 /**************************************************************************
797 IRQ - Enable, Disable, or Force interrupts
798 ***************************************************************************/
tlan_irq(struct nic * nic __unused,irq_action_t action __unused)799 static void tlan_irq(struct nic *nic __unused, irq_action_t action __unused)
800 {
801   switch ( action ) {
802   case DISABLE :
803     break;
804   case ENABLE :
805     break;
806   case FORCE :
807     break;
808   }
809 }
810 
TLan_SetMulticastList(struct nic * nic)811 static void TLan_SetMulticastList(struct nic *nic) {
812 	int i;
813 	u8 tmp;
814 
815 	/* !IFF_PROMISC */
816 	tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
817 	TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
818 
819 	/* IFF_ALLMULTI */
820 	for(i = 0; i< 3; i++)
821 		TLan_SetMac(nic, i + 1, NULL);
822 	TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
823 	TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
824 
825 
826 }
827 /**************************************************************************
828 PROBE - Look for an adapter, this routine's visible to the outside
829 ***************************************************************************/
830 
831 #define board_found 1
832 #define valid_link 0
833 #ifdef EB51
tlan_probe(struct dev * dev,struct pci_device * pci)834 static int tlan_probe(struct dev *dev, struct pci_device *pci)
835 {
836 	struct nic *nic = (struct nic *) dev;
837 #else
838 struct nic *tlan_probe(struct nic *nic, unsigned short *io_addrs, struct pci_device *pci)
839 {
840 #endif
841 		u16 data = 0;
842 	int err;
843 	int i;
844 
845 	if (pci->ioaddr == 0)
846 		return 0;
847 
848 	nic->irqno  = 0;
849 	nic->ioaddr = pci->ioaddr & ~3;
850 
851 	BASE = pci->ioaddr;
852 	printf("\n");
853 	printf("tlan.c: %s, %s\n", drv_version, drv_date);
854 	printf("%s: Probing for Vendor 0x%hX, Device 0x%hX",
855 	       pci->name, pci->vendor, pci->dev_id);
856 
857 
858 	/* I really must find out what this does */
859 	adjust_pci_device(pci);
860 
861 	/* Point to private storage */
862 	priv = &TLanPrivateInfo;
863 	/* Figure out which chip we're dealing with */
864 	i = 0;
865 	chip_idx = -1;
866 
867 	while (tlan_pci_tbl[i].name) {
868 		if ((((u32) pci->dev_id << 16) | pci->vendor) ==
869 		    (tlan_pci_tbl[i].id.pci & 0xffffffff)) {
870 			chip_idx = i;
871 			break;
872 		}
873 		i++;
874 	}
875 
876 	priv->vendor_id = pci->vendor;
877 	priv->dev_id = pci->dev_id;
878 	priv->nic_name = pci->name;
879 	priv->eoc = 0;
880 
881 	err = 0;
882 	for (i = 0; i < 6; i++)
883 		err |= TLan_EeReadByte(BASE,
884 				       (u8) tlan_pci_tbl[chip_idx].
885 				       addrOfs + i,
886 				       (u8 *) & nic->node_addr[i]);
887 	if (err) {
888 		printf("TLAN: %s: Error reading MAC from eeprom: %d\n",
889 		       pci->name, err);
890 	} else
891 		printf("\nAddress: %!\n", nic->node_addr);
892 
893 	priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
894 	printf("\nRevision = 0x%hX\n", priv->tlanRev);
895 
896 	TLan_ResetLists(nic);
897 	TLan_ResetAdapter(nic);
898 /*
899 	data = inl(BASE + TLAN_HOST_CMD);
900 	data |= TLAN_HC_EOC;
901 	outw(data, BASE + TLAN_HOST_CMD);
902 */
903 
904 	data = inl(BASE + TLAN_HOST_CMD);
905 	data |= TLAN_HC_INT_OFF;
906 	outw(data, BASE + TLAN_HOST_CMD);
907 
908 	TLan_SetMulticastList(nic);
909 	udelay(100);
910 	priv->txList = tx_ring;
911 	priv->rxList = rx_ring;
912 /*	if (board_found && valid_link)
913 	{*/
914 	/* point to NIC specific routines */
915 #ifdef EB51
916 	dev->disable = tlan_disable;
917 	nic->poll = tlan_poll;
918 	nic->transmit = tlan_transmit;
919 	nic->irq    = tlan_irq;
920 	return 1;
921 #else
922 	nic->disable = tlan_disable;
923 	nic->poll = tlan_poll;
924 	nic->transmit = tlan_transmit;
925 	nic->irq    = tlan_irq;
926 	return nic;
927 #endif
928 }
929 
930 
931 /*****************************************************************************
932 ******************************************************************************
933 
934 	ThunderLAN Driver Eeprom routines
935 
936 	The Compaq Netelligent 10 and 10/100 cards use a Microchip 24C02A
937 	EEPROM.  These functions are based on information in Microchip's
938 	data sheet.  I don't know how well this functions will work with
939 	other EEPROMs.
940 
941 ******************************************************************************
942 *****************************************************************************/
943 
944 
945 	/***************************************************************
946 	 *	TLan_EeSendStart
947 	 *
948 	 *	Returns:
949 	 *		Nothing
950 	 *	Parms:
951 	 *		io_base		The IO port base address for the
952 	 *				TLAN device with the EEPROM to
953 	 *				use.
954 	 *
955 	 *	This function sends a start cycle to an EEPROM attached
956 	 *	to a TLAN chip.
957 	 *
958 	 **************************************************************/
959 
960 void TLan_EeSendStart(u16 io_base)
961 {
962 	u16 sio;
963 
964 	outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
965 	sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
966 
967 	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
968 	TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
969 	TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
970 	TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
971 	TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
972 
973 }				/* TLan_EeSendStart */
974 
975 
976 
977 
978 	/***************************************************************
979 	 *	TLan_EeSendByte
980 	 *
981 	 *	Returns:
982 	 *		If the correct ack was received, 0, otherwise 1
983 	 *	Parms:	io_base		The IO port base address for the
984 	 *				TLAN device with the EEPROM to
985 	 *				use.
986 	 *		data		The 8 bits of information to
987 	 *				send to the EEPROM.
988 	 *		stop		If TLAN_EEPROM_STOP is passed, a
989 	 *				stop cycle is sent after the
990 	 *				byte is sent after the ack is
991 	 *				read.
992 	 *
993 	 *	This function sends a byte on the serial EEPROM line,
994 	 *	driving the clock to send each bit. The function then
995 	 *	reverses transmission direction and reads an acknowledge
996 	 *	bit.
997 	 *
998 	 **************************************************************/
999 
1000 int TLan_EeSendByte(u16 io_base, u8 data, int stop)
1001 {
1002 	int err;
1003 	u8 place;
1004 	u16 sio;
1005 
1006 	outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
1007 	sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
1008 
1009 	/* Assume clock is low, tx is enabled; */
1010 	for (place = 0x80; place != 0; place >>= 1) {
1011 		if (place & data)
1012 			TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
1013 		else
1014 			TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
1015 		TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1016 		TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1017 	}
1018 	TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
1019 	TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1020 	err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio);
1021 	TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1022 	TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
1023 
1024 	if ((!err) && stop) {
1025 		TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);	/* STOP, raise data while clock is high */
1026 		TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1027 		TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
1028 	}
1029 
1030 	return (err);
1031 
1032 }				/* TLan_EeSendByte */
1033 
1034 
1035 
1036 
1037 	/***************************************************************
1038 	 *	TLan_EeReceiveByte
1039 	 *
1040 	 *	Returns:
1041 	 *		Nothing
1042 	 *	Parms:
1043 	 *		io_base		The IO port base address for the
1044 	 *				TLAN device with the EEPROM to
1045 	 *				use.
1046 	 *		data		An address to a char to hold the
1047 	 *				data sent from the EEPROM.
1048 	 *		stop		If TLAN_EEPROM_STOP is passed, a
1049 	 *				stop cycle is sent after the
1050 	 *				byte is received, and no ack is
1051 	 *				sent.
1052 	 *
1053 	 *	This function receives 8 bits of data from the EEPROM
1054 	 *	over the serial link.  It then sends and ack bit, or no
1055 	 *	ack and a stop bit.  This function is used to retrieve
1056 	 *	data after the address of a byte in the EEPROM has been
1057 	 *	sent.
1058 	 *
1059 	 **************************************************************/
1060 
1061 void TLan_EeReceiveByte(u16 io_base, u8 * data, int stop)
1062 {
1063 	u8 place;
1064 	u16 sio;
1065 
1066 	outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
1067 	sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
1068 	*data = 0;
1069 
1070 	/* Assume clock is low, tx is enabled; */
1071 	TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
1072 	for (place = 0x80; place; place >>= 1) {
1073 		TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1074 		if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio))
1075 			*data |= place;
1076 		TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1077 	}
1078 
1079 	TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
1080 	if (!stop) {
1081 		TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);	/* Ack = 0 */
1082 		TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1083 		TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1084 	} else {
1085 		TLan_SetBit(TLAN_NET_SIO_EDATA, sio);	/* No ack = 1 (?) */
1086 		TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1087 		TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1088 		TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);	/* STOP, raise data while clock is high */
1089 		TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1090 		TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
1091 	}
1092 
1093 }				/* TLan_EeReceiveByte */
1094 
1095 
1096 
1097 	/***************************************************************
1098 	 *	TLan_EeReadByte
1099 	 *
1100 	 *	Returns:
1101 	 *		No error = 0, else, the stage at which the error
1102 	 *		occurred.
1103 	 *	Parms:
1104 	 *		io_base		The IO port base address for the
1105 	 *				TLAN device with the EEPROM to
1106 	 *				use.
1107 	 *		ee_addr		The address of the byte in the
1108 	 *				EEPROM whose contents are to be
1109 	 *				retrieved.
1110 	 *		data		An address to a char to hold the
1111 	 *				data obtained from the EEPROM.
1112 	 *
1113 	 *	This function reads a byte of information from an byte
1114 	 *	cell in the EEPROM.
1115 	 *
1116 	 **************************************************************/
1117 
1118 int TLan_EeReadByte(u16 io_base, u8 ee_addr, u8 * data)
1119 {
1120 	int err;
1121 	int ret = 0;
1122 
1123 
1124 	TLan_EeSendStart(io_base);
1125 	err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK);
1126 	if (err) {
1127 		ret = 1;
1128 		goto fail;
1129 	}
1130 	err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK);
1131 	if (err) {
1132 		ret = 2;
1133 		goto fail;
1134 	}
1135 	TLan_EeSendStart(io_base);
1136 	err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK);
1137 	if (err) {
1138 		ret = 3;
1139 		goto fail;
1140 	}
1141 	TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP);
1142       fail:
1143 
1144 	return ret;
1145 
1146 }				/* TLan_EeReadByte */
1147 
1148 
1149 /*****************************************************************************
1150 ******************************************************************************
1151 
1152 	ThunderLAN Driver MII Routines
1153 
1154 	These routines are based on the information in Chap. 2 of the
1155 	"ThunderLAN Programmer's Guide", pp. 15-24.
1156 
1157 ******************************************************************************
1158 *****************************************************************************/
1159 
1160 
1161 	/***************************************************************
1162 	 *	TLan_MiiReadReg
1163 	 *
1164 	 *	Returns:
1165 	 *		0	if ack received ok
1166 	 *		1	otherwise.
1167 	 *
1168 	 *	Parms:
1169 	 *		dev		The device structure containing
1170 	 *				The io address and interrupt count
1171 	 *				for this device.
1172 	 *		phy		The address of the PHY to be queried.
1173 	 *		reg		The register whose contents are to be
1174 	 *				retreived.
1175 	 *		val		A pointer to a variable to store the
1176 	 *				retrieved value.
1177 	 *
1178 	 *	This function uses the TLAN's MII bus to retreive the contents
1179 	 *	of a given register on a PHY.  It sends the appropriate info
1180 	 *	and then reads the 16-bit register value from the MII bus via
1181 	 *	the TLAN SIO register.
1182 	 *
1183 	 **************************************************************/
1184 
1185 int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val)
1186 {
1187 	u8 nack;
1188 	u16 sio, tmp;
1189 	u32 i;
1190 	int err;
1191 	int minten;
1192 
1193 	err = FALSE;
1194 	outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1195 	sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1196 
1197 	TLan_MiiSync(BASE);
1198 
1199 	minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1200 	if (minten)
1201 		TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1202 
1203 	TLan_MiiSendData(BASE, 0x1, 2);	/* Start ( 01b ) */
1204 	TLan_MiiSendData(BASE, 0x2, 2);	/* Read  ( 10b ) */
1205 	TLan_MiiSendData(BASE, phy, 5);	/* Device #      */
1206 	TLan_MiiSendData(BASE, reg, 5);	/* Register #    */
1207 
1208 
1209 	TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);	/* Change direction */
1210 
1211 	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);	/* Clock Idle bit */
1212 	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1213 	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);	/* Wait 300ns */
1214 
1215 	nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);	/* Check for ACK */
1216 	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);	/* Finish ACK */
1217 	if (nack) {		/* No ACK, so fake it */
1218 		for (i = 0; i < 16; i++) {
1219 			TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1220 			TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1221 		}
1222 		tmp = 0xffff;
1223 		err = TRUE;
1224 	} else {		/* ACK, so read data */
1225 		for (tmp = 0, i = 0x8000; i; i >>= 1) {
1226 			TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1227 			if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
1228 				tmp |= i;
1229 			TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1230 		}
1231 	}
1232 
1233 
1234 	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);	/* Idle cycle */
1235 	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1236 
1237 	if (minten)
1238 		TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1239 
1240 	*val = tmp;
1241 
1242 	return err;
1243 
1244 }				/* TLan_MiiReadReg */
1245 
1246 	/***************************************************************
1247 	 *	TLan_MiiSendData
1248 	 *
1249 	 *	Returns:
1250 	 *		Nothing
1251 	 *	Parms:
1252 	 *		base_port	The base IO port of the adapter	in
1253 	 *				question.
1254 	 *		dev		The address of the PHY to be queried.
1255 	 *		data		The value to be placed on the MII bus.
1256 	 *		num_bits	The number of bits in data that are to
1257 	 *				be placed on the MII bus.
1258 	 *
1259 	 *	This function sends on sequence of bits on the MII
1260 	 *	configuration bus.
1261 	 *
1262 	 **************************************************************/
1263 
1264 void TLan_MiiSendData(u16 base_port, u32 data, unsigned num_bits)
1265 {
1266 	u16 sio;
1267 	u32 i;
1268 
1269 	if (num_bits == 0)
1270 		return;
1271 
1272 	outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1273 	sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1274 	TLan_SetBit(TLAN_NET_SIO_MTXEN, sio);
1275 
1276 	for (i = (0x1 << (num_bits - 1)); i; i >>= 1) {
1277 		TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1278 		(void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1279 		if (data & i)
1280 			TLan_SetBit(TLAN_NET_SIO_MDATA, sio);
1281 		else
1282 			TLan_ClearBit(TLAN_NET_SIO_MDATA, sio);
1283 		TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1284 		(void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1285 	}
1286 
1287 }				/* TLan_MiiSendData */
1288 
1289 
1290 
1291 
1292 	/***************************************************************
1293 	 *	TLan_MiiSync
1294 	 *
1295 	 *	Returns:
1296 	 *		Nothing
1297 	 *	Parms:
1298 	 *		base_port	The base IO port of the adapter in
1299 	 *				question.
1300 	 *
1301 	 *	This functions syncs all PHYs in terms of the MII configuration
1302 	 *	bus.
1303 	 *
1304 	 **************************************************************/
1305 
1306 void TLan_MiiSync(u16 base_port)
1307 {
1308 	int i;
1309 	u16 sio;
1310 
1311 	outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1312 	sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1313 
1314 	TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
1315 	for (i = 0; i < 32; i++) {
1316 		TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1317 		TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1318 	}
1319 
1320 }				/* TLan_MiiSync */
1321 
1322 
1323 
1324 
1325 	/***************************************************************
1326 	 *	TLan_MiiWriteReg
1327 	 *
1328 	 *	Returns:
1329 	 *		Nothing
1330 	 *	Parms:
1331 	 *		dev		The device structure for the device
1332 	 *				to write to.
1333 	 *		phy		The address of the PHY to be written to.
1334 	 *		reg		The register whose contents are to be
1335 	 *				written.
1336 	 *		val		The value to be written to the register.
1337 	 *
1338 	 *	This function uses the TLAN's MII bus to write the contents of a
1339 	 *	given register on a PHY.  It sends the appropriate info and then
1340 	 *	writes the 16-bit register value from the MII configuration bus
1341 	 *	via the TLAN SIO register.
1342 	 *
1343 	 **************************************************************/
1344 
1345 void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val)
1346 {
1347 	u16 sio;
1348 	int minten;
1349 
1350 	outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1351 	sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1352 
1353 	TLan_MiiSync(BASE);
1354 
1355 	minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1356 	if (minten)
1357 		TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1358 
1359 	TLan_MiiSendData(BASE, 0x1, 2);	/* Start ( 01b ) */
1360 	TLan_MiiSendData(BASE, 0x1, 2);	/* Write ( 01b ) */
1361 	TLan_MiiSendData(BASE, phy, 5);	/* Device #      */
1362 	TLan_MiiSendData(BASE, reg, 5);	/* Register #    */
1363 
1364 	TLan_MiiSendData(BASE, 0x2, 2);	/* Send ACK */
1365 	TLan_MiiSendData(BASE, val, 16);	/* Send Data */
1366 
1367 	TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);	/* Idle cycle */
1368 	TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1369 
1370 	if (minten)
1371 		TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1372 
1373 
1374 }				/* TLan_MiiWriteReg */
1375 
1376 	/***************************************************************
1377 	 *	TLan_SetMac
1378 	 *
1379 	 *	Returns:
1380 	 *		Nothing
1381 	 *	Parms:
1382 	 *		dev	Pointer to device structure of adapter
1383 	 *			on which to change the AREG.
1384 	 *		areg	The AREG to set the address in (0 - 3).
1385 	 *		mac	A pointer to an array of chars.  Each
1386 	 *			element stores one byte of the address.
1387 	 *			IE, it isn't in ascii.
1388 	 *
1389 	 *	This function transfers a MAC address to one of the
1390 	 *	TLAN AREGs (address registers).  The TLAN chip locks
1391 	 *	the register on writing to offset 0 and unlocks the
1392 	 *	register after writing to offset 5.  If NULL is passed
1393 	 *	in mac, then the AREG is filled with 0's.
1394 	 *
1395 	 **************************************************************/
1396 
1397 void TLan_SetMac(struct nic *nic __unused, int areg, char *mac)
1398 {
1399 	int i;
1400 
1401 	areg *= 6;
1402 
1403 	if (mac != NULL) {
1404 		for (i = 0; i < 6; i++)
1405 			TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
1406 				       mac[i]);
1407 	} else {
1408 		for (i = 0; i < 6; i++)
1409 			TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
1410 	}
1411 
1412 }				/* TLan_SetMac */
1413 
1414 	/*********************************************************************
1415 	 *	TLan_PhyDetect
1416 	 *
1417 	 *	Returns:
1418 	 *		Nothing
1419 	 *	Parms:
1420 	 *		dev	A pointer to the device structure of the adapter
1421 	 *			for which the PHY needs determined.
1422 	 *
1423 	 *	So far I've found that adapters which have external PHYs
1424 	 *	may also use the internal PHY for part of the functionality.
1425 	 *	(eg, AUI/Thinnet).  This function finds out if this TLAN
1426 	 *	chip has an internal PHY, and then finds the first external
1427 	 *	PHY (starting from address 0) if it exists).
1428 	 *
1429 	 ********************************************************************/
1430 
1431 void TLan_PhyDetect(struct nic *nic)
1432 {
1433 	u16 control;
1434 	u16 hi;
1435 	u16 lo;
1436 	u32 phy;
1437 
1438 	if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
1439 		priv->phyNum = 0xFFFF;
1440 		return;
1441 	}
1442 
1443 	TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_GEN_ID_HI, &hi);
1444 
1445 	if (hi != 0xFFFF) {
1446 		priv->phy[0] = TLAN_PHY_MAX_ADDR;
1447 	} else {
1448 		priv->phy[0] = TLAN_PHY_NONE;
1449 	}
1450 
1451 	priv->phy[1] = TLAN_PHY_NONE;
1452 	for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {
1453 		TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &control);
1454 		TLan_MiiReadReg(nic, phy, MII_GEN_ID_HI, &hi);
1455 		TLan_MiiReadReg(nic, phy, MII_GEN_ID_LO, &lo);
1456 		if ((control != 0xFFFF) || (hi != 0xFFFF)
1457 		    || (lo != 0xFFFF)) {
1458 			printf("PHY found at %hX %hX %hX %hX\n", phy,
1459 			       control, hi, lo);
1460 			if ((priv->phy[1] == TLAN_PHY_NONE)
1461 			    && (phy != TLAN_PHY_MAX_ADDR)) {
1462 				priv->phy[1] = phy;
1463 			}
1464 		}
1465 	}
1466 
1467 	if (priv->phy[1] != TLAN_PHY_NONE) {
1468 		priv->phyNum = 1;
1469 	} else if (priv->phy[0] != TLAN_PHY_NONE) {
1470 		priv->phyNum = 0;
1471 	} else {
1472 		printf
1473 		    ("TLAN:  Cannot initialize device, no PHY was found!\n");
1474 	}
1475 
1476 }				/* TLan_PhyDetect */
1477 
1478 void TLan_PhyPowerDown(struct nic *nic)
1479 {
1480 
1481 	u16 value;
1482 	printf("%s: Powering down PHY(s).\n", priv->nic_name);
1483 	value = MII_GC_PDOWN | MII_GC_LOOPBK | MII_GC_ISOLATE;
1484 	TLan_MiiSync(BASE);
1485 	TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1486 	if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE)
1487 	    &&
1488 	    (!(tlan_pci_tbl[chip_idx].
1489 	       flags & TLAN_ADAPTER_USE_INTERN_10))) {
1490 		TLan_MiiSync(BASE);
1491 		TLan_MiiWriteReg(nic, priv->phy[1], MII_GEN_CTL, value);
1492 	}
1493 
1494 	/* Wait for 50 ms and powerup
1495 	 * This is abitrary.  It is intended to make sure the
1496 	 * tranceiver settles.
1497 	 */
1498 	/* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */
1499 	mdelay(50);
1500 	TLan_PhyPowerUp(nic);
1501 
1502 }				/* TLan_PhyPowerDown */
1503 
1504 
1505 void TLan_PhyPowerUp(struct nic *nic)
1506 {
1507 	u16 value;
1508 
1509 	printf("%s: Powering up PHY.\n", priv->nic_name);
1510 	TLan_MiiSync(BASE);
1511 	value = MII_GC_LOOPBK;
1512 	TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_GEN_CTL, value);
1513 	TLan_MiiSync(BASE);
1514 	/* Wait for 500 ms and reset the
1515 	 * tranceiver.  The TLAN docs say both 50 ms and
1516 	 * 500 ms, so do the longer, just in case.
1517 	 */
1518 	mdelay(500);
1519 	TLan_PhyReset(nic);
1520 	/* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */
1521 
1522 }				/* TLan_PhyPowerUp */
1523 
1524 void TLan_PhyReset(struct nic *nic)
1525 {
1526 	u16 phy;
1527 	u16 value;
1528 
1529 	phy = priv->phy[priv->phyNum];
1530 
1531 	printf("%s: Reseting PHY.\n", priv->nic_name);
1532 	TLan_MiiSync(BASE);
1533 	value = MII_GC_LOOPBK | MII_GC_RESET;
1534 	TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, value);
1535 	TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1536 	while (value & MII_GC_RESET) {
1537 		TLan_MiiReadReg(nic, phy, MII_GEN_CTL, &value);
1538 	}
1539 
1540 	/* Wait for 500 ms and initialize.
1541 	 * I don't remember why I wait this long.
1542 	 * I've changed this to 50ms, as it seems long enough.
1543 	 */
1544 	/* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */
1545 	mdelay(50);
1546 	TLan_PhyStartLink(nic);
1547 
1548 }				/* TLan_PhyReset */
1549 
1550 
1551 void TLan_PhyStartLink(struct nic *nic)
1552 {
1553 
1554 	u16 ability;
1555 	u16 control;
1556 	u16 data;
1557 	u16 phy;
1558 	u16 status;
1559 	u16 tctl;
1560 
1561 	phy = priv->phy[priv->phyNum];
1562 	printf("%s: Trying to activate link.\n", priv->nic_name);
1563 	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1564 	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &ability);
1565 
1566 	if ((status & MII_GS_AUTONEG) && (!priv->aui)) {
1567 		ability = status >> 11;
1568 		if (priv->speed == TLAN_SPEED_10 &&
1569 		    priv->duplex == TLAN_DUPLEX_HALF) {
1570 			TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0000);
1571 		} else if (priv->speed == TLAN_SPEED_10 &&
1572 			   priv->duplex == TLAN_DUPLEX_FULL) {
1573 			priv->tlanFullDuplex = TRUE;
1574 			TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x0100);
1575 		} else if (priv->speed == TLAN_SPEED_100 &&
1576 			   priv->duplex == TLAN_DUPLEX_HALF) {
1577 			TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2000);
1578 		} else if (priv->speed == TLAN_SPEED_100 &&
1579 			   priv->duplex == TLAN_DUPLEX_FULL) {
1580 			priv->tlanFullDuplex = TRUE;
1581 			TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x2100);
1582 		} else {
1583 
1584 			/* Set Auto-Neg advertisement */
1585 			TLan_MiiWriteReg(nic, phy, MII_AN_ADV,
1586 					 (ability << 5) | 1);
1587 			/* Enablee Auto-Neg */
1588 			TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1000);
1589 			/* Restart Auto-Neg */
1590 			TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, 0x1200);
1591 			/* Wait for 4 sec for autonegotiation
1592 			 * to complete.  The max spec time is less than this
1593 			 * but the card need additional time to start AN.
1594 			 * .5 sec should be plenty extra.
1595 			 */
1596 			printf("TLAN: %s: Starting autonegotiation.\n",
1597 			       priv->nic_name);
1598 			mdelay(4000);
1599 			TLan_PhyFinishAutoNeg(nic);
1600 			/* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1601 			return;
1602 		}
1603 
1604 	}
1605 
1606 	if ((priv->aui) && (priv->phyNum != 0)) {
1607 		priv->phyNum = 0;
1608 		data =
1609 		    TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1610 		    TLAN_NET_CFG_PHY_EN;
1611 		TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1612 		mdelay(50);
1613 		/* TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1614 		TLan_PhyPowerDown(nic);
1615 		return;
1616 	} else if (priv->phyNum == 0) {
1617 		control = 0;
1618 		TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl);
1619 		if (priv->aui) {
1620 			tctl |= TLAN_TC_AUISEL;
1621 		} else {
1622 			tctl &= ~TLAN_TC_AUISEL;
1623 			if (priv->duplex == TLAN_DUPLEX_FULL) {
1624 				control |= MII_GC_DUPLEX;
1625 				priv->tlanFullDuplex = TRUE;
1626 			}
1627 			if (priv->speed == TLAN_SPEED_100) {
1628 				control |= MII_GC_SPEEDSEL;
1629 			}
1630 		}
1631 		TLan_MiiWriteReg(nic, phy, MII_GEN_CTL, control);
1632 		TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl);
1633 	}
1634 
1635 	/* Wait for 2 sec to give the tranceiver time
1636 	 * to establish link.
1637 	 */
1638 	/* TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET ); */
1639 	mdelay(2000);
1640 	TLan_FinishReset(nic);
1641 
1642 }				/* TLan_PhyStartLink */
1643 
1644 void TLan_PhyFinishAutoNeg(struct nic *nic)
1645 {
1646 
1647 	u16 an_adv;
1648 	u16 an_lpa;
1649 	u16 data;
1650 	u16 mode;
1651 	u16 phy;
1652 	u16 status;
1653 
1654 	phy = priv->phy[priv->phyNum];
1655 
1656 	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1657 	udelay(1000);
1658 	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &status);
1659 
1660 	if (!(status & MII_GS_AUTOCMPLT)) {
1661 		/* Wait for 8 sec to give the process
1662 		 * more time.  Perhaps we should fail after a while.
1663 		 */
1664 		if (!priv->neg_be_verbose++) {
1665 			printf
1666 			    ("TLAN:  Giving autonegotiation more time.\n");
1667 			printf
1668 			    ("TLAN:  Please check that your adapter has\n");
1669 			printf
1670 			    ("TLAN:  been properly connected to a HUB or Switch.\n");
1671 			printf
1672 			    ("TLAN:  Trying to establish link in the background...\n");
1673 		}
1674 		mdelay(8000);
1675 		TLan_PhyFinishAutoNeg(nic);
1676 		/* TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1677 		return;
1678 	}
1679 
1680 	printf("TLAN: %s: Autonegotiation complete.\n", priv->nic_name);
1681 	TLan_MiiReadReg(nic, phy, MII_AN_ADV, &an_adv);
1682 	TLan_MiiReadReg(nic, phy, MII_AN_LPA, &an_lpa);
1683 	mode = an_adv & an_lpa & 0x03E0;
1684 	if (mode & 0x0100) {
1685 		printf("Full Duplex\n");
1686 		priv->tlanFullDuplex = TRUE;
1687 	} else if (!(mode & 0x0080) && (mode & 0x0040)) {
1688 		priv->tlanFullDuplex = TRUE;
1689 		printf("Full Duplex\n");
1690 	}
1691 
1692 	if ((!(mode & 0x0180))
1693 	    && (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10)
1694 	    && (priv->phyNum != 0)) {
1695 		priv->phyNum = 0;
1696 		data =
1697 		    TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1698 		    TLAN_NET_CFG_PHY_EN;
1699 		TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1700 		/* TLan_SetTimer( nic, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1701 		mdelay(400);
1702 		TLan_PhyPowerDown(nic);
1703 		return;
1704 	}
1705 
1706 	if (priv->phyNum == 0) {
1707 		if ((priv->duplex == TLAN_DUPLEX_FULL)
1708 		    || (an_adv & an_lpa & 0x0040)) {
1709 			TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1710 					 MII_GC_AUTOENB | MII_GC_DUPLEX);
1711 			printf
1712 			    ("TLAN:  Starting internal PHY with FULL-DUPLEX\n");
1713 		} else {
1714 			TLan_MiiWriteReg(nic, phy, MII_GEN_CTL,
1715 					 MII_GC_AUTOENB);
1716 			printf
1717 			    ("TLAN:  Starting internal PHY with HALF-DUPLEX\n");
1718 		}
1719 	}
1720 
1721 	/* Wait for 100 ms.  No reason in partiticular.
1722 	 */
1723 	/* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */
1724 	mdelay(100);
1725 	TLan_FinishReset(nic);
1726 
1727 }				/* TLan_PhyFinishAutoNeg */
1728 
1729 #ifdef MONITOR
1730 
1731 	/*********************************************************************
1732         *
1733         *      TLan_phyMonitor
1734         *
1735         *      Returns:
1736         *              None
1737         *
1738         *      Params:
1739         *              dev             The device structure of this device.
1740         *
1741         *
1742         *      This function monitors PHY condition by reading the status
1743         *      register via the MII bus. This can be used to give info
1744         *      about link changes (up/down), and possible switch to alternate
1745         *      media.
1746         *
1747         * ******************************************************************/
1748 
1749 void TLan_PhyMonitor(struct net_device *dev)
1750 {
1751 	TLanPrivateInfo *priv = dev->priv;
1752 	u16 phy;
1753 	u16 phy_status;
1754 
1755 	phy = priv->phy[priv->phyNum];
1756 
1757 	/* Get PHY status register */
1758 	TLan_MiiReadReg(nic, phy, MII_GEN_STS, &phy_status);
1759 
1760 	/* Check if link has been lost */
1761 	if (!(phy_status & MII_GS_LINK)) {
1762 		if (priv->link) {
1763 			priv->link = 0;
1764 			printf("TLAN: %s has lost link\n", priv->nic_name);
1765 			priv->flags &= ~IFF_RUNNING;
1766 			mdelay(2000);
1767 			TLan_PhyMonitor(nic);
1768 			/* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1769 			return;
1770 		}
1771 	}
1772 
1773 	/* Link restablished? */
1774 	if ((phy_status & MII_GS_LINK) && !priv->link) {
1775 		priv->link = 1;
1776 		printf("TLAN: %s has reestablished link\n",
1777 		       priv->nic_name);
1778 		priv->flags |= IFF_RUNNING;
1779 	}
1780 
1781 	/* Setup a new monitor */
1782 	/* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1783 	mdelay(2000);
1784 	TLan_PhyMonitor(nic);
1785 }
1786 
1787 #endif				/* MONITOR */
1788 
1789 #ifdef EB51
1790 static struct pci_id tlan_nics[] = {
1791 	PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP"),
1792 	PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP"),
1793 	PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P"),
1794 	PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P"),
1795 	PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P"),
1796 	PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP"),
1797 	PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP"),
1798 	PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP"),
1799 	PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185"),
1800 	PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325"),
1801 	PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326"),
1802 	PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP"),
1803 	PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax"),
1804 };
1805 
1806 struct pci_driver tlan_driver = {
1807 	.type = NIC_DRIVER,
1808 	.name = "TLAN/PCI",
1809 	.probe = tlan_probe,
1810 	.ids = tlan_nics,
1811 	.id_count = sizeof(tlan_nics) / sizeof(tlan_nics[0]),
1812 	.class = 0,
1813 };
1814 #endif
1815