1 #ifdef ALLMULTI 2 #error multicast support is not yet implemented 3 #endif 4 /* 5 DAVICOM DM9009/DM9102/DM9102A Etherboot Driver V1.00 6 7 This driver was ported from Marty Connor's Tulip Etherboot driver. 8 Thanks Marty Connor (mdc@etherboot.org) 9 10 This davicom etherboot driver supports DM9009/DM9102/DM9102A/ 11 DM9102A+DM9801/DM9102A+DM9802 NICs. 12 13 This software may be used and distributed according to the terms 14 of the GNU Public License, incorporated herein by reference. 15 16 */ 17 18 /*********************************************************************/ 19 /* Revision History */ 20 /*********************************************************************/ 21 22 /* 23 19 OCT 2000 Sten 1.00 24 Different half and full duplex mode 25 Do the different programming for DM9801/DM9802 26 27 12 OCT 2000 Sten 0.90 28 This driver was ported from tulip driver and it 29 has the following difference. 30 Changed symbol tulip/TULIP to davicom/DAVICOM 31 Deleted some code that did not use in this driver. 32 Used chain-strcture to replace ring structure 33 for both TX/RX descriptor. 34 Allocated two tx descriptor. 35 According current media mode to set operating 36 register(CR6) 37 */ 38 39 /*********************************************************************/ 40 /* Declarations */ 41 /*********************************************************************/ 42 43 #include "etherboot.h" 44 #include "nic.h" 45 #include "pci.h" 46 47 #undef DAVICOM_DEBUG 48 #undef DAVICOM_DEBUG_WHERE 49 50 #define TX_TIME_OUT 2*TICKS_PER_SEC 51 52 typedef unsigned char u8; 53 typedef signed char s8; 54 typedef unsigned short u16; 55 typedef signed short s16; 56 typedef unsigned int u32; 57 typedef signed int s32; 58 59 /* Register offsets for davicom device */ 60 enum davicom_offsets { 61 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28, 62 CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58, 63 CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0 64 }; 65 66 /* EEPROM Address width definitions */ 67 #define EEPROM_ADDRLEN 6 68 #define EEPROM_SIZE 32 /* 1 << EEPROM_ADDRLEN */ 69 /* Used to be 128, but we only need to read enough to get the MAC 70 address at bytes 20..25 */ 71 72 /* Data Read from the EEPROM */ 73 static unsigned char ee_data[EEPROM_SIZE]; 74 75 /* The EEPROM commands include the alway-set leading bit. */ 76 #define EE_WRITE_CMD (5 << addr_len) 77 #define EE_READ_CMD (6 << addr_len) 78 #define EE_ERASE_CMD (7 << addr_len) 79 80 /* EEPROM_Ctrl bits. */ 81 #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */ 82 #define EE_CS 0x01 /* EEPROM chip select. */ 83 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */ 84 #define EE_WRITE_0 0x01 85 #define EE_WRITE_1 0x05 86 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */ 87 #define EE_ENB (0x4800 | EE_CS) 88 89 /* Sten 10/11 for phyxcer */ 90 #define PHY_DATA_0 0x0 91 #define PHY_DATA_1 0x20000 92 #define MDCLKH 0x10000 93 94 /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI 95 implementations don't overrun the EEPROM clock. We add a bus 96 turn-around to insure that this remains true. */ 97 #define eeprom_delay() inl(ee_addr) 98 99 /* helpful macro if on a big_endian machine for changing byte order. 100 not strictly needed on Intel 101 Already defined in Etherboot includes 102 #define le16_to_cpu(val) (val) 103 */ 104 105 /* transmit and receive descriptor format */ 106 struct txdesc { 107 volatile unsigned long status; /* owner, status */ 108 unsigned long buf1sz:11, /* size of buffer 1 */ 109 buf2sz:11, /* size of buffer 2 */ 110 control:10; /* control bits */ 111 const unsigned char *buf1addr; /* buffer 1 address */ 112 const unsigned char *buf2addr; /* buffer 2 address */ 113 }; 114 115 struct rxdesc { 116 volatile unsigned long status; /* owner, status */ 117 unsigned long buf1sz:11, /* size of buffer 1 */ 118 buf2sz:11, /* size of buffer 2 */ 119 control:10; /* control bits */ 120 unsigned char *buf1addr; /* buffer 1 address */ 121 unsigned char *buf2addr; /* buffer 2 address */ 122 }; 123 124 /* Size of transmit and receive buffers */ 125 #define BUFLEN 1536 126 127 /*********************************************************************/ 128 /* Global Storage */ 129 /*********************************************************************/ 130 131 /* PCI Bus parameters */ 132 static unsigned short vendor, dev_id; 133 static unsigned long ioaddr; 134 135 /* Note: transmit and receive buffers must be longword aligned and 136 longword divisable */ 137 138 /* transmit descriptor and buffer */ 139 #define NTXD 2 140 static struct txdesc txd[NTXD] __attribute__ ((aligned(4))); 141 static unsigned char txb[BUFLEN] __attribute__ ((aligned(4))); 142 143 /* receive descriptor(s) and buffer(s) */ 144 #define NRXD 4 145 static struct rxdesc rxd[NRXD] __attribute__ ((aligned(4))); 146 static unsigned char rxb[NRXD * BUFLEN] __attribute__ ((aligned(4))); 147 static int rxd_tail; 148 static int TxPtr; 149 150 151 /*********************************************************************/ 152 /* Function Prototypes */ 153 /*********************************************************************/ 154 static void whereami(const char *str); 155 static int read_eeprom(unsigned long ioaddr, int location, int addr_len); 156 static int davicom_probe(struct dev *dev, struct pci_device *pci); 157 static void davicom_init_chain(struct nic *nic); /* Sten 10/9 */ 158 static void davicom_reset(struct nic *nic); 159 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t, 160 unsigned int s, const char *p); 161 static int davicom_poll(struct nic *nic, int retrieve); 162 static void davicom_disable(struct dev *dev); 163 #ifdef DAVICOM_DEBUG 164 static void davicom_more(void); 165 #endif /* DAVICOM_DEBUG */ 166 static void davicom_wait(unsigned int nticks); 167 static int phy_read(int); 168 static void phy_write(int, u16); 169 static void phy_write_1bit(u32, u32); 170 static int phy_read_1bit(u32); 171 static void davicom_media_chk(struct nic *); 172 173 174 /*********************************************************************/ 175 /* Utility Routines */ 176 /*********************************************************************/ 177 static inline void whereami(const char *str) 178 { 179 printf("%s\n", str); 180 /* sleep(2); */ 181 } 182 183 #ifdef DAVICOM_DEBUG 184 static void davicom_more() 185 { 186 printf("\n\n-- more --"); 187 while (!iskey()) 188 /* wait */; 189 getchar(); 190 printf("\n\n"); 191 } 192 #endif /* DAVICOM_DEBUG */ 193 194 static void davicom_wait(unsigned int nticks) 195 { 196 unsigned int to = currticks() + nticks; 197 while (currticks() < to) 198 /* wait */ ; 199 } 200 201 202 /*********************************************************************/ 203 /* For DAVICOM phyxcer register by MII interface */ 204 /*********************************************************************/ 205 /* 206 Read a word data from phy register 207 */ 208 static int phy_read(int location) 209 { 210 int i, phy_addr=1; 211 u16 phy_data; 212 u32 io_dcr9; 213 214 whereami("phy_read\n"); 215 216 io_dcr9 = ioaddr + CSR9; 217 218 /* Send 33 synchronization clock to Phy controller */ 219 for (i=0; i<34; i++) 220 phy_write_1bit(io_dcr9, PHY_DATA_1); 221 222 /* Send start command(01) to Phy */ 223 phy_write_1bit(io_dcr9, PHY_DATA_0); 224 phy_write_1bit(io_dcr9, PHY_DATA_1); 225 226 /* Send read command(10) to Phy */ 227 phy_write_1bit(io_dcr9, PHY_DATA_1); 228 phy_write_1bit(io_dcr9, PHY_DATA_0); 229 230 /* Send Phy addres */ 231 for (i=0x10; i>0; i=i>>1) 232 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); 233 234 /* Send register addres */ 235 for (i=0x10; i>0; i=i>>1) 236 phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0); 237 238 /* Skip transition state */ 239 phy_read_1bit(io_dcr9); 240 241 /* read 16bit data */ 242 for (phy_data=0, i=0; i<16; i++) { 243 phy_data<<=1; 244 phy_data|=phy_read_1bit(io_dcr9); 245 } 246 247 return phy_data; 248 } 249 250 /* 251 Write a word to Phy register 252 */ 253 static void phy_write(int location, u16 phy_data) 254 { 255 u16 i, phy_addr=1; 256 u32 io_dcr9; 257 258 whereami("phy_write\n"); 259 260 io_dcr9 = ioaddr + CSR9; 261 262 /* Send 33 synchronization clock to Phy controller */ 263 for (i=0; i<34; i++) 264 phy_write_1bit(io_dcr9, PHY_DATA_1); 265 266 /* Send start command(01) to Phy */ 267 phy_write_1bit(io_dcr9, PHY_DATA_0); 268 phy_write_1bit(io_dcr9, PHY_DATA_1); 269 270 /* Send write command(01) to Phy */ 271 phy_write_1bit(io_dcr9, PHY_DATA_0); 272 phy_write_1bit(io_dcr9, PHY_DATA_1); 273 274 /* Send Phy addres */ 275 for (i=0x10; i>0; i=i>>1) 276 phy_write_1bit(io_dcr9, phy_addr&i ? PHY_DATA_1: PHY_DATA_0); 277 278 /* Send register addres */ 279 for (i=0x10; i>0; i=i>>1) 280 phy_write_1bit(io_dcr9, location&i ? PHY_DATA_1: PHY_DATA_0); 281 282 /* written trasnition */ 283 phy_write_1bit(io_dcr9, PHY_DATA_1); 284 phy_write_1bit(io_dcr9, PHY_DATA_0); 285 286 /* Write a word data to PHY controller */ 287 for (i=0x8000; i>0; i>>=1) 288 phy_write_1bit(io_dcr9, phy_data&i ? PHY_DATA_1: PHY_DATA_0); 289 } 290 291 /* 292 Write one bit data to Phy Controller 293 */ 294 static void phy_write_1bit(u32 ee_addr, u32 phy_data) 295 { 296 whereami("phy_write_1bit\n"); 297 outl(phy_data, ee_addr); /* MII Clock Low */ 298 eeprom_delay(); 299 outl(phy_data|MDCLKH, ee_addr); /* MII Clock High */ 300 eeprom_delay(); 301 outl(phy_data, ee_addr); /* MII Clock Low */ 302 eeprom_delay(); 303 } 304 305 /* 306 Read one bit phy data from PHY controller 307 */ 308 static int phy_read_1bit(u32 ee_addr) 309 { 310 int phy_data; 311 312 whereami("phy_read_1bit\n"); 313 314 outl(0x50000, ee_addr); 315 eeprom_delay(); 316 317 phy_data=(inl(ee_addr)>>19) & 0x1; 318 319 outl(0x40000, ee_addr); 320 eeprom_delay(); 321 322 return phy_data; 323 } 324 325 /* 326 DM9801/DM9802 present check and program 327 */ 328 static void HPNA_process(void) 329 { 330 331 if ( (phy_read(3) & 0xfff0) == 0xb900 ) { 332 if ( phy_read(31) == 0x4404 ) { 333 /* DM9801 present */ 334 if (phy_read(3) == 0xb901) 335 phy_write(16, 0x5); /* DM9801 E4 */ 336 else 337 phy_write(16, 0x1005); /* DM9801 E3 and others */ 338 phy_write(25, ((phy_read(24) + 3) & 0xff) | 0xf000); 339 } else { 340 /* DM9802 present */ 341 phy_write(16, 0x5); 342 phy_write(25, (phy_read(25) & 0xff00) + 2); 343 } 344 } 345 } 346 347 /* 348 Sense media mode and set CR6 349 */ 350 static void davicom_media_chk(struct nic * nic __unused) 351 { 352 unsigned long to, csr6; 353 354 csr6 = 0x00200000; /* SF */ 355 outl(csr6, ioaddr + CSR6); 356 357 if (vendor == PCI_VENDOR_ID_DAVICOM && dev_id == PCI_DEVICE_ID_DM9009) { 358 /* Set to 10BaseT mode for DM9009 */ 359 phy_write(0, 0); 360 } else { 361 /* For DM9102/DM9102A */ 362 to = currticks() + 2 * TICKS_PER_SEC; 363 while ( ((phy_read(1) & 0x24)!=0x24) && (currticks() < to)) 364 /* wait */ ; 365 366 if ( (phy_read(1) & 0x24) == 0x24 ) { 367 if (phy_read(17) & 0xa000) 368 csr6 |= 0x00000200; /* Full Duplex mode */ 369 } else 370 csr6 |= 0x00040000; /* Select DM9801/DM9802 when Ethernet link failed */ 371 } 372 373 /* set the chip's operating mode */ 374 outl(csr6, ioaddr + CSR6); 375 376 /* DM9801/DM9802 present check & program */ 377 if (csr6 & 0x40000) 378 HPNA_process(); 379 } 380 381 382 /*********************************************************************/ 383 /* EEPROM Reading Code */ 384 /*********************************************************************/ 385 /* EEPROM routines adapted from the Linux Tulip Code */ 386 /* Reading a serial EEPROM is a "bit" grungy, but we work our way 387 through:->. 388 */ 389 static int read_eeprom(unsigned long ioaddr, int location, int addr_len) 390 { 391 int i; 392 unsigned short retval = 0; 393 long ee_addr = ioaddr + CSR9; 394 int read_cmd = location | EE_READ_CMD; 395 396 whereami("read_eeprom\n"); 397 398 outl(EE_ENB & ~EE_CS, ee_addr); 399 outl(EE_ENB, ee_addr); 400 401 /* Shift the read command bits out. */ 402 for (i = 4 + addr_len; i >= 0; i--) { 403 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0; 404 outl(EE_ENB | dataval, ee_addr); 405 eeprom_delay(); 406 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr); 407 eeprom_delay(); 408 } 409 outl(EE_ENB, ee_addr); 410 411 for (i = 16; i > 0; i--) { 412 outl(EE_ENB | EE_SHIFT_CLK, ee_addr); 413 eeprom_delay(); 414 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0); 415 outl(EE_ENB, ee_addr); 416 eeprom_delay(); 417 } 418 419 /* Terminate the EEPROM access. */ 420 outl(EE_ENB & ~EE_CS, ee_addr); 421 return retval; 422 } 423 424 /*********************************************************************/ 425 /* davicom_init_chain - setup the tx and rx descriptors */ 426 /* Sten 10/9 */ 427 /*********************************************************************/ 428 static void davicom_init_chain(struct nic *nic) 429 { 430 int i; 431 432 /* setup the transmit descriptor */ 433 /* Sten: Set 2 TX descriptor but use one TX buffer because 434 it transmit a packet and wait complete every time. */ 435 for (i=0; i<NTXD; i++) { 436 txd[i].buf1addr = (void *)virt_to_bus(&txb[0]); /* Used same TX buffer */ 437 txd[i].buf2addr = (void *)virt_to_bus(&txd[i+1]); /* Point to Next TX desc */ 438 txd[i].buf1sz = 0; 439 txd[i].buf2sz = 0; 440 txd[i].control = 0x184; /* Begin/End/Chain */ 441 txd[i].status = 0x00000000; /* give ownership to Host */ 442 } 443 444 /* construct perfect filter frame with mac address as first match 445 and broadcast address for all others */ 446 for (i=0; i<192; i++) txb[i] = 0xFF; 447 txb[0] = nic->node_addr[0]; 448 txb[1] = nic->node_addr[1]; 449 txb[4] = nic->node_addr[2]; 450 txb[5] = nic->node_addr[3]; 451 txb[8] = nic->node_addr[4]; 452 txb[9] = nic->node_addr[5]; 453 454 /* setup receive descriptor */ 455 for (i=0; i<NRXD; i++) { 456 rxd[i].buf1addr = (void *)virt_to_bus(&rxb[i * BUFLEN]); 457 rxd[i].buf2addr = (void *)virt_to_bus(&rxd[i+1]); /* Point to Next RX desc */ 458 rxd[i].buf1sz = BUFLEN; 459 rxd[i].buf2sz = 0; /* not used */ 460 rxd[i].control = 0x4; /* Chain Structure */ 461 rxd[i].status = 0x80000000; /* give ownership to device */ 462 } 463 464 /* Chain the last descriptor to first */ 465 txd[NTXD - 1].buf2addr = (void *)virt_to_bus(&txd[0]); 466 rxd[NRXD - 1].buf2addr = (void *)virt_to_bus(&rxd[0]); 467 TxPtr = 0; 468 rxd_tail = 0; 469 } 470 471 472 /*********************************************************************/ 473 /* davicom_reset - Reset adapter */ 474 /*********************************************************************/ 475 static void davicom_reset(struct nic *nic) 476 { 477 unsigned long to; 478 479 whereami("davicom_reset\n"); 480 481 /* Stop Tx and RX */ 482 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); 483 484 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */ 485 outl(0x00000001, ioaddr + CSR0); 486 487 davicom_wait(TICKS_PER_SEC); 488 489 /* TX/RX descriptor burst */ 490 outl(0x0C00000, ioaddr + CSR0); /* Sten 10/9 */ 491 492 /* set up transmit and receive descriptors */ 493 davicom_init_chain(nic); /* Sten 10/9 */ 494 495 /* Point to receive descriptor */ 496 outl(virt_to_bus(&rxd[0]), ioaddr + CSR3); 497 outl(virt_to_bus(&txd[0]), ioaddr + CSR4); /* Sten 10/9 */ 498 499 /* According phyxcer media mode to set CR6, 500 DM9102/A phyxcer can auto-detect media mode */ 501 davicom_media_chk(nic); 502 503 /* Prepare Setup Frame Sten 10/9 */ 504 txd[TxPtr].buf1sz = 192; 505 txd[TxPtr].control = 0x024; /* SF/CE */ 506 txd[TxPtr].status = 0x80000000; /* Give ownership to device */ 507 508 /* Start Tx */ 509 outl(inl(ioaddr + CSR6) | 0x00002000, ioaddr + CSR6); 510 /* immediate transmit demand */ 511 outl(0, ioaddr + CSR1); 512 513 to = currticks() + TX_TIME_OUT; 514 while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) /* Sten 10/9 */ 515 /* wait */ ; 516 517 if (currticks() >= to) { 518 printf ("TX Setup Timeout!\n"); 519 } 520 /* Point to next TX descriptor */ 521 TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */ 522 523 #ifdef DAVICOM_DEBUG 524 printf("txd.status = %X\n", txd.status); 525 printf("ticks = %d\n", currticks() - (to - TX_TIME_OUT)); 526 davicom_more(); 527 #endif 528 529 /* enable RX */ 530 outl(inl(ioaddr + CSR6) | 0x00000002, ioaddr + CSR6); 531 /* immediate poll demand */ 532 outl(0, ioaddr + CSR2); 533 } 534 535 536 /*********************************************************************/ 537 /* eth_transmit - Transmit a frame */ 538 /*********************************************************************/ 539 static void davicom_transmit(struct nic *nic, const char *d, unsigned int t, 540 unsigned int s, const char *p) 541 { 542 unsigned long to; 543 544 whereami("davicom_transmit\n"); 545 546 /* Stop Tx */ 547 /* outl(inl(ioaddr + CSR6) & ~0x00002000, ioaddr + CSR6); */ 548 549 /* setup ethernet header */ 550 memcpy(&txb[0], d, ETH_ALEN); /* DA 6byte */ 551 memcpy(&txb[ETH_ALEN], nic->node_addr, ETH_ALEN); /* SA 6byte*/ 552 txb[ETH_ALEN*2] = (t >> 8) & 0xFF; /* Frame type: 2byte */ 553 txb[ETH_ALEN*2+1] = t & 0xFF; 554 memcpy(&txb[ETH_HLEN], p, s); /* Frame data */ 555 556 /* setup the transmit descriptor */ 557 txd[TxPtr].buf1sz = ETH_HLEN+s; 558 txd[TxPtr].control = 0x00000184; /* LS+FS+CE */ 559 txd[TxPtr].status = 0x80000000; /* give ownership to device */ 560 561 /* immediate transmit demand */ 562 outl(0, ioaddr + CSR1); 563 564 to = currticks() + TX_TIME_OUT; 565 while ((txd[TxPtr].status & 0x80000000) && (currticks() < to)) 566 /* wait */ ; 567 568 if (currticks() >= to) { 569 printf ("TX Timeout!\n"); 570 } 571 572 /* Point to next TX descriptor */ 573 TxPtr = (++TxPtr >= NTXD) ? 0:TxPtr; /* Sten 10/9 */ 574 575 } 576 577 /*********************************************************************/ 578 /* eth_poll - Wait for a frame */ 579 /*********************************************************************/ 580 static int davicom_poll(struct nic *nic, int retrieve) 581 { 582 whereami("davicom_poll\n"); 583 584 if (rxd[rxd_tail].status & 0x80000000) 585 return 0; 586 587 if ( ! retrieve ) return 1; 588 589 whereami("davicom_poll got one\n"); 590 591 nic->packetlen = (rxd[rxd_tail].status & 0x3FFF0000) >> 16; 592 593 if( rxd[rxd_tail].status & 0x00008000){ 594 rxd[rxd_tail].status = 0x80000000; 595 rxd_tail++; 596 if (rxd_tail == NRXD) rxd_tail = 0; 597 return 0; 598 } 599 600 /* copy packet to working buffer */ 601 /* XXX - this copy could be avoided with a little more work 602 but for now we are content with it because the optimised 603 memcpy is quite fast */ 604 605 memcpy(nic->packet, rxb + rxd_tail * BUFLEN, nic->packetlen); 606 607 /* return the descriptor and buffer to receive ring */ 608 rxd[rxd_tail].status = 0x80000000; 609 rxd_tail++; 610 if (rxd_tail == NRXD) rxd_tail = 0; 611 612 return 1; 613 } 614 615 /*********************************************************************/ 616 /* eth_disable - Disable the interface */ 617 /*********************************************************************/ 618 static void davicom_disable(struct dev *dev) 619 { 620 struct nic *nic = (struct nic *)dev; 621 whereami("davicom_disable\n"); 622 623 davicom_reset(nic); 624 625 /* disable interrupts */ 626 outl(0x00000000, ioaddr + CSR7); 627 628 /* Stop the chip's Tx and Rx processes. */ 629 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); 630 631 /* Clear the missed-packet counter. */ 632 (volatile unsigned long)inl(ioaddr + CSR8); 633 } 634 635 636 /*********************************************************************/ 637 /* eth_irq - enable, disable and force interrupts */ 638 /*********************************************************************/ 639 static void davicom_irq(struct nic *nic __unused, irq_action_t action __unused) 640 { 641 switch ( action ) { 642 case DISABLE : 643 break; 644 case ENABLE : 645 break; 646 case FORCE : 647 break; 648 } 649 } 650 651 652 /*********************************************************************/ 653 /* eth_probe - Look for an adapter */ 654 /*********************************************************************/ 655 static int davicom_probe(struct dev *dev, struct pci_device *pci) 656 { 657 struct nic *nic = (struct nic *)dev; 658 unsigned int i; 659 660 whereami("davicom_probe\n"); 661 662 if (pci->ioaddr == 0) 663 return 0; 664 665 vendor = pci->vendor; 666 dev_id = pci->dev_id; 667 ioaddr = pci->ioaddr & ~3; 668 669 nic->irqno = 0; 670 nic->ioaddr = pci->ioaddr & ~3; 671 672 /* wakeup chip */ 673 pcibios_write_config_dword(pci->bus, pci->devfn, 0x40, 0x00000000); 674 675 /* Stop the chip's Tx and Rx processes. */ 676 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6); 677 678 /* Clear the missed-packet counter. */ 679 (volatile unsigned long)inl(ioaddr + CSR8); 680 681 /* Get MAC Address */ 682 /* read EEPROM data */ 683 for (i = 0; i < sizeof(ee_data)/2; i++) 684 ((unsigned short *)ee_data)[i] = 685 le16_to_cpu(read_eeprom(ioaddr, i, EEPROM_ADDRLEN)); 686 687 /* extract MAC address from EEPROM buffer */ 688 for (i=0; i<ETH_ALEN; i++) 689 nic->node_addr[i] = ee_data[20+i]; 690 691 printf("Davicom %! at ioaddr %#hX\n", nic->node_addr, ioaddr); 692 693 /* initialize device */ 694 davicom_reset(nic); 695 696 dev->disable = davicom_disable; 697 nic->poll = davicom_poll; 698 nic->transmit = davicom_transmit; 699 nic->irq = davicom_irq; 700 701 return 1; 702 } 703 704 static struct pci_id davicom_nics[] = { 705 PCI_ROM(0x1282, 0x9100, "davicom9100", "Davicom 9100"), 706 PCI_ROM(0x1282, 0x9102, "davicom9102", "Davicom 9102"), 707 PCI_ROM(0x1282, 0x9009, "davicom9009", "Davicom 9009"), 708 PCI_ROM(0x1282, 0x9132, "davicom9132", "Davicom 9132"), /* Needs probably some fixing */ 709 }; 710 711 struct pci_driver davicom_driver = { 712 .type = NIC_DRIVER, 713 .name = "DAVICOM", 714 .probe = davicom_probe, 715 .ids = davicom_nics, 716 .id_count = sizeof(davicom_nics)/sizeof(davicom_nics[0]), 717 .class = 0, 718 }; 719