1[ 2 { 3 "MATRIX_REQUEST": "DEMAND_DATA_RD", 4 "MATRIX_RESPONSE": "Null", 5 "MATRIX_VALUE": "0x0000000001", 6 "MATRIX_REGISTER": "0,1", 7 "DESCRIPTION": "Counts demand and DCU prefetch data read" 8 }, 9 { 10 "MATRIX_REQUEST": "DEMAND_RFO", 11 "MATRIX_RESPONSE": "Null", 12 "MATRIX_VALUE": "0x0000000002", 13 "MATRIX_REGISTER": "0,1", 14 "DESCRIPTION": "Counts demand and DCU prefetch RFOs" 15 }, 16 { 17 "MATRIX_REQUEST": "DEMAND_CODE_RD", 18 "MATRIX_RESPONSE": "Null", 19 "MATRIX_VALUE": "0x0000000004", 20 "MATRIX_REGISTER": "0,1", 21 "DESCRIPTION": "Counts demand and DCU prefetch instruction cacheline" 22 }, 23 { 24 "MATRIX_REQUEST": "COREWB", 25 "MATRIX_RESPONSE": "Null", 26 "MATRIX_VALUE": "0x0000000008", 27 "MATRIX_REGISTER": "0,1", 28 "DESCRIPTION": "Counts writeback (modified to exclusive)" 29 }, 30 { 31 "MATRIX_REQUEST": "PF_L2_DATA_RD", 32 "MATRIX_RESPONSE": "Null", 33 "MATRIX_VALUE": "0x0000000010", 34 "MATRIX_REGISTER": "0,1", 35 "DESCRIPTION": "Counts data cacheline reads generated by L2 prefetchers" 36 }, 37 { 38 "MATRIX_REQUEST": "PF_L2_RFO", 39 "MATRIX_RESPONSE": "Null", 40 "MATRIX_VALUE": "0x0000000020", 41 "MATRIX_REGISTER": "0,1", 42 "DESCRIPTION": "Counts RFO requests generated by L2 prefetchers" 43 }, 44 { 45 "MATRIX_REQUEST": "PF_L2_CODE_RD", 46 "MATRIX_RESPONSE": "Null", 47 "MATRIX_VALUE": "0x0000000040", 48 "MATRIX_REGISTER": "0,1", 49 "DESCRIPTION": "Counts code reads generated by L2 prefetchers" 50 }, 51 { 52 "MATRIX_REQUEST": "PARTIAL_READS", 53 "MATRIX_RESPONSE": "Null", 54 "MATRIX_VALUE": "0x0000000080", 55 "MATRIX_REGISTER": "0,1", 56 "DESCRIPTION": "Counts demand reads of partial cache lines (including UC and WC)" 57 }, 58 { 59 "MATRIX_REQUEST": "PARTIAL_WRITES", 60 "MATRIX_RESPONSE": "Null", 61 "MATRIX_VALUE": "0x0000000100", 62 "MATRIX_REGISTER": "0,1", 63 "DESCRIPTION": "Countsof demand RFO requests to write to partial cache lines" 64 }, 65 { 66 "MATRIX_REQUEST": "UC_CODE_READS", 67 "MATRIX_RESPONSE": "Null", 68 "MATRIX_VALUE": "0x0000000200", 69 "MATRIX_REGISTER": "0,1", 70 "DESCRIPTION": "Counts UC instruction fetch" 71 }, 72 { 73 "MATRIX_REQUEST": "BUS_LOCKS", 74 "MATRIX_RESPONSE": "Null", 75 "MATRIX_VALUE": "0x0000000400", 76 "MATRIX_REGISTER": "0,1", 77 "DESCRIPTION": "Bus lock and split lock" 78 }, 79 { 80 "MATRIX_REQUEST": "PF_L1_DATA_RD", 81 "MATRIX_RESPONSE": "Null", 82 "MATRIX_VALUE": "0x0000002000", 83 "MATRIX_REGISTER": "0,1", 84 "DESCRIPTION": "Counts DCU hardware prefetcher data read" 85 }, 86 { 87 "MATRIX_REQUEST": "ANY_REQUEST", 88 "MATRIX_RESPONSE": "Null", 89 "MATRIX_VALUE": "0x0000008008", 90 "MATRIX_REGISTER": "0,1", 91 "DESCRIPTION": "Counts any request" 92 }, 93 { 94 "MATRIX_REQUEST": "STREAMING_STORES", 95 "MATRIX_RESPONSE": "Null", 96 "MATRIX_VALUE": "0x0000004800", 97 "MATRIX_REGISTER": "0,1", 98 "DESCRIPTION": "Counts streaming store" 99 }, 100 { 101 "MATRIX_REQUEST": "ANY_DATA_RD", 102 "MATRIX_RESPONSE": "Null", 103 "MATRIX_VALUE": "0x0000003091", 104 "MATRIX_REGISTER": "0,1", 105 "DESCRIPTION": "Counts any data read (demand & prefetch)" 106 }, 107 { 108 "MATRIX_REQUEST": "ANY_RFO", 109 "MATRIX_RESPONSE": "Null", 110 "MATRIX_VALUE": "0x0000000022", 111 "MATRIX_REGISTER": "0,1", 112 "DESCRIPTION": "Counts any rfo reads (demand & prefetch)" 113 }, 114 { 115 "MATRIX_REQUEST": "ANY_CODE_RD", 116 "MATRIX_RESPONSE": "Null", 117 "MATRIX_VALUE": "0x0000000044", 118 "MATRIX_REGISTER": "0,1", 119 "DESCRIPTION": "Counts any code reads (demand & prefetch)" 120 }, 121 { 122 "MATRIX_REQUEST": "ANY_READS", 123 "MATRIX_RESPONSE": "Null", 124 "MATRIX_VALUE": "0x00000032f7", 125 "MATRIX_REGISTER": "0,1", 126 "DESCRIPTION": "Counts any data/code/rfo reads (demand & prefetch)" 127 }, 128 { 129 "MATRIX_REQUEST": "ANY_PF_L2", 130 "MATRIX_RESPONSE": "Null", 131 "MATRIX_VALUE": "0x0000000070", 132 "MATRIX_REGISTER": "0,1", 133 "DESCRIPTION": "Counts any prefetch read" 134 }, 135 { 136 "MATRIX_REQUEST": "Null", 137 "MATRIX_RESPONSE": "ANY_RESPONSE", 138 "MATRIX_VALUE": "0x0000010000", 139 "MATRIX_REGISTER": "0,1", 140 "DESCRIPTION": "have any response type." 141 }, 142 { 143 "MATRIX_REQUEST": "Null", 144 "MATRIX_RESPONSE": "L2_MISS.NO_SNOOP_NEEDED", 145 "MATRIX_VALUE": "0x0080000000", 146 "MATRIX_REGISTER": "0,1", 147 "DESCRIPTION": "miss L2 with no details on snoop-related information." 148 }, 149 { 150 "MATRIX_REQUEST": "Null", 151 "MATRIX_RESPONSE": "L2_MISS.SNOOP_MISS", 152 "MATRIX_VALUE": "0x0200000000", 153 "MATRIX_REGISTER": "0,1", 154 "DESCRIPTION": "miss L2 with a snoop miss response." 155 }, 156 { 157 "MATRIX_REQUEST": "Null", 158 "MATRIX_RESPONSE": "L2_MISS.HIT_OTHER_CORE_NO_FWD", 159 "MATRIX_VALUE": "0x0400000000", 160 "MATRIX_REGISTER": "0,1", 161 "DESCRIPTION": "miss L2 and the snoops to sibling cores hit in either E/S state and the line is not forwarded." 162 }, 163 { 164 "MATRIX_REQUEST": "Null", 165 "MATRIX_RESPONSE": "L2_MISS.HITM_OTHER_CORE", 166 "MATRIX_VALUE": "0x1000000000", 167 "MATRIX_REGISTER": "0,1", 168 "DESCRIPTION": "hit in the other module where modified copies were found in other core's L1 cache." 169 }, 170 { 171 "MATRIX_REQUEST": "Null", 172 "MATRIX_RESPONSE": "L2_MISS.NON_DRAM", 173 "MATRIX_VALUE": "0x2000000000", 174 "MATRIX_REGISTER": "0,1", 175 "DESCRIPTION": "miss L2 and the target was non-DRAM system address." 176 }, 177 { 178 "MATRIX_REQUEST": "Null", 179 "MATRIX_RESPONSE": "L2_MISS.ANY", 180 "MATRIX_VALUE": "0x1680000000", 181 "MATRIX_REGISTER": "0,1", 182 "DESCRIPTION": "miss L2." 183 }, 184 { 185 "MATRIX_REQUEST": "Null", 186 "MATRIX_RESPONSE": "OUTSTANDING", 187 "MATRIX_VALUE": "0x4000000000", 188 "MATRIX_REGISTER": "0", 189 "DESCRIPTION": "are outstanding, per cycle, from the time of the L2 miss to when any response is received." 190 } 191]