1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 1991 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. Neither the name of the University nor the names of its contributors 16 * may be used to endorse or promote products derived from this software 17 * without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 29 * SUCH DAMAGE. 30 * 31 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91 32 * $FreeBSD$ 33 */ 34 35 #ifndef _MACHINE_SPECIALREG_H_ 36 #define _MACHINE_SPECIALREG_H_ 37 38 /* 39 * Bits in 386 special registers: 40 */ 41 #define CR0_PE 0x00000001 /* Protected mode Enable */ 42 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */ 43 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */ 44 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */ 45 #define CR0_PG 0x80000000 /* PaGing enable */ 46 47 /* 48 * Bits in 486 special registers: 49 */ 50 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */ 51 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in 52 all modes) */ 53 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */ 54 #define CR0_NW 0x20000000 /* Not Write-through */ 55 #define CR0_CD 0x40000000 /* Cache Disable */ 56 57 #define CR3_PCID_SAVE 0x8000000000000000 58 #define CR3_PCID_MASK 0xfff 59 60 /* 61 * Bits in PPro special registers 62 */ 63 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */ 64 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */ 65 #define CR4_TSD 0x00000004 /* Time stamp disable */ 66 #define CR4_DE 0x00000008 /* Debugging extensions */ 67 #define CR4_PSE 0x00000010 /* Page size extensions */ 68 #define CR4_PAE 0x00000020 /* Physical address extension */ 69 #define CR4_MCE 0x00000040 /* Machine check enable */ 70 #define CR4_PGE 0x00000080 /* Page global enable */ 71 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */ 72 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */ 73 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */ 74 #define CR4_VMXE 0x00002000 /* enable VMX operation (Intel-specific) */ 75 #define CR4_FSGSBASE 0x00010000 /* Enable FS/GS BASE accessing instructions */ 76 #define CR4_PCIDE 0x00020000 /* Enable Context ID */ 77 #define CR4_XSAVE 0x00040000 /* XSETBV/XGETBV */ 78 #define CR4_SMEP 0x00100000 /* Supervisor-Mode Execution Prevention */ 79 #define CR4_SMAP 0x00200000 /* Supervisor-Mode Access Prevention */ 80 #define CR4_PKE 0x00400000 /* Protection Keys Enable */ 81 82 /* 83 * Bits in AMD64 special registers. EFER is 64 bits wide. 84 */ 85 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */ 86 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */ 87 #define EFER_LMA 0x000000400 /* Long mode active (R) */ 88 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */ 89 #define EFER_SVM 0x000001000 /* SVM enable bit for AMD, reserved for Intel */ 90 #define EFER_LMSLE 0x000002000 /* Long Mode Segment Limit Enable */ 91 #define EFER_FFXSR 0x000004000 /* Fast FXSAVE/FSRSTOR */ 92 #define EFER_TCE 0x000008000 /* Translation Cache Extension */ 93 94 /* 95 * Intel Extended Features registers 96 */ 97 #define XCR0 0 /* XFEATURE_ENABLED_MASK register */ 98 99 #define XFEATURE_ENABLED_X87 0x00000001 100 #define XFEATURE_ENABLED_SSE 0x00000002 101 #define XFEATURE_ENABLED_YMM_HI128 0x00000004 102 #define XFEATURE_ENABLED_AVX XFEATURE_ENABLED_YMM_HI128 103 #define XFEATURE_ENABLED_BNDREGS 0x00000008 104 #define XFEATURE_ENABLED_BNDCSR 0x00000010 105 #define XFEATURE_ENABLED_OPMASK 0x00000020 106 #define XFEATURE_ENABLED_ZMM_HI256 0x00000040 107 #define XFEATURE_ENABLED_HI16_ZMM 0x00000080 108 109 #define XFEATURE_AVX \ 110 (XFEATURE_ENABLED_X87 | XFEATURE_ENABLED_SSE | XFEATURE_ENABLED_AVX) 111 #define XFEATURE_AVX512 \ 112 (XFEATURE_ENABLED_OPMASK | XFEATURE_ENABLED_ZMM_HI256 | \ 113 XFEATURE_ENABLED_HI16_ZMM) 114 #define XFEATURE_MPX \ 115 (XFEATURE_ENABLED_BNDREGS | XFEATURE_ENABLED_BNDCSR) 116 117 /* 118 * CPUID instruction features register 119 */ 120 #define CPUID_FPU 0x00000001 121 #define CPUID_VME 0x00000002 122 #define CPUID_DE 0x00000004 123 #define CPUID_PSE 0x00000008 124 #define CPUID_TSC 0x00000010 125 #define CPUID_MSR 0x00000020 126 #define CPUID_PAE 0x00000040 127 #define CPUID_MCE 0x00000080 128 #define CPUID_CX8 0x00000100 129 #define CPUID_APIC 0x00000200 130 #define CPUID_B10 0x00000400 131 #define CPUID_SEP 0x00000800 132 #define CPUID_MTRR 0x00001000 133 #define CPUID_PGE 0x00002000 134 #define CPUID_MCA 0x00004000 135 #define CPUID_CMOV 0x00008000 136 #define CPUID_PAT 0x00010000 137 #define CPUID_PSE36 0x00020000 138 #define CPUID_PSN 0x00040000 139 #define CPUID_CLFSH 0x00080000 140 #define CPUID_B20 0x00100000 141 #define CPUID_DS 0x00200000 142 #define CPUID_ACPI 0x00400000 143 #define CPUID_MMX 0x00800000 144 #define CPUID_FXSR 0x01000000 145 #define CPUID_SSE 0x02000000 146 #define CPUID_XMM 0x02000000 147 #define CPUID_SSE2 0x04000000 148 #define CPUID_SS 0x08000000 149 #define CPUID_HTT 0x10000000 150 #define CPUID_TM 0x20000000 151 #define CPUID_IA64 0x40000000 152 #define CPUID_PBE 0x80000000 153 154 #define CPUID2_SSE3 0x00000001 155 #define CPUID2_PCLMULQDQ 0x00000002 156 #define CPUID2_DTES64 0x00000004 157 #define CPUID2_MON 0x00000008 158 #define CPUID2_DS_CPL 0x00000010 159 #define CPUID2_VMX 0x00000020 160 #define CPUID2_SMX 0x00000040 161 #define CPUID2_EST 0x00000080 162 #define CPUID2_TM2 0x00000100 163 #define CPUID2_SSSE3 0x00000200 164 #define CPUID2_CNXTID 0x00000400 165 #define CPUID2_SDBG 0x00000800 166 #define CPUID2_FMA 0x00001000 167 #define CPUID2_CX16 0x00002000 168 #define CPUID2_XTPR 0x00004000 169 #define CPUID2_PDCM 0x00008000 170 #define CPUID2_PCID 0x00020000 171 #define CPUID2_DCA 0x00040000 172 #define CPUID2_SSE41 0x00080000 173 #define CPUID2_SSE42 0x00100000 174 #define CPUID2_X2APIC 0x00200000 175 #define CPUID2_MOVBE 0x00400000 176 #define CPUID2_POPCNT 0x00800000 177 #define CPUID2_TSCDLT 0x01000000 178 #define CPUID2_AESNI 0x02000000 179 #define CPUID2_XSAVE 0x04000000 180 #define CPUID2_OSXSAVE 0x08000000 181 #define CPUID2_AVX 0x10000000 182 #define CPUID2_F16C 0x20000000 183 #define CPUID2_RDRAND 0x40000000 184 #define CPUID2_HV 0x80000000 185 186 /* 187 * Important bits in the Thermal and Power Management flags 188 * CPUID.6 EAX and ECX. 189 */ 190 #define CPUTPM1_SENSOR 0x00000001 191 #define CPUTPM1_TURBO 0x00000002 192 #define CPUTPM1_ARAT 0x00000004 193 #define CPUTPM1_HWP 0x00000080 194 #define CPUTPM1_HWP_NOTIFICATION 0x00000100 195 #define CPUTPM1_HWP_ACTIVITY_WINDOW 0x00000200 196 #define CPUTPM1_HWP_PERF_PREF 0x00000400 197 #define CPUTPM1_HWP_PKG 0x00000800 198 #define CPUTPM1_HWP_FLEXIBLE 0x00020000 199 #define CPUTPM2_EFFREQ 0x00000001 200 201 /* Intel Processor Trace CPUID. */ 202 203 /* Leaf 0 ebx. */ 204 #define CPUPT_CR3 (1 << 0) /* CR3 Filtering Support */ 205 #define CPUPT_PSB (1 << 1) /* Configurable PSB and Cycle-Accurate Mode Supported */ 206 #define CPUPT_IPF (1 << 2) /* IP Filtering and TraceStop supported */ 207 #define CPUPT_MTC (1 << 3) /* MTC Supported */ 208 #define CPUPT_PRW (1 << 4) /* PTWRITE Supported */ 209 #define CPUPT_PWR (1 << 5) /* Power Event Trace Supported */ 210 211 /* Leaf 0 ecx. */ 212 #define CPUPT_TOPA (1 << 0) /* ToPA Output Supported */ 213 #define CPUPT_TOPA_MULTI (1 << 1) /* ToPA Tables Allow Multiple Output Entries */ 214 #define CPUPT_SINGLE (1 << 2) /* Single-Range Output Supported */ 215 #define CPUPT_TT_OUT (1 << 3) /* Output to Trace Transport Subsystem Supported */ 216 #define CPUPT_LINEAR_IP (1 << 31) /* IP Payloads are Linear IP, otherwise IP is effective */ 217 218 /* Leaf 1 eax. */ 219 #define CPUPT_NADDR_S 0 /* Number of Address Ranges */ 220 #define CPUPT_NADDR_M (0x7 << CPUPT_NADDR_S) 221 #define CPUPT_MTC_BITMAP_S 16 /* Bitmap of supported MTC Period Encodings */ 222 #define CPUPT_MTC_BITMAP_M (0xffff << CPUPT_MTC_BITMAP_S) 223 224 /* Leaf 1 ebx. */ 225 #define CPUPT_CT_BITMAP_S 0 /* Bitmap of supported Cycle Threshold values */ 226 #define CPUPT_CT_BITMAP_M (0xffff << CPUPT_CT_BITMAP_S) 227 #define CPUPT_PFE_BITMAP_S 16 /* Bitmap of supported Configurable PSB Frequency encoding */ 228 #define CPUPT_PFE_BITMAP_M (0xffff << CPUPT_PFE_BITMAP_S) 229 230 /* 231 * Important bits in the AMD extended cpuid flags 232 */ 233 #define AMDID_SYSCALL 0x00000800 234 #define AMDID_MP 0x00080000 235 #define AMDID_NX 0x00100000 236 #define AMDID_EXT_MMX 0x00400000 237 #define AMDID_FFXSR 0x02000000 238 #define AMDID_PAGE1GB 0x04000000 239 #define AMDID_RDTSCP 0x08000000 240 #define AMDID_LM 0x20000000 241 #define AMDID_EXT_3DNOW 0x40000000 242 #define AMDID_3DNOW 0x80000000 243 244 #define AMDID2_LAHF 0x00000001 245 #define AMDID2_CMP 0x00000002 246 #define AMDID2_SVM 0x00000004 247 #define AMDID2_EXT_APIC 0x00000008 248 #define AMDID2_CR8 0x00000010 249 #define AMDID2_ABM 0x00000020 250 #define AMDID2_SSE4A 0x00000040 251 #define AMDID2_MAS 0x00000080 252 #define AMDID2_PREFETCH 0x00000100 253 #define AMDID2_OSVW 0x00000200 254 #define AMDID2_IBS 0x00000400 255 #define AMDID2_XOP 0x00000800 256 #define AMDID2_SKINIT 0x00001000 257 #define AMDID2_WDT 0x00002000 258 #define AMDID2_LWP 0x00008000 259 #define AMDID2_FMA4 0x00010000 260 #define AMDID2_TCE 0x00020000 261 #define AMDID2_NODE_ID 0x00080000 262 #define AMDID2_TBM 0x00200000 263 #define AMDID2_TOPOLOGY 0x00400000 264 #define AMDID2_PCXC 0x00800000 265 #define AMDID2_PNXC 0x01000000 266 #define AMDID2_DBE 0x04000000 267 #define AMDID2_PTSC 0x08000000 268 #define AMDID2_PTSCEL2I 0x10000000 269 #define AMDID2_MWAITX 0x20000000 270 271 /* 272 * CPUID instruction 1 eax info 273 */ 274 #define CPUID_STEPPING 0x0000000f 275 #define CPUID_MODEL 0x000000f0 276 #define CPUID_FAMILY 0x00000f00 277 #define CPUID_EXT_MODEL 0x000f0000 278 #define CPUID_EXT_FAMILY 0x0ff00000 279 #ifdef __i386__ 280 #define CPUID_TO_MODEL(id) \ 281 ((((id) & CPUID_MODEL) >> 4) | \ 282 ((((id) & CPUID_FAMILY) >= 0x600) ? \ 283 (((id) & CPUID_EXT_MODEL) >> 12) : 0)) 284 #define CPUID_TO_FAMILY(id) \ 285 ((((id) & CPUID_FAMILY) >> 8) + \ 286 ((((id) & CPUID_FAMILY) == 0xf00) ? \ 287 (((id) & CPUID_EXT_FAMILY) >> 20) : 0)) 288 #else 289 #define CPUID_TO_MODEL(id) \ 290 ((((id) & CPUID_MODEL) >> 4) | \ 291 (((id) & CPUID_EXT_MODEL) >> 12)) 292 #define CPUID_TO_FAMILY(id) \ 293 ((((id) & CPUID_FAMILY) >> 8) + \ 294 (((id) & CPUID_EXT_FAMILY) >> 20)) 295 #endif 296 297 /* 298 * CPUID instruction 1 ebx info 299 */ 300 #define CPUID_BRAND_INDEX 0x000000ff 301 #define CPUID_CLFUSH_SIZE 0x0000ff00 302 #define CPUID_HTT_CORES 0x00ff0000 303 #define CPUID_LOCAL_APIC_ID 0xff000000 304 305 /* 306 * CPUID instruction 5 info 307 */ 308 #define CPUID5_MON_MIN_SIZE 0x0000ffff /* eax */ 309 #define CPUID5_MON_MAX_SIZE 0x0000ffff /* ebx */ 310 #define CPUID5_MON_MWAIT_EXT 0x00000001 /* ecx */ 311 #define CPUID5_MWAIT_INTRBREAK 0x00000002 /* ecx */ 312 313 /* 314 * MWAIT cpu power states. Lower 4 bits are sub-states. 315 */ 316 #define MWAIT_C0 0xf0 317 #define MWAIT_C1 0x00 318 #define MWAIT_C2 0x10 319 #define MWAIT_C3 0x20 320 #define MWAIT_C4 0x30 321 322 /* 323 * MWAIT extensions. 324 */ 325 /* Interrupt breaks MWAIT even when masked. */ 326 #define MWAIT_INTRBREAK 0x00000001 327 328 /* 329 * CPUID instruction 6 ecx info 330 */ 331 #define CPUID_PERF_STAT 0x00000001 332 #define CPUID_PERF_BIAS 0x00000008 333 334 /* 335 * CPUID instruction 0xb ebx info. 336 */ 337 #define CPUID_TYPE_INVAL 0 338 #define CPUID_TYPE_SMT 1 339 #define CPUID_TYPE_CORE 2 340 341 /* 342 * CPUID instruction 0xd Processor Extended State Enumeration Sub-leaf 1 343 */ 344 #define CPUID_EXTSTATE_XSAVEOPT 0x00000001 345 #define CPUID_EXTSTATE_XSAVEC 0x00000002 346 #define CPUID_EXTSTATE_XINUSE 0x00000004 347 #define CPUID_EXTSTATE_XSAVES 0x00000008 348 349 /* 350 * AMD extended function 8000_0007h ebx info 351 */ 352 #define AMDRAS_MCA_OF_RECOV 0x00000001 353 #define AMDRAS_SUCCOR 0x00000002 354 #define AMDRAS_HW_ASSERT 0x00000004 355 #define AMDRAS_SCALABLE_MCA 0x00000008 356 #define AMDRAS_PFEH_SUPPORT 0x00000010 357 358 /* 359 * AMD extended function 8000_0007h edx info 360 */ 361 #define AMDPM_TS 0x00000001 362 #define AMDPM_FID 0x00000002 363 #define AMDPM_VID 0x00000004 364 #define AMDPM_TTP 0x00000008 365 #define AMDPM_TM 0x00000010 366 #define AMDPM_STC 0x00000020 367 #define AMDPM_100MHZ_STEPS 0x00000040 368 #define AMDPM_HW_PSTATE 0x00000080 369 #define AMDPM_TSC_INVARIANT 0x00000100 370 #define AMDPM_CPB 0x00000200 371 372 /* 373 * AMD extended function 8000_0008h ebx info (amd_extended_feature_extensions) 374 */ 375 #define AMDFEID_CLZERO 0x00000001 376 #define AMDFEID_IRPERF 0x00000002 377 #define AMDFEID_XSAVEERPTR 0x00000004 378 #define AMDFEID_IBPB 0x00001000 379 #define AMDFEID_IBRS 0x00004000 380 #define AMDFEID_STIBP 0x00008000 381 /* The below are only defined if the corresponding base feature above exists. */ 382 #define AMDFEID_IBRS_ALWAYSON 0x00010000 383 #define AMDFEID_STIBP_ALWAYSON 0x00020000 384 #define AMDFEID_PREFER_IBRS 0x00040000 385 #define AMDFEID_SSBD 0x01000000 386 /* SSBD via MSRC001_011F instead of MSR 0x48: */ 387 #define AMDFEID_VIRT_SSBD 0x02000000 388 #define AMDFEID_SSB_NO 0x04000000 389 390 /* 391 * AMD extended function 8000_0008h ecx info 392 */ 393 #define AMDID_CMP_CORES 0x000000ff 394 #define AMDID_COREID_SIZE 0x0000f000 395 #define AMDID_COREID_SIZE_SHIFT 12 396 397 /* 398 * CPUID instruction 7 Structured Extended Features, leaf 0 ebx info 399 */ 400 #define CPUID_STDEXT_FSGSBASE 0x00000001 401 #define CPUID_STDEXT_TSC_ADJUST 0x00000002 402 #define CPUID_STDEXT_SGX 0x00000004 403 #define CPUID_STDEXT_BMI1 0x00000008 404 #define CPUID_STDEXT_HLE 0x00000010 405 #define CPUID_STDEXT_AVX2 0x00000020 406 #define CPUID_STDEXT_FDP_EXC 0x00000040 407 #define CPUID_STDEXT_SMEP 0x00000080 408 #define CPUID_STDEXT_BMI2 0x00000100 409 #define CPUID_STDEXT_ERMS 0x00000200 410 #define CPUID_STDEXT_INVPCID 0x00000400 411 #define CPUID_STDEXT_RTM 0x00000800 412 #define CPUID_STDEXT_PQM 0x00001000 413 #define CPUID_STDEXT_NFPUSG 0x00002000 414 #define CPUID_STDEXT_MPX 0x00004000 415 #define CPUID_STDEXT_PQE 0x00008000 416 #define CPUID_STDEXT_AVX512F 0x00010000 417 #define CPUID_STDEXT_AVX512DQ 0x00020000 418 #define CPUID_STDEXT_RDSEED 0x00040000 419 #define CPUID_STDEXT_ADX 0x00080000 420 #define CPUID_STDEXT_SMAP 0x00100000 421 #define CPUID_STDEXT_AVX512IFMA 0x00200000 422 #define CPUID_STDEXT_PCOMMIT 0x00400000 423 #define CPUID_STDEXT_CLFLUSHOPT 0x00800000 424 #define CPUID_STDEXT_CLWB 0x01000000 425 #define CPUID_STDEXT_PROCTRACE 0x02000000 426 #define CPUID_STDEXT_AVX512PF 0x04000000 427 #define CPUID_STDEXT_AVX512ER 0x08000000 428 #define CPUID_STDEXT_AVX512CD 0x10000000 429 #define CPUID_STDEXT_SHA 0x20000000 430 #define CPUID_STDEXT_AVX512BW 0x40000000 431 #define CPUID_STDEXT_AVX512VL 0x80000000 432 433 /* 434 * CPUID instruction 7 Structured Extended Features, leaf 0 ecx info 435 */ 436 #define CPUID_STDEXT2_PREFETCHWT1 0x00000001 437 #define CPUID_STDEXT2_AVX512VBMI 0x00000002 438 #define CPUID_STDEXT2_UMIP 0x00000004 439 #define CPUID_STDEXT2_PKU 0x00000008 440 #define CPUID_STDEXT2_OSPKE 0x00000010 441 #define CPUID_STDEXT2_WAITPKG 0x00000020 442 #define CPUID_STDEXT2_AVX512VBMI2 0x00000040 443 #define CPUID_STDEXT2_GFNI 0x00000100 444 #define CPUID_STDEXT2_VAES 0x00000200 445 #define CPUID_STDEXT2_VPCLMULQDQ 0x00000400 446 #define CPUID_STDEXT2_AVX512VNNI 0x00000800 447 #define CPUID_STDEXT2_AVX512BITALG 0x00001000 448 #define CPUID_STDEXT2_AVX512VPOPCNTDQ 0x00004000 449 #define CPUID_STDEXT2_RDPID 0x00400000 450 #define CPUID_STDEXT2_CLDEMOTE 0x02000000 451 #define CPUID_STDEXT2_MOVDIRI 0x08000000 452 #define CPUID_STDEXT2_MOVDIRI64B 0x10000000 453 #define CPUID_STDEXT2_ENQCMD 0x20000000 454 #define CPUID_STDEXT2_SGXLC 0x40000000 455 456 /* 457 * CPUID instruction 7 Structured Extended Features, leaf 0 edx info 458 */ 459 #define CPUID_STDEXT3_AVX5124VNNIW 0x00000004 460 #define CPUID_STDEXT3_AVX5124FMAPS 0x00000008 461 #define CPUID_STDEXT3_AVX512VP2INTERSECT 0x00000100 462 #define CPUID_STDEXT3_MD_CLEAR 0x00000400 463 #define CPUID_STDEXT3_TSXFA 0x00002000 464 #define CPUID_STDEXT3_PCONFIG 0x00040000 465 #define CPUID_STDEXT3_IBPB 0x04000000 466 #define CPUID_STDEXT3_STIBP 0x08000000 467 #define CPUID_STDEXT3_L1D_FLUSH 0x10000000 468 #define CPUID_STDEXT3_ARCH_CAP 0x20000000 469 #define CPUID_STDEXT3_CORE_CAP 0x40000000 470 #define CPUID_STDEXT3_SSBD 0x80000000 471 472 /* MSR IA32_ARCH_CAP(ABILITIES) bits */ 473 #define IA32_ARCH_CAP_RDCL_NO 0x00000001 474 #define IA32_ARCH_CAP_IBRS_ALL 0x00000002 475 #define IA32_ARCH_CAP_RSBA 0x00000004 476 #define IA32_ARCH_CAP_SKIP_L1DFL_VMENTRY 0x00000008 477 #define IA32_ARCH_CAP_SSB_NO 0x00000010 478 #define IA32_ARCH_CAP_MDS_NO 0x00000020 479 480 /* 481 * CPUID manufacturers identifiers 482 */ 483 #define AMD_VENDOR_ID "AuthenticAMD" 484 #define CENTAUR_VENDOR_ID "CentaurHauls" 485 #define CYRIX_VENDOR_ID "CyrixInstead" 486 #define INTEL_VENDOR_ID "GenuineIntel" 487 #define NEXGEN_VENDOR_ID "NexGenDriven" 488 #define NSC_VENDOR_ID "Geode by NSC" 489 #define RISE_VENDOR_ID "RiseRiseRise" 490 #define SIS_VENDOR_ID "SiS SiS SiS " 491 #define TRANSMETA_VENDOR_ID "GenuineTMx86" 492 #define UMC_VENDOR_ID "UMC UMC UMC " 493 494 /* 495 * Model-specific registers for the i386 family 496 */ 497 #define MSR_P5_MC_ADDR 0x000 498 #define MSR_P5_MC_TYPE 0x001 499 #define MSR_TSC 0x010 500 #define MSR_P5_CESR 0x011 501 #define MSR_P5_CTR0 0x012 502 #define MSR_P5_CTR1 0x013 503 #define MSR_IA32_PLATFORM_ID 0x017 504 #define MSR_APICBASE 0x01b 505 #define MSR_EBL_CR_POWERON 0x02a 506 #define MSR_TEST_CTL 0x033 507 #define MSR_IA32_FEATURE_CONTROL 0x03a 508 #define MSR_IA32_SPEC_CTRL 0x048 509 #define MSR_IA32_PRED_CMD 0x049 510 #define MSR_BIOS_UPDT_TRIG 0x079 511 #define MSR_BBL_CR_D0 0x088 512 #define MSR_BBL_CR_D1 0x089 513 #define MSR_BBL_CR_D2 0x08a 514 #define MSR_BIOS_SIGN 0x08b 515 #define MSR_PERFCTR0 0x0c1 516 #define MSR_PERFCTR1 0x0c2 517 #define MSR_PLATFORM_INFO 0x0ce 518 #define MSR_MPERF 0x0e7 519 #define MSR_APERF 0x0e8 520 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */ 521 #define MSR_MTRRcap 0x0fe 522 #define MSR_IA32_ARCH_CAP 0x10a 523 #define MSR_IA32_FLUSH_CMD 0x10b 524 #define MSR_TSX_FORCE_ABORT 0x10f 525 #define MSR_BBL_CR_ADDR 0x116 526 #define MSR_BBL_CR_DECC 0x118 527 #define MSR_BBL_CR_CTL 0x119 528 #define MSR_BBL_CR_TRIG 0x11a 529 #define MSR_BBL_CR_BUSY 0x11b 530 #define MSR_BBL_CR_CTL3 0x11e 531 #define MSR_SYSENTER_CS_MSR 0x174 532 #define MSR_SYSENTER_ESP_MSR 0x175 533 #define MSR_SYSENTER_EIP_MSR 0x176 534 #define MSR_MCG_CAP 0x179 535 #define MSR_MCG_STATUS 0x17a 536 #define MSR_MCG_CTL 0x17b 537 #define MSR_EVNTSEL0 0x186 538 #define MSR_EVNTSEL1 0x187 539 #define MSR_THERM_CONTROL 0x19a 540 #define MSR_THERM_INTERRUPT 0x19b 541 #define MSR_THERM_STATUS 0x19c 542 #define MSR_IA32_MISC_ENABLE 0x1a0 543 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2 544 #define MSR_TURBO_RATIO_LIMIT 0x1ad 545 #define MSR_TURBO_RATIO_LIMIT1 0x1ae 546 #define MSR_DEBUGCTLMSR 0x1d9 547 #define MSR_LASTBRANCHFROMIP 0x1db 548 #define MSR_LASTBRANCHTOIP 0x1dc 549 #define MSR_LASTINTFROMIP 0x1dd 550 #define MSR_LASTINTTOIP 0x1de 551 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0 552 #define MSR_MTRRVarBase 0x200 553 #define MSR_MTRR64kBase 0x250 554 #define MSR_MTRR16kBase 0x258 555 #define MSR_MTRR4kBase 0x268 556 #define MSR_PAT 0x277 557 #define MSR_MC0_CTL2 0x280 558 #define MSR_MTRRdefType 0x2ff 559 #define MSR_MC0_CTL 0x400 560 #define MSR_MC0_STATUS 0x401 561 #define MSR_MC0_ADDR 0x402 562 #define MSR_MC0_MISC 0x403 563 #define MSR_MC1_CTL 0x404 564 #define MSR_MC1_STATUS 0x405 565 #define MSR_MC1_ADDR 0x406 566 #define MSR_MC1_MISC 0x407 567 #define MSR_MC2_CTL 0x408 568 #define MSR_MC2_STATUS 0x409 569 #define MSR_MC2_ADDR 0x40a 570 #define MSR_MC2_MISC 0x40b 571 #define MSR_MC3_CTL 0x40c 572 #define MSR_MC3_STATUS 0x40d 573 #define MSR_MC3_ADDR 0x40e 574 #define MSR_MC3_MISC 0x40f 575 #define MSR_MC4_CTL 0x410 576 #define MSR_MC4_STATUS 0x411 577 #define MSR_MC4_ADDR 0x412 578 #define MSR_MC4_MISC 0x413 579 #define MSR_RAPL_POWER_UNIT 0x606 580 #define MSR_PKG_ENERGY_STATUS 0x611 581 #define MSR_DRAM_ENERGY_STATUS 0x619 582 #define MSR_PP0_ENERGY_STATUS 0x639 583 #define MSR_PP1_ENERGY_STATUS 0x641 584 #define MSR_PPERF 0x64e 585 #define MSR_TSC_DEADLINE 0x6e0 /* Writes are not serializing */ 586 #define MSR_IA32_PM_ENABLE 0x770 587 #define MSR_IA32_HWP_CAPABILITIES 0x771 588 #define MSR_IA32_HWP_REQUEST_PKG 0x772 589 #define MSR_IA32_HWP_INTERRUPT 0x773 590 #define MSR_IA32_HWP_REQUEST 0x774 591 #define MSR_IA32_HWP_STATUS 0x777 592 593 /* 594 * VMX MSRs 595 */ 596 #define MSR_VMX_BASIC 0x480 597 #define MSR_VMX_PINBASED_CTLS 0x481 598 #define MSR_VMX_PROCBASED_CTLS 0x482 599 #define MSR_VMX_EXIT_CTLS 0x483 600 #define MSR_VMX_ENTRY_CTLS 0x484 601 #define MSR_VMX_CR0_FIXED0 0x486 602 #define MSR_VMX_CR0_FIXED1 0x487 603 #define MSR_VMX_CR4_FIXED0 0x488 604 #define MSR_VMX_CR4_FIXED1 0x489 605 #define MSR_VMX_PROCBASED_CTLS2 0x48b 606 #define MSR_VMX_EPT_VPID_CAP 0x48c 607 #define MSR_VMX_TRUE_PINBASED_CTLS 0x48d 608 #define MSR_VMX_TRUE_PROCBASED_CTLS 0x48e 609 #define MSR_VMX_TRUE_EXIT_CTLS 0x48f 610 #define MSR_VMX_TRUE_ENTRY_CTLS 0x490 611 612 /* 613 * X2APIC MSRs. 614 * Writes are not serializing. 615 */ 616 #define MSR_APIC_000 0x800 617 #define MSR_APIC_ID 0x802 618 #define MSR_APIC_VERSION 0x803 619 #define MSR_APIC_TPR 0x808 620 #define MSR_APIC_EOI 0x80b 621 #define MSR_APIC_LDR 0x80d 622 #define MSR_APIC_SVR 0x80f 623 #define MSR_APIC_ISR0 0x810 624 #define MSR_APIC_ISR1 0x811 625 #define MSR_APIC_ISR2 0x812 626 #define MSR_APIC_ISR3 0x813 627 #define MSR_APIC_ISR4 0x814 628 #define MSR_APIC_ISR5 0x815 629 #define MSR_APIC_ISR6 0x816 630 #define MSR_APIC_ISR7 0x817 631 #define MSR_APIC_TMR0 0x818 632 #define MSR_APIC_IRR0 0x820 633 #define MSR_APIC_ESR 0x828 634 #define MSR_APIC_LVT_CMCI 0x82F 635 #define MSR_APIC_ICR 0x830 636 #define MSR_APIC_LVT_TIMER 0x832 637 #define MSR_APIC_LVT_THERMAL 0x833 638 #define MSR_APIC_LVT_PCINT 0x834 639 #define MSR_APIC_LVT_LINT0 0x835 640 #define MSR_APIC_LVT_LINT1 0x836 641 #define MSR_APIC_LVT_ERROR 0x837 642 #define MSR_APIC_ICR_TIMER 0x838 643 #define MSR_APIC_CCR_TIMER 0x839 644 #define MSR_APIC_DCR_TIMER 0x83e 645 #define MSR_APIC_SELF_IPI 0x83f 646 647 #define MSR_IA32_XSS 0xda0 648 649 /* 650 * Intel Processor Trace (PT) MSRs. 651 */ 652 #define MSR_IA32_RTIT_OUTPUT_BASE 0x560 /* Trace Output Base Register (R/W) */ 653 #define MSR_IA32_RTIT_OUTPUT_MASK_PTRS 0x561 /* Trace Output Mask Pointers Register (R/W) */ 654 #define MSR_IA32_RTIT_CTL 0x570 /* Trace Control Register (R/W) */ 655 #define RTIT_CTL_TRACEEN (1 << 0) 656 #define RTIT_CTL_CYCEN (1 << 1) 657 #define RTIT_CTL_OS (1 << 2) 658 #define RTIT_CTL_USER (1 << 3) 659 #define RTIT_CTL_PWREVTEN (1 << 4) 660 #define RTIT_CTL_FUPONPTW (1 << 5) 661 #define RTIT_CTL_FABRICEN (1 << 6) 662 #define RTIT_CTL_CR3FILTER (1 << 7) 663 #define RTIT_CTL_TOPA (1 << 8) 664 #define RTIT_CTL_MTCEN (1 << 9) 665 #define RTIT_CTL_TSCEN (1 << 10) 666 #define RTIT_CTL_DISRETC (1 << 11) 667 #define RTIT_CTL_PTWEN (1 << 12) 668 #define RTIT_CTL_BRANCHEN (1 << 13) 669 #define RTIT_CTL_MTC_FREQ_S 14 670 #define RTIT_CTL_MTC_FREQ(n) ((n) << RTIT_CTL_MTC_FREQ_S) 671 #define RTIT_CTL_MTC_FREQ_M (0xf << RTIT_CTL_MTC_FREQ_S) 672 #define RTIT_CTL_CYC_THRESH_S 19 673 #define RTIT_CTL_CYC_THRESH_M (0xf << RTIT_CTL_CYC_THRESH_S) 674 #define RTIT_CTL_PSB_FREQ_S 24 675 #define RTIT_CTL_PSB_FREQ_M (0xf << RTIT_CTL_PSB_FREQ_S) 676 #define RTIT_CTL_ADDR_CFG_S(n) (32 + (n) * 4) 677 #define RTIT_CTL_ADDR0_CFG_S 32 678 #define RTIT_CTL_ADDR0_CFG_M (0xfULL << RTIT_CTL_ADDR0_CFG_S) 679 #define RTIT_CTL_ADDR1_CFG_S 36 680 #define RTIT_CTL_ADDR1_CFG_M (0xfULL << RTIT_CTL_ADDR1_CFG_S) 681 #define RTIT_CTL_ADDR2_CFG_S 40 682 #define RTIT_CTL_ADDR2_CFG_M (0xfULL << RTIT_CTL_ADDR2_CFG_S) 683 #define RTIT_CTL_ADDR3_CFG_S 44 684 #define RTIT_CTL_ADDR3_CFG_M (0xfULL << RTIT_CTL_ADDR3_CFG_S) 685 #define MSR_IA32_RTIT_STATUS 0x571 /* Tracing Status Register (R/W) */ 686 #define RTIT_STATUS_FILTEREN (1 << 0) 687 #define RTIT_STATUS_CONTEXTEN (1 << 1) 688 #define RTIT_STATUS_TRIGGEREN (1 << 2) 689 #define RTIT_STATUS_ERROR (1 << 4) 690 #define RTIT_STATUS_STOPPED (1 << 5) 691 #define RTIT_STATUS_PACKETBYTECNT_S 32 692 #define RTIT_STATUS_PACKETBYTECNT_M (0x1ffffULL << RTIT_STATUS_PACKETBYTECNT_S) 693 #define MSR_IA32_RTIT_CR3_MATCH 0x572 /* Trace Filter CR3 Match Register (R/W) */ 694 #define MSR_IA32_RTIT_ADDR_A(n) (0x580 + (n) * 2) 695 #define MSR_IA32_RTIT_ADDR_B(n) (0x581 + (n) * 2) 696 #define MSR_IA32_RTIT_ADDR0_A 0x580 /* Region 0 Start Address (R/W) */ 697 #define MSR_IA32_RTIT_ADDR0_B 0x581 /* Region 0 End Address (R/W) */ 698 #define MSR_IA32_RTIT_ADDR1_A 0x582 /* Region 1 Start Address (R/W) */ 699 #define MSR_IA32_RTIT_ADDR1_B 0x583 /* Region 1 End Address (R/W) */ 700 #define MSR_IA32_RTIT_ADDR2_A 0x584 /* Region 2 Start Address (R/W) */ 701 #define MSR_IA32_RTIT_ADDR2_B 0x585 /* Region 2 End Address (R/W) */ 702 #define MSR_IA32_RTIT_ADDR3_A 0x586 /* Region 3 Start Address (R/W) */ 703 #define MSR_IA32_RTIT_ADDR3_B 0x587 /* Region 3 End Address (R/W) */ 704 705 /* Intel Processor Trace Table of Physical Addresses (ToPA). */ 706 #define TOPA_SIZE_S 6 707 #define TOPA_SIZE_M (0xf << TOPA_SIZE_S) 708 #define TOPA_SIZE_4K (0 << TOPA_SIZE_S) 709 #define TOPA_SIZE_8K (1 << TOPA_SIZE_S) 710 #define TOPA_SIZE_16K (2 << TOPA_SIZE_S) 711 #define TOPA_SIZE_32K (3 << TOPA_SIZE_S) 712 #define TOPA_SIZE_64K (4 << TOPA_SIZE_S) 713 #define TOPA_SIZE_128K (5 << TOPA_SIZE_S) 714 #define TOPA_SIZE_256K (6 << TOPA_SIZE_S) 715 #define TOPA_SIZE_512K (7 << TOPA_SIZE_S) 716 #define TOPA_SIZE_1M (8 << TOPA_SIZE_S) 717 #define TOPA_SIZE_2M (9 << TOPA_SIZE_S) 718 #define TOPA_SIZE_4M (10 << TOPA_SIZE_S) 719 #define TOPA_SIZE_8M (11 << TOPA_SIZE_S) 720 #define TOPA_SIZE_16M (12 << TOPA_SIZE_S) 721 #define TOPA_SIZE_32M (13 << TOPA_SIZE_S) 722 #define TOPA_SIZE_64M (14 << TOPA_SIZE_S) 723 #define TOPA_SIZE_128M (15 << TOPA_SIZE_S) 724 #define TOPA_STOP (1 << 4) 725 #define TOPA_INT (1 << 2) 726 #define TOPA_END (1 << 0) 727 728 /* 729 * Constants related to MSR's. 730 */ 731 #define APICBASE_RESERVED 0x000002ff 732 #define APICBASE_BSP 0x00000100 733 #define APICBASE_X2APIC 0x00000400 734 #define APICBASE_ENABLED 0x00000800 735 #define APICBASE_ADDRESS 0xfffff000 736 737 /* MSR_IA32_FEATURE_CONTROL related */ 738 #define IA32_FEATURE_CONTROL_LOCK 0x01 /* lock bit */ 739 #define IA32_FEATURE_CONTROL_SMX_EN 0x02 /* enable VMX inside SMX */ 740 #define IA32_FEATURE_CONTROL_VMX_EN 0x04 /* enable VMX outside SMX */ 741 742 /* MSR IA32_MISC_ENABLE */ 743 #define IA32_MISC_EN_FASTSTR 0x0000000000000001ULL 744 #define IA32_MISC_EN_ATCCE 0x0000000000000008ULL 745 #define IA32_MISC_EN_PERFMON 0x0000000000000080ULL 746 #define IA32_MISC_EN_PEBSU 0x0000000000001000ULL 747 #define IA32_MISC_EN_ESSTE 0x0000000000010000ULL 748 #define IA32_MISC_EN_MONE 0x0000000000040000ULL 749 #define IA32_MISC_EN_LIMCPUID 0x0000000000400000ULL 750 #define IA32_MISC_EN_xTPRD 0x0000000000800000ULL 751 #define IA32_MISC_EN_XDD 0x0000000400000000ULL 752 753 /* 754 * IA32_SPEC_CTRL and IA32_PRED_CMD MSRs are described in the Intel' 755 * document 336996-001 Speculative Execution Side Channel Mitigations. 756 * 757 * AMD uses the same MSRs and bit definitions, as described in 111006-B 758 * "Indirect Branch Control Extension" and 124441 "Speculative Store Bypass 759 * Disable." 760 */ 761 /* MSR IA32_SPEC_CTRL */ 762 #define IA32_SPEC_CTRL_IBRS 0x00000001 763 #define IA32_SPEC_CTRL_STIBP 0x00000002 764 #define IA32_SPEC_CTRL_SSBD 0x00000004 765 766 /* MSR IA32_PRED_CMD */ 767 #define IA32_PRED_CMD_IBPB_BARRIER 0x0000000000000001ULL 768 769 /* MSR IA32_FLUSH_CMD */ 770 #define IA32_FLUSH_CMD_L1D 0x00000001 771 772 /* MSR IA32_HWP_CAPABILITIES */ 773 #define IA32_HWP_CAPABILITIES_HIGHEST_PERFORMANCE(x) (((x) >> 0) & 0xff) 774 #define IA32_HWP_CAPABILITIES_GUARANTEED_PERFORMANCE(x) (((x) >> 8) & 0xff) 775 #define IA32_HWP_CAPABILITIES_EFFICIENT_PERFORMANCE(x) (((x) >> 16) & 0xff) 776 #define IA32_HWP_CAPABILITIES_LOWEST_PERFORMANCE(x) (((x) >> 24) & 0xff) 777 778 /* MSR IA32_HWP_REQUEST */ 779 #define IA32_HWP_REQUEST_MINIMUM_VALID (1ULL << 63) 780 #define IA32_HWP_REQUEST_MAXIMUM_VALID (1ULL << 62) 781 #define IA32_HWP_REQUEST_DESIRED_VALID (1ULL << 61) 782 #define IA32_HWP_REQUEST_EPP_VALID (1ULL << 60) 783 #define IA32_HWP_REQUEST_ACTIVITY_WINDOW_VALID (1ULL << 59) 784 #define IA32_HWP_REQUEST_PACKAGE_CONTROL (1ULL << 42) 785 #define IA32_HWP_ACTIVITY_WINDOW (0x3ffULL << 32) 786 #define IA32_HWP_REQUEST_ENERGY_PERFORMANCE_PREFERENCE (0xffULL << 24) 787 #define IA32_HWP_DESIRED_PERFORMANCE (0xffULL << 16) 788 #define IA32_HWP_REQUEST_MAXIMUM_PERFORMANCE (0xffULL << 8) 789 #define IA32_HWP_MINIMUM_PERFORMANCE (0xffULL << 0) 790 791 /* 792 * PAT modes. 793 */ 794 #define PAT_UNCACHEABLE 0x00 795 #define PAT_WRITE_COMBINING 0x01 796 #define PAT_WRITE_THROUGH 0x04 797 #define PAT_WRITE_PROTECTED 0x05 798 #define PAT_WRITE_BACK 0x06 799 #define PAT_UNCACHED 0x07 800 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i))) 801 #define PAT_MASK(i) PAT_VALUE(i, 0xff) 802 803 /* 804 * Constants related to MTRRs 805 */ 806 #define MTRR_UNCACHEABLE 0x00 807 #define MTRR_WRITE_COMBINING 0x01 808 #define MTRR_WRITE_THROUGH 0x04 809 #define MTRR_WRITE_PROTECTED 0x05 810 #define MTRR_WRITE_BACK 0x06 811 #define MTRR_N64K 8 /* numbers of fixed-size entries */ 812 #define MTRR_N16K 16 813 #define MTRR_N4K 64 814 #define MTRR_CAP_WC 0x0000000000000400 815 #define MTRR_CAP_FIXED 0x0000000000000100 816 #define MTRR_CAP_VCNT 0x00000000000000ff 817 #define MTRR_DEF_ENABLE 0x0000000000000800 818 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400 819 #define MTRR_DEF_TYPE 0x00000000000000ff 820 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000 821 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff 822 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000 823 #define MTRR_PHYSMASK_VALID 0x0000000000000800 824 825 /* 826 * Cyrix configuration registers, accessible as IO ports. 827 */ 828 #define CCR0 0xc0 /* Configuration control register 0 */ 829 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is 830 non-cacheable */ 831 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */ 832 #define CCR0_A20M 0x04 /* Enables A20M# input pin */ 833 #define CCR0_KEN 0x08 /* Enables KEN# input pin */ 834 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */ 835 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold 836 state */ 837 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set 838 assoc */ 839 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */ 840 841 #define CCR1 0xc1 /* Configuration control register 1 */ 842 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */ 843 #define CCR1_SMI 0x02 /* Enables SMM pins */ 844 #define CCR1_SMAC 0x04 /* System management memory access */ 845 #define CCR1_MMAC 0x08 /* Main memory access */ 846 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */ 847 #define CCR1_SM3 0x80 /* SMM address space address region 3 */ 848 849 #define CCR2 0xc2 850 #define CCR2_WB 0x02 /* Enables WB cache interface pins */ 851 #define CCR2_SADS 0x02 /* Slow ADS */ 852 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */ 853 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */ 854 #define CCR2_WT1 0x10 /* WT region 1 */ 855 #define CCR2_WPR1 0x10 /* Write-protect region 1 */ 856 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering 857 hold state. */ 858 #define CCR2_BWRT 0x40 /* Enables burst write cycles */ 859 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */ 860 861 #define CCR3 0xc3 862 #define CCR3_SMILOCK 0x01 /* SMM register lock */ 863 #define CCR3_NMI 0x02 /* Enables NMI during SMM */ 864 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */ 865 #define CCR3_SMMMODE 0x08 /* SMM Mode */ 866 #define CCR3_MAPEN0 0x10 /* Enables Map0 */ 867 #define CCR3_MAPEN1 0x20 /* Enables Map1 */ 868 #define CCR3_MAPEN2 0x40 /* Enables Map2 */ 869 #define CCR3_MAPEN3 0x80 /* Enables Map3 */ 870 871 #define CCR4 0xe8 872 #define CCR4_IOMASK 0x07 873 #define CCR4_MEM 0x08 /* Enables momory bypassing */ 874 #define CCR4_DTE 0x10 /* Enables directory table entry cache */ 875 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */ 876 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */ 877 878 #define CCR5 0xe9 879 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */ 880 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */ 881 #define CCR5_LBR1 0x10 /* Local bus region 1 */ 882 #define CCR5_ARREN 0x20 /* Enables ARR region */ 883 884 #define CCR6 0xea 885 886 #define CCR7 0xeb 887 888 /* Performance Control Register (5x86 only). */ 889 #define PCR0 0x20 890 #define PCR0_RSTK 0x01 /* Enables return stack */ 891 #define PCR0_BTB 0x02 /* Enables branch target buffer */ 892 #define PCR0_LOOP 0x04 /* Enables loop */ 893 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to 894 serialize pipe. */ 895 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */ 896 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */ 897 #define PCR0_LSSER 0x80 /* Disable reorder */ 898 899 /* Device Identification Registers */ 900 #define DIR0 0xfe 901 #define DIR1 0xff 902 903 /* 904 * Machine Check register constants. 905 */ 906 #define MCG_CAP_COUNT 0x000000ff 907 #define MCG_CAP_CTL_P 0x00000100 908 #define MCG_CAP_EXT_P 0x00000200 909 #define MCG_CAP_CMCI_P 0x00000400 910 #define MCG_CAP_TES_P 0x00000800 911 #define MCG_CAP_EXT_CNT 0x00ff0000 912 #define MCG_CAP_SER_P 0x01000000 913 #define MCG_STATUS_RIPV 0x00000001 914 #define MCG_STATUS_EIPV 0x00000002 915 #define MCG_STATUS_MCIP 0x00000004 916 #define MCG_CTL_ENABLE 0xffffffffffffffff 917 #define MCG_CTL_DISABLE 0x0000000000000000 918 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4) 919 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4) 920 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4) 921 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4) 922 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */ 923 #define MC_STATUS_MCA_ERROR 0x000000000000ffff 924 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000 925 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000 926 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_CMCI_P */ 927 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */ 928 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_TES_P */ 929 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_TES_P */ 930 #define MC_STATUS_PCC 0x0200000000000000 931 #define MC_STATUS_ADDRV 0x0400000000000000 932 #define MC_STATUS_MISCV 0x0800000000000000 933 #define MC_STATUS_EN 0x1000000000000000 934 #define MC_STATUS_UC 0x2000000000000000 935 #define MC_STATUS_OVER 0x4000000000000000 936 #define MC_STATUS_VAL 0x8000000000000000 937 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */ 938 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */ 939 #define MC_CTL2_THRESHOLD 0x0000000000007fff 940 #define MC_CTL2_CMCI_EN 0x0000000040000000 941 #define MC_AMDNB_BANK 4 942 #define MC_MISC_AMD_VAL 0x8000000000000000 /* Counter presence valid */ 943 #define MC_MISC_AMD_CNTP 0x4000000000000000 /* Counter present */ 944 #define MC_MISC_AMD_LOCK 0x2000000000000000 /* Register locked */ 945 #define MC_MISC_AMD_INTP 0x1000000000000000 /* Int. type can generate interrupts */ 946 #define MC_MISC_AMD_LVT_MASK 0x00f0000000000000 /* Extended LVT offset */ 947 #define MC_MISC_AMD_LVT_SHIFT 52 948 #define MC_MISC_AMD_CNTEN 0x0008000000000000 /* Counter enabled */ 949 #define MC_MISC_AMD_INT_MASK 0x0006000000000000 /* Interrupt type */ 950 #define MC_MISC_AMD_INT_LVT 0x0002000000000000 /* Interrupt via Extended LVT */ 951 #define MC_MISC_AMD_INT_SMI 0x0004000000000000 /* SMI */ 952 #define MC_MISC_AMD_OVERFLOW 0x0001000000000000 /* Counter overflow */ 953 #define MC_MISC_AMD_CNT_MASK 0x00000fff00000000 /* Counter value */ 954 #define MC_MISC_AMD_CNT_SHIFT 32 955 #define MC_MISC_AMD_CNT_MAX 0xfff 956 #define MC_MISC_AMD_PTR_MASK 0x00000000ff000000 /* Pointer to additional registers */ 957 #define MC_MISC_AMD_PTR_SHIFT 24 958 959 /* AMD Scalable MCA */ 960 #define MSR_SMCA_MC0_CTL 0xc0002000 961 #define MSR_SMCA_MC0_STATUS 0xc0002001 962 #define MSR_SMCA_MC0_ADDR 0xc0002002 963 #define MSR_SMCA_MC0_MISC0 0xc0002003 964 #define MSR_SMCA_MC_CTL(x) (MSR_SMCA_MC0_CTL + 0x10 * (x)) 965 #define MSR_SMCA_MC_STATUS(x) (MSR_SMCA_MC0_STATUS + 0x10 * (x)) 966 #define MSR_SMCA_MC_ADDR(x) (MSR_SMCA_MC0_ADDR + 0x10 * (x)) 967 #define MSR_SMCA_MC_MISC(x) (MSR_SMCA_MC0_MISC0 + 0x10 * (x)) 968 969 /* 970 * The following four 3-byte registers control the non-cacheable regions. 971 * These registers must be written as three separate bytes. 972 * 973 * NCRx+0: A31-A24 of starting address 974 * NCRx+1: A23-A16 of starting address 975 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx. 976 * 977 * The non-cacheable region's starting address must be aligned to the 978 * size indicated by the NCR_SIZE_xx field. 979 */ 980 #define NCR1 0xc4 981 #define NCR2 0xc7 982 #define NCR3 0xca 983 #define NCR4 0xcd 984 985 #define NCR_SIZE_0K 0 986 #define NCR_SIZE_4K 1 987 #define NCR_SIZE_8K 2 988 #define NCR_SIZE_16K 3 989 #define NCR_SIZE_32K 4 990 #define NCR_SIZE_64K 5 991 #define NCR_SIZE_128K 6 992 #define NCR_SIZE_256K 7 993 #define NCR_SIZE_512K 8 994 #define NCR_SIZE_1M 9 995 #define NCR_SIZE_2M 10 996 #define NCR_SIZE_4M 11 997 #define NCR_SIZE_8M 12 998 #define NCR_SIZE_16M 13 999 #define NCR_SIZE_32M 14 1000 #define NCR_SIZE_4G 15 1001 1002 /* 1003 * The address region registers are used to specify the location and 1004 * size for the eight address regions. 1005 * 1006 * ARRx + 0: A31-A24 of start address 1007 * ARRx + 1: A23-A16 of start address 1008 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx 1009 */ 1010 #define ARR0 0xc4 1011 #define ARR1 0xc7 1012 #define ARR2 0xca 1013 #define ARR3 0xcd 1014 #define ARR4 0xd0 1015 #define ARR5 0xd3 1016 #define ARR6 0xd6 1017 #define ARR7 0xd9 1018 1019 #define ARR_SIZE_0K 0 1020 #define ARR_SIZE_4K 1 1021 #define ARR_SIZE_8K 2 1022 #define ARR_SIZE_16K 3 1023 #define ARR_SIZE_32K 4 1024 #define ARR_SIZE_64K 5 1025 #define ARR_SIZE_128K 6 1026 #define ARR_SIZE_256K 7 1027 #define ARR_SIZE_512K 8 1028 #define ARR_SIZE_1M 9 1029 #define ARR_SIZE_2M 10 1030 #define ARR_SIZE_4M 11 1031 #define ARR_SIZE_8M 12 1032 #define ARR_SIZE_16M 13 1033 #define ARR_SIZE_32M 14 1034 #define ARR_SIZE_4G 15 1035 1036 /* 1037 * The region control registers specify the attributes associated with 1038 * the ARRx addres regions. 1039 */ 1040 #define RCR0 0xdc 1041 #define RCR1 0xdd 1042 #define RCR2 0xde 1043 #define RCR3 0xdf 1044 #define RCR4 0xe0 1045 #define RCR5 0xe1 1046 #define RCR6 0xe2 1047 #define RCR7 0xe3 1048 1049 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */ 1050 #define RCR_RCE 0x01 /* Enables caching for ARR7. */ 1051 #define RCR_WWO 0x02 /* Weak write ordering. */ 1052 #define RCR_WL 0x04 /* Weak locking. */ 1053 #define RCR_WG 0x08 /* Write gathering. */ 1054 #define RCR_WT 0x10 /* Write-through. */ 1055 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */ 1056 1057 /* AMD Write Allocate Top-Of-Memory and Control Register */ 1058 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */ 1059 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */ 1060 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */ 1061 1062 /* AMD64 MSR's */ 1063 #define MSR_EFER 0xc0000080 /* extended features */ 1064 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */ 1065 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */ 1066 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */ 1067 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */ 1068 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */ 1069 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */ 1070 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */ 1071 #define MSR_TSC_AUX 0xc0000103 1072 #define MSR_PERFEVSEL0 0xc0010000 1073 #define MSR_PERFEVSEL1 0xc0010001 1074 #define MSR_PERFEVSEL2 0xc0010002 1075 #define MSR_PERFEVSEL3 0xc0010003 1076 #define MSR_K7_PERFCTR0 0xc0010004 1077 #define MSR_K7_PERFCTR1 0xc0010005 1078 #define MSR_K7_PERFCTR2 0xc0010006 1079 #define MSR_K7_PERFCTR3 0xc0010007 1080 #define MSR_SYSCFG 0xc0010010 1081 #define MSR_HWCR 0xc0010015 1082 #define MSR_IORRBASE0 0xc0010016 1083 #define MSR_IORRMASK0 0xc0010017 1084 #define MSR_IORRBASE1 0xc0010018 1085 #define MSR_IORRMASK1 0xc0010019 1086 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */ 1087 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */ 1088 #define MSR_NB_CFG1 0xc001001f /* NB configuration 1 */ 1089 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */ 1090 #define MSR_MC0_CTL_MASK 0xc0010044 1091 #define MSR_P_STATE_LIMIT 0xc0010061 /* P-state Current Limit Register */ 1092 #define MSR_P_STATE_CONTROL 0xc0010062 /* P-state Control Register */ 1093 #define MSR_P_STATE_STATUS 0xc0010063 /* P-state Status Register */ 1094 #define MSR_P_STATE_CONFIG(n) (0xc0010064 + (n)) /* P-state Config */ 1095 #define MSR_SMM_ADDR 0xc0010112 /* SMM TSEG base address */ 1096 #define MSR_SMM_MASK 0xc0010113 /* SMM TSEG address mask */ 1097 #define MSR_VM_CR 0xc0010114 /* SVM: feature control */ 1098 #define MSR_VM_HSAVE_PA 0xc0010117 /* SVM: host save area address */ 1099 #define MSR_AMD_CPUID07 0xc0011002 /* CPUID 07 %ebx override */ 1100 #define MSR_EXTFEATURES 0xc0011005 /* Extended CPUID Features override */ 1101 #define MSR_LS_CFG 0xc0011020 1102 #define MSR_IC_CFG 0xc0011021 /* Instruction Cache Configuration */ 1103 #define MSR_DE_CFG 0xc0011029 /* Decode Configuration */ 1104 1105 /* MSR_VM_CR related */ 1106 #define VM_CR_SVMDIS 0x10 /* SVM: disabled by BIOS */ 1107 1108 /* VIA ACE crypto featureset: for via_feature_rng */ 1109 #define VIA_HAS_RNG 1 /* cpu has RNG */ 1110 1111 /* VIA ACE crypto featureset: for via_feature_xcrypt */ 1112 #define VIA_HAS_AES 1 /* cpu has AES */ 1113 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */ 1114 #define VIA_HAS_MM 4 /* cpu has RSA instructions */ 1115 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */ 1116 1117 /* Centaur Extended Feature flags */ 1118 #define VIA_CPUID_HAS_RNG 0x000004 1119 #define VIA_CPUID_DO_RNG 0x000008 1120 #define VIA_CPUID_HAS_ACE 0x000040 1121 #define VIA_CPUID_DO_ACE 0x000080 1122 #define VIA_CPUID_HAS_ACE2 0x000100 1123 #define VIA_CPUID_DO_ACE2 0x000200 1124 #define VIA_CPUID_HAS_PHE 0x000400 1125 #define VIA_CPUID_DO_PHE 0x000800 1126 #define VIA_CPUID_HAS_PMM 0x001000 1127 #define VIA_CPUID_DO_PMM 0x002000 1128 1129 /* VIA ACE xcrypt-* instruction context control options */ 1130 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f 1131 #define VIA_CRYPT_CWLO_ALG_M 0x00000070 1132 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000 1133 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080 1134 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000 1135 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080 1136 #define VIA_CRYPT_CWLO_NORMAL 0x00000000 1137 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100 1138 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000 1139 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200 1140 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */ 1141 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */ 1142 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */ 1143 1144 #endif /* !_MACHINE_SPECIALREG_H_ */ 1145