1 /* 2 * Implement fast Fletcher4 using superscalar pipelines. 3 * 4 * Use regular C code to compute 5 * Fletcher4 in two incremental 64-bit parallel accumulator streams, 6 * and then combine the streams to form the final four checksum words. 7 * This implementation is a derivative of the AVX SIMD implementation by 8 * James Guilford and Jinshan Xiong from Intel (see zfs_fletcher_intel.c). 9 * 10 * Copyright (C) 2016 Romain Dolbeau. 11 * 12 * Authors: 13 * Romain Dolbeau <romain.dolbeau@atos.net> 14 * 15 * This software is available to you under a choice of one of two 16 * licenses. You may choose to be licensed under the terms of the GNU 17 * General Public License (GPL) Version 2, available from the file 18 * COPYING in the main directory of this source tree, or the 19 * OpenIB.org BSD license below: 20 * 21 * Redistribution and use in source and binary forms, with or 22 * without modification, are permitted provided that the following 23 * conditions are met: 24 * 25 * - Redistributions of source code must retain the above 26 * copyright notice, this list of conditions and the following 27 * disclaimer. 28 * 29 * - Redistributions in binary form must reproduce the above 30 * copyright notice, this list of conditions and the following 31 * disclaimer in the documentation and/or other materials 32 * provided with the distribution. 33 * 34 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 35 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 36 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 37 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 38 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 39 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 40 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 41 * SOFTWARE. 42 */ 43 44 #include <sys/types.h> 45 #include <sys/sunddi.h> 46 #include <sys/byteorder.h> 47 #include <sys/simd.h> 48 #include <sys/spa_checksum.h> 49 #include <zfs_fletcher.h> 50 #ifndef _KERNEL 51 #include <strings.h> 52 #endif 53 54 static void 55 fletcher_4_superscalar_init(fletcher_4_ctx_t *ctx) 56 { 57 bzero(ctx->superscalar, 4 * sizeof (zfs_fletcher_superscalar_t)); 58 } 59 60 static void 61 fletcher_4_superscalar_fini(fletcher_4_ctx_t *ctx, zio_cksum_t *zcp) 62 { 63 uint64_t A, B, C, D; 64 A = ctx->superscalar[0].v[0] + ctx->superscalar[0].v[1]; 65 B = 2 * ctx->superscalar[1].v[0] + 2 * ctx->superscalar[1].v[1] - 66 ctx->superscalar[0].v[1]; 67 C = 4 * ctx->superscalar[2].v[0] - ctx->superscalar[1].v[0] + 68 4 * ctx->superscalar[2].v[1] - 3 * ctx->superscalar[1].v[1]; 69 D = 8 * ctx->superscalar[3].v[0] - 4 * ctx->superscalar[2].v[0] + 70 8 * ctx->superscalar[3].v[1] - 8 * ctx->superscalar[2].v[1] + 71 ctx->superscalar[1].v[1]; 72 ZIO_SET_CHECKSUM(zcp, A, B, C, D); 73 } 74 75 static void 76 fletcher_4_superscalar_native(fletcher_4_ctx_t *ctx, 77 const void *buf, size_t size) 78 { 79 const uint32_t *ip = buf; 80 const uint32_t *ipend = ip + (size / sizeof (uint32_t)); 81 uint64_t a, b, c, d; 82 uint64_t a2, b2, c2, d2; 83 84 a = ctx->superscalar[0].v[0]; 85 b = ctx->superscalar[1].v[0]; 86 c = ctx->superscalar[2].v[0]; 87 d = ctx->superscalar[3].v[0]; 88 a2 = ctx->superscalar[0].v[1]; 89 b2 = ctx->superscalar[1].v[1]; 90 c2 = ctx->superscalar[2].v[1]; 91 d2 = ctx->superscalar[3].v[1]; 92 93 do { 94 a += ip[0]; 95 a2 += ip[1]; 96 b += a; 97 b2 += a2; 98 c += b; 99 c2 += b2; 100 d += c; 101 d2 += c2; 102 } while ((ip += 2) < ipend); 103 104 ctx->superscalar[0].v[0] = a; 105 ctx->superscalar[1].v[0] = b; 106 ctx->superscalar[2].v[0] = c; 107 ctx->superscalar[3].v[0] = d; 108 ctx->superscalar[0].v[1] = a2; 109 ctx->superscalar[1].v[1] = b2; 110 ctx->superscalar[2].v[1] = c2; 111 ctx->superscalar[3].v[1] = d2; 112 } 113 114 static void 115 fletcher_4_superscalar_byteswap(fletcher_4_ctx_t *ctx, 116 const void *buf, size_t size) 117 { 118 const uint32_t *ip = buf; 119 const uint32_t *ipend = ip + (size / sizeof (uint32_t)); 120 uint64_t a, b, c, d; 121 uint64_t a2, b2, c2, d2; 122 123 a = ctx->superscalar[0].v[0]; 124 b = ctx->superscalar[1].v[0]; 125 c = ctx->superscalar[2].v[0]; 126 d = ctx->superscalar[3].v[0]; 127 a2 = ctx->superscalar[0].v[1]; 128 b2 = ctx->superscalar[1].v[1]; 129 c2 = ctx->superscalar[2].v[1]; 130 d2 = ctx->superscalar[3].v[1]; 131 132 do { 133 a += BSWAP_32(ip[0]); 134 a2 += BSWAP_32(ip[1]); 135 b += a; 136 b2 += a2; 137 c += b; 138 c2 += b2; 139 d += c; 140 d2 += c2; 141 } while ((ip += 2) < ipend); 142 143 ctx->superscalar[0].v[0] = a; 144 ctx->superscalar[1].v[0] = b; 145 ctx->superscalar[2].v[0] = c; 146 ctx->superscalar[3].v[0] = d; 147 ctx->superscalar[0].v[1] = a2; 148 ctx->superscalar[1].v[1] = b2; 149 ctx->superscalar[2].v[1] = c2; 150 ctx->superscalar[3].v[1] = d2; 151 } 152 153 static boolean_t 154 fletcher_4_superscalar_valid(void) 155 { 156 return (B_TRUE); 157 } 158 159 const fletcher_4_ops_t fletcher_4_superscalar_ops = { 160 .init_native = fletcher_4_superscalar_init, 161 .compute_native = fletcher_4_superscalar_native, 162 .fini_native = fletcher_4_superscalar_fini, 163 .init_byteswap = fletcher_4_superscalar_init, 164 .compute_byteswap = fletcher_4_superscalar_byteswap, 165 .fini_byteswap = fletcher_4_superscalar_fini, 166 .valid = fletcher_4_superscalar_valid, 167 .uses_fpu_native = B_FALSE, 168 .uses_fpu_byteswap = B_FALSE, 169 .name = "superscalar" 170 }; 171