1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 * 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <mcamd_api.h> 29 #include <mcamd_err.h> 30 #include <mcamd_rowcol_impl.h> 31 32 /* 33 * Chip-Select Bank Address Mode Encodings - BKDG 3.29 3.5.6 34 */ 35 static const struct bankaddr_mode bankaddr_modes_pre_d[]; 36 static const struct bankaddr_mode bankaddr_modes_d_e[]; 37 38 static const struct bam_desc { 39 int rev; 40 int nmodes; 41 const struct bankaddr_mode *modetbl; 42 } bankaddr_modes[] = { 43 { MC_REV_PRE_D, 7, bankaddr_modes_pre_d }, 44 { MC_REV_D_E, 11, bankaddr_modes_d_e }, 45 }; 46 47 /* 48 * DRAM Address Mappings for bank/row/column - BKDG 3.29 3.5.6.1 49 */ 50 static const struct csrcb_map_tbl dram_addrmap_pre_d_128; 51 static const struct csrcb_map_tbl dram_addrmap_pre_d_64; 52 static const struct csrcb_map_tbl dram_addrmap_d_e_64; 53 static const struct csrcb_map_tbl dram_addrmap_d_e_128; 54 55 static const struct rcbmap_desc { 56 int nmodes; 57 const struct csrcb_map_tbl *rcbmap; 58 } rcbmaps[] = { 59 { 7, &dram_addrmap_pre_d_64 }, 60 { 7, &dram_addrmap_pre_d_128 }, 61 { 11, &dram_addrmap_d_e_64 }, 62 { 11, &dram_addrmap_d_e_128 }, 63 }; 64 65 /* 66 * Lookup the Chip-Select Bank Address Mode Encoding table for a given 67 * chip revision and chip-select mode. 68 */ 69 const struct bankaddr_mode * 70 rct_bankaddr_mode(uint_t mcrev, uint_t csmode) 71 { 72 int i; 73 const struct bam_desc *bdp = bankaddr_modes; 74 75 for (i = 0; i < sizeof (bankaddr_modes) / sizeof (struct bam_desc); 76 i++, bdp++) { 77 if (bdp->rev == mcrev && csmode < bdp->nmodes) 78 return (&bdp->modetbl[csmode]); 79 80 } 81 82 return (NULL); 83 } 84 85 /* 86 * Lookup the DRAM Address Mapping table for a given chip revision, access 87 * width, bank-swizzle and chip-select mode. 88 */ 89 const struct csrcb_map * 90 rct_rcbmap(uint_t mcrev, int width, uint_t csmode) 91 { 92 const struct csrcb_map_tbl *rcbm; 93 int i; 94 95 for (i = 0; i < sizeof (rcbmaps) / sizeof (struct rcbmap_desc); i++) { 96 rcbm = rcbmaps[i].rcbmap; 97 if (rcbm->mt_rev == mcrev && rcbm->mt_width == width && 98 csmode < rcbmaps[i].nmodes) 99 return (&rcbm->mt_csmap[csmode]); 100 } 101 102 return (NULL); 103 } 104 105 /* 106 * DRAM Address Mapping in Interleaving Mode - BKDG 3.29 section 3.5.6.2. 107 * 108 * Chip-select interleave is performed by addressing across the columns 109 * of the first row of internal bank-select 0 on a chip-select, then the 110 * next row on internal bank-select 1, then 2 then 3; instead of then 111 * moving on to the next row of this chip-select we then rotate across 112 * other chip-selects in the interleave. The row/column/bank mappings 113 * described elsewhere in this file show that a DRAM InputAddr breaks down 114 * as follows (example is the first line of table 7 which is for a 32MB 115 * chip-select requiring 25 bits to address all of it) for the non-interleaved 116 * case: 117 * 118 * chip-selection bits | offset within chip-select bits | 119 * | row bits | bank bits | column bits | - | 120 * 24 13 12 11 10 3 2 0 121 * 122 * The high-order chip-selection bits select the chip-select and the 123 * offset bits offset within the chosen chip-select. 124 * 125 * To establish say a 2-way interleave in which we consume all of one 126 * row number and all internal bank numbers on one cs before moving on 127 * to the next to do the same we will target the first row bit - bit 13; 128 * a 4-way interleave would use bits 14 and 13, and an 8-way interleave 129 * bits 15, 14 and 13. We swap the chosen bits with the least significant 130 * high order chip-selection bits. 131 * 132 * Tables 13-16 of BKDG 3.5.6.2 really just describe the above. Working 133 * out the high-order bits to swap is easy since that is derived directly 134 * from the chip-select size. The low-order bits depend on the device 135 * parameters since we need to target the least significant row address bits - 136 * but we have that information from the rcbmaps since the first row bit 137 * simply follows the last bank address bit. 138 * 139 * Short version: we will do tables 13 to 16 programatically rather than 140 * replicating those tables. 141 */ 142 143 /* 144 * Yet another highbit function. This really needs to go to common source. 145 * Returns range 0 to 64 inclusive; 146 */ 147 static int 148 topbit(uint64_t i) 149 { 150 int h = 1; 151 152 if (i == 0) 153 return (0); 154 155 if (i & 0xffffffff00000000ULL) { 156 h += 32; 157 i >>= 32; 158 } 159 160 if (i & 0xffff0000) { 161 h += 16; 162 i >>= 16; 163 } 164 165 if (i & 0xff00) { 166 h += 8; 167 i >>= 8; 168 } 169 170 if (i & 0xf0) { 171 h += 4; 172 i >>= 4; 173 } 174 175 if (i & 0xc) { 176 h += 2; 177 i >>= 2; 178 } 179 180 if (i & 0x2) 181 h += 1; 182 183 return (h); 184 } 185 186 void 187 rct_csintlv_bits(uint_t mcrev, int width, uint_t csmode, int factor, 188 struct csintlv_desc *csid) 189 { 190 int i, lstbnkbit; 191 size_t csz; 192 const struct bankaddr_mode *bam; 193 const struct csrcb_map *rcm; 194 195 /* 196 * Dispatch the three "Not implemented" exceptions. 197 */ 198 if ((mcrev == MC_REV_PRE_D && width == 128 && csmode == 0x6) || 199 (mcrev == MC_REV_D_E && width == 128 && (csmode == 0x9 || 200 csmode == 0xa))) { 201 csid->csi_factor = 0; 202 return; 203 } 204 205 if ((bam = rct_bankaddr_mode(mcrev, csmode)) == NULL || 206 (rcm = rct_rcbmap(mcrev, width, csmode)) == NULL) { 207 csid->csi_factor = 0; 208 return; 209 } 210 211 csz = MC_CS_SIZE(bam, width); 212 213 switch (factor) { 214 case 2: 215 csid->csi_nbits = 1; 216 break; 217 case 4: 218 csid->csi_nbits = 2; 219 break; 220 case 8: 221 csid->csi_nbits = 3; 222 break; 223 default: 224 csid->csi_factor = 0; 225 return; 226 } 227 228 csid->csi_hibit = topbit(csz) - 1; 229 230 lstbnkbit = 0; 231 for (i = 0; i < MC_RC_BANKBITS; i++) { 232 /* first bank arg for a bit is "real" bank bit */ 233 if (rcm->csrcb_bankargs[i][0] > lstbnkbit) 234 lstbnkbit = rcm->csrcb_bankargs[i][0]; 235 } 236 237 /* first row bit is immediately after last bank bit */ 238 csid->csi_lobit = lstbnkbit + 1; 239 240 csid->csi_factor = factor; 241 } 242 243 244 /* 245 * General notes for CS Bank Address Mode Encoding tables. 246 * 247 * These are the tables of BKDG 3.29 section 3.5.6. They are indexed 248 * by chip-select mode. Where the numbers of rows and columns is 249 * ambiguous (as it is for a number of rev CG and earlier cases) 250 * the bam_config should be initialized to 1 and the numbers of rows 251 * and columns should be the maximums. 252 */ 253 254 /* 255 * Chip Select Bank Address Mode Encoding for rev CG and earlier. 256 */ 257 static const struct bankaddr_mode bankaddr_modes_pre_d[] = { 258 { /* 000 */ 259 32, 12, 8 260 }, 261 { /* 001 */ 262 64, 12, 9 263 }, 264 { /* 010 */ 265 128, 13, 10, 1 266 }, 267 { /* 011 */ 268 256, 13, 11, 1 269 }, 270 { /* 100 */ 271 512, 14, 11, 1 272 }, 273 { /* 101 */ 274 1024, 14, 12, 1 275 }, 276 { /* 110 */ 277 2048, 14, 12 278 } 279 }; 280 281 /* 282 * Chip Select Bank Address Mode Encoding for revs D and E. 283 */ 284 static const struct bankaddr_mode bankaddr_modes_d_e[] = { 285 { /* 0000 */ 286 32, 12, 8 287 }, 288 { /* 0001 */ 289 64, 12, 9 290 }, 291 { /* 0010 */ 292 128, 13, 9 293 }, 294 { /* 0011 */ 295 128, 12, 10 296 }, 297 { /* 0100 */ 298 256, 13, 10 299 }, 300 { /* 0101 */ 301 512, 14, 10 302 }, 303 { /* 0110 */ 304 256, 12, 11 305 }, 306 { /* 0111 */ 307 512, 13, 11 308 }, 309 { /* 1000 */ 310 1024, 14, 11 311 }, 312 { /* 1001 */ 313 1024, 13, 12 314 }, 315 { /* 1010 */ 316 2048, 14, 12 317 } 318 }; 319 320 /* 321 * General notes on Row/Column/Bank table initialisation. 322 * 323 * These are the tables 7, 8, 9, 10, 11 and 12 of BKDG 3.29 section 3.5.6.1. 324 * They apply in non-interleave (node or cs) mode and describe how for 325 * a given revision, access width, bank-swizzle mode, and current chip-select 326 * mode the row, column and internal sdram bank are derived from the 327 * normalizied InputAddr presented to the DRAM controller. 328 * 329 * The mt_csmap array is indexed by chip-select mode. Within it the 330 * bankargs, rowbits and colbits arrays are indexed by bit number, so 331 * match the BKDG tables if the latter are read right-to-left. 332 * 333 * The bankargs list up to three bit numbers per bank bit. For revisions 334 * CG and earlier there is no bank swizzling, so just a single number 335 * should be listed. Revisions D and E have the same row/column/bank mapping, 336 * but rev E has the additional feature of being able to xor two row bits 337 * into each bank bit. The consumer will know whether they are using bank 338 * swizzling - if so then they should xor the bankargs bits together. 339 * The first argument must be the bit number not already used in forming 340 * part of the row address - eg in table 12 for csmode 0000b bank address 341 * bit 0 is bit 12 xor bit 18 xor bit 21, and 18 and 21 are also mentioned in 342 * the row address (bits 10 and 1) so we must list bit 12 first. We will 343 * use this information in chip-select interleave decoding in which we need 344 * to know which is the first bit after column and bank address bits. 345 * 346 * Column address A10 is always used for the Precharge All signal. Where 347 * "PC" appears in the BKDG tables we will include MC_PC_ALL in the 348 * corresponding bit position. 349 * 350 * For some rev CG and earlier chipselect modes the number of rows and columns 351 * is ambiguous. This is reflected in these tables by some bit being 352 * duplicated between row and column address. In practice we will follow 353 * the convention of always assigning the floating bit to the row address. 354 */ 355 356 /* 357 * Row/Column/Bank address mappings for rev CG in 64-bit mode, no interleave. 358 * See BKDG 3.29 3.5.6 Table 7. 359 */ 360 static const struct csrcb_map_tbl dram_addrmap_pre_d_64 = { 361 MC_REV_PRE_D, 362 64, 363 { 364 { /* 000 */ 365 { { 11 }, { 12 } }, 366 { 19, 20, 21, 22, 23, 24, 13, 14, 15, 16, 17, 18 }, 367 { 3, 4, 5, 6, 7, 8, 9, 10 } 368 }, 369 { /* 001 */ 370 { { 13 }, { 12 } }, 371 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18 }, 372 { 3, 4, 5, 6, 7, 8, 9, 10, 11 } 373 }, 374 { /* 010 */ 375 { { 13 }, { 12 } }, 376 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 }, 377 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 26 } 378 }, 379 { /* 011 */ 380 { { 13 }, { 14 } }, 381 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27 }, 382 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 27 } 383 }, 384 { /* 100 */ 385 { { 13 }, { 14 } }, 386 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 }, 387 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 28 } 388 }, 389 { /* 101 */ 390 { { 15 }, { 14 } }, 391 { 19, 20, 21, 22, 23, 24, 25, 26, 29, 16, 17, 18, 27, 28 }, 392 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 28 } 393 }, 394 { /* 110 */ 395 { { 15 }, { 14 } }, 396 { 19, 20, 21, 22, 23, 24, 25, 26, 29, 16, 17, 18, 27, 28 }, 397 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 30 } 398 }, 399 /* 400 * remainder unused 401 */ 402 } 403 404 }; 405 406 /* 407 * Row/Column/Bank address mappings for rev CG in 128-bit mode, no interleave. 408 * See BKDG 3.29 3.5.6 Table 8. 409 */ 410 static const struct csrcb_map_tbl dram_addrmap_pre_d_128 = { 411 MC_REV_PRE_D, 412 128, 413 { 414 { /* 000 */ 415 { { 12 }, { 13 } }, 416 { 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 19 }, 417 { 4, 5, 6, 7, 8, 9, 10, 11 } 418 }, 419 { /* 001 */ 420 { { 14 }, { 13 } }, 421 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19 }, 422 { 4, 5, 6, 7, 8, 9, 10, 11, 12 } 423 }, 424 { /* 010 */ 425 { { 14 }, { 13 } }, 426 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 }, 427 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 27 } 428 }, 429 { /* 011 */ 430 { { 14 }, { 15 } }, 431 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28 }, 432 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 28 } 433 }, 434 { /* 100 */ 435 { { 14 }, { 15 } }, 436 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 }, 437 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 29 } 438 }, 439 { /* 101 */ 440 { { 16 }, { 15 } }, 441 { 20, 21, 22, 23, 24, 25, 26, 27, 30, 17, 18, 19, 28, 29 }, 442 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 29 } 443 }, 444 { /* 110 */ 445 { { 16 }, { 15 } }, 446 { 20, 21, 22, 23, 24, 25, 26, 27, 30, 17, 18, 19, 28, 29 }, 447 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 31 } 448 }, 449 /* 450 * remainder unused 451 */ 452 } 453 }; 454 455 /* 456 * Row/Column/Bank address mappings for rev D/E in 64-bit mode, no interleave. 457 * See BKDG 3.29 3.5.6 Table 9. 458 */ 459 static const struct csrcb_map_tbl dram_addrmap_d_e_64 = { 460 MC_REV_D_E, 461 64, 462 { 463 { /* 0000 */ 464 { { 11, 17, 20 }, { 12, 18, 21 } }, 465 { 19, 20, 21, 22, 23, 24, 13, 14, 15, 16, 17, 18 }, 466 { 3, 4, 5, 6, 7, 8, 9, 10 } 467 }, 468 { /* 0001 */ 469 { { 12, 17, 20 }, { 13, 18, 21 } }, 470 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 }, 471 { 3, 4, 5, 6, 7, 8, 9, 10, 11 } 472 }, 473 { /* 0010 */ 474 { { 12, 17, 20 }, { 13, 18, 21 } }, 475 { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 }, 476 { 3, 4, 5, 6, 7, 8, 9, 10, 11 } 477 }, 478 { /* 0011 */ 479 { { 13, 17, 20 }, { 14, 18, 21 } }, 480 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 }, 481 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 } 482 }, 483 { /* 0100 */ 484 { { 13, 17, 20 }, { 14, 18, 21 } }, 485 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 }, 486 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 } 487 }, 488 { /* 0101 */ 489 { { 13, 17, 20 }, { 14, 18, 21 } }, 490 { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 }, 491 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 } 492 }, 493 { /* 0110 */ 494 { { 14, 17, 20 }, { 15, 18, 21 } }, 495 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 }, 496 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 } 497 }, 498 { /* 0111 */ 499 { { 14, 17, 20 }, { 15, 18, 21 } }, 500 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 }, 501 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 } 502 }, 503 { /* 1000 */ 504 { { 14, 17, 20 }, { 15, 18, 21 } }, 505 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 }, 506 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 } 507 }, 508 { /* 1001 */ 509 { { 15, 17, 20 }, { 16, 18, 21 } }, 510 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 29, 30 }, 511 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 14 } 512 }, 513 { /* 1010 */ 514 { { 15, 17, 20 }, { 16, 18, 21 } }, 515 { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 29, 30 }, 516 { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 14 } 517 }, 518 /* 519 * remainder unused 520 */ 521 } 522 }; 523 524 /* 525 * Row/Column/Bank address mappings for rev D/E in 128-bit mode, no interleave. 526 * See BKDG 3.29 3.5.6 Table 9. 527 */ 528 static const struct csrcb_map_tbl dram_addrmap_d_e_128 = { 529 MC_REV_D_E, 530 128, 531 { 532 { /* 0000 */ 533 { { 12, 18, 21 }, { 13, 19, 22 } }, 534 { 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 19 }, 535 { 4, 5, 6, 7, 8, 9, 10, 11 } 536 }, 537 { /* 0001 */ 538 { { 13, 18, 21 }, { 14, 19, 22 } }, 539 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 }, 540 { 4, 5, 6, 7, 8, 9, 10, 11, 12 } 541 }, 542 { /* 0010 */ 543 { { 13, 18, 21 }, { 14, 19, 22 } }, 544 { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 }, 545 { 4, 5, 6, 7, 8, 9, 10, 11, 12 } 546 }, 547 { /* 0011 */ 548 { { 14, 18, 21 }, { 15, 19, 22 } }, 549 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 }, 550 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 } 551 }, 552 { /* 0100 */ 553 { { 14, 18, 21 }, { 15, 19, 22 } }, 554 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 }, 555 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 } 556 }, 557 { /* 0101 */ 558 { { 14, 18, 21 }, { 15, 19, 22 } }, 559 { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 }, 560 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 } 561 }, 562 { /* 0110 */ 563 { { 15, 18, 21 }, { 16, 19, 22 } }, 564 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 }, 565 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 } 566 }, 567 { /* 0111 */ 568 { { 15, 18, 21 }, { 16, 19, 22 } }, 569 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 }, 570 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 } 571 }, 572 { /* 1000 */ 573 { { 15, 18, 21 }, { 16, 19, 22 } }, 574 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 }, 575 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 } 576 }, 577 { /* 1001 */ 578 { { 16, 18, 21 }, { 17, 19, 22 } }, 579 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 18, 19, 30, 31 }, 580 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 15 } 581 }, 582 { /* 1010 */ 583 { { 16, 18, 21 }, { 17, 19, 22 } }, 584 { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 18, 19, 30, 31 }, 585 { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 15 } 586 }, 587 /* 588 * remainder unused 589 */ 590 } 591 }; 592