17aec1d6eScindi /*
27aec1d6eScindi * CDDL HEADER START
37aec1d6eScindi *
47aec1d6eScindi * The contents of this file are subject to the terms of the
55f25dc2aSgavinm * Common Development and Distribution License (the "License").
65f25dc2aSgavinm * You may not use this file except in compliance with the License.
77aec1d6eScindi *
87aec1d6eScindi * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
97aec1d6eScindi * or http://www.opensolaris.org/os/licensing.
107aec1d6eScindi * See the License for the specific language governing permissions
117aec1d6eScindi * and limitations under the License.
127aec1d6eScindi *
137aec1d6eScindi * When distributing Covered Code, include this CDDL HEADER in each
147aec1d6eScindi * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
157aec1d6eScindi * If applicable, add the following below this CDDL HEADER, with the
167aec1d6eScindi * fields enclosed by brackets "[]" replaced with your own identifying
177aec1d6eScindi * information: Portions Copyright [yyyy] [name of copyright owner]
187aec1d6eScindi *
197aec1d6eScindi * CDDL HEADER END
205f25dc2aSgavinm */
215f25dc2aSgavinm
225f25dc2aSgavinm /*
237aec1d6eScindi *
24*20c794b3Sgavinm * Copyright 2007 Sun Microsystems, Inc. All rights reserved.
257aec1d6eScindi * Use is subject to license terms.
267aec1d6eScindi */
277aec1d6eScindi
287aec1d6eScindi #include <mcamd_api.h>
297aec1d6eScindi #include <mcamd_err.h>
307aec1d6eScindi #include <mcamd_rowcol_impl.h>
317aec1d6eScindi
327aec1d6eScindi /*
338a40a695Sgavinm * =========== Chip-Select Bank Address Mode Encodings =======================
347aec1d6eScindi */
357aec1d6eScindi
368a40a695Sgavinm /* Individual table declarations */
378a40a695Sgavinm static const struct rct_bnkaddrmode bnkaddr_tbls_pre_d[];
388a40a695Sgavinm static const struct rct_bnkaddrmode bnkaddr_tbls_d_e[];
398a40a695Sgavinm static const struct rct_bnkaddrmode bnkaddr_tbls_f[];
408a40a695Sgavinm
418a40a695Sgavinm /* Managing bank address mode tables */
428a40a695Sgavinm static const struct _bnkaddrmode_tbldesc {
438a40a695Sgavinm uint_t revmask;
447aec1d6eScindi int nmodes;
458a40a695Sgavinm const struct rct_bnkaddrmode *modetbl;
468a40a695Sgavinm } bnkaddr_tbls[] = {
47*20c794b3Sgavinm { MC_F_REVS_BC, 7, bnkaddr_tbls_pre_d },
48*20c794b3Sgavinm { MC_F_REVS_DE, 11, bnkaddr_tbls_d_e },
49*20c794b3Sgavinm { MC_F_REVS_FG, 12, bnkaddr_tbls_f },
507aec1d6eScindi };
517aec1d6eScindi
527aec1d6eScindi /*
538a40a695Sgavinm * =========== DRAM Address Mappings for bank/row/column =====================
547aec1d6eScindi */
557aec1d6eScindi
568a40a695Sgavinm
578a40a695Sgavinm /* Individual table declarations */
588a40a695Sgavinm struct _rcbmap_tbl {
598a40a695Sgavinm uint_t mt_revmask; /* revision to which this applies */
608a40a695Sgavinm int mt_width; /* MC mode (64 or 128) */
618a40a695Sgavinm const struct rct_rcbmap mt_csmap[MC_RC_CSMODES];
628a40a695Sgavinm };
638a40a695Sgavinm
648a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_pre_d_64;
658a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_pre_d_128;
668a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_d_e_64;
678a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_d_e_128;
688a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_f_64;
698a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_f_128;
708a40a695Sgavinm
718a40a695Sgavinm /* Managing row/column/bank tables */
728a40a695Sgavinm static const struct _rcbmap_tbldesc {
737aec1d6eScindi int nmodes;
748a40a695Sgavinm const struct _rcbmap_tbl *rcbmap;
758a40a695Sgavinm } rcbmap_tbls[] = {
767aec1d6eScindi { 7, &dram_addrmap_pre_d_64 },
777aec1d6eScindi { 7, &dram_addrmap_pre_d_128 },
787aec1d6eScindi { 11, &dram_addrmap_d_e_64 },
797aec1d6eScindi { 11, &dram_addrmap_d_e_128 },
808a40a695Sgavinm { 12, &dram_addrmap_f_64 },
818a40a695Sgavinm { 12, &dram_addrmap_f_128 },
827aec1d6eScindi };
837aec1d6eScindi
847aec1d6eScindi /*
858a40a695Sgavinm * =========== Bank swizzling information ====================================
867aec1d6eScindi */
877aec1d6eScindi
888a40a695Sgavinm /* Individual table declarations */
898a40a695Sgavinm struct _bnkswzl_tbl {
908a40a695Sgavinm uint_t swzt_revmask; /* revision to which this applies */
918a40a695Sgavinm int swzt_width; /* MC mode (64 or 128) */
928a40a695Sgavinm const struct rct_bnkswzlinfo swzt_bits;
938a40a695Sgavinm };
947aec1d6eScindi
958a40a695Sgavinm static const struct _bnkswzl_tbl bnswzl_info_e_64;
968a40a695Sgavinm static const struct _bnkswzl_tbl bnswzl_info_e_128;
978a40a695Sgavinm static const struct _bnkswzl_tbl bnswzl_info_f_64;
988a40a695Sgavinm static const struct _bnkswzl_tbl bnswzl_info_f_128;
997aec1d6eScindi
1008a40a695Sgavinm /* Managing bank swizzle tables */
1018a40a695Sgavinm static const struct _bnkswzl_tbl *bnkswzl_tbls[] = {
1028a40a695Sgavinm &bnswzl_info_e_64,
1038a40a695Sgavinm &bnswzl_info_e_128,
1048a40a695Sgavinm &bnswzl_info_f_64,
1058a40a695Sgavinm &bnswzl_info_f_128,
1068a40a695Sgavinm };
1077aec1d6eScindi
1087aec1d6eScindi /*
1098a40a695Sgavinm * ======================================================================
1108a40a695Sgavinm * | Tables reflecting those in the BKDG |
1118a40a695Sgavinm * ======================================================================
1127aec1d6eScindi */
1137aec1d6eScindi
1147aec1d6eScindi /*
1158a40a695Sgavinm * DRAM Address Mapping in Interleaving Mode
1167aec1d6eScindi *
1177aec1d6eScindi * Chip-select interleave is performed by addressing across the columns
1187aec1d6eScindi * of the first row of internal bank-select 0 on a chip-select, then the
1197aec1d6eScindi * next row on internal bank-select 1, then 2 then 3; instead of then
1207aec1d6eScindi * moving on to the next row of this chip-select we then rotate across
1217aec1d6eScindi * other chip-selects in the interleave. The row/column/bank mappings
1227aec1d6eScindi * described elsewhere in this file show that a DRAM InputAddr breaks down
1238a40a695Sgavinm * as follows, using an example for CS Mode 0000 revision CG and earlier 64-bit
1248a40a695Sgavinm * mode; the cs size is 32MB, requiring 25 bits to address all of it.
1257aec1d6eScindi *
1267aec1d6eScindi * chip-selection bits | offset within chip-select bits |
1277aec1d6eScindi * | row bits | bank bits | column bits | - |
1287aec1d6eScindi * 24 13 12 11 10 3 2 0
1297aec1d6eScindi *
1307aec1d6eScindi * The high-order chip-selection bits select the chip-select and the
1317aec1d6eScindi * offset bits offset within the chosen chip-select.
1327aec1d6eScindi *
1337aec1d6eScindi * To establish say a 2-way interleave in which we consume all of one
1347aec1d6eScindi * row number and all internal bank numbers on one cs before moving on
1357aec1d6eScindi * to the next to do the same we will target the first row bit - bit 13;
1367aec1d6eScindi * a 4-way interleave would use bits 14 and 13, and an 8-way interleave
1377aec1d6eScindi * bits 15, 14 and 13. We swap the chosen bits with the least significant
1387aec1d6eScindi * high order chip-selection bits.
1397aec1d6eScindi *
1408a40a695Sgavinm * The BKDG interleave tables really just describe the above. Working
1417aec1d6eScindi * out the high-order bits to swap is easy since that is derived directly
1427aec1d6eScindi * from the chip-select size. The low-order bits depend on the device
1437aec1d6eScindi * parameters since we need to target the least significant row address bits -
1448a40a695Sgavinm * but we have that information from the rcbmap_tbls since the first row bit
1457aec1d6eScindi * simply follows the last bank address bit.
1467aec1d6eScindi */
1477aec1d6eScindi
1487aec1d6eScindi /*
1498a40a695Sgavinm * General notes for CS Bank Address Mode Encoding tables.
1508a40a695Sgavinm *
1518a40a695Sgavinm * These are indexed by chip-select mode. Where the numbers of rows and
1528a40a695Sgavinm * columns is ambiguous (as it is for a number of rev CG and earlier cases)
1538a40a695Sgavinm * the bam_config should be initialized to 1 and the numbers of rows
1548a40a695Sgavinm * and columns should be the maximums.
1558a40a695Sgavinm */
1568a40a695Sgavinm
1578a40a695Sgavinm /*
1588a40a695Sgavinm * Chip Select Bank Address Mode Encoding for rev CG and earlier.
1598a40a695Sgavinm */
1608a40a695Sgavinm static const struct rct_bnkaddrmode bnkaddr_tbls_pre_d[] = {
1618a40a695Sgavinm { /* 000 */
1628a40a695Sgavinm 32, 12, 8
1638a40a695Sgavinm },
1648a40a695Sgavinm { /* 001 */
1658a40a695Sgavinm 64, 12, 9
1668a40a695Sgavinm },
1678a40a695Sgavinm { /* 010 */
1688a40a695Sgavinm 128, 13, 10, 1 /* AMBIG */
1698a40a695Sgavinm },
1708a40a695Sgavinm { /* 011 */
1718a40a695Sgavinm 256, 13, 11, 1 /* AMBIG */
1728a40a695Sgavinm },
1738a40a695Sgavinm { /* 100 */
1748a40a695Sgavinm 512, 14, 11, 1 /* AMBIG */
1758a40a695Sgavinm },
1768a40a695Sgavinm { /* 101 */
1778a40a695Sgavinm 1024, 14, 12, 1 /* AMBIG */
1788a40a695Sgavinm },
1798a40a695Sgavinm { /* 110 */
1808a40a695Sgavinm 2048, 14, 12
1818a40a695Sgavinm }
1828a40a695Sgavinm };
1838a40a695Sgavinm
1848a40a695Sgavinm /*
1858a40a695Sgavinm * Chip Select Bank Address Mode Encoding for revs D and E.
1868a40a695Sgavinm */
1878a40a695Sgavinm static const struct rct_bnkaddrmode bnkaddr_tbls_d_e[] = {
1888a40a695Sgavinm { /* 0000 */
1898a40a695Sgavinm 32, 12, 8
1908a40a695Sgavinm },
1918a40a695Sgavinm { /* 0001 */
1928a40a695Sgavinm 64, 12, 9
1938a40a695Sgavinm },
1948a40a695Sgavinm { /* 0010 */
1958a40a695Sgavinm 128, 13, 9
1968a40a695Sgavinm },
1978a40a695Sgavinm { /* 0011 */
1988a40a695Sgavinm 128, 12, 10
1998a40a695Sgavinm },
2008a40a695Sgavinm { /* 0100 */
2018a40a695Sgavinm 256, 13, 10
2028a40a695Sgavinm },
2038a40a695Sgavinm { /* 0101 */
2048a40a695Sgavinm 512, 14, 10
2058a40a695Sgavinm },
2068a40a695Sgavinm { /* 0110 */
2078a40a695Sgavinm 256, 12, 11
2088a40a695Sgavinm },
2098a40a695Sgavinm { /* 0111 */
2108a40a695Sgavinm 512, 13, 11
2118a40a695Sgavinm },
2128a40a695Sgavinm { /* 1000 */
2138a40a695Sgavinm 1024, 14, 11
2148a40a695Sgavinm },
2158a40a695Sgavinm { /* 1001 */
2168a40a695Sgavinm 1024, 13, 12
2178a40a695Sgavinm },
2188a40a695Sgavinm { /* 1010 */
2198a40a695Sgavinm 2048, 14, 12
2208a40a695Sgavinm }
2218a40a695Sgavinm };
2228a40a695Sgavinm
2238a40a695Sgavinm /*
2248a40a695Sgavinm * Chip Select Bank Address Mode Encoding for rev F
2258a40a695Sgavinm */
2268a40a695Sgavinm static const struct rct_bnkaddrmode bnkaddr_tbls_f[] = {
2278a40a695Sgavinm { /* 0000 */
2288a40a695Sgavinm 128, 13, 9
2298a40a695Sgavinm },
2308a40a695Sgavinm { /* 0001 */
2318a40a695Sgavinm 256, 13, 10
2328a40a695Sgavinm },
2338a40a695Sgavinm { /* 0010 */
2348a40a695Sgavinm 512, 14, 10
2358a40a695Sgavinm },
2368a40a695Sgavinm { /* 0011 */
2378a40a695Sgavinm 512, 13, 11
2388a40a695Sgavinm },
2398a40a695Sgavinm { /* 0100 */
2408a40a695Sgavinm 512, 13, 10
2418a40a695Sgavinm },
2428a40a695Sgavinm { /* 0101 */
2438a40a695Sgavinm 1024, 14, 10
2448a40a695Sgavinm },
2458a40a695Sgavinm { /* 0110 */
2468a40a695Sgavinm 1024, 14, 11
2478a40a695Sgavinm },
2488a40a695Sgavinm { /* 0111 */
2498a40a695Sgavinm 2048, 15, 10
2508a40a695Sgavinm },
2518a40a695Sgavinm { /* 1000 */
2528a40a695Sgavinm 2048, 14, 11
2538a40a695Sgavinm },
2548a40a695Sgavinm { /* 1001 */
2558a40a695Sgavinm 4096, 15, 11
2568a40a695Sgavinm },
2578a40a695Sgavinm { /* 1010 */
2588a40a695Sgavinm 4096, 16, 10
2598a40a695Sgavinm },
2608a40a695Sgavinm { /* 1011 */
2618a40a695Sgavinm 8192, 16, 11
2628a40a695Sgavinm }
2638a40a695Sgavinm
2648a40a695Sgavinm };
2658a40a695Sgavinm
2668a40a695Sgavinm /*
2678a40a695Sgavinm * General notes on Row/Column/Bank table initialisation.
2688a40a695Sgavinm *
2698a40a695Sgavinm * These are the tables 7, 8, 9, 10, 11 and 12 of BKDG 3.29 section 3.5.6.1.
2708a40a695Sgavinm * They apply in non-interleave (node or cs) mode and describe how for
2718a40a695Sgavinm * a given revision, access width, bank-swizzle mode, and current chip-select
2728a40a695Sgavinm * mode the row, column and internal sdram bank are derived from the
2738a40a695Sgavinm * normalizied InputAddr presented to the DRAM controller.
2748a40a695Sgavinm *
2758a40a695Sgavinm * The mt_csmap array is indexed by chip-select mode. Within it the
2768a40a695Sgavinm * bankargs, rowbits and colbits arrays are indexed by bit number, so
2778a40a695Sgavinm * match the BKDG tables if the latter are read right-to-left.
2788a40a695Sgavinm *
2798a40a695Sgavinm * The bankargs list up to three bit numbers per bank bit. For revisions
2808a40a695Sgavinm * CG and earlier there is no bank swizzling, so just a single number
2818a40a695Sgavinm * should be listed. Revisions D and E have the same row/column/bank mapping,
2828a40a695Sgavinm * but rev E has the additional feature of being able to xor two row bits
2838a40a695Sgavinm * into each bank bit. The consumer will know whether they are using bank
2848a40a695Sgavinm * swizzling - if so then they should xor the bankargs bits together.
2858a40a695Sgavinm * The first argument must be the bit number not already used in forming
2868a40a695Sgavinm * part of the row address - eg in table 12 for csmode 0000b bank address
2878a40a695Sgavinm * bit 0 is bit 12 xor bit 18 xor bit 21, and 18 and 21 are also mentioned in
2888a40a695Sgavinm * the row address (bits 10 and 1) so we must list bit 12 first. We will
2898a40a695Sgavinm * use this information in chip-select interleave decoding in which we need
2908a40a695Sgavinm * to know which is the first bit after column and bank address bits.
2918a40a695Sgavinm *
2928a40a695Sgavinm * Column address A10 is always used for the Precharge All signal. Where
2938a40a695Sgavinm * "PC" appears in the BKDG tables we will include MC_PC_ALL in the
2948a40a695Sgavinm * corresponding bit position.
2958a40a695Sgavinm *
2968a40a695Sgavinm * For some rev CG and earlier chipselect modes the number of rows and columns
2978a40a695Sgavinm * is ambiguous. This is reflected in these tables by some bit being
2988a40a695Sgavinm * duplicated between row and column address. In practice we will follow
2998a40a695Sgavinm * the convention of always assigning the floating bit to the row address.
3008a40a695Sgavinm */
3018a40a695Sgavinm
3028a40a695Sgavinm /*
3038a40a695Sgavinm * Row/Column/Bank address mappings for rev CG in 64-bit mode, no interleave.
3048a40a695Sgavinm * See BKDG 3.29 3.5.6 Table 7.
3058a40a695Sgavinm */
3068a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_pre_d_64 = {
307*20c794b3Sgavinm MC_F_REVS_BC,
3088a40a695Sgavinm 64,
3098a40a695Sgavinm {
3108a40a695Sgavinm { /* 000 */
3118a40a695Sgavinm 2, { 11, 12 },
3128a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 13, 14, 15, 16, 17, 18 },
3138a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10 }
3148a40a695Sgavinm },
3158a40a695Sgavinm { /* 001 */
3168a40a695Sgavinm 2, { 13, 12 },
3178a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18 },
3188a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11 }
3198a40a695Sgavinm },
3208a40a695Sgavinm { /* 010 */
3218a40a695Sgavinm 2, { 13, 12 },
3228a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 },
3238a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 26 }
3248a40a695Sgavinm },
3258a40a695Sgavinm { /* 011 */
3268a40a695Sgavinm 2, { 13, 14 },
3278a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27 },
3288a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 27 }
3298a40a695Sgavinm },
3308a40a695Sgavinm { /* 100 */
3318a40a695Sgavinm 2, { 13, 14 },
3328a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 },
3338a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 28 }
3348a40a695Sgavinm },
3358a40a695Sgavinm { /* 101 */
3368a40a695Sgavinm 2, { 15, 14 },
3378a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 29, 16, 17, 18, 27, 28 },
3388a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 28 }
3398a40a695Sgavinm },
3408a40a695Sgavinm { /* 110 */
3418a40a695Sgavinm 2, { 15, 14 },
3428a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 29, 16, 17, 18, 27, 28 },
3438a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 30 }
3448a40a695Sgavinm },
3458a40a695Sgavinm /*
3468a40a695Sgavinm * remainder unused
3478a40a695Sgavinm */
3488a40a695Sgavinm }
3498a40a695Sgavinm
3508a40a695Sgavinm };
3518a40a695Sgavinm
3528a40a695Sgavinm /*
3538a40a695Sgavinm * Row/Column/Bank address mappings for rev CG in 128-bit mode, no interleave.
3548a40a695Sgavinm * See BKDG 3.29 3.5.6 Table 8.
3558a40a695Sgavinm */
3568a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_pre_d_128 = {
357*20c794b3Sgavinm MC_F_REVS_BC,
3588a40a695Sgavinm 128,
3598a40a695Sgavinm {
3608a40a695Sgavinm { /* 000 */
3618a40a695Sgavinm 2, { 12, 13 },
3628a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 19 },
3638a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11 }
3648a40a695Sgavinm },
3658a40a695Sgavinm { /* 001 */
3668a40a695Sgavinm 2, { 14, 13 },
3678a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19 },
3688a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12 }
3698a40a695Sgavinm },
3708a40a695Sgavinm { /* 010 */
3718a40a695Sgavinm 2, { 14, 13 },
3728a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 },
3738a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 27 }
3748a40a695Sgavinm },
3758a40a695Sgavinm { /* 011 */
3768a40a695Sgavinm 2, { 14, 15 },
3778a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28 },
3788a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 28 }
3798a40a695Sgavinm },
3808a40a695Sgavinm { /* 100 */
3818a40a695Sgavinm 2, { 14, 15 },
3828a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 },
3838a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 29 }
3848a40a695Sgavinm },
3858a40a695Sgavinm { /* 101 */
3868a40a695Sgavinm 2, { 16, 15 },
3878a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 30, 17, 18, 19, 28, 29 },
3888a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 29 }
3898a40a695Sgavinm },
3908a40a695Sgavinm { /* 110 */
3918a40a695Sgavinm 2, { 16, 15 },
3928a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 30, 17, 18, 19, 28, 29 },
3938a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 31 }
3948a40a695Sgavinm },
3958a40a695Sgavinm /*
3968a40a695Sgavinm * remainder unused
3978a40a695Sgavinm */
3988a40a695Sgavinm }
3998a40a695Sgavinm };
4008a40a695Sgavinm
4018a40a695Sgavinm /*
4028a40a695Sgavinm * Row/Column/Bank address mappings for rev D/E in 64-bit mode, no interleave.
4038a40a695Sgavinm * See BKDG 3.29 3.5.6 Table 9.
4048a40a695Sgavinm */
4058a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_d_e_64 = {
406*20c794b3Sgavinm MC_F_REVS_DE,
4078a40a695Sgavinm 64,
4088a40a695Sgavinm {
4098a40a695Sgavinm { /* 0000 */
4108a40a695Sgavinm 2, { 11, 12 },
4118a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 13, 14, 15, 16, 17, 18 },
4128a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10 }
4138a40a695Sgavinm },
4148a40a695Sgavinm { /* 0001 */
4158a40a695Sgavinm 2, { 12, 13 },
4168a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 },
4178a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11 }
4188a40a695Sgavinm },
4198a40a695Sgavinm { /* 0010 */
4208a40a695Sgavinm 2, { 12, 13 },
4218a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 26 },
4228a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11 }
4238a40a695Sgavinm },
4248a40a695Sgavinm { /* 0011 */
4258a40a695Sgavinm 2, { 13, 14 },
4268a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 },
4278a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
4288a40a695Sgavinm },
4298a40a695Sgavinm { /* 0100 */
4308a40a695Sgavinm 2, { 13, 14 },
4318a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 },
4328a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
4338a40a695Sgavinm },
4348a40a695Sgavinm { /* 0101 */
4358a40a695Sgavinm 2, { 13, 14 },
4368a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 27, 28 },
4378a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
4388a40a695Sgavinm },
4398a40a695Sgavinm { /* 0110 */
4408a40a695Sgavinm 2, { 14, 15 },
4418a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 },
4428a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 }
4438a40a695Sgavinm },
4448a40a695Sgavinm { /* 0111 */
4458a40a695Sgavinm 2, { 14, 15 },
4468a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 },
4478a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 }
4488a40a695Sgavinm },
4498a40a695Sgavinm { /* 1000 */
4508a40a695Sgavinm 2, { 14, 15 },
4518a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 28, 29 },
4528a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 }
4538a40a695Sgavinm },
4548a40a695Sgavinm { /* 1001 */
4558a40a695Sgavinm 2, { 15, 16 },
4568a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 29, 30 },
4578a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 14 }
4588a40a695Sgavinm },
4598a40a695Sgavinm { /* 1010 */
4608a40a695Sgavinm 2, { 15, 16 },
4618a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 29, 30 },
4628a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13, 14 }
4638a40a695Sgavinm },
4648a40a695Sgavinm /*
4658a40a695Sgavinm * remainder unused
4668a40a695Sgavinm */
4678a40a695Sgavinm }
4688a40a695Sgavinm };
4698a40a695Sgavinm
4708a40a695Sgavinm /*
4718a40a695Sgavinm * Row/Column/Bank address mappings for rev D/E in 128-bit mode, no interleave.
4728a40a695Sgavinm * See BKDG 3.29 3.5.6 Table 9.
4738a40a695Sgavinm */
4748a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_d_e_128 = {
475*20c794b3Sgavinm MC_F_REVS_DE,
4768a40a695Sgavinm 128,
4778a40a695Sgavinm {
4788a40a695Sgavinm { /* 0000 */
4798a40a695Sgavinm 2, { 12, 13 },
4808a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 14, 15, 16, 17, 18, 19 },
4818a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11 }
4828a40a695Sgavinm },
4838a40a695Sgavinm { /* 0001 */
4848a40a695Sgavinm 2, { 13, 14 },
4858a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 },
4868a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12 }
4878a40a695Sgavinm },
4888a40a695Sgavinm { /* 0010 */
4898a40a695Sgavinm 2, { 13, 14 },
4908a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 15, 16, 17, 18, 19, 27 },
4918a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12 }
4928a40a695Sgavinm },
4938a40a695Sgavinm { /* 0011 */
4948a40a695Sgavinm 2, { 14, 15 },
4958a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 },
4968a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }
4978a40a695Sgavinm },
4988a40a695Sgavinm { /* 0100 */
4998a40a695Sgavinm 2, { 14, 15 },
5008a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 },
5018a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }
5028a40a695Sgavinm },
5038a40a695Sgavinm { /* 0101 */
5048a40a695Sgavinm 2, { 14, 15 },
5058a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 16, 17, 18, 19, 28, 29 },
5068a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 }
5078a40a695Sgavinm },
5088a40a695Sgavinm { /* 0110 */
5098a40a695Sgavinm 2, { 15, 16 },
5108a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 },
5118a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 }
5128a40a695Sgavinm },
5138a40a695Sgavinm { /* 0111 */
5148a40a695Sgavinm 2, { 15, 16 },
5158a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 },
5168a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 }
5178a40a695Sgavinm },
5188a40a695Sgavinm { /* 1000 */
5198a40a695Sgavinm 2, { 15, 16 },
5208a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 28, 17, 18, 19, 29, 30 },
5218a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 }
5228a40a695Sgavinm },
5238a40a695Sgavinm { /* 1001 */
5248a40a695Sgavinm 2, { 16, 17 },
5258a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 18, 19, 30, 31 },
5268a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 15 }
5278a40a695Sgavinm },
5288a40a695Sgavinm { /* 1010 */
5298a40a695Sgavinm 2, { 16, 17 },
5308a40a695Sgavinm { 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 18, 19, 30, 31 },
5318a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14, 15 }
5328a40a695Sgavinm },
5338a40a695Sgavinm /*
5348a40a695Sgavinm * remainder unused
5358a40a695Sgavinm */
5368a40a695Sgavinm }
5378a40a695Sgavinm };
5388a40a695Sgavinm
5398a40a695Sgavinm /*
5408a40a695Sgavinm * Row/Column/Bank address mappings for revs F/G in 64-bit mode, no interleave.
5418a40a695Sgavinm */
5428a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_f_64 = {
543*20c794b3Sgavinm MC_F_REVS_FG,
5448a40a695Sgavinm 64,
5458a40a695Sgavinm {
5468a40a695Sgavinm { /* 0000 */
5478a40a695Sgavinm 2, { 12, 13 },
5488a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 14, 15, 16, 17 },
5498a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11 },
5508a40a695Sgavinm },
5518a40a695Sgavinm { /* 0001 */
5528a40a695Sgavinm 2, { 13, 14 },
5538a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 15, 16, 17 },
5548a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 },
5558a40a695Sgavinm },
5568a40a695Sgavinm { /* 0010 */
5578a40a695Sgavinm 2, { 13, 14 },
5588a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 15, 16, 17 },
5598a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 },
5608a40a695Sgavinm },
5618a40a695Sgavinm { /* 0011 */
5628a40a695Sgavinm 2, { 14, 15 },
5638a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 16, 17 },
5648a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
5658a40a695Sgavinm },
5668a40a695Sgavinm { /* 0100 */
5678a40a695Sgavinm 3, { 13, 14, 15 },
5688a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 16, 17 },
5698a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
5708a40a695Sgavinm },
5718a40a695Sgavinm { /* 0101 */
5728a40a695Sgavinm 3, { 13, 14, 15 },
5738a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 16, 17 },
5748a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
5758a40a695Sgavinm },
5768a40a695Sgavinm { /* 0110 */
5778a40a695Sgavinm 2, { 14, 15 },
5788a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 16, 17 },
5798a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
5808a40a695Sgavinm },
5818a40a695Sgavinm { /* 0111 */
5828a40a695Sgavinm 3, { 13, 14, 15 },
5838a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 16, 17 },
5848a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
5858a40a695Sgavinm },
5868a40a695Sgavinm { /* 1000 */
5878a40a695Sgavinm 3, { 14, 15, 16 },
5888a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 17 },
5898a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
5908a40a695Sgavinm },
5918a40a695Sgavinm { /* 1001 */
5928a40a695Sgavinm 3, { 14, 15, 16 },
5938a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 17 },
5948a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
5958a40a695Sgavinm },
5968a40a695Sgavinm { /* 1010 */
5978a40a695Sgavinm 3, { 13, 14, 15 },
5988a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
5998a40a695Sgavinm 16, 17 },
6008a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12 }
6018a40a695Sgavinm },
6028a40a695Sgavinm { /* 1011 */
6038a40a695Sgavinm 3, { 14, 15, 16 },
6048a40a695Sgavinm { 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
6058a40a695Sgavinm 17 },
6068a40a695Sgavinm { 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, MC_PC_ALL, 13 },
6078a40a695Sgavinm },
6088a40a695Sgavinm /*
6098a40a695Sgavinm * remainder unused
6108a40a695Sgavinm */
6118a40a695Sgavinm }
6128a40a695Sgavinm };
6138a40a695Sgavinm
6148a40a695Sgavinm /*
6158a40a695Sgavinm * Row/Column/Bank address mappings for revs F/G in 128-bit mode, no interleave.
6168a40a695Sgavinm */
6178a40a695Sgavinm static const struct _rcbmap_tbl dram_addrmap_f_128 = {
618*20c794b3Sgavinm MC_F_REVS_FG,
6198a40a695Sgavinm 128,
6208a40a695Sgavinm {
6218a40a695Sgavinm { /* 0000 */
6228a40a695Sgavinm 2, { 13, 14 },
6238a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 15, 16, 17, 18 },
6248a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12 },
6258a40a695Sgavinm },
6268a40a695Sgavinm { /* 0001 */
6278a40a695Sgavinm 2, { 14, 15 },
6288a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 16, 17, 18 },
6298a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
6308a40a695Sgavinm },
6318a40a695Sgavinm { /* 0010 */
6328a40a695Sgavinm 2, { 14, 15 },
6338a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 16, 17, 18 },
6348a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
6358a40a695Sgavinm },
6368a40a695Sgavinm { /* 0011 */
6378a40a695Sgavinm 2, { 15, 16 },
6388a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 17, 18 },
6398a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
6408a40a695Sgavinm },
6418a40a695Sgavinm { /* 0100 */
6428a40a695Sgavinm 3, { 14, 15, 16 },
6438a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 17, 18 },
6448a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
6458a40a695Sgavinm },
6468a40a695Sgavinm { /* 0101 */
6478a40a695Sgavinm 3, { 14, 15, 16 },
6488a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 17, 18 },
6498a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
6508a40a695Sgavinm },
6518a40a695Sgavinm { /* 0110 */
6528a40a695Sgavinm 2, { 15, 16 },
6538a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 17, 18 },
6548a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
6558a40a695Sgavinm },
6568a40a695Sgavinm { /* 0111 */
6578a40a695Sgavinm 3, { 14, 15, 16 },
6588a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
6598a40a695Sgavinm 17, 18 },
6608a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
6618a40a695Sgavinm },
6628a40a695Sgavinm { /* 1000 */
6638a40a695Sgavinm 3, { 15, 16, 17 },
6648a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
6658a40a695Sgavinm 18 },
6668a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
6678a40a695Sgavinm },
6688a40a695Sgavinm { /* 1001 */
6698a40a695Sgavinm 3, { 15, 16, 17 },
6708a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
6718a40a695Sgavinm 18 },
6728a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
6738a40a695Sgavinm },
6748a40a695Sgavinm { /* 1010 */
6758a40a695Sgavinm 3, { 14, 15, 16 },
6768a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,
6778a40a695Sgavinm 17, 18 },
6788a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13 },
6798a40a695Sgavinm },
6808a40a695Sgavinm { /* 1011 */
6818a40a695Sgavinm 3, { 15, 16, 17 },
6828a40a695Sgavinm { 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
6838a40a695Sgavinm 18 },
6848a40a695Sgavinm { 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, MC_PC_ALL, 14 },
6858a40a695Sgavinm },
6868a40a695Sgavinm /*
6878a40a695Sgavinm * remainder unused
6888a40a695Sgavinm */
6898a40a695Sgavinm }
6908a40a695Sgavinm };
6918a40a695Sgavinm
6928a40a695Sgavinm /*
6938a40a695Sgavinm * Bank swizzling is an option in revisions E and later. Each internal-bank-
6948a40a695Sgavinm * select address bit is xor'd with two row address bits. Which row
6958a40a695Sgavinm * address bits to use is not dependent on bank address mode but on
6968a40a695Sgavinm * revision and dram controller width alone.
6978a40a695Sgavinm *
6988a40a695Sgavinm * While rev E only supports 2 bank address bits, rev F supports 3 but not
6998a40a695Sgavinm * all chip-select bank address modes use all 3. These tables will list
7008a40a695Sgavinm * the row bits to use in swizzling for the maximum number of supported
7018a40a695Sgavinm * bank address bits - the consumer musr determine how many should be
7028a40a695Sgavinm * applied (listed in the above row/col/bank tables).
7038a40a695Sgavinm */
7048a40a695Sgavinm
7058a40a695Sgavinm static const struct _bnkswzl_tbl bnswzl_info_e_64 = {
706*20c794b3Sgavinm MC_F_REV_E,
7078a40a695Sgavinm 64,
7088a40a695Sgavinm {
7098a40a695Sgavinm {
7108a40a695Sgavinm { 17, 20 }, /* rows bits to swizzle with BA0 */
7118a40a695Sgavinm { 18, 21 }, /* rows bits to swizzle with BA1 */
7128a40a695Sgavinm /* only 2 bankaddr bits on rev E */
7138a40a695Sgavinm }
7148a40a695Sgavinm }
7158a40a695Sgavinm };
7168a40a695Sgavinm
7178a40a695Sgavinm static const struct _bnkswzl_tbl bnswzl_info_e_128 = {
718*20c794b3Sgavinm MC_F_REV_E,
7198a40a695Sgavinm 128,
7208a40a695Sgavinm {
7218a40a695Sgavinm {
7228a40a695Sgavinm { 18, 21 }, /* rows bits to swizzle with BA0 */
7238a40a695Sgavinm { 19, 22 }, /* rows bits to swizzle with BA1 */
7248a40a695Sgavinm /* only 2 bankaddr bits on rev E */
7258a40a695Sgavinm }
7268a40a695Sgavinm }
7278a40a695Sgavinm };
7288a40a695Sgavinm
7298a40a695Sgavinm static const struct _bnkswzl_tbl bnswzl_info_f_64 = {
730*20c794b3Sgavinm MC_F_REVS_FG,
7318a40a695Sgavinm 64,
7328a40a695Sgavinm {
7338a40a695Sgavinm {
7348a40a695Sgavinm { 17, 22 }, /* rows bits to swizzle with BA0 */
7358a40a695Sgavinm { 18, 23 }, /* rows bits to swizzle with BA1 */
7368a40a695Sgavinm { 19, 24 }, /* rows bits to swizzle with BA2 */
7378a40a695Sgavinm }
7388a40a695Sgavinm }
7398a40a695Sgavinm };
7408a40a695Sgavinm
7418a40a695Sgavinm static const struct _bnkswzl_tbl bnswzl_info_f_128 = {
742*20c794b3Sgavinm MC_F_REVS_FG,
7438a40a695Sgavinm 128,
7448a40a695Sgavinm {
7458a40a695Sgavinm {
7468a40a695Sgavinm { 18, 23 }, /* rows bits to swizzle with BA0 */
7478a40a695Sgavinm { 19, 24 }, /* rows bits to swizzle with BA1 */
7488a40a695Sgavinm { 20, 25 }, /* rows bits to swizzle with BA2 */
7498a40a695Sgavinm }
7508a40a695Sgavinm }
7518a40a695Sgavinm };
7528a40a695Sgavinm
7538a40a695Sgavinm /*
7547aec1d6eScindi * Yet another highbit function. This really needs to go to common source.
7557aec1d6eScindi * Returns range 0 to 64 inclusive;
7567aec1d6eScindi */
7577aec1d6eScindi static int
topbit(uint64_t i)7587aec1d6eScindi topbit(uint64_t i)
7597aec1d6eScindi {
7607aec1d6eScindi int h = 1;
7617aec1d6eScindi
7627aec1d6eScindi if (i == 0)
7637aec1d6eScindi return (0);
7647aec1d6eScindi
7657aec1d6eScindi if (i & 0xffffffff00000000ULL) {
7667aec1d6eScindi h += 32;
7677aec1d6eScindi i >>= 32;
7687aec1d6eScindi }
7697aec1d6eScindi
7707aec1d6eScindi if (i & 0xffff0000) {
7717aec1d6eScindi h += 16;
7727aec1d6eScindi i >>= 16;
7737aec1d6eScindi }
7747aec1d6eScindi
7757aec1d6eScindi if (i & 0xff00) {
7767aec1d6eScindi h += 8;
7777aec1d6eScindi i >>= 8;
7787aec1d6eScindi }
7797aec1d6eScindi
7807aec1d6eScindi if (i & 0xf0) {
7817aec1d6eScindi h += 4;
7827aec1d6eScindi i >>= 4;
7837aec1d6eScindi }
7847aec1d6eScindi
7857aec1d6eScindi if (i & 0xc) {
7867aec1d6eScindi h += 2;
7877aec1d6eScindi i >>= 2;
7887aec1d6eScindi }
7897aec1d6eScindi
7907aec1d6eScindi if (i & 0x2)
7917aec1d6eScindi h += 1;
7927aec1d6eScindi
7937aec1d6eScindi return (h);
7947aec1d6eScindi }
7957aec1d6eScindi
7968a40a695Sgavinm /*
7978a40a695Sgavinm * Lookup the Chip-Select Bank Address Mode Encoding table for a given
7988a40a695Sgavinm * chip revision and chip-select mode.
7998a40a695Sgavinm */
8008a40a695Sgavinm const struct rct_bnkaddrmode *
rct_bnkaddrmode(uint_t mcrev,uint_t csmode)8018a40a695Sgavinm rct_bnkaddrmode(uint_t mcrev, uint_t csmode)
8028a40a695Sgavinm {
8038a40a695Sgavinm int i;
8048a40a695Sgavinm const struct _bnkaddrmode_tbldesc *bdp = bnkaddr_tbls;
8058a40a695Sgavinm
8068a40a695Sgavinm for (i = 0; i < sizeof (bnkaddr_tbls) /
8078a40a695Sgavinm sizeof (struct _bnkaddrmode_tbldesc);
8088a40a695Sgavinm i++, bdp++) {
8098a40a695Sgavinm if (MC_REV_MATCH(mcrev, bdp->revmask) && csmode < bdp->nmodes)
8108a40a695Sgavinm return (&bdp->modetbl[csmode]);
8118a40a695Sgavinm
8128a40a695Sgavinm }
8138a40a695Sgavinm
8148a40a695Sgavinm return (NULL);
8158a40a695Sgavinm }
8168a40a695Sgavinm
8178a40a695Sgavinm /*
8188a40a695Sgavinm * Lookup the DRAM Address Mapping table for a given chip revision, access
8198a40a695Sgavinm * width, bank-swizzle and chip-select mode.
8208a40a695Sgavinm */
8218a40a695Sgavinm const struct rct_rcbmap *
rct_rcbmap(uint_t mcrev,int width,uint_t csmode)8228a40a695Sgavinm rct_rcbmap(uint_t mcrev, int width, uint_t csmode)
8238a40a695Sgavinm {
8248a40a695Sgavinm const struct _rcbmap_tbl *rcbm;
8258a40a695Sgavinm int i;
8268a40a695Sgavinm
8278a40a695Sgavinm for (i = 0; i < sizeof (rcbmap_tbls) /
8288a40a695Sgavinm sizeof (struct _rcbmap_tbldesc); i++) {
8298a40a695Sgavinm rcbm = rcbmap_tbls[i].rcbmap;
8308a40a695Sgavinm if (MC_REV_MATCH(mcrev, rcbm->mt_revmask) &&
8318a40a695Sgavinm rcbm->mt_width == width && csmode < rcbmap_tbls[i].nmodes)
8328a40a695Sgavinm return (&rcbm->mt_csmap[csmode]);
8338a40a695Sgavinm }
8348a40a695Sgavinm
8358a40a695Sgavinm return (NULL);
8368a40a695Sgavinm }
8378a40a695Sgavinm
8388a40a695Sgavinm /*
8398a40a695Sgavinm * Lookup the bank swizzling information for a given chip revision and
8408a40a695Sgavinm * access width.
8418a40a695Sgavinm */
8428a40a695Sgavinm const struct rct_bnkswzlinfo *
rct_bnkswzlinfo(uint_t mcrev,int width)8438a40a695Sgavinm rct_bnkswzlinfo(uint_t mcrev, int width)
8448a40a695Sgavinm {
8458a40a695Sgavinm int i;
8468a40a695Sgavinm const struct _bnkswzl_tbl *swztp;
8478a40a695Sgavinm
8488a40a695Sgavinm for (i = 0; i < sizeof (bnkswzl_tbls) /
8498a40a695Sgavinm sizeof (struct rcb_bnkswzl_tbl *); i++) {
8508a40a695Sgavinm swztp = bnkswzl_tbls[i];
8518a40a695Sgavinm if (MC_REV_MATCH(mcrev, swztp->swzt_revmask) &&
8528a40a695Sgavinm swztp->swzt_width == width)
8538a40a695Sgavinm return (&swztp->swzt_bits);
8548a40a695Sgavinm }
8558a40a695Sgavinm
8568a40a695Sgavinm return (NULL);
8578a40a695Sgavinm }
8588a40a695Sgavinm
8597aec1d6eScindi void
rct_csintlv_bits(uint_t mcrev,int width,uint_t csmode,int factor,struct rct_csintlv * csid)8607aec1d6eScindi rct_csintlv_bits(uint_t mcrev, int width, uint_t csmode, int factor,
8618a40a695Sgavinm struct rct_csintlv *csid)
8627aec1d6eScindi {
8637aec1d6eScindi int i, lstbnkbit;
8647aec1d6eScindi size_t csz;
8658a40a695Sgavinm const struct rct_bnkaddrmode *bam;
8668a40a695Sgavinm const struct rct_rcbmap *rcm;
8677aec1d6eScindi
8687aec1d6eScindi /*
8695f25dc2aSgavinm * 8-way cs interleave for some large cs sizes in 128-bit mode is
8708a40a695Sgavinm * not implemented prior to rev F.
8717aec1d6eScindi */
8725f25dc2aSgavinm if (factor == 8 && width == 128 &&
873*20c794b3Sgavinm ((MC_REV_MATCH(mcrev, MC_F_REVS_BC) && csmode == 0x6) ||
874*20c794b3Sgavinm (MC_REV_MATCH(mcrev, MC_F_REVS_DE) &&
8758a40a695Sgavinm (csmode == 0x9 || csmode == 0xa)))) {
8767aec1d6eScindi csid->csi_factor = 0;
8777aec1d6eScindi return;
8787aec1d6eScindi }
8797aec1d6eScindi
8808a40a695Sgavinm if ((bam = rct_bnkaddrmode(mcrev, csmode)) == NULL ||
8817aec1d6eScindi (rcm = rct_rcbmap(mcrev, width, csmode)) == NULL) {
8827aec1d6eScindi csid->csi_factor = 0;
8837aec1d6eScindi return;
8847aec1d6eScindi }
8857aec1d6eScindi
8867aec1d6eScindi csz = MC_CS_SIZE(bam, width);
8877aec1d6eScindi
8887aec1d6eScindi switch (factor) {
8897aec1d6eScindi case 2:
8907aec1d6eScindi csid->csi_nbits = 1;
8917aec1d6eScindi break;
8927aec1d6eScindi case 4:
8937aec1d6eScindi csid->csi_nbits = 2;
8947aec1d6eScindi break;
8957aec1d6eScindi case 8:
8967aec1d6eScindi csid->csi_nbits = 3;
8977aec1d6eScindi break;
8987aec1d6eScindi default:
8997aec1d6eScindi csid->csi_factor = 0;
9007aec1d6eScindi return;
9017aec1d6eScindi }
9027aec1d6eScindi
9037aec1d6eScindi csid->csi_hibit = topbit(csz) - 1;
9047aec1d6eScindi
9058a40a695Sgavinm /*
9068a40a695Sgavinm * The first row bit is immediately after the last bank bit.
9078a40a695Sgavinm */
9087aec1d6eScindi lstbnkbit = 0;
9098a40a695Sgavinm for (i = 0; i < rcm->rcb_nbankbits; i++)
9108a40a695Sgavinm if (rcm->rcb_bankbit[i] > lstbnkbit)
9118a40a695Sgavinm lstbnkbit = rcm->rcb_bankbit[i];
9127aec1d6eScindi
9137aec1d6eScindi csid->csi_lobit = lstbnkbit + 1;
9147aec1d6eScindi
9157aec1d6eScindi csid->csi_factor = factor;
9167aec1d6eScindi }
917