1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2017 Joyent, Inc. 25 */ 26 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* Copyright (c) 1988 AT&T */ 33 /* All Rights Reserved */ 34 35 #include "dis_tables.h" 36 37 /* BEGIN CSTYLED */ 38 39 /* 40 * Disassembly begins in dis_distable, which is equivalent to the One-byte 41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 42 * decoding loops then traverse out through the other tables as necessary to 43 * decode a given instruction. 44 * 45 * The behavior of this file can be controlled by one of the following flags: 46 * 47 * DIS_TEXT Include text for disassembly 48 * DIS_MEM Include memory-size calculations 49 * 50 * Either or both of these can be defined. 51 * 52 * This file is not, and will never be, cstyled. If anything, the tables should 53 * be taken out another tab stop or two so nothing overlaps. 54 */ 55 56 /* 57 * These functions must be provided for the consumer to do disassembly. 58 */ 59 #ifdef DIS_TEXT 60 extern char *strncpy(char *, const char *, size_t); 61 extern size_t strlen(const char *); 62 extern int strcmp(const char *, const char *); 63 extern int strncmp(const char *, const char *, size_t); 64 extern size_t strlcat(char *, const char *, size_t); 65 #endif 66 67 68 #define TERM 0 /* used to indicate that the 'indirect' */ 69 /* field terminates - no pointer. */ 70 71 /* Used to decode instructions. */ 72 typedef struct instable { 73 struct instable *it_indirect; /* for decode op codes */ 74 uchar_t it_adrmode; 75 #ifdef DIS_TEXT 76 char it_name[NCPS]; 77 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 78 #endif 79 #ifdef DIS_MEM 80 uint_t it_size:16; 81 #endif 82 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 83 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 84 uint_t it_invalid32:1; /* invalid in IA32 */ 85 uint_t it_stackop:1; /* push/pop stack operation */ 86 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ 87 uint_t it_avxsuf:2; /* AVX2/AVX512 suffix rqd. */ 88 uint_t it_vexopmask:1; /* VEX inst. that use opmask */ 89 } instable_t; 90 91 /* 92 * Instruction formats. 93 */ 94 enum { 95 UNKNOWN, 96 MRw, 97 IMlw, 98 IMw, 99 IR, 100 OA, 101 AO, 102 MS, 103 SM, 104 Mv, 105 Mw, 106 M, /* register or memory */ 107 MG9, /* register or memory in group 9 (prefix optional) */ 108 Mb, /* register or memory, always byte sized */ 109 MO, /* memory only (no registers) */ 110 PREF, 111 SWAPGS_RDTSCP, 112 MONITOR_MWAIT, 113 R, 114 RA, 115 SEG, 116 MR, 117 RM, 118 RM_66r, /* RM, but with a required 0x66 prefix */ 119 IA, 120 MA, 121 SD, 122 AD, 123 SA, 124 D, 125 INM, 126 SO, 127 BD, 128 I, 129 P, 130 V, 131 DSHIFT, /* for double shift that has an 8-bit immediate */ 132 U, 133 OVERRIDE, 134 NORM, /* instructions w/o ModR/M byte, no memory access */ 135 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 136 O, /* for call */ 137 JTAB, /* jump table */ 138 IMUL, /* for 186 iimul instr */ 139 CBW, /* so data16 can be evaluated for cbw and variants */ 140 MvI, /* for 186 logicals */ 141 ENTER, /* for 186 enter instr */ 142 RMw, /* for 286 arpl instr */ 143 Ib, /* for push immediate byte */ 144 F, /* for 287 instructions */ 145 FF, /* for 287 instructions */ 146 FFC, /* for 287 instructions */ 147 DM, /* 16-bit data */ 148 AM, /* 16-bit addr */ 149 LSEG, /* for 3-bit seg reg encoding */ 150 MIb, /* for 386 logicals */ 151 SREG, /* for 386 special registers */ 152 PREFIX, /* a REP instruction prefix */ 153 LOCK, /* a LOCK instruction prefix */ 154 INT3, /* The int 3 instruction, which has a fake operand */ 155 INTx, /* The normal int instruction, with explicit int num */ 156 DSHIFTcl, /* for double shift that implicitly uses %cl */ 157 CWD, /* so data16 can be evaluated for cwd and variants */ 158 RET, /* single immediate 16-bit operand */ 159 MOVZ, /* for movs and movz, with different size operands */ 160 CRC32, /* for crc32, with different size operands */ 161 XADDB, /* for xaddb */ 162 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 163 MOVBE, /* movbe instruction */ 164 165 /* 166 * MMX/SIMD addressing modes. 167 */ 168 169 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 170 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 171 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 172 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 173 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 174 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 175 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 176 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 177 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 178 MMOSH, /* Prefixable MMX mm,imm8 */ 179 MM, /* MMX/SIMD-Int mm/mem -> mm */ 180 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 181 MMSH, /* MMX mm,imm8 */ 182 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 183 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 184 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 185 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 186 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 187 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 188 XMMOM, /* Prefixable SIMD xmm -> mem */ 189 XMMOMS, /* Prefixable SIMD mem -> xmm */ 190 XMM, /* SIMD xmm/mem -> xmm */ 191 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 192 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 193 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 194 XMM3P, /* SIMD xmm -> r32,imm8 */ 195 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 196 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 197 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 198 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 199 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 200 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 201 XMMS, /* SIMD xmm -> xmm/mem */ 202 XMMM, /* SIMD mem -> xmm */ 203 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 204 XMMMS, /* SIMD xmm -> mem */ 205 XMM3MX, /* SIMD r32/mem -> xmm */ 206 XMM3MXS, /* SIMD xmm -> r32/mem */ 207 XMMSH, /* SIMD xmm,imm8 */ 208 XMMXM3, /* SIMD xmm/mem -> r32 */ 209 XMMX3, /* SIMD xmm -> r32 */ 210 XMMXMM, /* SIMD xmm/mem -> mm */ 211 XMMMX, /* SIMD mm -> xmm */ 212 XMMXM, /* SIMD xmm -> mm */ 213 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 214 XMM2I, /* SIMD xmm, imm, imm */ 215 XMMFENCE, /* SIMD lfence or mfence */ 216 XMMSFNC, /* SIMD sfence (none or mem) */ 217 XGETBV_XSETBV, 218 VEX_NONE, /* VEX no operand */ 219 VEX_MO, /* VEX mod_rm -> implicit reg */ 220 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 221 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */ 222 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 223 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 224 VEX_MX, /* VEX mod_rm -> mod_reg */ 225 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 226 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 227 VEX_MR, /* VEX mod_rm -> mod_reg */ 228 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 229 VEX_RX, /* VEX mod_reg -> mod_rm */ 230 VEX_KRR, /* VEX mod_rm -> mod_reg */ 231 VEX_KMR, /* VEX mod_reg -> mod_rm */ 232 VEX_KRM, /* VEX mod_rm -> mod_reg */ 233 VEX_RR, /* VEX mod_rm -> mod_reg */ 234 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 235 VEX_RM, /* VEX mod_reg -> mod_rm */ 236 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */ 237 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 238 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 239 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */ 240 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 241 VMxo, /* VMx instruction with optional prefix */ 242 SVM, /* AMD SVM instructions */ 243 BLS, /* BLSR, BLSMSK, BLSI */ 244 FMA, /* FMA instructions, all VEX_RMrX */ 245 ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */ 246 EVEX_RX, /* EVEX mod_reg -> mod_rm */ 247 EVEX_MX, /* EVEX mod_rm -> mod_reg */ 248 EVEX_RMrX /* EVEX EVEX.vvvv, mod_rm -> mod_reg */ 249 }; 250 251 /* 252 * VEX prefixes 253 */ 254 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 255 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 256 257 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 258 259 /* 260 ** Register numbers for the i386 261 */ 262 #define EAX_REGNO 0 263 #define ECX_REGNO 1 264 #define EDX_REGNO 2 265 #define EBX_REGNO 3 266 #define ESP_REGNO 4 267 #define EBP_REGNO 5 268 #define ESI_REGNO 6 269 #define EDI_REGNO 7 270 271 /* 272 * modes for immediate values 273 */ 274 #define MODE_NONE 0 275 #define MODE_IPREL 1 /* signed IP relative value */ 276 #define MODE_SIGNED 2 /* sign extended immediate */ 277 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 278 #define MODE_OFFSET 4 /* offset part of an address */ 279 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 280 281 /* 282 * The letters used in these macros are: 283 * IND - indirect to another to another table 284 * "T" - means to Terminate indirections (this is the final opcode) 285 * "S" - means "operand length suffix required" 286 * "Sa" - means AVX2 suffix (q/d) required 287 * "Sq" - means AVX512 suffix (q/d) required 288 * "Sd" - means AVX512 suffix (d/s) required 289 * "NS" - means "no suffix" which is the operand length suffix of the opcode 290 * "Z" - means instruction size arg required 291 * "u" - means the opcode is invalid in IA32 but valid in amd64 292 * "x" - means the opcode is invalid in amd64, but not IA32 293 * "y" - means the operand size is always 64 bits in 64 bit mode 294 * "p" - means push/pop stack operation 295 * "vr" - means VEX instruction that operates on normal registers, not fpu 296 * "vo" - means VEX instruction that operates on opmask registers, not fpu 297 */ 298 299 #define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling */ 300 #define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix handling */ 301 #define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix handling */ 302 303 #if defined(DIS_TEXT) && defined(DIS_MEM) 304 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 305 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 306 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 307 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 308 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 309 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 310 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 311 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 312 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 313 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} 314 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} 315 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 316 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 317 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 318 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 319 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 320 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2} 321 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q} 322 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D} 323 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 324 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 325 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 326 #elif defined(DIS_TEXT) 327 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 328 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 329 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 330 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 331 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 332 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 333 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 334 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 335 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 336 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1} 337 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1} 338 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 339 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 340 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 341 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 342 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 343 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2} 344 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q} 345 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5D} 346 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 347 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 348 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 349 #elif defined(DIS_MEM) 350 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 351 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 352 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 353 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 354 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 355 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 356 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 357 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 358 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 359 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1} 360 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1} 361 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 362 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 363 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 364 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 365 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 366 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2} 367 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q} 368 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5D} 369 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 370 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 371 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 372 #else 373 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 374 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 375 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 376 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 377 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 378 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 379 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 380 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 381 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 382 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1} 383 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1} 384 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 385 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 386 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 387 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 388 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 389 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2} 390 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q} 391 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D} 392 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 393 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 394 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 395 #endif 396 397 #ifdef DIS_TEXT 398 /* 399 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 400 */ 401 const char *const dis_addr16[3][8] = { 402 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 403 "(%bx)", 404 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 405 "(%bx)", 406 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 407 "(%bx)", 408 }; 409 410 411 /* 412 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 413 */ 414 const char *const dis_addr32_mode0[16] = { 415 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 416 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 417 }; 418 419 const char *const dis_addr32_mode12[16] = { 420 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 421 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 422 }; 423 424 /* 425 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 426 */ 427 const char *const dis_addr64_mode0[16] = { 428 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 429 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 430 }; 431 const char *const dis_addr64_mode12[16] = { 432 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 433 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 434 }; 435 436 /* 437 * decode for scale from SIB byte 438 */ 439 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 440 441 /* 442 * decode for scale from VSIB byte, note that we always include the scale factor 443 * to match gas. 444 */ 445 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" }; 446 447 /* 448 * register decoding for normal references to registers (ie. not addressing) 449 */ 450 const char *const dis_REG8[16] = { 451 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 452 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 453 }; 454 455 const char *const dis_REG8_REX[16] = { 456 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 457 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 458 }; 459 460 const char *const dis_REG16[16] = { 461 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 462 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 463 }; 464 465 const char *const dis_REG32[16] = { 466 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 467 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 468 }; 469 470 const char *const dis_REG64[16] = { 471 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 472 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 473 }; 474 475 const char *const dis_DEBUGREG[16] = { 476 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 477 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 478 }; 479 480 const char *const dis_CONTROLREG[16] = { 481 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 482 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 483 }; 484 485 const char *const dis_TESTREG[16] = { 486 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 487 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 488 }; 489 490 const char *const dis_MMREG[16] = { 491 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 492 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 493 }; 494 495 const char *const dis_XMMREG[32] = { 496 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 497 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 498 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 499 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 500 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 501 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 502 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 503 "%xmm28", "%xmm29", "%xmm30", "%xmm31", 504 }; 505 506 const char *const dis_YMMREG[32] = { 507 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 508 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 509 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 510 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 511 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 512 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 513 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 514 "%ymm28", "%ymm29", "%ymm30", "%ymm31", 515 }; 516 517 const char *const dis_ZMMREG[32] = { 518 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 519 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 520 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 521 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 522 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 523 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 524 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 525 "%zmm28", "%zmm29", "%zmm30", "%zmm31", 526 }; 527 528 const char *const dis_KOPMASKREG[8] = { 529 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 530 }; 531 532 const char *const dis_SEGREG[16] = { 533 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 534 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 535 }; 536 537 /* 538 * SIMD predicate suffixes 539 */ 540 const char *const dis_PREDSUFFIX[8] = { 541 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 542 }; 543 544 const char *const dis_AVXvgrp7[3][8] = { 545 /*0 1 2 3 4 5 6 7*/ 546 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 547 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 548 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 549 }; 550 551 #endif /* DIS_TEXT */ 552 553 /* 554 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 555 */ 556 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 557 558 /* 559 * "decode table" for pause and clflush instructions 560 */ 561 const instable_t dis_opPause = TNS("pause", NORM); 562 563 /* 564 * Decode table for 0x0F00 opcodes 565 */ 566 const instable_t dis_op0F00[8] = { 567 568 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 569 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 570 }; 571 572 573 /* 574 * Decode table for 0x0F01 opcodes 575 */ 576 const instable_t dis_op0F01[8] = { 577 578 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 579 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 580 }; 581 582 /* 583 * Decode table for 0x0F18 opcodes -- SIMD prefetch 584 */ 585 const instable_t dis_op0F18[8] = { 586 587 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 588 /* [4] */ INVALID, INVALID, INVALID, INVALID, 589 }; 590 591 /* 592 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 593 */ 594 const instable_t dis_op0FAE[8] = { 595 /* [0] */ TNSZ("fxsave",M,512), TNSZ("fxrstor",M,512), TNS("ldmxcsr",M), TNS("stmxcsr",M), 596 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 597 }; 598 599 /* 600 * Decode table for 0x0FBA opcodes 601 */ 602 603 const instable_t dis_op0FBA[8] = { 604 605 /* [0] */ INVALID, INVALID, INVALID, INVALID, 606 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 607 }; 608 609 /* 610 * Decode table for 0x0FC7 opcode (group 9) 611 */ 612 613 const instable_t dis_op0FC7[8] = { 614 615 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9), 616 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9), 617 }; 618 619 /* 620 * Decode table for 0x0FC7 opcode (group 9) mode 3 621 */ 622 623 const instable_t dis_op0FC7m3[8] = { 624 625 /* [0] */ INVALID, INVALID, INVALID, INVALID, 626 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9), 627 }; 628 629 /* 630 * Decode table for 0x0FC7 opcode with 0x66 prefix 631 */ 632 633 const instable_t dis_op660FC7[8] = { 634 635 /* [0] */ INVALID, INVALID, INVALID, INVALID, 636 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 637 }; 638 639 /* 640 * Decode table for 0x0FC7 opcode with 0xF3 prefix 641 */ 642 643 const instable_t dis_opF30FC7[8] = { 644 645 /* [0] */ INVALID, INVALID, INVALID, INVALID, 646 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 647 }; 648 649 /* 650 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 651 * 652 *bit pattern: 0000 1111 1100 1reg 653 */ 654 const instable_t dis_op0FC8[4] = { 655 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 656 }; 657 658 /* 659 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 660 */ 661 const instable_t dis_op0F7123[4][8] = { 662 { 663 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 664 /* .4 */ INVALID, INVALID, INVALID, INVALID, 665 }, { 666 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 667 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 668 }, { 669 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 670 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 671 }, { 672 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 673 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 674 } }; 675 676 /* 677 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 678 */ 679 const instable_t dis_opSIMD7123[32] = { 680 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 681 /* .4 */ INVALID, INVALID, INVALID, INVALID, 682 683 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 684 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 685 686 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 687 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 688 689 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 690 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 691 }; 692 693 /* 694 * SIMD instructions have been wedged into the existing IA32 instruction 695 * set through the use of prefixes. That is, while 0xf0 0x58 may be 696 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 697 * instruction - addss. At present, three prefixes have been coopted in 698 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 699 * following tables are used to provide the prefixed instruction names. 700 * The arrays are sparse, but they're fast. 701 */ 702 703 /* 704 * Decode table for SIMD instructions with the address size (0x66) prefix. 705 */ 706 const instable_t dis_opSIMDdata16[256] = { 707 /* [00] */ INVALID, INVALID, INVALID, INVALID, 708 /* [04] */ INVALID, INVALID, INVALID, INVALID, 709 /* [08] */ INVALID, INVALID, INVALID, INVALID, 710 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 711 712 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 713 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 714 /* [18] */ INVALID, INVALID, INVALID, INVALID, 715 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 716 717 /* [20] */ INVALID, INVALID, INVALID, INVALID, 718 /* [24] */ INVALID, INVALID, INVALID, INVALID, 719 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 720 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 721 722 /* [30] */ INVALID, INVALID, INVALID, INVALID, 723 /* [34] */ INVALID, INVALID, INVALID, INVALID, 724 /* [38] */ INVALID, INVALID, INVALID, INVALID, 725 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 726 727 /* [40] */ INVALID, INVALID, INVALID, INVALID, 728 /* [44] */ INVALID, INVALID, INVALID, INVALID, 729 /* [48] */ INVALID, INVALID, INVALID, INVALID, 730 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 731 732 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 733 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 734 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 735 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 736 737 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 738 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 739 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 740 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 741 742 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 743 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 744 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 745 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 746 747 /* [80] */ INVALID, INVALID, INVALID, INVALID, 748 /* [84] */ INVALID, INVALID, INVALID, INVALID, 749 /* [88] */ INVALID, INVALID, INVALID, INVALID, 750 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 751 752 /* [90] */ INVALID, INVALID, INVALID, INVALID, 753 /* [94] */ INVALID, INVALID, INVALID, INVALID, 754 /* [98] */ INVALID, INVALID, INVALID, INVALID, 755 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 756 757 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 758 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 759 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 760 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 761 762 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 763 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 764 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 765 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 766 767 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 768 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 769 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 770 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 771 772 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 773 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 774 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 775 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 776 777 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 778 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 779 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 780 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 781 782 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 783 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 784 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 785 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 786 }; 787 788 const instable_t dis_opAVX660F[256] = { 789 /* [00] */ INVALID, INVALID, INVALID, INVALID, 790 /* [04] */ INVALID, INVALID, INVALID, INVALID, 791 /* [08] */ INVALID, INVALID, INVALID, INVALID, 792 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 793 794 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 795 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 796 /* [18] */ INVALID, INVALID, INVALID, INVALID, 797 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 798 799 /* [20] */ INVALID, INVALID, INVALID, INVALID, 800 /* [24] */ INVALID, INVALID, INVALID, INVALID, 801 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 802 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 803 804 /* [30] */ INVALID, INVALID, INVALID, INVALID, 805 /* [34] */ INVALID, INVALID, INVALID, INVALID, 806 /* [38] */ INVALID, INVALID, INVALID, INVALID, 807 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 808 809 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 810 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 811 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 812 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 813 814 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 815 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 816 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 817 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 818 819 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 820 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 821 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 822 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 823 824 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 825 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 826 /* [78] */ INVALID, INVALID, INVALID, INVALID, 827 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 828 829 /* [80] */ INVALID, INVALID, INVALID, INVALID, 830 /* [84] */ INVALID, INVALID, INVALID, INVALID, 831 /* [88] */ INVALID, INVALID, INVALID, INVALID, 832 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 833 834 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 835 /* [94] */ INVALID, INVALID, INVALID, INVALID, 836 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 837 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 838 839 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 840 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 841 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 842 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 843 844 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 845 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 846 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 847 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 848 849 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 850 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 851 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 852 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 853 854 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 855 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 856 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 857 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 858 859 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 860 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 861 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 862 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 863 864 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 865 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 866 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 867 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 868 }; 869 870 /* 871 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 872 */ 873 const instable_t dis_opSIMDrepnz[256] = { 874 /* [00] */ INVALID, INVALID, INVALID, INVALID, 875 /* [04] */ INVALID, INVALID, INVALID, INVALID, 876 /* [08] */ INVALID, INVALID, INVALID, INVALID, 877 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 878 879 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID, 880 /* [14] */ INVALID, INVALID, INVALID, INVALID, 881 /* [18] */ INVALID, INVALID, INVALID, INVALID, 882 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 883 884 /* [20] */ INVALID, INVALID, INVALID, INVALID, 885 /* [24] */ INVALID, INVALID, INVALID, INVALID, 886 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 887 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 888 889 /* [30] */ INVALID, INVALID, INVALID, INVALID, 890 /* [34] */ INVALID, INVALID, INVALID, INVALID, 891 /* [38] */ INVALID, INVALID, INVALID, INVALID, 892 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 893 894 /* [40] */ INVALID, INVALID, INVALID, INVALID, 895 /* [44] */ INVALID, INVALID, INVALID, INVALID, 896 /* [48] */ INVALID, INVALID, INVALID, INVALID, 897 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 898 899 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 900 /* [54] */ INVALID, INVALID, INVALID, INVALID, 901 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 902 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 903 904 /* [60] */ INVALID, INVALID, INVALID, INVALID, 905 /* [64] */ INVALID, INVALID, INVALID, INVALID, 906 /* [68] */ INVALID, INVALID, INVALID, INVALID, 907 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 908 909 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 910 /* [74] */ INVALID, INVALID, INVALID, INVALID, 911 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 912 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID, 913 914 /* [80] */ INVALID, INVALID, INVALID, INVALID, 915 /* [84] */ INVALID, INVALID, INVALID, INVALID, 916 /* [88] */ INVALID, INVALID, INVALID, INVALID, 917 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 918 919 /* [90] */ INVALID, INVALID, INVALID, INVALID, 920 /* [94] */ INVALID, INVALID, INVALID, INVALID, 921 /* [98] */ INVALID, INVALID, INVALID, INVALID, 922 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 923 924 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 925 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 926 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 927 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 928 929 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 930 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 931 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 932 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 933 934 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 935 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 936 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 937 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 938 939 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID, 940 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 941 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 942 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 943 944 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 945 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 946 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 947 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 948 949 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID, 950 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 951 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 952 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 953 }; 954 955 const instable_t dis_opAVXF20F[256] = { 956 /* [00] */ INVALID, INVALID, INVALID, INVALID, 957 /* [04] */ INVALID, INVALID, INVALID, INVALID, 958 /* [08] */ INVALID, INVALID, INVALID, INVALID, 959 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 960 961 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 962 /* [14] */ INVALID, INVALID, INVALID, INVALID, 963 /* [18] */ INVALID, INVALID, INVALID, INVALID, 964 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 965 966 /* [20] */ INVALID, INVALID, INVALID, INVALID, 967 /* [24] */ INVALID, INVALID, INVALID, INVALID, 968 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 969 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 970 971 /* [30] */ INVALID, INVALID, INVALID, INVALID, 972 /* [34] */ INVALID, INVALID, INVALID, INVALID, 973 /* [38] */ INVALID, INVALID, INVALID, INVALID, 974 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 975 976 /* [40] */ INVALID, INVALID, INVALID, INVALID, 977 /* [44] */ INVALID, INVALID, INVALID, INVALID, 978 /* [48] */ INVALID, INVALID, INVALID, INVALID, 979 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 980 981 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 982 /* [54] */ INVALID, INVALID, INVALID, INVALID, 983 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 984 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 985 986 /* [60] */ INVALID, INVALID, INVALID, INVALID, 987 /* [64] */ INVALID, INVALID, INVALID, INVALID, 988 /* [68] */ INVALID, INVALID, INVALID, INVALID, 989 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 990 991 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 992 /* [74] */ INVALID, INVALID, INVALID, INVALID, 993 /* [78] */ INVALID, INVALID, INVALID, INVALID, 994 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 995 996 /* [80] */ INVALID, INVALID, INVALID, INVALID, 997 /* [84] */ INVALID, INVALID, INVALID, INVALID, 998 /* [88] */ INVALID, INVALID, INVALID, INVALID, 999 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1000 1001 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 1002 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1003 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1004 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1005 1006 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1008 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1009 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1010 1011 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1012 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1013 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1014 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1015 1016 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 1017 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1018 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1019 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1020 1021 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 1022 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1023 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1024 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1025 1026 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 1028 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1029 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1030 1031 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 1032 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1033 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1034 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1035 }; 1036 1037 const instable_t dis_opAVXF20F3A[256] = { 1038 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1039 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1040 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1041 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1042 1043 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1044 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1045 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1046 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1047 1048 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1049 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1050 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1051 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1052 1053 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1054 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1055 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1056 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1057 1058 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1059 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1060 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1061 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1062 1063 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1064 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1065 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1066 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1067 1068 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1069 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1070 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1071 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1072 1073 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1074 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1075 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1076 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1077 1078 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1079 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1080 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1081 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1082 1083 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1085 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1086 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1087 1088 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1090 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1091 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1092 1093 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1095 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1096 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1097 1098 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1100 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1101 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1102 1103 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1105 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1106 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1107 1108 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1110 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1111 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1112 1113 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID, 1114 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1115 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1116 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1117 }; 1118 1119 const instable_t dis_opAVXF20F38[256] = { 1120 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1121 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1122 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1123 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1124 1125 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1126 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1127 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1128 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1129 1130 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1131 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1132 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1133 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1134 1135 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1136 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1137 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1138 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1139 1140 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1141 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1142 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1143 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1144 1145 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1146 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1147 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1148 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1149 1150 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1151 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1152 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1153 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1154 1155 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1156 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1157 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1158 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1159 1160 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1161 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1162 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1163 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1164 1165 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1166 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1167 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1168 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1169 1170 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1171 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1172 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1173 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1174 1175 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1176 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1177 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1178 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1179 1180 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1181 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1182 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1183 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1184 1185 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1186 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1187 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1188 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1189 1190 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1191 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1192 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1193 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1194 1195 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1196 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5), 1197 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1198 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1199 }; 1200 1201 const instable_t dis_opAVXF30F38[256] = { 1202 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1203 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1204 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1206 1207 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1208 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1209 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1210 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1211 1212 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1213 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1214 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1215 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1216 1217 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1218 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1219 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1220 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1221 1222 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1223 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1224 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1225 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1226 1227 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1228 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1229 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1230 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1231 1232 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1233 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1234 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1235 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1236 1237 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1238 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1239 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1240 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1241 1242 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1243 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1244 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1245 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1246 1247 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1248 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1250 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1251 1252 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1253 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1254 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1255 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1256 1257 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1258 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1260 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1261 1262 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1263 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1265 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1266 1267 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1268 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1270 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1271 1272 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1273 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1275 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1276 1277 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1278 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5), 1279 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1280 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1281 }; 1282 /* 1283 * Decode table for SIMD instructions with the repz (0xf3) prefix. 1284 */ 1285 const instable_t dis_opSIMDrepz[256] = { 1286 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1287 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1288 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1290 1291 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID, 1292 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID, 1293 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1294 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1295 1296 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1297 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1298 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 1299 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 1300 1301 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1302 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1303 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1304 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1305 1306 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1307 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1308 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1309 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1310 1311 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 1312 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1313 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 1314 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 1315 1316 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1317 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1318 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1319 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 1320 1321 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1322 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1323 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1324 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1325 1326 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1327 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1328 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1329 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1330 1331 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1332 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1333 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1334 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1335 1336 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1337 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1338 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1339 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1340 1341 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1342 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1343 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1344 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID, 1345 1346 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1347 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1348 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1349 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1350 1351 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1352 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1353 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1354 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1355 1356 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1357 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1358 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1359 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1360 1361 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1362 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1363 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1364 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1365 }; 1366 1367 const instable_t dis_opAVXF30F[256] = { 1368 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1369 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1370 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1372 1373 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1374 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1375 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1376 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1377 1378 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1379 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1380 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1381 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1382 1383 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1384 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1385 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1386 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1387 1388 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1389 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1390 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1391 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1392 1393 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1394 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1395 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1396 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1397 1398 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1399 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1400 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1401 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1402 1403 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1404 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1405 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1406 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1407 1408 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1409 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1410 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1411 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1412 1413 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1414 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1415 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1416 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1417 1418 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1419 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1420 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1421 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1422 1423 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1424 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1425 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1426 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1427 1428 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1429 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1430 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1431 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1432 1433 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1434 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1435 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1436 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1437 1438 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1439 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1440 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1441 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1442 1443 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1444 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1445 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1446 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1447 }; 1448 1449 /* 1450 * Table for instructions with an EVEX prefix. 1451 */ 1452 const instable_t dis_opAVX62[256] = { 1453 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1454 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1455 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1456 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1457 1458 /* [10] */ TSd("vmovup",EVEX_MX), TSd("vmovup",EVEX_RX), INVALID, INVALID, 1459 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1460 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1461 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1462 1463 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1464 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1465 /* [28] */ TSd("vmovap",EVEX_MX), TSd("vmovap",EVEX_RX), INVALID, INVALID, 1466 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1467 1468 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1469 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1470 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1471 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1472 1473 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1474 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1475 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1476 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1477 1478 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1479 /* [54] */ TSd("vandp",EVEX_RMrX), TSd("vandnp",EVEX_RMrX), TSd("vorp",EVEX_RMrX), TSd("vxorp",EVEX_RMrX), 1480 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1481 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1482 1483 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1484 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1485 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1486 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_MX), 1487 1488 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1489 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1490 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1491 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_RX), 1492 1493 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1494 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1495 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1496 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1497 1498 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1499 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1500 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1501 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1502 1503 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1504 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1505 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1506 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1507 1508 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1509 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1510 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1511 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1512 1513 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1514 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1515 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1516 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1517 1518 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1519 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1520 /* [D8] */ INVALID, INVALID, INVALID, TSq("vpand",EVEX_RMrX), 1521 /* [DC] */ INVALID, INVALID, INVALID, TSq("vpandn",EVEX_RMrX), 1522 1523 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1524 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1525 /* [E8] */ INVALID, INVALID, INVALID, TSq("vpor",EVEX_RMrX), 1526 /* [EC] */ INVALID, INVALID, INVALID, TSq("vpxor",EVEX_RMrX), 1527 1528 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1529 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1530 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1531 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1532 }; 1533 1534 /* 1535 * The following two tables are used to encode crc32 and movbe 1536 * since they share the same opcodes. 1537 */ 1538 const instable_t dis_op0F38F0[2] = { 1539 /* [00] */ TNS("crc32b",CRC32), 1540 TS("movbe",MOVBE), 1541 }; 1542 1543 const instable_t dis_op0F38F1[2] = { 1544 /* [00] */ TS("crc32",CRC32), 1545 TS("movbe",MOVBE), 1546 }; 1547 1548 /* 1549 * The following table is used to distinguish between adox and adcx which share 1550 * the same opcodes. 1551 */ 1552 const instable_t dis_op0F38F6[2] = { 1553 /* [00] */ TNS("adcx",ADX), 1554 TNS("adox",ADX), 1555 }; 1556 1557 const instable_t dis_op0F38[256] = { 1558 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1559 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1560 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1561 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1562 1563 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1564 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1565 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1566 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1567 1568 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 1569 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 1570 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 1571 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1572 1573 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 1574 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 1575 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 1576 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 1577 1578 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 1579 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1580 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1581 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1582 1583 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1584 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1585 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1586 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1587 1588 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1589 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1590 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1591 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1592 1593 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1594 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1595 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1596 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1597 1598 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID, 1599 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1600 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1601 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1602 1603 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1604 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1605 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1606 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1607 1608 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1609 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1610 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1611 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1612 1613 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1614 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1615 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1616 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1617 1618 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1619 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1620 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16), 1621 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, INVALID, 1622 1623 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1624 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1625 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 1626 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 1627 1628 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1629 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1630 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1631 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1632 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1633 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID, 1634 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1635 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1636 }; 1637 1638 const instable_t dis_opAVX660F38[256] = { 1639 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 1640 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 1641 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 1642 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 1643 1644 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 1645 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16), 1646 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 1647 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 1648 1649 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 1650 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 1651 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 1652 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 1653 1654 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 1655 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16), 1656 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 1657 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 1658 1659 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 1660 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16), 1661 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1662 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1663 1664 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1665 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1666 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID, 1667 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1668 1669 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1670 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1671 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1672 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1673 1674 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1675 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1676 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID, 1677 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1678 1679 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1680 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1681 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1682 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID, 1683 1684 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16), 1685 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 1686 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 1687 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16), 1688 1689 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1690 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16), 1691 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16), 1692 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16), 1693 1694 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1695 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16), 1696 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16), 1697 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16), 1698 1699 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1700 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1701 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1702 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1703 1704 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1705 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1706 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 1707 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 1708 1709 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1710 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1711 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1712 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1713 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1714 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5), 1715 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1716 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1717 }; 1718 1719 const instable_t dis_op0F3A[256] = { 1720 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1721 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1722 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 1723 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 1724 1725 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1726 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 1727 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1728 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1729 1730 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 1731 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1732 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1733 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1734 1735 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1736 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1737 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1738 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1739 1740 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 1741 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 1742 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1743 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1744 1745 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1746 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1747 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1748 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1749 1750 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 1751 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1752 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1753 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1754 1755 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1756 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1757 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1758 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1759 1760 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1761 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1762 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1763 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1764 1765 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1766 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1767 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1768 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1769 1770 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1771 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1772 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1773 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1774 1775 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1776 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1777 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1778 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1779 1780 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1781 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1782 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1783 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, INVALID, INVALID, 1784 1785 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1786 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1787 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1788 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 1789 1790 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1791 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1792 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1793 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1794 1795 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1796 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1797 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1798 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1799 }; 1800 1801 const instable_t dis_opAVX660F3A[256] = { 1802 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID, 1803 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 1804 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 1805 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 1806 1807 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1808 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 1809 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 1810 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 1811 1812 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 1813 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1814 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1815 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1816 1817 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI), 1818 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1819 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID, 1820 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1821 1822 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 1823 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID, 1824 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 1825 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 1826 1827 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1828 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1829 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1830 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1831 1832 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 1833 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1834 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1835 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1836 1837 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1838 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1839 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1840 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1841 1842 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1843 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1844 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1845 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1846 1847 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1848 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1849 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1850 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1851 1852 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1853 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1854 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1855 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1856 1857 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1858 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1859 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1860 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1861 1862 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1863 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1864 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1865 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1866 1867 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1868 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1869 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1870 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 1871 1872 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1873 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1874 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1875 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1876 1877 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1878 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1879 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1880 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1881 }; 1882 1883 /* 1884 * Decode table for 0x0F0D which uses the first byte of the mod_rm to 1885 * indicate a sub-code. 1886 */ 1887 const instable_t dis_op0F0D[8] = { 1888 /* [00] */ INVALID, TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID, 1889 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1890 }; 1891 1892 /* 1893 * Decode table for 0x0F opcodes 1894 */ 1895 1896 const instable_t dis_op0F[16][16] = { 1897 { 1898 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 1899 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 1900 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 1901 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID, 1902 }, { 1903 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 1904 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 1905 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 1906 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 1907 }, { 1908 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 1909 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 1910 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 1911 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 1912 }, { 1913 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 1914 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID, 1915 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1916 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1917 }, { 1918 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 1919 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 1920 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 1921 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 1922 }, { 1923 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 1924 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 1925 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 1926 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 1927 }, { 1928 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 1929 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 1930 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 1931 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 1932 }, { 1933 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 1934 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 1935 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 1936 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 1937 }, { 1938 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 1939 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 1940 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 1941 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 1942 }, { 1943 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 1944 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 1945 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 1946 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 1947 }, { 1948 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 1949 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 1950 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 1951 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 1952 }, { 1953 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 1954 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 1955 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 1956 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 1957 }, { 1958 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 1959 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 1960 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1961 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1962 }, { 1963 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 1964 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 1965 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 1966 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 1967 }, { 1968 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 1969 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 1970 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 1971 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 1972 }, { 1973 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 1974 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 1975 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 1976 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 1977 } }; 1978 1979 const instable_t dis_opAVX0F[16][16] = { 1980 { 1981 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1982 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1983 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1984 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1985 }, { 1986 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 1987 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 1988 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1989 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1990 }, { 1991 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1992 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1993 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 1994 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 1995 }, { 1996 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1997 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1998 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1999 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2000 }, { 2001 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 2002 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 2003 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 2004 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2005 }, { 2006 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 2007 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 2008 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 2009 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 2010 }, { 2011 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2012 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2013 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2014 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2015 }, { 2016 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2017 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 2018 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2019 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2020 }, { 2021 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2022 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2023 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2024 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2025 }, { 2026 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 2027 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2028 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 2029 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2030 }, { 2031 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2032 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2033 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2034 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 2035 }, { 2036 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2037 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2038 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2039 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2040 }, { 2041 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 2042 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 2043 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2044 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2045 }, { 2046 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2047 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2048 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2049 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2050 }, { 2051 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2052 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2053 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2054 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2055 }, { 2056 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5), 2057 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5), 2058 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2059 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2060 } }; 2061 2062 /* 2063 * Decode table for 0x80 opcodes 2064 */ 2065 2066 const instable_t dis_op80[8] = { 2067 2068 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 2069 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 2070 }; 2071 2072 2073 /* 2074 * Decode table for 0x81 opcodes. 2075 */ 2076 2077 const instable_t dis_op81[8] = { 2078 2079 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 2080 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 2081 }; 2082 2083 2084 /* 2085 * Decode table for 0x82 opcodes. 2086 */ 2087 2088 const instable_t dis_op82[8] = { 2089 2090 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 2091 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 2092 }; 2093 /* 2094 * Decode table for 0x83 opcodes. 2095 */ 2096 2097 const instable_t dis_op83[8] = { 2098 2099 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 2100 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 2101 }; 2102 2103 /* 2104 * Decode table for 0xC0 opcodes. 2105 */ 2106 2107 const instable_t dis_opC0[8] = { 2108 2109 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 2110 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 2111 }; 2112 2113 /* 2114 * Decode table for 0xD0 opcodes. 2115 */ 2116 2117 const instable_t dis_opD0[8] = { 2118 2119 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2120 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2121 }; 2122 2123 /* 2124 * Decode table for 0xC1 opcodes. 2125 * 186 instruction set 2126 */ 2127 2128 const instable_t dis_opC1[8] = { 2129 2130 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 2131 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 2132 }; 2133 2134 /* 2135 * Decode table for 0xD1 opcodes. 2136 */ 2137 2138 const instable_t dis_opD1[8] = { 2139 2140 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2141 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 2142 }; 2143 2144 2145 /* 2146 * Decode table for 0xD2 opcodes. 2147 */ 2148 2149 const instable_t dis_opD2[8] = { 2150 2151 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2152 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2153 }; 2154 /* 2155 * Decode table for 0xD3 opcodes. 2156 */ 2157 2158 const instable_t dis_opD3[8] = { 2159 2160 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2161 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 2162 }; 2163 2164 2165 /* 2166 * Decode table for 0xF6 opcodes. 2167 */ 2168 2169 const instable_t dis_opF6[8] = { 2170 2171 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 2172 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 2173 }; 2174 2175 2176 /* 2177 * Decode table for 0xF7 opcodes. 2178 */ 2179 2180 const instable_t dis_opF7[8] = { 2181 2182 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 2183 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 2184 }; 2185 2186 2187 /* 2188 * Decode table for 0xFE opcodes. 2189 */ 2190 2191 const instable_t dis_opFE[8] = { 2192 2193 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 2194 /* [4] */ INVALID, INVALID, INVALID, INVALID, 2195 }; 2196 /* 2197 * Decode table for 0xFF opcodes. 2198 */ 2199 2200 const instable_t dis_opFF[8] = { 2201 2202 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 2203 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 2204 }; 2205 2206 /* for 287 instructions, which are a mess to decode */ 2207 2208 const instable_t dis_opFP1n2[8][8] = { 2209 { 2210 /* bit pattern: 1101 1xxx MODxx xR/M */ 2211 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 2212 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 2213 }, { 2214 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 2215 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 2216 }, { 2217 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 2218 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 2219 }, { 2220 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M), 2221 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 2222 }, { 2223 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 2224 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 2225 }, { 2226 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 2227 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 2228 }, { 2229 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 2230 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 2231 }, { 2232 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2), 2233 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 2234 } }; 2235 2236 const instable_t dis_opFP3[8][8] = { 2237 { 2238 /* bit pattern: 1101 1xxx 11xx xREG */ 2239 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2240 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2241 }, { 2242 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 2243 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 2244 }, { 2245 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 2246 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 2247 }, { 2248 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 2249 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 2250 }, { 2251 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2252 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2253 }, { 2254 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 2255 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 2256 }, { 2257 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 2258 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 2259 }, { 2260 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 2261 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 2262 } }; 2263 2264 const instable_t dis_opFP4[4][8] = { 2265 { 2266 /* bit pattern: 1101 1001 111x xxxx */ 2267 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 2268 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 2269 }, { 2270 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 2271 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 2272 }, { 2273 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 2274 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 2275 }, { 2276 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 2277 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 2278 } }; 2279 2280 const instable_t dis_opFP5[8] = { 2281 /* bit pattern: 1101 1011 111x xxxx */ 2282 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 2283 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 2284 }; 2285 2286 const instable_t dis_opFP6[8] = { 2287 /* bit pattern: 1101 1011 11yy yxxx */ 2288 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 2289 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 2290 }; 2291 2292 const instable_t dis_opFP7[8] = { 2293 /* bit pattern: 1101 1010 11yy yxxx */ 2294 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 2295 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2296 }; 2297 2298 /* 2299 * Main decode table for the op codes. The first two nibbles 2300 * will be used as an index into the table. If there is a 2301 * a need to further decode an instruction, the array to be 2302 * referenced is indicated with the other two entries being 2303 * empty. 2304 */ 2305 2306 const instable_t dis_distable[16][16] = { 2307 { 2308 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 2309 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 2310 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 2311 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 2312 }, { 2313 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 2314 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 2315 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 2316 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 2317 }, { 2318 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 2319 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 2320 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 2321 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 2322 }, { 2323 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 2324 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 2325 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 2326 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 2327 }, { 2328 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2329 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2330 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2331 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2332 }, { 2333 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2334 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2335 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2336 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2337 }, { 2338 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw), 2339 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 2340 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 2341 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 2342 }, { 2343 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 2344 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 2345 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 2346 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 2347 }, { 2348 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 2349 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 2350 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 2351 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 2352 }, { 2353 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2354 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2355 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 2356 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM), 2357 }, { 2358 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 2359 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 2360 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 2361 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 2362 }, { 2363 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2364 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2365 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2366 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2367 }, { 2368 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 2369 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 2370 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 2371 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 2372 }, { 2373 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 2374 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 2375 2376 /* 287 instructions. Note that although the indirect field */ 2377 /* indicates opFP1n2 for further decoding, this is not necessarily */ 2378 /* the case since the opFP arrays are not partitioned according to key1 */ 2379 /* and key2. opFP1n2 is given only to indicate that we haven't */ 2380 /* finished decoding the instruction. */ 2381 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2382 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2383 }, { 2384 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 2385 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 2386 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 2387 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 2388 }, { 2389 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 2390 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 2391 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 2392 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 2393 } }; 2394 2395 /* END CSTYLED */ 2396 2397 /* 2398 * common functions to decode and disassemble an x86 or amd64 instruction 2399 */ 2400 2401 /* 2402 * These are the individual fields of a REX prefix. Note that a REX 2403 * prefix with none of these set is still needed to: 2404 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 2405 * - access the %sil, %dil, %bpl, %spl registers 2406 */ 2407 #define REX_W 0x08 /* 64 bit operand size when set */ 2408 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 2409 #define REX_X 0x02 /* high order bit extension of SIB index field */ 2410 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 2411 2412 /* 2413 * These are the individual fields of a VEX/EVEX prefix. 2414 */ 2415 #define VEX_R 0x08 /* REX.R in 1's complement form */ 2416 #define VEX_X 0x04 /* REX.X in 1's complement form */ 2417 #define VEX_B 0x02 /* REX.B in 1's complement form */ 2418 2419 /* Additional EVEX prefix definitions */ 2420 #define EVEX_R 0x01 /* REX.R' in 1's complement form */ 2421 #define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */ 2422 #define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */ 2423 2424 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 2425 #define VEX_L 0x04 2426 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */ 2427 #define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */ 2428 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 2429 #define VEX_m 0x1F /* VEX m-mmmm field */ 2430 #define EVEX_m 0x3 /* EVEX mm field */ 2431 #define VEX_v 0x78 /* VEX/EVEX register specifier */ 2432 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 2433 2434 /* VEX m-mmmm field, only used by three bytes prefix */ 2435 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 2436 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 2437 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 2438 2439 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 2440 #define VEX_p_66 0x01 2441 #define VEX_p_F3 0x02 2442 #define VEX_p_F2 0x03 2443 2444 /* 2445 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2446 */ 2447 static int isize[] = {1, 2, 4, 4}; 2448 static int isize64[] = {1, 2, 4, 8}; 2449 2450 /* 2451 * Just a bunch of useful macros. 2452 */ 2453 #define WBIT(x) (x & 0x1) /* to get w bit */ 2454 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2455 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2456 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2457 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2458 2459 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2460 2461 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2462 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2463 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2464 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2465 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2466 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2467 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2468 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2469 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2470 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2471 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ 2472 #define ZMM_OPND 11 /* "value" used to indicate a zmm reg */ 2473 2474 /* 2475 * The AVX2 gather instructions are a bit of a mess. While there's a pattern, 2476 * there's not really a consistent scheme that we can use to know what the mode 2477 * is supposed to be for a given type. Various instructions, like VPGATHERDD, 2478 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have 2479 * some registers match VEX_L, but the VSIB is always XMM. 2480 * 2481 * The simplest way to deal with this is to just define a table based on the 2482 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into 2483 * them. 2484 * 2485 * We further have to subdivide this based on the value of VEX_W and the value 2486 * of VEX_L. The array is constructed to be indexed as: 2487 * [opcode - 0x90][VEX_W][VEX_L]. 2488 */ 2489 /* w = 0, 0x90 */ 2490 typedef struct dis_gather_regs { 2491 uint_t dgr_arg0; /* src reg */ 2492 uint_t dgr_arg1; /* vsib reg */ 2493 uint_t dgr_arg2; /* dst reg */ 2494 char *dgr_suffix; /* suffix to append */ 2495 } dis_gather_regs_t; 2496 2497 static dis_gather_regs_t dis_vgather[4][2][2] = { 2498 { 2499 /* op 0x90, W.0 */ 2500 { 2501 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2502 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2503 }, 2504 /* op 0x90, W.1 */ 2505 { 2506 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2507 { YMM_OPND, XMM_OPND, YMM_OPND, "q" } 2508 } 2509 }, 2510 { 2511 /* op 0x91, W.0 */ 2512 { 2513 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2514 { XMM_OPND, YMM_OPND, XMM_OPND, "d" }, 2515 }, 2516 /* op 0x91, W.1 */ 2517 { 2518 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2519 { YMM_OPND, YMM_OPND, YMM_OPND, "q" }, 2520 } 2521 }, 2522 { 2523 /* op 0x92, W.0 */ 2524 { 2525 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2526 { YMM_OPND, YMM_OPND, YMM_OPND, "s" } 2527 }, 2528 /* op 0x92, W.1 */ 2529 { 2530 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2531 { YMM_OPND, XMM_OPND, YMM_OPND, "d" } 2532 } 2533 }, 2534 { 2535 /* op 0x93, W.0 */ 2536 { 2537 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2538 { XMM_OPND, YMM_OPND, XMM_OPND, "s" } 2539 }, 2540 /* op 0x93, W.1 */ 2541 { 2542 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2543 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2544 } 2545 } 2546 }; 2547 2548 /* 2549 * Get the next byte and separate the op code into the high and low nibbles. 2550 */ 2551 static int 2552 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2553 { 2554 int byte; 2555 2556 /* 2557 * x86 instructions have a maximum length of 15 bytes. Bail out if 2558 * we try to read more. 2559 */ 2560 if (x->d86_len >= 15) 2561 return (x->d86_error = 1); 2562 2563 if (x->d86_error) 2564 return (1); 2565 byte = x->d86_get_byte(x->d86_data); 2566 if (byte < 0) 2567 return (x->d86_error = 1); 2568 x->d86_bytes[x->d86_len++] = byte; 2569 *low = byte & 0xf; /* ----xxxx low 4 bits */ 2570 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 2571 return (0); 2572 } 2573 2574 /* 2575 * Get and decode an SIB (scaled index base) byte 2576 */ 2577 static void 2578 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 2579 { 2580 int byte; 2581 2582 if (x->d86_error) 2583 return; 2584 2585 byte = x->d86_get_byte(x->d86_data); 2586 if (byte < 0) { 2587 x->d86_error = 1; 2588 return; 2589 } 2590 x->d86_bytes[x->d86_len++] = byte; 2591 2592 *base = byte & 0x7; 2593 *index = (byte >> 3) & 0x7; 2594 *ss = (byte >> 6) & 0x3; 2595 } 2596 2597 /* 2598 * Get the byte following the op code and separate it into the 2599 * mode, register, and r/m fields. 2600 */ 2601 static void 2602 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 2603 { 2604 if (x->d86_got_modrm == 0) { 2605 if (x->d86_rmindex == -1) 2606 x->d86_rmindex = x->d86_len; 2607 dtrace_get_SIB(x, mode, reg, r_m); 2608 x->d86_got_modrm = 1; 2609 } 2610 } 2611 2612 /* 2613 * Adjust register selection based on any REX prefix bits present. 2614 */ 2615 /*ARGSUSED*/ 2616 static void 2617 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 2618 { 2619 if (reg != NULL && r_m == NULL) { 2620 if (rex_prefix & REX_B) 2621 *reg += 8; 2622 } else { 2623 if (reg != NULL && (REX_R & rex_prefix) != 0) 2624 *reg += 8; 2625 if (r_m != NULL && (REX_B & rex_prefix) != 0) 2626 *r_m += 8; 2627 } 2628 } 2629 2630 /* 2631 * Adjust register selection based on any VEX prefix bits present. 2632 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 2633 */ 2634 /*ARGSUSED*/ 2635 static void 2636 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 2637 { 2638 if (reg != NULL && r_m == NULL) { 2639 if (!(vex_byte1 & VEX_B)) 2640 *reg += 8; 2641 } else { 2642 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 2643 *reg += 8; 2644 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 2645 *r_m += 8; 2646 } 2647 } 2648 2649 /* 2650 * Adjust the instruction mnemonic with the appropriate suffix. 2651 */ 2652 /* ARGSUSED */ 2653 static void 2654 dtrace_evex_mnem_adjust(dis86_t *x, instable_t *dp, uint_t vex_W, 2655 uint_t evex_byte2) 2656 { 2657 #ifdef DIS_TEXT 2658 if (dp == &dis_opAVX62[0x7f] || /* vmovdq */ 2659 dp == &dis_opAVX62[0x6f]) { 2660 /* Aligned or Unaligned? */ 2661 if ((evex_byte2 & 0x3) == 0x01) { 2662 (void) strlcat(x->d86_mnem, "a", OPLEN); 2663 (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32", 2664 OPLEN); 2665 } else { 2666 (void) strlcat(x->d86_mnem, "u", OPLEN); 2667 switch (evex_byte2 & 0x81) { 2668 case 0x0: 2669 (void) strlcat(x->d86_mnem, "32", OPLEN); 2670 break; 2671 case 0x1: 2672 (void) strlcat(x->d86_mnem, "8", OPLEN); 2673 break; 2674 case 0x80: 2675 (void) strlcat(x->d86_mnem, "64", OPLEN); 2676 break; 2677 case 0x81: 2678 (void) strlcat(x->d86_mnem, "16", OPLEN); 2679 break; 2680 } 2681 } 2682 2683 } else { 2684 if (dp->it_avxsuf == AVS5Q) { 2685 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 2686 OPLEN); 2687 } else { 2688 (void) strlcat(x->d86_mnem, vex_W != 0 ? "d" : "s", 2689 OPLEN); 2690 } 2691 } 2692 #endif 2693 } 2694 2695 /* 2696 * The following three functions adjust the register selection based on any 2697 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software 2698 * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and 2699 * section 2.6.2 Table 2-31. 2700 */ 2701 static void 2702 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg) 2703 { 2704 if (reg != NULL) { 2705 if ((VEX_R & evex_byte1) == 0) { 2706 *reg += 8; 2707 } 2708 if ((EVEX_R & evex_byte1) == 0) { 2709 *reg += 16; 2710 } 2711 } 2712 } 2713 2714 static void 2715 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m) 2716 { 2717 if (r_m != NULL) { 2718 if ((VEX_B & evex_byte1) == 0) { 2719 *r_m += 8; 2720 } 2721 if ((VEX_X & evex_byte1) == 0) { 2722 *r_m += 16; 2723 } 2724 } 2725 } 2726 2727 /* 2728 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36. 2729 */ 2730 static void 2731 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp) 2732 { 2733 switch (evex_L) { 2734 case 0x0: 2735 *wbitp = XMM_OPND; 2736 break; 2737 case 0x1: 2738 *wbitp = YMM_OPND; 2739 break; 2740 case 0x2: 2741 *wbitp = ZMM_OPND; 2742 break; 2743 } 2744 } 2745 2746 /* 2747 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5. 2748 * This currently only handles a subset of the possibilities. 2749 */ 2750 static void 2751 dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) 2752 { 2753 d86opnd_t *opnd = &x->d86_opnd[opindex]; 2754 2755 if (x->d86_error) 2756 return; 2757 2758 /* Check disp8 bit in the ModR/M byte */ 2759 if ((modrm & 0x80) == 0x80) 2760 return; 2761 2762 /* use evex_L to adjust the value */ 2763 switch (L) { 2764 case 0x0: 2765 opnd->d86_value *= 16; 2766 break; 2767 case 0x1: 2768 opnd->d86_value *= 32; 2769 break; 2770 case 0x2: 2771 opnd->d86_value *= 64; 2772 break; 2773 } 2774 } 2775 2776 /* 2777 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30. 2778 */ 2779 /* ARGSUSED */ 2780 static void 2781 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3) 2782 { 2783 #ifdef DIS_TEXT 2784 char *opnd = x->d86_opnd[tgtop].d86_opnd; 2785 int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; 2786 #endif 2787 if (x->d86_error) 2788 return; 2789 2790 #ifdef DIS_TEXT 2791 if (opmask_reg != 0) { 2792 /* Append the opmask register to operand 1 */ 2793 (void) strlcat(opnd, "{", OPLEN); 2794 (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN); 2795 (void) strlcat(opnd, "}", OPLEN); 2796 } 2797 if ((evex_byte3 & EVEX_ZERO_MASK) != 0) { 2798 /* Append the 'zeroing' modifier to operand 1 */ 2799 (void) strlcat(opnd, "{z}", OPLEN); 2800 } 2801 #endif /* DIS_TEXT */ 2802 } 2803 2804 /* 2805 * Get an immediate operand of the given size, with sign extension. 2806 */ 2807 static void 2808 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 2809 { 2810 int i; 2811 int byte; 2812 int valsize; 2813 2814 if (x->d86_numopnds < opindex + 1) 2815 x->d86_numopnds = opindex + 1; 2816 2817 switch (wbit) { 2818 case BYTE_OPND: 2819 valsize = 1; 2820 break; 2821 case LONG_OPND: 2822 if (x->d86_opnd_size == SIZE16) 2823 valsize = 2; 2824 else if (x->d86_opnd_size == SIZE32) 2825 valsize = 4; 2826 else 2827 valsize = 8; 2828 break; 2829 case MM_OPND: 2830 case XMM_OPND: 2831 case YMM_OPND: 2832 case ZMM_OPND: 2833 case SEG_OPND: 2834 case CONTROL_OPND: 2835 case DEBUG_OPND: 2836 case TEST_OPND: 2837 valsize = size; 2838 break; 2839 case WORD_OPND: 2840 valsize = 2; 2841 break; 2842 } 2843 if (valsize < size) 2844 valsize = size; 2845 2846 if (x->d86_error) 2847 return; 2848 x->d86_opnd[opindex].d86_value = 0; 2849 for (i = 0; i < size; ++i) { 2850 byte = x->d86_get_byte(x->d86_data); 2851 if (byte < 0) { 2852 x->d86_error = 1; 2853 return; 2854 } 2855 x->d86_bytes[x->d86_len++] = byte; 2856 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 2857 } 2858 /* Do sign extension */ 2859 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 2860 for (; i < sizeof (uint64_t); i++) 2861 x->d86_opnd[opindex].d86_value |= 2862 (uint64_t)0xff << (i * 8); 2863 } 2864 #ifdef DIS_TEXT 2865 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2866 x->d86_opnd[opindex].d86_value_size = valsize; 2867 x->d86_imm_bytes += size; 2868 #endif 2869 } 2870 2871 /* 2872 * Get an ip relative operand of the given size, with sign extension. 2873 */ 2874 static void 2875 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 2876 { 2877 dtrace_imm_opnd(x, wbit, size, opindex); 2878 #ifdef DIS_TEXT 2879 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 2880 #endif 2881 } 2882 2883 /* 2884 * Check to see if there is a segment override prefix pending. 2885 * If so, print it in the current 'operand' location and set 2886 * the override flag back to false. 2887 */ 2888 /*ARGSUSED*/ 2889 static void 2890 dtrace_check_override(dis86_t *x, int opindex) 2891 { 2892 #ifdef DIS_TEXT 2893 if (x->d86_seg_prefix) { 2894 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 2895 x->d86_seg_prefix, PFIXLEN); 2896 } 2897 #endif 2898 x->d86_seg_prefix = NULL; 2899 } 2900 2901 2902 /* 2903 * Process a single instruction Register or Memory operand. 2904 * 2905 * mode = addressing mode from ModRM byte 2906 * r_m = r_m (or reg if mode == 3) field from ModRM byte 2907 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 2908 * o = index of operand that we are processing (0, 1 or 2) 2909 * 2910 * the value of reg or r_m must have already been adjusted for any REX prefix. 2911 */ 2912 /*ARGSUSED*/ 2913 static void 2914 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 2915 { 2916 int have_SIB = 0; /* flag presence of scale-index-byte */ 2917 uint_t ss; /* scale-factor from opcode */ 2918 uint_t index; /* index register number */ 2919 uint_t base; /* base register number */ 2920 int dispsize; /* size of displacement in bytes */ 2921 #ifdef DIS_TEXT 2922 char *opnd = x->d86_opnd[opindex].d86_opnd; 2923 #endif 2924 2925 if (x->d86_numopnds < opindex + 1) 2926 x->d86_numopnds = opindex + 1; 2927 2928 if (x->d86_error) 2929 return; 2930 2931 /* 2932 * first handle a simple register 2933 */ 2934 if (mode == REG_ONLY) { 2935 #ifdef DIS_TEXT 2936 switch (wbit) { 2937 case MM_OPND: 2938 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 2939 break; 2940 case XMM_OPND: 2941 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 2942 break; 2943 case YMM_OPND: 2944 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 2945 break; 2946 case ZMM_OPND: 2947 (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN); 2948 break; 2949 case KOPMASK_OPND: 2950 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); 2951 break; 2952 case SEG_OPND: 2953 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 2954 break; 2955 case CONTROL_OPND: 2956 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 2957 break; 2958 case DEBUG_OPND: 2959 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 2960 break; 2961 case TEST_OPND: 2962 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 2963 break; 2964 case BYTE_OPND: 2965 if (x->d86_rex_prefix == 0) 2966 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 2967 else 2968 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 2969 break; 2970 case WORD_OPND: 2971 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2972 break; 2973 case LONG_OPND: 2974 if (x->d86_opnd_size == SIZE16) 2975 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2976 else if (x->d86_opnd_size == SIZE32) 2977 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 2978 else 2979 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 2980 break; 2981 } 2982 #endif /* DIS_TEXT */ 2983 return; 2984 } 2985 2986 /* 2987 * if symbolic representation, skip override prefix, if any 2988 */ 2989 dtrace_check_override(x, opindex); 2990 2991 /* 2992 * Handle 16 bit memory references first, since they decode 2993 * the mode values more simply. 2994 * mode 1 is r_m + 8 bit displacement 2995 * mode 2 is r_m + 16 bit displacement 2996 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 2997 */ 2998 if (x->d86_addr_size == SIZE16) { 2999 if ((mode == 0 && r_m == 6) || mode == 2) 3000 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 3001 else if (mode == 1) 3002 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 3003 #ifdef DIS_TEXT 3004 if (mode == 0 && r_m == 6) 3005 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3006 else if (mode == 0) 3007 x->d86_opnd[opindex].d86_mode = MODE_NONE; 3008 else 3009 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3010 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 3011 #endif 3012 return; 3013 } 3014 3015 /* 3016 * 32 and 64 bit addressing modes are more complex since they 3017 * can involve an SIB (scaled index and base) byte to decode. 3018 */ 3019 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) { 3020 have_SIB = 1; 3021 dtrace_get_SIB(x, &ss, &index, &base); 3022 if (x->d86_error) 3023 return; 3024 if (base != 5 || mode != 0) 3025 if (x->d86_rex_prefix & REX_B) 3026 base += 8; 3027 if (x->d86_rex_prefix & REX_X) 3028 index += 8; 3029 } else { 3030 base = r_m; 3031 } 3032 3033 /* 3034 * Compute the displacement size and get its bytes 3035 */ 3036 dispsize = 0; 3037 3038 if (mode == 1) 3039 dispsize = 1; 3040 else if (mode == 2) 3041 dispsize = 4; 3042 else if ((r_m & 7) == EBP_REGNO || 3043 (have_SIB && (base & 7) == EBP_REGNO)) 3044 dispsize = 4; 3045 3046 if (dispsize > 0) { 3047 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 3048 dispsize, opindex); 3049 if (x->d86_error) 3050 return; 3051 } 3052 3053 #ifdef DIS_TEXT 3054 if (dispsize > 0) 3055 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3056 3057 if (have_SIB == 0) { 3058 if (x->d86_mode == SIZE32) { 3059 if (mode == 0) 3060 (void) strlcat(opnd, dis_addr32_mode0[r_m], 3061 OPLEN); 3062 else 3063 (void) strlcat(opnd, dis_addr32_mode12[r_m], 3064 OPLEN); 3065 } else { 3066 if (mode == 0) { 3067 (void) strlcat(opnd, dis_addr64_mode0[r_m], 3068 OPLEN); 3069 if (r_m == 5) { 3070 x->d86_opnd[opindex].d86_mode = 3071 MODE_RIPREL; 3072 } 3073 } else { 3074 (void) strlcat(opnd, dis_addr64_mode12[r_m], 3075 OPLEN); 3076 } 3077 } 3078 } else { 3079 uint_t need_paren = 0; 3080 char **regs; 3081 char **bregs; 3082 const char *const *sf; 3083 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 3084 regs = (char **)dis_REG32; 3085 else 3086 regs = (char **)dis_REG64; 3087 3088 if (x->d86_vsib != 0) { 3089 if (wbit == YMM_OPND) { /* NOTE this is not addr_size */ 3090 bregs = (char **)dis_YMMREG; 3091 } else if (wbit == XMM_OPND) { 3092 bregs = (char **)dis_XMMREG; 3093 } else { 3094 bregs = (char **)dis_ZMMREG; 3095 } 3096 sf = dis_vscale_factor; 3097 } else { 3098 bregs = regs; 3099 sf = dis_scale_factor; 3100 } 3101 3102 /* 3103 * print the base (if any) 3104 */ 3105 if (base == EBP_REGNO && mode == 0) { 3106 if (index != ESP_REGNO || x->d86_vsib != 0) { 3107 (void) strlcat(opnd, "(", OPLEN); 3108 need_paren = 1; 3109 } 3110 } else { 3111 (void) strlcat(opnd, "(", OPLEN); 3112 (void) strlcat(opnd, regs[base], OPLEN); 3113 need_paren = 1; 3114 } 3115 3116 /* 3117 * print the index (if any) 3118 */ 3119 if (index != ESP_REGNO || x->d86_vsib) { 3120 (void) strlcat(opnd, ",", OPLEN); 3121 (void) strlcat(opnd, bregs[index], OPLEN); 3122 (void) strlcat(opnd, sf[ss], OPLEN); 3123 } else 3124 if (need_paren) 3125 (void) strlcat(opnd, ")", OPLEN); 3126 } 3127 #endif 3128 } 3129 3130 /* 3131 * Operand sequence for standard instruction involving one register 3132 * and one register/memory operand. 3133 * wbit indicates a byte(0) or opnd_size(1) operation 3134 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 3135 */ 3136 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 3137 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3138 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3139 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3140 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 3141 } 3142 3143 /* 3144 * Similar to above, but allows for the two operands to be of different 3145 * classes (ie. wbit). 3146 * wbit is for the r_m operand 3147 * w2 is for the reg operand 3148 */ 3149 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 3150 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3151 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3152 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3153 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 3154 } 3155 3156 /* 3157 * Similar, but for 2 operands plus an immediate. 3158 * vbit indicates direction 3159 * 0 for "opcode imm, r, r_m" or 3160 * 1 for "opcode imm, r_m, r" 3161 */ 3162 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 3163 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3164 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3165 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 3166 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 3167 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3168 } 3169 3170 /* 3171 * Similar, but for 2 operands plus two immediates. 3172 */ 3173 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 3174 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3175 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3176 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3177 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 3178 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3179 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3180 } 3181 3182 /* 3183 * 1 operands plus two immediates. 3184 */ 3185 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 3186 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3187 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3188 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3189 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3190 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3191 } 3192 3193 /* 3194 * Dissassemble a single x86 or amd64 instruction. 3195 * 3196 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 3197 * for interpreting instructions. 3198 * 3199 * returns non-zero for bad opcode 3200 */ 3201 int 3202 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 3203 { 3204 instable_t *dp; /* decode table being used */ 3205 #ifdef DIS_TEXT 3206 uint_t i; 3207 #endif 3208 #ifdef DIS_MEM 3209 uint_t nomem = 0; 3210 #define NOMEM (nomem = 1) 3211 #else 3212 #define NOMEM /* nothing */ 3213 #endif 3214 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 3215 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 3216 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 3217 uint_t w2; /* wbit value for second operand */ 3218 uint_t vbit; 3219 uint_t mode = 0; /* mode value from ModRM byte */ 3220 uint_t reg; /* reg value from ModRM byte */ 3221 uint_t r_m; /* r_m value from ModRM byte */ 3222 3223 uint_t opcode1; /* high nibble of 1st byte */ 3224 uint_t opcode2; /* low nibble of 1st byte */ 3225 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 3226 uint_t opcode4; /* high nibble of 2nd byte */ 3227 uint_t opcode5; /* low nibble of 2nd byte */ 3228 uint_t opcode6; /* high nibble of 3rd byte */ 3229 uint_t opcode7; /* low nibble of 3rd byte */ 3230 uint_t opcode8; /* high nibble of 4th byte */ 3231 uint_t opcode9; /* low nibble of 4th byte */ 3232 uint_t opcode_bytes = 1; 3233 3234 /* 3235 * legacy prefixes come in 5 flavors, you should have only one of each 3236 */ 3237 uint_t opnd_size_prefix = 0; 3238 uint_t addr_size_prefix = 0; 3239 uint_t segment_prefix = 0; 3240 uint_t lock_prefix = 0; 3241 uint_t rep_prefix = 0; 3242 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 3243 3244 /* 3245 * Intel VEX instruction encoding prefix and fields 3246 */ 3247 3248 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 3249 uint_t vex_prefix = 0; 3250 3251 /* 3252 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 3253 * (for 3 bytes prefix) 3254 */ 3255 uint_t vex_byte1 = 0; 3256 3257 /* 3258 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r. 3259 */ 3260 uint_t evex_byte1 = 0; 3261 uint_t evex_byte2 = 0; 3262 uint_t evex_byte3 = 0; 3263 3264 /* 3265 * For 32-bit mode, it should prefetch the next byte to 3266 * distinguish between AVX and les/lds 3267 */ 3268 uint_t vex_prefetch = 0; 3269 3270 uint_t vex_m = 0; 3271 uint_t vex_v = 0; 3272 uint_t vex_p = 0; 3273 uint_t vex_R = 1; 3274 uint_t vex_X = 1; 3275 uint_t vex_B = 1; 3276 uint_t vex_W = 0; 3277 uint_t vex_L = 0; 3278 uint_t evex_L = 0; 3279 uint_t evex_modrm = 0; 3280 dis_gather_regs_t *vreg; 3281 3282 #ifdef DIS_TEXT 3283 /* Instruction name for BLS* family of instructions */ 3284 char *blsinstr; 3285 #endif 3286 3287 size_t off; 3288 3289 instable_t dp_mmx; 3290 3291 x->d86_len = 0; 3292 x->d86_rmindex = -1; 3293 x->d86_error = 0; 3294 #ifdef DIS_TEXT 3295 x->d86_numopnds = 0; 3296 x->d86_seg_prefix = NULL; 3297 x->d86_mnem[0] = 0; 3298 for (i = 0; i < 4; ++i) { 3299 x->d86_opnd[i].d86_opnd[0] = 0; 3300 x->d86_opnd[i].d86_prefix[0] = 0; 3301 x->d86_opnd[i].d86_value_size = 0; 3302 x->d86_opnd[i].d86_value = 0; 3303 x->d86_opnd[i].d86_mode = MODE_NONE; 3304 } 3305 #endif 3306 x->d86_rex_prefix = 0; 3307 x->d86_got_modrm = 0; 3308 x->d86_memsize = 0; 3309 x->d86_vsib = 0; 3310 3311 if (cpu_mode == SIZE16) { 3312 opnd_size = SIZE16; 3313 addr_size = SIZE16; 3314 } else if (cpu_mode == SIZE32) { 3315 opnd_size = SIZE32; 3316 addr_size = SIZE32; 3317 } else { 3318 opnd_size = SIZE32; 3319 addr_size = SIZE64; 3320 } 3321 3322 /* 3323 * Get one opcode byte and check for zero padding that follows 3324 * jump tables. 3325 */ 3326 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3327 goto error; 3328 3329 if (opcode1 == 0 && opcode2 == 0 && 3330 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 3331 #ifdef DIS_TEXT 3332 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 3333 #endif 3334 goto done; 3335 } 3336 3337 /* 3338 * Gather up legacy x86 prefix bytes. 3339 */ 3340 for (;;) { 3341 uint_t *which_prefix = NULL; 3342 3343 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3344 3345 switch (dp->it_adrmode) { 3346 case PREFIX: 3347 which_prefix = &rep_prefix; 3348 break; 3349 case LOCK: 3350 which_prefix = &lock_prefix; 3351 break; 3352 case OVERRIDE: 3353 which_prefix = &segment_prefix; 3354 #ifdef DIS_TEXT 3355 x->d86_seg_prefix = (char *)dp->it_name; 3356 #endif 3357 if (dp->it_invalid64 && cpu_mode == SIZE64) 3358 goto error; 3359 break; 3360 case AM: 3361 which_prefix = &addr_size_prefix; 3362 break; 3363 case DM: 3364 which_prefix = &opnd_size_prefix; 3365 break; 3366 } 3367 if (which_prefix == NULL) 3368 break; 3369 *which_prefix = (opcode1 << 4) | opcode2; 3370 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3371 goto error; 3372 } 3373 3374 /* 3375 * Handle amd64 mode PREFIX values. 3376 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 3377 * We might have a REX prefix (opcodes 0x40-0x4f) 3378 */ 3379 if (cpu_mode == SIZE64) { 3380 if (segment_prefix != 0x64 && segment_prefix != 0x65) 3381 segment_prefix = 0; 3382 3383 if (opcode1 == 0x4) { 3384 rex_prefix = (opcode1 << 4) | opcode2; 3385 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3386 goto error; 3387 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3388 } else if (opcode1 == 0xC && 3389 (opcode2 == 0x4 || opcode2 == 0x5)) { 3390 /* AVX instructions */ 3391 vex_prefix = (opcode1 << 4) | opcode2; 3392 x->d86_rex_prefix = 0x40; 3393 } 3394 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 3395 /* LDS, LES or AVX */ 3396 dtrace_get_modrm(x, &mode, ®, &r_m); 3397 vex_prefetch = 1; 3398 3399 if (mode == REG_ONLY) { 3400 /* AVX */ 3401 vex_prefix = (opcode1 << 4) | opcode2; 3402 x->d86_rex_prefix = 0x40; 3403 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 3404 opcode4 = ((reg << 3) | r_m) & 0x0F; 3405 } 3406 } 3407 3408 /* 3409 * The EVEX prefix and "bound" instruction share the same first byte. 3410 * "bound" is only valid for 32-bit. For 64-bit this byte begins the 3411 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0. 3412 */ 3413 if (opcode1 == 0x6 && opcode2 == 0x2) { 3414 /* 3415 * An EVEX prefix is 4 bytes long, get the next 3 bytes. 3416 */ 3417 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3418 goto error; 3419 3420 if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) { 3421 /* 3422 * Upper bits in 2nd byte == 0 is 'bound' instn. 3423 * 3424 * We've already read the byte so perform the 3425 * equivalent of dtrace_get_modrm on the byte and set 3426 * the flag to indicate we've already read it. 3427 */ 3428 char b = (opcode4 << 4) | opcode5; 3429 3430 r_m = b & 0x7; 3431 reg = (b >> 3) & 0x7; 3432 mode = (b >> 6) & 0x3; 3433 vex_prefetch = 1; 3434 goto not_avx512; 3435 } 3436 3437 /* check for correct bits being 0 in 2nd byte */ 3438 if ((opcode5 & 0xc) != 0) 3439 goto error; 3440 3441 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3442 goto error; 3443 /* check for correct bit being 1 in 3rd byte */ 3444 if ((opcode7 & 0x4) == 0) 3445 goto error; 3446 3447 if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0) 3448 goto error; 3449 3450 /* Reuse opcode1 & opcode2 to get the real opcode now */ 3451 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3452 goto error; 3453 3454 /* 3455 * We only use the high nibble from the 2nd byte of the prefix 3456 * and save it in the low bits of evex_byte1. This is because 3457 * two of the bits in opcode5 are constant 0 (checked above), 3458 * and the other two bits are captured in vex_m. Also, the VEX 3459 * constants we check in evex_byte1 are against the low bits. 3460 */ 3461 evex_byte1 = opcode4; 3462 evex_byte2 = (opcode6 << 4) | opcode7; 3463 evex_byte3 = (opcode8 << 4) | opcode9; 3464 3465 vex_m = opcode5 & EVEX_m; 3466 vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3; 3467 vex_W = (opcode6 & VEX_W) >> 3; 3468 vex_p = opcode7 & VEX_p; 3469 3470 /* Currently only 3 valid values for evex L'L: 00, 01, 10 */ 3471 evex_L = (opcode8 & EVEX_L) >> 1; 3472 3473 dp = (instable_t *)&dis_opAVX62[(opcode1 << 4) | opcode2]; 3474 } 3475 not_avx512: 3476 3477 if (vex_prefix == VEX_2bytes) { 3478 if (!vex_prefetch) { 3479 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3480 goto error; 3481 } 3482 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 3483 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 3484 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 3485 vex_p = opcode4 & VEX_p; 3486 /* 3487 * The vex.x and vex.b bits are not defined in two bytes 3488 * mode vex prefix, their default values are 1 3489 */ 3490 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 3491 3492 if (vex_R == 0) 3493 x->d86_rex_prefix |= REX_R; 3494 3495 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3496 goto error; 3497 3498 switch (vex_p) { 3499 case VEX_p_66: 3500 dp = (instable_t *) 3501 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 3502 break; 3503 case VEX_p_F3: 3504 dp = (instable_t *) 3505 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 3506 break; 3507 case VEX_p_F2: 3508 dp = (instable_t *) 3509 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 3510 break; 3511 default: 3512 dp = (instable_t *) 3513 &dis_opAVX0F[opcode1][opcode2]; 3514 3515 } 3516 3517 } else if (vex_prefix == VEX_3bytes) { 3518 if (!vex_prefetch) { 3519 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3520 goto error; 3521 } 3522 vex_R = (opcode3 & VEX_R) >> 3; 3523 vex_X = (opcode3 & VEX_X) >> 2; 3524 vex_B = (opcode3 & VEX_B) >> 1; 3525 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 3526 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 3527 3528 if (vex_R == 0) 3529 x->d86_rex_prefix |= REX_R; 3530 if (vex_X == 0) 3531 x->d86_rex_prefix |= REX_X; 3532 if (vex_B == 0) 3533 x->d86_rex_prefix |= REX_B; 3534 3535 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 3536 goto error; 3537 vex_W = (opcode5 & VEX_W) >> 3; 3538 vex_L = (opcode6 & VEX_L) >> 2; 3539 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 3540 vex_p = opcode6 & VEX_p; 3541 3542 if (vex_W) 3543 x->d86_rex_prefix |= REX_W; 3544 3545 /* Only these three vex_m values valid; others are reserved */ 3546 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 3547 (vex_m != VEX_m_0F3A)) 3548 goto error; 3549 3550 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3551 goto error; 3552 3553 switch (vex_p) { 3554 case VEX_p_66: 3555 if (vex_m == VEX_m_0F) { 3556 dp = (instable_t *) 3557 &dis_opAVX660F 3558 [(opcode1 << 4) | opcode2]; 3559 } else if (vex_m == VEX_m_0F38) { 3560 dp = (instable_t *) 3561 &dis_opAVX660F38 3562 [(opcode1 << 4) | opcode2]; 3563 } else if (vex_m == VEX_m_0F3A) { 3564 dp = (instable_t *) 3565 &dis_opAVX660F3A 3566 [(opcode1 << 4) | opcode2]; 3567 } else { 3568 goto error; 3569 } 3570 break; 3571 case VEX_p_F3: 3572 if (vex_m == VEX_m_0F) { 3573 dp = (instable_t *) 3574 &dis_opAVXF30F 3575 [(opcode1 << 4) | opcode2]; 3576 } else if (vex_m == VEX_m_0F38) { 3577 dp = (instable_t *) 3578 &dis_opAVXF30F38 3579 [(opcode1 << 4) | opcode2]; 3580 } else { 3581 goto error; 3582 } 3583 break; 3584 case VEX_p_F2: 3585 if (vex_m == VEX_m_0F) { 3586 dp = (instable_t *) 3587 &dis_opAVXF20F 3588 [(opcode1 << 4) | opcode2]; 3589 } else if (vex_m == VEX_m_0F3A) { 3590 dp = (instable_t *) 3591 &dis_opAVXF20F3A 3592 [(opcode1 << 4) | opcode2]; 3593 } else if (vex_m == VEX_m_0F38) { 3594 dp = (instable_t *) 3595 &dis_opAVXF20F38 3596 [(opcode1 << 4) | opcode2]; 3597 } else { 3598 goto error; 3599 } 3600 break; 3601 default: 3602 dp = (instable_t *) 3603 &dis_opAVX0F[opcode1][opcode2]; 3604 3605 } 3606 } 3607 if (vex_prefix) { 3608 if (dp->it_vexwoxmm) { 3609 wbit = LONG_OPND; 3610 } else if (dp->it_vexopmask) { 3611 wbit = KOPMASK_OPND; 3612 } else { 3613 if (vex_L) { 3614 wbit = YMM_OPND; 3615 } else { 3616 wbit = XMM_OPND; 3617 } 3618 } 3619 } 3620 3621 /* 3622 * Deal with selection of operand and address size now. 3623 * Note that the REX.W bit being set causes opnd_size_prefix to be 3624 * ignored. 3625 */ 3626 if (cpu_mode == SIZE64) { 3627 if ((rex_prefix & REX_W) || vex_W) 3628 opnd_size = SIZE64; 3629 else if (opnd_size_prefix) 3630 opnd_size = SIZE16; 3631 3632 if (addr_size_prefix) 3633 addr_size = SIZE32; 3634 } else if (cpu_mode == SIZE32) { 3635 if (opnd_size_prefix) 3636 opnd_size = SIZE16; 3637 if (addr_size_prefix) 3638 addr_size = SIZE16; 3639 } else { 3640 if (opnd_size_prefix) 3641 opnd_size = SIZE32; 3642 if (addr_size_prefix) 3643 addr_size = SIZE32; 3644 } 3645 /* 3646 * The pause instruction - a repz'd nop. This doesn't fit 3647 * with any of the other prefix goop added for SSE, so we'll 3648 * special-case it here. 3649 */ 3650 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 3651 rep_prefix = 0; 3652 dp = (instable_t *)&dis_opPause; 3653 } 3654 3655 /* 3656 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 3657 * byte so we may need to perform a table indirection. 3658 */ 3659 if (dp->it_indirect == (instable_t *)dis_op0F) { 3660 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3661 goto error; 3662 opcode_bytes = 2; 3663 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 3664 uint_t subcode; 3665 3666 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3667 goto error; 3668 opcode_bytes = 3; 3669 subcode = ((opcode6 & 0x3) << 1) | 3670 ((opcode7 & 0x8) >> 3); 3671 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 3672 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 3673 dp = (instable_t *)&dis_op0FC8[0]; 3674 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 3675 opcode_bytes = 3; 3676 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3677 goto error; 3678 if (opnd_size == SIZE16) 3679 opnd_size = SIZE32; 3680 3681 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 3682 #ifdef DIS_TEXT 3683 if (strcmp(dp->it_name, "INVALID") == 0) 3684 goto error; 3685 #endif 3686 switch (dp->it_adrmode) { 3687 case XMMP: 3688 break; 3689 case XMMP_66r: 3690 case XMMPRM_66r: 3691 case XMM3PM_66r: 3692 if (opnd_size_prefix == 0) { 3693 goto error; 3694 } 3695 3696 break; 3697 case XMMP_66o: 3698 if (opnd_size_prefix == 0) { 3699 /* SSSE3 MMX instructions */ 3700 dp_mmx = *dp; 3701 dp = &dp_mmx; 3702 dp->it_adrmode = MMOPM_66o; 3703 #ifdef DIS_MEM 3704 dp->it_size = 8; 3705 #endif 3706 } 3707 break; 3708 default: 3709 goto error; 3710 } 3711 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 3712 opcode_bytes = 3; 3713 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3714 goto error; 3715 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 3716 3717 /* 3718 * Both crc32 and movbe have the same 3rd opcode 3719 * byte of either 0xF0 or 0xF1, so we use another 3720 * indirection to distinguish between the two. 3721 */ 3722 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 3723 dp->it_indirect == (instable_t *)dis_op0F38F1) { 3724 3725 dp = dp->it_indirect; 3726 if (rep_prefix != 0xF2) { 3727 /* It is movbe */ 3728 dp++; 3729 } 3730 } 3731 3732 /* 3733 * The adx family of instructions (adcx and adox) 3734 * continue the classic Intel tradition of abusing 3735 * arbitrary prefixes without actually meaning the 3736 * prefix bit. Therefore, if we find either the 3737 * opnd_size_prefix or rep_prefix we end up zeroing it 3738 * out after making our determination so as to ensure 3739 * that we don't get confused and accidentally print 3740 * repz prefixes and the like on these instructions. 3741 * 3742 * In addition, these instructions are actually much 3743 * closer to AVX instructions in semantics. Importantly, 3744 * they always default to having 32-bit operands. 3745 * However, if the CPU is in 64-bit mode, then and only 3746 * then, does it use REX.w promotes things to 64-bits 3747 * and REX.r allows 64-bit mode to use register r8-r15. 3748 */ 3749 if (dp->it_indirect == (instable_t *)dis_op0F38F6) { 3750 dp = dp->it_indirect; 3751 if (opnd_size_prefix == 0 && 3752 rep_prefix == 0xf3) { 3753 /* It is adox */ 3754 dp++; 3755 } else if (opnd_size_prefix != 0x66 && 3756 rep_prefix != 0) { 3757 /* It isn't adcx */ 3758 goto error; 3759 } 3760 opnd_size_prefix = 0; 3761 rep_prefix = 0; 3762 opnd_size = SIZE32; 3763 if (rex_prefix & REX_W) 3764 opnd_size = SIZE64; 3765 } 3766 3767 #ifdef DIS_TEXT 3768 if (strcmp(dp->it_name, "INVALID") == 0) 3769 goto error; 3770 #endif 3771 switch (dp->it_adrmode) { 3772 case ADX: 3773 case XMM: 3774 break; 3775 case RM_66r: 3776 case XMM_66r: 3777 case XMMM_66r: 3778 if (opnd_size_prefix == 0) { 3779 goto error; 3780 } 3781 break; 3782 case XMM_66o: 3783 if (opnd_size_prefix == 0) { 3784 /* SSSE3 MMX instructions */ 3785 dp_mmx = *dp; 3786 dp = &dp_mmx; 3787 dp->it_adrmode = MM; 3788 #ifdef DIS_MEM 3789 dp->it_size = 8; 3790 #endif 3791 } 3792 break; 3793 case CRC32: 3794 if (rep_prefix != 0xF2) { 3795 goto error; 3796 } 3797 rep_prefix = 0; 3798 break; 3799 case MOVBE: 3800 if (rep_prefix != 0x0) { 3801 goto error; 3802 } 3803 break; 3804 default: 3805 goto error; 3806 } 3807 } else { 3808 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 3809 } 3810 } 3811 3812 /* 3813 * If still not at a TERM decode entry, then a ModRM byte 3814 * exists and its fields further decode the instruction. 3815 */ 3816 x->d86_got_modrm = 0; 3817 if (dp->it_indirect != TERM) { 3818 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 3819 if (x->d86_error) 3820 goto error; 3821 reg = opcode3; 3822 3823 /* 3824 * decode 287 instructions (D8-DF) from opcodeN 3825 */ 3826 if (opcode1 == 0xD && opcode2 >= 0x8) { 3827 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 3828 dp = (instable_t *)&dis_opFP5[r_m]; 3829 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 3830 dp = (instable_t *)&dis_opFP7[opcode3]; 3831 else if (opcode2 == 0xB && mode == 0x3) 3832 dp = (instable_t *)&dis_opFP6[opcode3]; 3833 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 3834 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 3835 else if (mode == 0x3) 3836 dp = (instable_t *) 3837 &dis_opFP3[opcode2 - 8][opcode3]; 3838 else 3839 dp = (instable_t *) 3840 &dis_opFP1n2[opcode2 - 8][opcode3]; 3841 } else { 3842 dp = (instable_t *)dp->it_indirect + opcode3; 3843 } 3844 } 3845 3846 /* 3847 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 3848 * (sign extend 32bit to 64 bit) 3849 */ 3850 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 3851 opcode1 == 0x6 && opcode2 == 0x3) 3852 dp = (instable_t *)&dis_opMOVSLD; 3853 3854 /* 3855 * at this point we should have a correct (or invalid) opcode 3856 */ 3857 if (cpu_mode == SIZE64 && dp->it_invalid64 || 3858 cpu_mode != SIZE64 && dp->it_invalid32) 3859 goto error; 3860 if (dp->it_indirect != TERM) 3861 goto error; 3862 3863 /* 3864 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do 3865 * need to include UNKNOWN below, as we may have instructions that 3866 * actually have a prefix, but don't exist in any other form. 3867 */ 3868 switch (dp->it_adrmode) { 3869 case UNKNOWN: 3870 case MMO: 3871 case MMOIMPL: 3872 case MMO3P: 3873 case MMOM3: 3874 case MMOMS: 3875 case MMOPM: 3876 case MMOPRM: 3877 case MMOS: 3878 case XMMO: 3879 case XMMOM: 3880 case XMMOMS: 3881 case XMMOPM: 3882 case XMMOS: 3883 case XMMOMX: 3884 case XMMOX3: 3885 case XMMOXMM: 3886 /* 3887 * This is horrible. Some SIMD instructions take the 3888 * form 0x0F 0x?? ..., which is easily decoded using the 3889 * existing tables. Other SIMD instructions use various 3890 * prefix bytes to overload existing instructions. For 3891 * Example, addps is F0, 58, whereas addss is F3 (repz), 3892 * F0, 58. Presumably someone got a raise for this. 3893 * 3894 * If we see one of the instructions which can be 3895 * modified in this way (if we've got one of the SIMDO* 3896 * address modes), we'll check to see if the last prefix 3897 * was a repz. If it was, we strip the prefix from the 3898 * mnemonic, and we indirect using the dis_opSIMDrepz 3899 * table. 3900 */ 3901 3902 /* 3903 * Calculate our offset in dis_op0F 3904 */ 3905 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 3906 goto error; 3907 3908 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3909 sizeof (instable_t); 3910 3911 /* 3912 * Rewrite if this instruction used one of the magic prefixes. 3913 */ 3914 if (rep_prefix) { 3915 if (rep_prefix == 0xf2) 3916 dp = (instable_t *)&dis_opSIMDrepnz[off]; 3917 else 3918 dp = (instable_t *)&dis_opSIMDrepz[off]; 3919 rep_prefix = 0; 3920 } else if (opnd_size_prefix) { 3921 dp = (instable_t *)&dis_opSIMDdata16[off]; 3922 opnd_size_prefix = 0; 3923 if (opnd_size == SIZE16) 3924 opnd_size = SIZE32; 3925 } 3926 break; 3927 3928 case MG9: 3929 /* 3930 * More horribleness: the group 9 (0xF0 0xC7) instructions are 3931 * allowed an optional prefix of 0x66 or 0xF3. This is similar 3932 * to the SIMD business described above, but with a different 3933 * addressing mode (and an indirect table), so we deal with it 3934 * separately (if similarly). 3935 * 3936 * Intel further complicated this with the release of Ivy Bridge 3937 * where they overloaded these instructions based on the ModR/M 3938 * bytes. The VMX instructions have a mode of 0 since they are 3939 * memory instructions but rdrand instructions have a mode of 3940 * 0b11 (REG_ONLY) because they only operate on registers. While 3941 * there are different prefix formats, for now it is sufficient 3942 * to use a single different table. 3943 */ 3944 3945 /* 3946 * Calculate our offset in dis_op0FC7 (the group 9 table) 3947 */ 3948 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 3949 goto error; 3950 3951 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 3952 sizeof (instable_t); 3953 3954 /* 3955 * If we have a mode of 0b11 then we have to rewrite this. 3956 */ 3957 dtrace_get_modrm(x, &mode, ®, &r_m); 3958 if (mode == REG_ONLY) { 3959 dp = (instable_t *)&dis_op0FC7m3[off]; 3960 break; 3961 } 3962 3963 /* 3964 * Rewrite if this instruction used one of the magic prefixes. 3965 */ 3966 if (rep_prefix) { 3967 if (rep_prefix == 0xf3) 3968 dp = (instable_t *)&dis_opF30FC7[off]; 3969 else 3970 goto error; 3971 rep_prefix = 0; 3972 } else if (opnd_size_prefix) { 3973 dp = (instable_t *)&dis_op660FC7[off]; 3974 opnd_size_prefix = 0; 3975 if (opnd_size == SIZE16) 3976 opnd_size = SIZE32; 3977 } else if (reg == 4 || reg == 5) { 3978 /* 3979 * We have xsavec (4) or xsaves (5), so rewrite. 3980 */ 3981 dp = (instable_t *)&dis_op0FC7[reg]; 3982 break; 3983 } 3984 break; 3985 3986 3987 case MMOSH: 3988 /* 3989 * As with the "normal" SIMD instructions, the MMX 3990 * shuffle instructions are overloaded. These 3991 * instructions, however, are special in that they use 3992 * an extra byte, and thus an extra table. As of this 3993 * writing, they only use the opnd_size prefix. 3994 */ 3995 3996 /* 3997 * Calculate our offset in dis_op0F7123 3998 */ 3999 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 4000 sizeof (dis_op0F7123)) 4001 goto error; 4002 4003 if (opnd_size_prefix) { 4004 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 4005 sizeof (instable_t); 4006 dp = (instable_t *)&dis_opSIMD7123[off]; 4007 opnd_size_prefix = 0; 4008 if (opnd_size == SIZE16) 4009 opnd_size = SIZE32; 4010 } 4011 break; 4012 case MRw: 4013 if (rep_prefix) { 4014 if (rep_prefix == 0xf3) { 4015 4016 /* 4017 * Calculate our offset in dis_op0F 4018 */ 4019 if ((uintptr_t)dp - (uintptr_t)dis_op0F 4020 > sizeof (dis_op0F)) 4021 goto error; 4022 4023 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4024 sizeof (instable_t); 4025 4026 dp = (instable_t *)&dis_opSIMDrepz[off]; 4027 rep_prefix = 0; 4028 } else { 4029 goto error; 4030 } 4031 } 4032 break; 4033 } 4034 4035 /* 4036 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 4037 */ 4038 if (cpu_mode == SIZE64) 4039 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 4040 opnd_size = SIZE64; 4041 4042 #ifdef DIS_TEXT 4043 /* 4044 * At this point most instructions can format the opcode mnemonic 4045 * including the prefixes. 4046 */ 4047 if (lock_prefix) 4048 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 4049 4050 if (rep_prefix == 0xf2) 4051 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 4052 else if (rep_prefix == 0xf3) 4053 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 4054 4055 if (cpu_mode == SIZE64 && addr_size_prefix) 4056 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 4057 4058 if (dp->it_adrmode != CBW && 4059 dp->it_adrmode != CWD && 4060 dp->it_adrmode != XMMSFNC) { 4061 if (strcmp(dp->it_name, "INVALID") == 0) 4062 goto error; 4063 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 4064 if (dp->it_avxsuf == AVS2 && dp->it_suffix) { 4065 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 4066 OPLEN); 4067 } else if (dp->it_vexopmask && dp->it_suffix) { 4068 /* opmask instructions */ 4069 4070 if (opcode1 == 4 && opcode2 == 0xb) { 4071 /* It's a kunpck. */ 4072 if (vex_prefix == VEX_2bytes) { 4073 (void) strlcat(x->d86_mnem, 4074 vex_p == 0 ? "wd" : "bw", OPLEN); 4075 } else { 4076 /* vex_prefix == VEX_3bytes */ 4077 (void) strlcat(x->d86_mnem, 4078 "dq", OPLEN); 4079 } 4080 } else if (opcode1 == 3) { 4081 /* It's a kshift[l|r]. */ 4082 if (vex_W == 0) { 4083 (void) strlcat(x->d86_mnem, 4084 opcode2 == 2 || 4085 opcode2 == 0 ? 4086 "b" : "d", OPLEN); 4087 } else { 4088 /* W == 1 */ 4089 (void) strlcat(x->d86_mnem, 4090 opcode2 == 3 || opcode2 == 1 ? 4091 "q" : "w", OPLEN); 4092 } 4093 } else { 4094 /* if (vex_prefix == VEX_2bytes) { */ 4095 if ((cpu_mode == SIZE64 && opnd_size == 2) || 4096 vex_prefix == VEX_2bytes) { 4097 (void) strlcat(x->d86_mnem, 4098 vex_p == 0 ? "w" : 4099 vex_p == 1 ? "b" : "d", 4100 OPLEN); 4101 } else { 4102 /* vex_prefix == VEX_3bytes */ 4103 (void) strlcat(x->d86_mnem, 4104 vex_p == 1 ? "d" : "q", OPLEN); 4105 } 4106 } 4107 } else if (dp->it_suffix) { 4108 char *types[] = {"", "w", "l", "q"}; 4109 if (opcode_bytes == 2 && opcode4 == 4) { 4110 /* It's a cmovx.yy. Replace the suffix x */ 4111 for (i = 5; i < OPLEN; i++) { 4112 if (x->d86_mnem[i] == '.') 4113 break; 4114 } 4115 x->d86_mnem[i - 1] = *types[opnd_size]; 4116 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 4117 ((opcode6 == 1 && opcode7 == 6) || 4118 (opcode6 == 2 && opcode7 == 2))) { 4119 /* 4120 * To handle PINSRD and PEXTRD 4121 */ 4122 (void) strlcat(x->d86_mnem, "d", OPLEN); 4123 } else if (dp != &dis_distable[0x6][0x2]) { 4124 /* bound instructions (0x62) have no suffix */ 4125 (void) strlcat(x->d86_mnem, types[opnd_size], 4126 OPLEN); 4127 } 4128 } 4129 } 4130 #endif 4131 4132 /* 4133 * Process operands based on the addressing modes. 4134 */ 4135 x->d86_mode = cpu_mode; 4136 /* 4137 * In vex mode the rex_prefix has no meaning 4138 */ 4139 if (!vex_prefix) 4140 x->d86_rex_prefix = rex_prefix; 4141 x->d86_opnd_size = opnd_size; 4142 x->d86_addr_size = addr_size; 4143 vbit = 0; /* initialize for mem/reg -> reg */ 4144 switch (dp->it_adrmode) { 4145 /* 4146 * amd64 instruction to sign extend 32 bit reg/mem operands 4147 * into 64 bit register values 4148 */ 4149 case MOVSXZ: 4150 #ifdef DIS_TEXT 4151 if (rex_prefix == 0) 4152 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 4153 #endif 4154 dtrace_get_modrm(x, &mode, ®, &r_m); 4155 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4156 x->d86_opnd_size = SIZE64; 4157 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4158 x->d86_opnd_size = opnd_size = SIZE32; 4159 wbit = LONG_OPND; 4160 dtrace_get_operand(x, mode, r_m, wbit, 0); 4161 break; 4162 4163 /* 4164 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 4165 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 4166 * wbit lives in 2nd byte, note that operands 4167 * are different sized 4168 */ 4169 case MOVZ: 4170 if (rex_prefix & REX_W) { 4171 /* target register size = 64 bit */ 4172 x->d86_mnem[5] = 'q'; 4173 } 4174 dtrace_get_modrm(x, &mode, ®, &r_m); 4175 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4176 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4177 x->d86_opnd_size = opnd_size = SIZE16; 4178 wbit = WBIT(opcode5); 4179 dtrace_get_operand(x, mode, r_m, wbit, 0); 4180 break; 4181 case CRC32: 4182 opnd_size = SIZE32; 4183 if (rex_prefix & REX_W) 4184 opnd_size = SIZE64; 4185 x->d86_opnd_size = opnd_size; 4186 4187 dtrace_get_modrm(x, &mode, ®, &r_m); 4188 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4189 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4190 wbit = WBIT(opcode7); 4191 if (opnd_size_prefix) 4192 x->d86_opnd_size = opnd_size = SIZE16; 4193 dtrace_get_operand(x, mode, r_m, wbit, 0); 4194 break; 4195 case MOVBE: 4196 opnd_size = SIZE32; 4197 if (rex_prefix & REX_W) 4198 opnd_size = SIZE64; 4199 x->d86_opnd_size = opnd_size; 4200 4201 dtrace_get_modrm(x, &mode, ®, &r_m); 4202 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4203 wbit = WBIT(opcode7); 4204 if (opnd_size_prefix) 4205 x->d86_opnd_size = opnd_size = SIZE16; 4206 if (wbit) { 4207 /* reg -> mem */ 4208 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4209 dtrace_get_operand(x, mode, r_m, wbit, 1); 4210 } else { 4211 /* mem -> reg */ 4212 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4213 dtrace_get_operand(x, mode, r_m, wbit, 0); 4214 } 4215 break; 4216 4217 /* 4218 * imul instruction, with either 8-bit or longer immediate 4219 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 4220 */ 4221 case IMUL: 4222 wbit = LONG_OPND; 4223 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 4224 OPSIZE(opnd_size, opcode2 == 0x9), 1); 4225 break; 4226 4227 /* memory or register operand to register, with 'w' bit */ 4228 case MRw: 4229 case ADX: 4230 wbit = WBIT(opcode2); 4231 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4232 break; 4233 4234 /* register to memory or register operand, with 'w' bit */ 4235 /* arpl happens to fit here also because it is odd */ 4236 case RMw: 4237 if (opcode_bytes == 2) 4238 wbit = WBIT(opcode5); 4239 else 4240 wbit = WBIT(opcode2); 4241 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4242 break; 4243 4244 /* xaddb instruction */ 4245 case XADDB: 4246 wbit = 0; 4247 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4248 break; 4249 4250 /* MMX register to memory or register operand */ 4251 case MMS: 4252 case MMOS: 4253 #ifdef DIS_TEXT 4254 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4255 #else 4256 wbit = LONG_OPND; 4257 #endif 4258 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4259 break; 4260 4261 /* MMX register to memory */ 4262 case MMOMS: 4263 dtrace_get_modrm(x, &mode, ®, &r_m); 4264 if (mode == REG_ONLY) 4265 goto error; 4266 wbit = MM_OPND; 4267 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4268 break; 4269 4270 /* Double shift. Has immediate operand specifying the shift. */ 4271 case DSHIFT: 4272 wbit = LONG_OPND; 4273 dtrace_get_modrm(x, &mode, ®, &r_m); 4274 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4275 dtrace_get_operand(x, mode, r_m, wbit, 2); 4276 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4277 dtrace_imm_opnd(x, wbit, 1, 0); 4278 break; 4279 4280 /* 4281 * Double shift. With no immediate operand, specifies using %cl. 4282 */ 4283 case DSHIFTcl: 4284 wbit = LONG_OPND; 4285 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4286 break; 4287 4288 /* immediate to memory or register operand */ 4289 case IMlw: 4290 wbit = WBIT(opcode2); 4291 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4292 dtrace_get_operand(x, mode, r_m, wbit, 1); 4293 /* 4294 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 4295 */ 4296 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 4297 break; 4298 4299 /* immediate to memory or register operand with the */ 4300 /* 'w' bit present */ 4301 case IMw: 4302 wbit = WBIT(opcode2); 4303 dtrace_get_modrm(x, &mode, ®, &r_m); 4304 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4305 dtrace_get_operand(x, mode, r_m, wbit, 1); 4306 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4307 break; 4308 4309 /* immediate to register with register in low 3 bits */ 4310 /* of op code */ 4311 case IR: 4312 /* w-bit here (with regs) is bit 3 */ 4313 wbit = opcode2 >>3 & 0x1; 4314 reg = REGNO(opcode2); 4315 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4316 mode = REG_ONLY; 4317 r_m = reg; 4318 dtrace_get_operand(x, mode, r_m, wbit, 1); 4319 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 4320 break; 4321 4322 /* MMX immediate shift of register */ 4323 case MMSH: 4324 case MMOSH: 4325 wbit = MM_OPND; 4326 goto mm_shift; /* in next case */ 4327 4328 /* SIMD immediate shift of register */ 4329 case XMMSH: 4330 wbit = XMM_OPND; 4331 mm_shift: 4332 reg = REGNO(opcode7); 4333 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4334 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4335 dtrace_imm_opnd(x, wbit, 1, 0); 4336 NOMEM; 4337 break; 4338 4339 /* accumulator to memory operand */ 4340 case AO: 4341 vbit = 1; 4342 /*FALLTHROUGH*/ 4343 4344 /* memory operand to accumulator */ 4345 case OA: 4346 wbit = WBIT(opcode2); 4347 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 4348 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 4349 #ifdef DIS_TEXT 4350 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 4351 #endif 4352 break; 4353 4354 4355 /* segment register to memory or register operand */ 4356 case SM: 4357 vbit = 1; 4358 /*FALLTHROUGH*/ 4359 4360 /* memory or register operand to segment register */ 4361 case MS: 4362 dtrace_get_modrm(x, &mode, ®, &r_m); 4363 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4364 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 4365 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 4366 break; 4367 4368 /* 4369 * rotate or shift instructions, which may shift by 1 or 4370 * consult the cl register, depending on the 'v' bit 4371 */ 4372 case Mv: 4373 vbit = VBIT(opcode2); 4374 wbit = WBIT(opcode2); 4375 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4376 dtrace_get_operand(x, mode, r_m, wbit, 1); 4377 #ifdef DIS_TEXT 4378 if (vbit) { 4379 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 4380 } else { 4381 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4382 x->d86_opnd[0].d86_value_size = 1; 4383 x->d86_opnd[0].d86_value = 1; 4384 } 4385 #endif 4386 break; 4387 /* 4388 * immediate rotate or shift instructions 4389 */ 4390 case MvI: 4391 wbit = WBIT(opcode2); 4392 normal_imm_mem: 4393 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4394 dtrace_get_operand(x, mode, r_m, wbit, 1); 4395 dtrace_imm_opnd(x, wbit, 1, 0); 4396 break; 4397 4398 /* bit test instructions */ 4399 case MIb: 4400 wbit = LONG_OPND; 4401 goto normal_imm_mem; 4402 4403 /* single memory or register operand with 'w' bit present */ 4404 case Mw: 4405 wbit = WBIT(opcode2); 4406 just_mem: 4407 dtrace_get_modrm(x, &mode, ®, &r_m); 4408 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4409 dtrace_get_operand(x, mode, r_m, wbit, 0); 4410 break; 4411 4412 case SWAPGS_RDTSCP: 4413 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 4414 #ifdef DIS_TEXT 4415 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 4416 #endif 4417 NOMEM; 4418 break; 4419 } else if (mode == 3 && r_m == 1) { 4420 #ifdef DIS_TEXT 4421 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 4422 #endif 4423 NOMEM; 4424 break; 4425 } 4426 4427 /*FALLTHROUGH*/ 4428 4429 /* prefetch instruction - memory operand, but no memory acess */ 4430 case PREF: 4431 NOMEM; 4432 /*FALLTHROUGH*/ 4433 4434 /* single memory or register operand */ 4435 case M: 4436 case MG9: 4437 wbit = LONG_OPND; 4438 goto just_mem; 4439 4440 /* single memory or register byte operand */ 4441 case Mb: 4442 wbit = BYTE_OPND; 4443 goto just_mem; 4444 4445 case VMx: 4446 if (mode == 3) { 4447 #ifdef DIS_TEXT 4448 char *vminstr; 4449 4450 switch (r_m) { 4451 case 1: 4452 vminstr = "vmcall"; 4453 break; 4454 case 2: 4455 vminstr = "vmlaunch"; 4456 break; 4457 case 3: 4458 vminstr = "vmresume"; 4459 break; 4460 case 4: 4461 vminstr = "vmxoff"; 4462 break; 4463 default: 4464 goto error; 4465 } 4466 4467 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 4468 #else 4469 if (r_m < 1 || r_m > 4) 4470 goto error; 4471 #endif 4472 4473 NOMEM; 4474 break; 4475 } 4476 /*FALLTHROUGH*/ 4477 case SVM: 4478 if (mode == 3) { 4479 #if DIS_TEXT 4480 char *vinstr; 4481 4482 switch (r_m) { 4483 case 0: 4484 vinstr = "vmrun"; 4485 break; 4486 case 1: 4487 vinstr = "vmmcall"; 4488 break; 4489 case 2: 4490 vinstr = "vmload"; 4491 break; 4492 case 3: 4493 vinstr = "vmsave"; 4494 break; 4495 case 4: 4496 vinstr = "stgi"; 4497 break; 4498 case 5: 4499 vinstr = "clgi"; 4500 break; 4501 case 6: 4502 vinstr = "skinit"; 4503 break; 4504 case 7: 4505 vinstr = "invlpga"; 4506 break; 4507 } 4508 4509 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 4510 #endif 4511 NOMEM; 4512 break; 4513 } 4514 /*FALLTHROUGH*/ 4515 case MONITOR_MWAIT: 4516 if (mode == 3) { 4517 if (r_m == 0) { 4518 #ifdef DIS_TEXT 4519 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 4520 #endif 4521 NOMEM; 4522 break; 4523 } else if (r_m == 1) { 4524 #ifdef DIS_TEXT 4525 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 4526 #endif 4527 NOMEM; 4528 break; 4529 } else if (r_m == 2) { 4530 #ifdef DIS_TEXT 4531 (void) strncpy(x->d86_mnem, "clac", OPLEN); 4532 #endif 4533 NOMEM; 4534 break; 4535 } else if (r_m == 3) { 4536 #ifdef DIS_TEXT 4537 (void) strncpy(x->d86_mnem, "stac", OPLEN); 4538 #endif 4539 NOMEM; 4540 break; 4541 } else { 4542 goto error; 4543 } 4544 } 4545 /*FALLTHROUGH*/ 4546 case XGETBV_XSETBV: 4547 if (mode == 3) { 4548 if (r_m == 0) { 4549 #ifdef DIS_TEXT 4550 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 4551 #endif 4552 NOMEM; 4553 break; 4554 } else if (r_m == 1) { 4555 #ifdef DIS_TEXT 4556 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 4557 #endif 4558 NOMEM; 4559 break; 4560 } else { 4561 goto error; 4562 } 4563 4564 } 4565 /*FALLTHROUGH*/ 4566 case MO: 4567 /* Similar to M, but only memory (no direct registers) */ 4568 wbit = LONG_OPND; 4569 dtrace_get_modrm(x, &mode, ®, &r_m); 4570 if (mode == 3) 4571 goto error; 4572 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4573 dtrace_get_operand(x, mode, r_m, wbit, 0); 4574 break; 4575 4576 /* move special register to register or reverse if vbit */ 4577 case SREG: 4578 switch (opcode5) { 4579 4580 case 2: 4581 vbit = 1; 4582 /*FALLTHROUGH*/ 4583 case 0: 4584 wbit = CONTROL_OPND; 4585 break; 4586 4587 case 3: 4588 vbit = 1; 4589 /*FALLTHROUGH*/ 4590 case 1: 4591 wbit = DEBUG_OPND; 4592 break; 4593 4594 case 6: 4595 vbit = 1; 4596 /*FALLTHROUGH*/ 4597 case 4: 4598 wbit = TEST_OPND; 4599 break; 4600 4601 } 4602 dtrace_get_modrm(x, &mode, ®, &r_m); 4603 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4604 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 4605 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 4606 NOMEM; 4607 break; 4608 4609 /* 4610 * single register operand with register in the low 3 4611 * bits of op code 4612 */ 4613 case R: 4614 if (opcode_bytes == 2) 4615 reg = REGNO(opcode5); 4616 else 4617 reg = REGNO(opcode2); 4618 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4619 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4620 NOMEM; 4621 break; 4622 4623 /* 4624 * register to accumulator with register in the low 3 4625 * bits of op code, xchg instructions 4626 */ 4627 case RA: 4628 NOMEM; 4629 reg = REGNO(opcode2); 4630 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4631 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4632 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 4633 break; 4634 4635 /* 4636 * single segment register operand, with register in 4637 * bits 3-4 of op code byte 4638 */ 4639 case SEG: 4640 NOMEM; 4641 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 4642 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4643 break; 4644 4645 /* 4646 * single segment register operand, with register in 4647 * bits 3-5 of op code 4648 */ 4649 case LSEG: 4650 NOMEM; 4651 /* long seg reg from opcode */ 4652 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 4653 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4654 break; 4655 4656 /* memory or register operand to register */ 4657 case MR: 4658 if (vex_prefetch) 4659 x->d86_got_modrm = 1; 4660 wbit = LONG_OPND; 4661 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4662 break; 4663 4664 case RM: 4665 case RM_66r: 4666 if (vex_prefetch) 4667 x->d86_got_modrm = 1; 4668 wbit = LONG_OPND; 4669 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4670 break; 4671 4672 /* MMX/SIMD-Int memory or mm reg to mm reg */ 4673 case MM: 4674 case MMO: 4675 #ifdef DIS_TEXT 4676 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4677 #else 4678 wbit = LONG_OPND; 4679 #endif 4680 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4681 break; 4682 4683 case MMOIMPL: 4684 #ifdef DIS_TEXT 4685 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4686 #else 4687 wbit = LONG_OPND; 4688 #endif 4689 dtrace_get_modrm(x, &mode, ®, &r_m); 4690 if (mode != REG_ONLY) 4691 goto error; 4692 4693 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4694 dtrace_get_operand(x, mode, r_m, wbit, 0); 4695 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 4696 mode = 0; /* change for memory access size... */ 4697 break; 4698 4699 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 4700 case MMO3P: 4701 wbit = MM_OPND; 4702 goto xmm3p; 4703 case XMM3P: 4704 wbit = XMM_OPND; 4705 xmm3p: 4706 dtrace_get_modrm(x, &mode, ®, &r_m); 4707 if (mode != REG_ONLY) 4708 goto error; 4709 4710 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 4711 1); 4712 NOMEM; 4713 break; 4714 4715 case XMM3PM_66r: 4716 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 4717 1, 0); 4718 break; 4719 4720 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 4721 case MMOPRM: 4722 wbit = LONG_OPND; 4723 w2 = MM_OPND; 4724 goto xmmprm; 4725 case XMMPRM: 4726 case XMMPRM_66r: 4727 wbit = LONG_OPND; 4728 w2 = XMM_OPND; 4729 xmmprm: 4730 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 4731 break; 4732 4733 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 4734 case MMOPM: 4735 case MMOPM_66o: 4736 wbit = w2 = MM_OPND; 4737 goto xmmprm; 4738 4739 /* MMX/SIMD-Int mm reg to r32 */ 4740 case MMOM3: 4741 NOMEM; 4742 dtrace_get_modrm(x, &mode, ®, &r_m); 4743 if (mode != REG_ONLY) 4744 goto error; 4745 wbit = MM_OPND; 4746 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4747 break; 4748 4749 /* SIMD memory or xmm reg operand to xmm reg */ 4750 case XMM: 4751 case XMM_66o: 4752 case XMM_66r: 4753 case XMMO: 4754 case XMMXIMPL: 4755 wbit = XMM_OPND; 4756 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4757 4758 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 4759 goto error; 4760 4761 #ifdef DIS_TEXT 4762 /* 4763 * movlps and movhlps share opcodes. They differ in the 4764 * addressing modes allowed for their operands. 4765 * movhps and movlhps behave similarly. 4766 */ 4767 if (mode == REG_ONLY) { 4768 if (strcmp(dp->it_name, "movlps") == 0) 4769 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 4770 else if (strcmp(dp->it_name, "movhps") == 0) 4771 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4772 } 4773 #endif 4774 if (dp->it_adrmode == XMMXIMPL) 4775 mode = 0; /* change for memory access size... */ 4776 break; 4777 4778 /* SIMD xmm reg to memory or xmm reg */ 4779 case XMMS: 4780 case XMMOS: 4781 case XMMMS: 4782 case XMMOMS: 4783 dtrace_get_modrm(x, &mode, ®, &r_m); 4784 #ifdef DIS_TEXT 4785 if ((strcmp(dp->it_name, "movlps") == 0 || 4786 strcmp(dp->it_name, "movhps") == 0 || 4787 strcmp(dp->it_name, "movntps") == 0) && 4788 mode == REG_ONLY) 4789 goto error; 4790 #endif 4791 wbit = XMM_OPND; 4792 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4793 break; 4794 4795 /* SIMD memory to xmm reg */ 4796 case XMMM: 4797 case XMMM_66r: 4798 case XMMOM: 4799 wbit = XMM_OPND; 4800 dtrace_get_modrm(x, &mode, ®, &r_m); 4801 #ifdef DIS_TEXT 4802 if (mode == REG_ONLY) { 4803 if (strcmp(dp->it_name, "movhps") == 0) 4804 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4805 else 4806 goto error; 4807 } 4808 #endif 4809 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4810 break; 4811 4812 /* SIMD memory or r32 to xmm reg */ 4813 case XMM3MX: 4814 wbit = LONG_OPND; 4815 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4816 break; 4817 4818 case XMM3MXS: 4819 wbit = LONG_OPND; 4820 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4821 break; 4822 4823 /* SIMD memory or mm reg to xmm reg */ 4824 case XMMOMX: 4825 /* SIMD mm to xmm */ 4826 case XMMMX: 4827 wbit = MM_OPND; 4828 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4829 break; 4830 4831 /* SIMD memory or xmm reg to mm reg */ 4832 case XMMXMM: 4833 case XMMOXMM: 4834 case XMMXM: 4835 wbit = XMM_OPND; 4836 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4837 break; 4838 4839 4840 /* SIMD memory or xmm reg to r32 */ 4841 case XMMXM3: 4842 wbit = XMM_OPND; 4843 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4844 break; 4845 4846 /* SIMD xmm to r32 */ 4847 case XMMX3: 4848 case XMMOX3: 4849 dtrace_get_modrm(x, &mode, ®, &r_m); 4850 if (mode != REG_ONLY) 4851 goto error; 4852 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4853 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 4854 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4855 NOMEM; 4856 break; 4857 4858 /* SIMD predicated memory or xmm reg with/to xmm reg */ 4859 case XMMP: 4860 case XMMP_66r: 4861 case XMMP_66o: 4862 case XMMOPM: 4863 wbit = XMM_OPND; 4864 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 4865 1); 4866 4867 #ifdef DIS_TEXT 4868 /* 4869 * cmpps and cmpss vary their instruction name based 4870 * on the value of imm8. Other XMMP instructions, 4871 * such as shufps, require explicit specification of 4872 * the predicate. 4873 */ 4874 if (dp->it_name[0] == 'c' && 4875 dp->it_name[1] == 'm' && 4876 dp->it_name[2] == 'p' && 4877 strlen(dp->it_name) == 5) { 4878 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 4879 4880 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 4881 goto error; 4882 4883 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 4884 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 4885 OPLEN); 4886 (void) strlcat(x->d86_mnem, 4887 dp->it_name + strlen(dp->it_name) - 2, 4888 OPLEN); 4889 x->d86_opnd[0] = x->d86_opnd[1]; 4890 x->d86_opnd[1] = x->d86_opnd[2]; 4891 x->d86_numopnds = 2; 4892 } 4893 4894 /* 4895 * The pclmulqdq instruction has a series of alternate names for 4896 * various encodings of the immediate byte. As such, if we 4897 * happen to find it and the immediate value matches, we'll 4898 * rewrite the mnemonic. 4899 */ 4900 if (strcmp(dp->it_name, "pclmulqdq") == 0) { 4901 boolean_t changed = B_TRUE; 4902 switch (x->d86_opnd[0].d86_value) { 4903 case 0x00: 4904 (void) strncpy(x->d86_mnem, "pclmullqlqdq", 4905 OPLEN); 4906 break; 4907 case 0x01: 4908 (void) strncpy(x->d86_mnem, "pclmulhqlqdq", 4909 OPLEN); 4910 break; 4911 case 0x10: 4912 (void) strncpy(x->d86_mnem, "pclmullqhqdq", 4913 OPLEN); 4914 break; 4915 case 0x11: 4916 (void) strncpy(x->d86_mnem, "pclmulhqhqdq", 4917 OPLEN); 4918 break; 4919 default: 4920 changed = B_FALSE; 4921 break; 4922 } 4923 4924 if (changed == B_TRUE) { 4925 x->d86_opnd[0].d86_value_size = 0; 4926 x->d86_opnd[0] = x->d86_opnd[1]; 4927 x->d86_opnd[1] = x->d86_opnd[2]; 4928 x->d86_numopnds = 2; 4929 } 4930 } 4931 #endif 4932 break; 4933 4934 case XMMX2I: 4935 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 4936 1); 4937 NOMEM; 4938 break; 4939 4940 case XMM2I: 4941 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 4942 NOMEM; 4943 break; 4944 4945 /* immediate operand to accumulator */ 4946 case IA: 4947 wbit = WBIT(opcode2); 4948 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4949 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4950 NOMEM; 4951 break; 4952 4953 /* memory or register operand to accumulator */ 4954 case MA: 4955 wbit = WBIT(opcode2); 4956 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4957 dtrace_get_operand(x, mode, r_m, wbit, 0); 4958 break; 4959 4960 /* si register to di register used to reference memory */ 4961 case SD: 4962 #ifdef DIS_TEXT 4963 dtrace_check_override(x, 0); 4964 x->d86_numopnds = 2; 4965 if (addr_size == SIZE64) { 4966 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 4967 OPLEN); 4968 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 4969 OPLEN); 4970 } else if (addr_size == SIZE32) { 4971 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 4972 OPLEN); 4973 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 4974 OPLEN); 4975 } else { 4976 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 4977 OPLEN); 4978 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 4979 OPLEN); 4980 } 4981 #endif 4982 wbit = LONG_OPND; 4983 break; 4984 4985 /* accumulator to di register */ 4986 case AD: 4987 wbit = WBIT(opcode2); 4988 #ifdef DIS_TEXT 4989 dtrace_check_override(x, 1); 4990 x->d86_numopnds = 2; 4991 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 4992 if (addr_size == SIZE64) 4993 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 4994 OPLEN); 4995 else if (addr_size == SIZE32) 4996 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 4997 OPLEN); 4998 else 4999 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5000 OPLEN); 5001 #endif 5002 break; 5003 5004 /* si register to accumulator */ 5005 case SA: 5006 wbit = WBIT(opcode2); 5007 #ifdef DIS_TEXT 5008 dtrace_check_override(x, 0); 5009 x->d86_numopnds = 2; 5010 if (addr_size == SIZE64) 5011 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5012 OPLEN); 5013 else if (addr_size == SIZE32) 5014 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5015 OPLEN); 5016 else 5017 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5018 OPLEN); 5019 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5020 #endif 5021 break; 5022 5023 /* 5024 * single operand, a 16/32 bit displacement 5025 */ 5026 case D: 5027 wbit = LONG_OPND; 5028 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5029 NOMEM; 5030 break; 5031 5032 /* jmp/call indirect to memory or register operand */ 5033 case INM: 5034 #ifdef DIS_TEXT 5035 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 5036 #endif 5037 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5038 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5039 wbit = LONG_OPND; 5040 break; 5041 5042 /* 5043 * for long jumps and long calls -- a new code segment 5044 * register and an offset in IP -- stored in object 5045 * code in reverse order. Note - not valid in amd64 5046 */ 5047 case SO: 5048 dtrace_check_override(x, 1); 5049 wbit = LONG_OPND; 5050 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 5051 #ifdef DIS_TEXT 5052 x->d86_opnd[1].d86_mode = MODE_SIGNED; 5053 #endif 5054 /* will now get segment operand */ 5055 dtrace_imm_opnd(x, wbit, 2, 0); 5056 break; 5057 5058 /* 5059 * jmp/call. single operand, 8 bit displacement. 5060 * added to current EIP in 'compofff' 5061 */ 5062 case BD: 5063 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 5064 NOMEM; 5065 break; 5066 5067 /* single 32/16 bit immediate operand */ 5068 case I: 5069 wbit = LONG_OPND; 5070 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5071 break; 5072 5073 /* single 8 bit immediate operand */ 5074 case Ib: 5075 wbit = LONG_OPND; 5076 dtrace_imm_opnd(x, wbit, 1, 0); 5077 break; 5078 5079 case ENTER: 5080 wbit = LONG_OPND; 5081 dtrace_imm_opnd(x, wbit, 2, 0); 5082 dtrace_imm_opnd(x, wbit, 1, 1); 5083 switch (opnd_size) { 5084 case SIZE64: 5085 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 5086 break; 5087 case SIZE32: 5088 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 5089 break; 5090 case SIZE16: 5091 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 5092 break; 5093 } 5094 5095 break; 5096 5097 /* 16-bit immediate operand */ 5098 case RET: 5099 wbit = LONG_OPND; 5100 dtrace_imm_opnd(x, wbit, 2, 0); 5101 break; 5102 5103 /* single 8 bit port operand */ 5104 case P: 5105 dtrace_check_override(x, 0); 5106 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5107 NOMEM; 5108 break; 5109 5110 /* single operand, dx register (variable port instruction) */ 5111 case V: 5112 x->d86_numopnds = 1; 5113 dtrace_check_override(x, 0); 5114 #ifdef DIS_TEXT 5115 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 5116 #endif 5117 NOMEM; 5118 break; 5119 5120 /* 5121 * The int instruction, which has two forms: 5122 * int 3 (breakpoint) or 5123 * int n, where n is indicated in the subsequent 5124 * byte (format Ib). The int 3 instruction (opcode 0xCC), 5125 * where, although the 3 looks like an operand, 5126 * it is implied by the opcode. It must be converted 5127 * to the correct base and output. 5128 */ 5129 case INT3: 5130 #ifdef DIS_TEXT 5131 x->d86_numopnds = 1; 5132 x->d86_opnd[0].d86_mode = MODE_SIGNED; 5133 x->d86_opnd[0].d86_value_size = 1; 5134 x->d86_opnd[0].d86_value = 3; 5135 #endif 5136 NOMEM; 5137 break; 5138 5139 /* single 8 bit immediate operand */ 5140 case INTx: 5141 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5142 NOMEM; 5143 break; 5144 5145 /* an unused byte must be discarded */ 5146 case U: 5147 if (x->d86_get_byte(x->d86_data) < 0) 5148 goto error; 5149 x->d86_len++; 5150 NOMEM; 5151 break; 5152 5153 case CBW: 5154 #ifdef DIS_TEXT 5155 if (opnd_size == SIZE16) 5156 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 5157 else if (opnd_size == SIZE32) 5158 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 5159 else 5160 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 5161 #endif 5162 wbit = LONG_OPND; 5163 NOMEM; 5164 break; 5165 5166 case CWD: 5167 #ifdef DIS_TEXT 5168 if (opnd_size == SIZE16) 5169 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 5170 else if (opnd_size == SIZE32) 5171 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 5172 else 5173 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 5174 #endif 5175 wbit = LONG_OPND; 5176 NOMEM; 5177 break; 5178 5179 case XMMSFNC: 5180 /* 5181 * sfence is sfence if mode is REG_ONLY. If mode isn't 5182 * REG_ONLY, mnemonic should be 'clflush'. 5183 */ 5184 dtrace_get_modrm(x, &mode, ®, &r_m); 5185 5186 /* sfence doesn't take operands */ 5187 #ifdef DIS_TEXT 5188 if (mode == REG_ONLY) { 5189 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 5190 } else { 5191 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 5192 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5193 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5194 NOMEM; 5195 } 5196 #else 5197 if (mode != REG_ONLY) { 5198 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5199 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5200 NOMEM; 5201 } 5202 #endif 5203 break; 5204 5205 /* 5206 * no disassembly, the mnemonic was all there was so go on 5207 */ 5208 case NORM: 5209 if (dp->it_invalid32 && cpu_mode != SIZE64) 5210 goto error; 5211 NOMEM; 5212 /*FALLTHROUGH*/ 5213 case IMPLMEM: 5214 break; 5215 5216 case XMMFENCE: 5217 /* 5218 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but 5219 * differ in mode and reg. 5220 */ 5221 dtrace_get_modrm(x, &mode, ®, &r_m); 5222 5223 if (mode == REG_ONLY) { 5224 /* 5225 * Only the following exact byte sequences are allowed: 5226 * 5227 * 0f ae e8 lfence 5228 * 0f ae f0 mfence 5229 */ 5230 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 5231 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 5232 goto error; 5233 } else { 5234 #ifdef DIS_TEXT 5235 if (reg == 5) { 5236 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 5237 } else if (reg == 6) { 5238 (void) strncpy(x->d86_mnem, "xsaveopt", OPLEN); 5239 } else { 5240 goto error; 5241 } 5242 #endif 5243 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5244 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5245 } 5246 break; 5247 5248 /* float reg */ 5249 case F: 5250 #ifdef DIS_TEXT 5251 x->d86_numopnds = 1; 5252 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 5253 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 5254 #endif 5255 NOMEM; 5256 break; 5257 5258 /* float reg to float reg, with ret bit present */ 5259 case FF: 5260 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 5261 /*FALLTHROUGH*/ 5262 case FFC: /* case for vbit always = 0 */ 5263 #ifdef DIS_TEXT 5264 x->d86_numopnds = 2; 5265 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 5266 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 5267 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 5268 #endif 5269 NOMEM; 5270 break; 5271 5272 /* AVX instructions */ 5273 case VEX_MO: 5274 /* op(ModR/M.r/m) */ 5275 x->d86_numopnds = 1; 5276 dtrace_get_modrm(x, &mode, ®, &r_m); 5277 #ifdef DIS_TEXT 5278 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 5279 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 5280 #endif 5281 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5282 dtrace_get_operand(x, mode, r_m, wbit, 0); 5283 break; 5284 case VEX_RMrX: 5285 case FMA: 5286 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 5287 x->d86_numopnds = 3; 5288 dtrace_get_modrm(x, &mode, ®, &r_m); 5289 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5290 5291 /* 5292 * In classic Intel fashion, the opcodes for all of the FMA 5293 * instructions all have two possible mnemonics which vary by 5294 * one letter, which is selected based on the value of the wbit. 5295 * When wbit is one, they have the 'd' suffix and when 'wbit' is 5296 * 0, they have the 's' suffix. Otherwise, the FMA instructions 5297 * are all a standard VEX_RMrX. 5298 */ 5299 #ifdef DIS_TEXT 5300 if (dp->it_adrmode == FMA) { 5301 size_t len = strlen(dp->it_name); 5302 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5303 if (len + 1 < OPLEN) { 5304 (void) strncpy(x->d86_mnem + len, 5305 vex_W != 0 ? "d" : "s", OPLEN - len); 5306 } 5307 } 5308 #endif 5309 5310 if (mode != REG_ONLY) { 5311 if ((dp == &dis_opAVXF20F[0x10]) || 5312 (dp == &dis_opAVXF30F[0x10])) { 5313 /* vmovsd <m64>, <xmm> */ 5314 /* or vmovss <m64>, <xmm> */ 5315 x->d86_numopnds = 2; 5316 goto L_VEX_MX; 5317 } 5318 } 5319 5320 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5321 /* 5322 * VEX prefix uses the 1's complement form to encode the 5323 * XMM/YMM regs 5324 */ 5325 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5326 5327 if ((dp == &dis_opAVXF20F[0x2A]) || 5328 (dp == &dis_opAVXF30F[0x2A])) { 5329 /* 5330 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 5331 * <xmm>, <xmm> 5332 */ 5333 wbit = LONG_OPND; 5334 } 5335 #ifdef DIS_TEXT 5336 else if ((mode == REG_ONLY) && 5337 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 5338 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 5339 } else if ((mode == REG_ONLY) && 5340 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 5341 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 5342 } 5343 #endif 5344 dtrace_get_operand(x, mode, r_m, wbit, 0); 5345 5346 break; 5347 5348 case VEX_VRMrX: 5349 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */ 5350 x->d86_numopnds = 3; 5351 dtrace_get_modrm(x, &mode, ®, &r_m); 5352 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5353 5354 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5355 /* 5356 * VEX prefix uses the 1's complement form to encode the 5357 * XMM/YMM regs 5358 */ 5359 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0); 5360 5361 dtrace_get_operand(x, mode, r_m, wbit, 1); 5362 break; 5363 5364 case VEX_SbVM: 5365 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */ 5366 x->d86_numopnds = 3; 5367 x->d86_vsib = 1; 5368 5369 /* 5370 * All instructions that use VSIB are currently a mess. See the 5371 * comment around the dis_gather_regs_t structure definition. 5372 */ 5373 5374 vreg = &dis_vgather[opcode2][vex_W][vex_L]; 5375 5376 #ifdef DIS_TEXT 5377 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5378 (void) strlcat(x->d86_mnem + strlen(dp->it_name), 5379 vreg->dgr_suffix, OPLEN - strlen(dp->it_name)); 5380 #endif 5381 5382 dtrace_get_modrm(x, &mode, ®, &r_m); 5383 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5384 5385 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2); 5386 /* 5387 * VEX prefix uses the 1's complement form to encode the 5388 * XMM/YMM regs 5389 */ 5390 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0, 5391 0); 5392 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1); 5393 break; 5394 5395 case VEX_RRX: 5396 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5397 x->d86_numopnds = 3; 5398 5399 dtrace_get_modrm(x, &mode, ®, &r_m); 5400 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5401 5402 if (mode != REG_ONLY) { 5403 if ((dp == &dis_opAVXF20F[0x11]) || 5404 (dp == &dis_opAVXF30F[0x11])) { 5405 /* vmovsd <xmm>, <m64> */ 5406 /* or vmovss <xmm>, <m64> */ 5407 x->d86_numopnds = 2; 5408 goto L_VEX_RM; 5409 } 5410 } 5411 5412 dtrace_get_operand(x, mode, r_m, wbit, 2); 5413 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5414 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5415 break; 5416 5417 case VEX_RMRX: 5418 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 5419 x->d86_numopnds = 4; 5420 5421 dtrace_get_modrm(x, &mode, ®, &r_m); 5422 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5423 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 5424 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5425 if (dp == &dis_opAVX660F3A[0x18]) { 5426 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 5427 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 5428 } else if ((dp == &dis_opAVX660F3A[0x20]) || 5429 (dp == & dis_opAVX660F[0xC4])) { 5430 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 5431 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 5432 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5433 } else if (dp == &dis_opAVX660F3A[0x22]) { 5434 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 5435 #ifdef DIS_TEXT 5436 if (vex_W) 5437 x->d86_mnem[6] = 'q'; 5438 #endif 5439 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5440 } else { 5441 dtrace_get_operand(x, mode, r_m, wbit, 1); 5442 } 5443 5444 /* one byte immediate number */ 5445 dtrace_imm_opnd(x, wbit, 1, 0); 5446 5447 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 5448 if ((dp == &dis_opAVX660F3A[0x4A]) || 5449 (dp == &dis_opAVX660F3A[0x4B]) || 5450 (dp == &dis_opAVX660F3A[0x4C])) { 5451 #ifdef DIS_TEXT 5452 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 5453 #endif 5454 x->d86_opnd[0].d86_mode = MODE_NONE; 5455 #ifdef DIS_TEXT 5456 if (vex_L) 5457 (void) strncpy(x->d86_opnd[0].d86_opnd, 5458 dis_YMMREG[regnum], OPLEN); 5459 else 5460 (void) strncpy(x->d86_opnd[0].d86_opnd, 5461 dis_XMMREG[regnum], OPLEN); 5462 #endif 5463 } 5464 break; 5465 5466 case VEX_MX: 5467 /* ModR/M.reg := op(ModR/M.rm) */ 5468 x->d86_numopnds = 2; 5469 5470 dtrace_get_modrm(x, &mode, ®, &r_m); 5471 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5472 L_VEX_MX: 5473 5474 if ((dp == &dis_opAVXF20F[0xE6]) || 5475 (dp == &dis_opAVX660F[0x5A]) || 5476 (dp == &dis_opAVX660F[0xE6])) { 5477 /* vcvtpd2dq <ymm>, <xmm> */ 5478 /* or vcvtpd2ps <ymm>, <xmm> */ 5479 /* or vcvttpd2dq <ymm>, <xmm> */ 5480 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 5481 dtrace_get_operand(x, mode, r_m, wbit, 0); 5482 } else if ((dp == &dis_opAVXF30F[0xE6]) || 5483 (dp == &dis_opAVX0F[0x5][0xA]) || 5484 (dp == &dis_opAVX660F38[0x13]) || 5485 (dp == &dis_opAVX660F38[0x18]) || 5486 (dp == &dis_opAVX660F38[0x19]) || 5487 (dp == &dis_opAVX660F38[0x58]) || 5488 (dp == &dis_opAVX660F38[0x78]) || 5489 (dp == &dis_opAVX660F38[0x79]) || 5490 (dp == &dis_opAVX660F38[0x59])) { 5491 /* vcvtdq2pd <xmm>, <ymm> */ 5492 /* or vcvtps2pd <xmm>, <ymm> */ 5493 /* or vcvtph2ps <xmm>, <ymm> */ 5494 /* or vbroadcasts* <xmm>, <ymm> */ 5495 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5496 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 5497 } else if (dp == &dis_opAVX660F[0x6E]) { 5498 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5499 #ifdef DIS_TEXT 5500 if (vex_W) 5501 x->d86_mnem[4] = 'q'; 5502 #endif 5503 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5504 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5505 } else { 5506 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5507 dtrace_get_operand(x, mode, r_m, wbit, 0); 5508 } 5509 5510 break; 5511 5512 case VEX_MXI: 5513 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 5514 x->d86_numopnds = 3; 5515 5516 dtrace_get_modrm(x, &mode, ®, &r_m); 5517 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5518 5519 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5520 dtrace_get_operand(x, mode, r_m, wbit, 1); 5521 5522 /* one byte immediate number */ 5523 dtrace_imm_opnd(x, wbit, 1, 0); 5524 break; 5525 5526 case VEX_XXI: 5527 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 5528 x->d86_numopnds = 3; 5529 5530 dtrace_get_modrm(x, &mode, ®, &r_m); 5531 #ifdef DIS_TEXT 5532 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 5533 OPLEN); 5534 #endif 5535 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5536 5537 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5538 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 5539 5540 /* one byte immediate number */ 5541 dtrace_imm_opnd(x, wbit, 1, 0); 5542 break; 5543 5544 case VEX_MR: 5545 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 5546 if (dp == &dis_opAVX660F[0xC5]) { 5547 /* vpextrw <imm8>, <xmm>, <reg> */ 5548 x->d86_numopnds = 2; 5549 vbit = 2; 5550 } else { 5551 x->d86_numopnds = 2; 5552 vbit = 1; 5553 } 5554 5555 dtrace_get_modrm(x, &mode, ®, &r_m); 5556 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5557 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 5558 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 5559 5560 if (vbit == 2) 5561 dtrace_imm_opnd(x, wbit, 1, 0); 5562 5563 break; 5564 5565 case VEX_KMR: 5566 /* opmask: mod_rm := %k */ 5567 x->d86_numopnds = 2; 5568 dtrace_get_modrm(x, &mode, ®, &r_m); 5569 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5570 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5571 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5572 break; 5573 5574 case VEX_KRM: 5575 /* opmask: mod_reg := mod_rm */ 5576 x->d86_numopnds = 2; 5577 dtrace_get_modrm(x, &mode, ®, &r_m); 5578 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5579 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5580 if (mode == REG_ONLY) { 5581 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0); 5582 } else { 5583 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5584 } 5585 break; 5586 5587 case VEX_KRR: 5588 /* opmask: mod_reg := mod_rm */ 5589 x->d86_numopnds = 2; 5590 dtrace_get_modrm(x, &mode, ®, &r_m); 5591 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5592 dtrace_get_operand(x, mode, reg, wbit, 1); 5593 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0); 5594 break; 5595 5596 case VEX_RRI: 5597 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 5598 x->d86_numopnds = 2; 5599 5600 dtrace_get_modrm(x, &mode, ®, &r_m); 5601 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5602 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5603 dtrace_get_operand(x, mode, r_m, wbit, 0); 5604 break; 5605 5606 case VEX_RX: 5607 /* ModR/M.rm := op(ModR/M.reg) */ 5608 /* vextractf128 || vcvtps2ph */ 5609 if (dp == &dis_opAVX660F3A[0x19] || 5610 dp == &dis_opAVX660F3A[0x1d]) { 5611 x->d86_numopnds = 3; 5612 5613 dtrace_get_modrm(x, &mode, ®, &r_m); 5614 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5615 5616 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5617 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5618 5619 /* one byte immediate number */ 5620 dtrace_imm_opnd(x, wbit, 1, 0); 5621 break; 5622 } 5623 5624 x->d86_numopnds = 2; 5625 5626 dtrace_get_modrm(x, &mode, ®, &r_m); 5627 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5628 dtrace_get_operand(x, mode, r_m, wbit, 1); 5629 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5630 break; 5631 5632 case VEX_RR: 5633 /* ModR/M.rm := op(ModR/M.reg) */ 5634 x->d86_numopnds = 2; 5635 5636 dtrace_get_modrm(x, &mode, ®, &r_m); 5637 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5638 5639 if (dp == &dis_opAVX660F[0x7E]) { 5640 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5641 #ifdef DIS_TEXT 5642 if (vex_W) 5643 x->d86_mnem[4] = 'q'; 5644 #endif 5645 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5646 } else 5647 dtrace_get_operand(x, mode, r_m, wbit, 1); 5648 5649 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5650 break; 5651 5652 case VEX_RRi: 5653 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5654 x->d86_numopnds = 3; 5655 5656 dtrace_get_modrm(x, &mode, ®, &r_m); 5657 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5658 5659 #ifdef DIS_TEXT 5660 if (dp == &dis_opAVX660F3A[0x16]) { 5661 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 5662 if (vex_W) 5663 x->d86_mnem[6] = 'q'; 5664 } 5665 #endif 5666 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5667 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5668 5669 /* one byte immediate number */ 5670 dtrace_imm_opnd(x, wbit, 1, 0); 5671 break; 5672 case VEX_RIM: 5673 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5674 x->d86_numopnds = 3; 5675 5676 dtrace_get_modrm(x, &mode, ®, &r_m); 5677 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5678 5679 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5680 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5681 /* one byte immediate number */ 5682 dtrace_imm_opnd(x, wbit, 1, 0); 5683 break; 5684 5685 case VEX_RM: 5686 /* ModR/M.rm := op(ModR/M.reg) */ 5687 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 5688 x->d86_numopnds = 3; 5689 5690 dtrace_get_modrm(x, &mode, ®, &r_m); 5691 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5692 5693 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5694 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5695 /* one byte immediate number */ 5696 dtrace_imm_opnd(x, wbit, 1, 0); 5697 break; 5698 } 5699 x->d86_numopnds = 2; 5700 5701 dtrace_get_modrm(x, &mode, ®, &r_m); 5702 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5703 L_VEX_RM: 5704 vbit = 1; 5705 dtrace_get_operand(x, mode, r_m, wbit, vbit); 5706 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 5707 5708 break; 5709 5710 case VEX_RRM: 5711 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5712 x->d86_numopnds = 3; 5713 5714 dtrace_get_modrm(x, &mode, ®, &r_m); 5715 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5716 dtrace_get_operand(x, mode, r_m, wbit, 2); 5717 /* VEX use the 1's complement form encode the XMM/YMM regs */ 5718 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5719 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5720 break; 5721 5722 case VEX_RMX: 5723 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 5724 x->d86_numopnds = 3; 5725 5726 dtrace_get_modrm(x, &mode, ®, &r_m); 5727 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5728 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5729 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5730 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 5731 break; 5732 5733 case VEX_NONE: 5734 #ifdef DIS_TEXT 5735 if (vex_L) 5736 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 5737 #endif 5738 break; 5739 case BLS: { 5740 5741 /* 5742 * The BLS instructions are VEX instructions that are based on 5743 * VEX.0F38.F3; however, they are considered special group 17 5744 * and like everything else, they use the bits in 3-5 of the 5745 * MOD R/M to determine the sub instruction. Unlike many others 5746 * like the VMX instructions, these are valid both for memory 5747 * and register forms. 5748 */ 5749 5750 dtrace_get_modrm(x, &mode, ®, &r_m); 5751 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5752 5753 switch (reg) { 5754 case 1: 5755 #ifdef DIS_TEXT 5756 blsinstr = "blsr"; 5757 #endif 5758 break; 5759 case 2: 5760 #ifdef DIS_TEXT 5761 blsinstr = "blsmsk"; 5762 #endif 5763 break; 5764 case 3: 5765 #ifdef DIS_TEXT 5766 blsinstr = "blsi"; 5767 #endif 5768 break; 5769 default: 5770 goto error; 5771 } 5772 5773 x->d86_numopnds = 2; 5774 #ifdef DIS_TEXT 5775 (void) strncpy(x->d86_mnem, blsinstr, OPLEN); 5776 #endif 5777 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5778 dtrace_get_operand(x, mode, r_m, wbit, 0); 5779 break; 5780 } 5781 case EVEX_MX: 5782 /* ModR/M.reg := op(ModR/M.rm) */ 5783 x->d86_numopnds = 2; 5784 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5785 dtrace_get_modrm(x, &mode, ®, &r_m); 5786 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5787 dtrace_evex_adjust_reg(evex_byte1, ®); 5788 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5789 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5790 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5791 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 5792 dtrace_get_operand(x, mode, r_m, wbit, 0); 5793 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 5794 break; 5795 case EVEX_RX: 5796 /* ModR/M.rm := op(ModR/M.reg) */ 5797 x->d86_numopnds = 2; 5798 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5799 dtrace_get_modrm(x, &mode, ®, &r_m); 5800 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5801 dtrace_evex_adjust_reg(evex_byte1, ®); 5802 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5803 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5804 dtrace_get_operand(x, mode, r_m, wbit, 1); 5805 dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); 5806 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 5807 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5808 break; 5809 case EVEX_RMrX: 5810 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */ 5811 x->d86_numopnds = 3; 5812 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5813 dtrace_get_modrm(x, &mode, ®, &r_m); 5814 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5815 dtrace_evex_adjust_reg(evex_byte1, ®); 5816 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5817 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5818 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5819 /* 5820 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 5821 * register specifier). The EVEX prefix handling uses the vex_v 5822 * variable for these bits. 5823 */ 5824 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5825 dtrace_get_operand(x, mode, r_m, wbit, 0); 5826 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 5827 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); 5828 break; 5829 /* an invalid op code */ 5830 case AM: 5831 case DM: 5832 case OVERRIDE: 5833 case PREFIX: 5834 case UNKNOWN: 5835 NOMEM; 5836 default: 5837 goto error; 5838 } /* end switch */ 5839 if (x->d86_error) 5840 goto error; 5841 5842 done: 5843 #ifdef DIS_MEM 5844 /* 5845 * compute the size of any memory accessed by the instruction 5846 */ 5847 if (x->d86_memsize != 0) { 5848 return (0); 5849 } else if (dp->it_stackop) { 5850 switch (opnd_size) { 5851 case SIZE16: 5852 x->d86_memsize = 2; 5853 break; 5854 case SIZE32: 5855 x->d86_memsize = 4; 5856 break; 5857 case SIZE64: 5858 x->d86_memsize = 8; 5859 break; 5860 } 5861 } else if (nomem || mode == REG_ONLY) { 5862 x->d86_memsize = 0; 5863 5864 } else if (dp->it_size != 0) { 5865 /* 5866 * In 64 bit mode descriptor table entries 5867 * go up to 10 bytes and popf/pushf are always 8 bytes 5868 */ 5869 if (x->d86_mode == SIZE64 && dp->it_size == 6) 5870 x->d86_memsize = 10; 5871 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 5872 (opcode2 == 0xc || opcode2 == 0xd)) 5873 x->d86_memsize = 8; 5874 else 5875 x->d86_memsize = dp->it_size; 5876 5877 } else if (wbit == 0) { 5878 x->d86_memsize = 1; 5879 5880 } else if (wbit == LONG_OPND) { 5881 if (opnd_size == SIZE64) 5882 x->d86_memsize = 8; 5883 else if (opnd_size == SIZE32) 5884 x->d86_memsize = 4; 5885 else 5886 x->d86_memsize = 2; 5887 5888 } else if (wbit == SEG_OPND) { 5889 x->d86_memsize = 4; 5890 5891 } else { 5892 x->d86_memsize = 8; 5893 } 5894 #endif 5895 return (0); 5896 5897 error: 5898 #ifdef DIS_TEXT 5899 (void) strlcat(x->d86_mnem, "undef", OPLEN); 5900 #endif 5901 return (1); 5902 } 5903 5904 #ifdef DIS_TEXT 5905 5906 /* 5907 * Some instructions should have immediate operands printed 5908 * as unsigned integers. We compare against this table. 5909 */ 5910 static char *unsigned_ops[] = { 5911 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 5912 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 5913 0 5914 }; 5915 5916 5917 static int 5918 isunsigned_op(char *opcode) 5919 { 5920 char *where; 5921 int i; 5922 int is_unsigned = 0; 5923 5924 /* 5925 * Work back to start of last mnemonic, since we may have 5926 * prefixes on some opcodes. 5927 */ 5928 where = opcode + strlen(opcode) - 1; 5929 while (where > opcode && *where != ' ') 5930 --where; 5931 if (*where == ' ') 5932 ++where; 5933 5934 for (i = 0; unsigned_ops[i]; ++i) { 5935 if (strncmp(where, unsigned_ops[i], 5936 strlen(unsigned_ops[i]))) 5937 continue; 5938 is_unsigned = 1; 5939 break; 5940 } 5941 return (is_unsigned); 5942 } 5943 5944 /* 5945 * Print a numeric immediate into end of buf, maximum length buflen. 5946 * The immediate may be an address or a displacement. Mask is set 5947 * for address size. If the immediate is a "small negative", or 5948 * if it's a negative displacement of any magnitude, print as -<absval>. 5949 * Respect the "octal" flag. "Small negative" is defined as "in the 5950 * interval [NEG_LIMIT, 0)". 5951 * 5952 * Also, "isunsigned_op()" instructions never print negatives. 5953 * 5954 * Return whether we decided to print a negative value or not. 5955 */ 5956 5957 #define NEG_LIMIT -255 5958 enum {IMM, DISP}; 5959 enum {POS, TRY_NEG}; 5960 5961 static int 5962 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 5963 size_t buflen, int disp, int try_neg) 5964 { 5965 int curlen; 5966 int64_t sv = (int64_t)usv; 5967 int octal = dis->d86_flags & DIS_F_OCTAL; 5968 5969 curlen = strlen(buf); 5970 5971 if (try_neg == TRY_NEG && sv < 0 && 5972 (disp || sv >= NEG_LIMIT) && 5973 !isunsigned_op(dis->d86_mnem)) { 5974 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 5975 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 5976 return (1); 5977 } else { 5978 if (disp == DISP) 5979 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 5980 octal ? "+0%llo" : "+0x%llx", usv & mask); 5981 else 5982 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 5983 octal ? "0%llo" : "0x%llx", usv & mask); 5984 return (0); 5985 5986 } 5987 } 5988 5989 5990 static int 5991 log2(int size) 5992 { 5993 switch (size) { 5994 case 1: return (0); 5995 case 2: return (1); 5996 case 4: return (2); 5997 case 8: return (3); 5998 } 5999 return (0); 6000 } 6001 6002 /* ARGSUSED */ 6003 void 6004 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 6005 size_t buflen) 6006 { 6007 uint64_t reltgt = 0; 6008 uint64_t tgt = 0; 6009 int curlen; 6010 int (*lookup)(void *, uint64_t, char *, size_t); 6011 int i; 6012 int64_t sv; 6013 uint64_t usv, mask, save_mask, save_usv; 6014 static uint64_t masks[] = 6015 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 6016 save_usv = 0; 6017 6018 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 6019 6020 /* 6021 * For PC-relative jumps, the pc is really the next pc after executing 6022 * this instruction, so increment it appropriately. 6023 */ 6024 pc += dis->d86_len; 6025 6026 for (i = 0; i < dis->d86_numopnds; i++) { 6027 d86opnd_t *op = &dis->d86_opnd[i]; 6028 6029 if (i != 0) 6030 (void) strlcat(buf, ",", buflen); 6031 6032 (void) strlcat(buf, op->d86_prefix, buflen); 6033 6034 /* 6035 * sv is for the signed, possibly-truncated immediate or 6036 * displacement; usv retains the original size and 6037 * unsignedness for symbol lookup. 6038 */ 6039 6040 sv = usv = op->d86_value; 6041 6042 /* 6043 * About masks: for immediates that represent 6044 * addresses, the appropriate display size is 6045 * the effective address size of the instruction. 6046 * This includes MODE_OFFSET, MODE_IPREL, and 6047 * MODE_RIPREL. Immediates that are simply 6048 * immediate values should display in the operand's 6049 * size, however, since they don't represent addresses. 6050 */ 6051 6052 /* d86_addr_size is SIZEnn, which is log2(real size) */ 6053 mask = masks[dis->d86_addr_size]; 6054 6055 /* d86_value_size and d86_imm_bytes are in bytes */ 6056 if (op->d86_mode == MODE_SIGNED || 6057 op->d86_mode == MODE_IMPLIED) 6058 mask = masks[log2(op->d86_value_size)]; 6059 6060 switch (op->d86_mode) { 6061 6062 case MODE_NONE: 6063 6064 (void) strlcat(buf, op->d86_opnd, buflen); 6065 break; 6066 6067 case MODE_SIGNED: 6068 case MODE_IMPLIED: 6069 case MODE_OFFSET: 6070 6071 tgt = usv; 6072 6073 if (dis->d86_seg_prefix) 6074 (void) strlcat(buf, dis->d86_seg_prefix, 6075 buflen); 6076 6077 if (op->d86_mode == MODE_SIGNED || 6078 op->d86_mode == MODE_IMPLIED) { 6079 (void) strlcat(buf, "$", buflen); 6080 } 6081 6082 if (print_imm(dis, usv, mask, buf, buflen, 6083 IMM, TRY_NEG) && 6084 (op->d86_mode == MODE_SIGNED || 6085 op->d86_mode == MODE_IMPLIED)) { 6086 6087 /* 6088 * We printed a negative value for an 6089 * immediate that wasn't a 6090 * displacement. Note that fact so we can 6091 * print the positive value as an 6092 * annotation. 6093 */ 6094 6095 save_usv = usv; 6096 save_mask = mask; 6097 } 6098 (void) strlcat(buf, op->d86_opnd, buflen); 6099 6100 break; 6101 6102 case MODE_IPREL: 6103 case MODE_RIPREL: 6104 6105 reltgt = pc + sv; 6106 6107 switch (mode) { 6108 case SIZE16: 6109 reltgt = (uint16_t)reltgt; 6110 break; 6111 case SIZE32: 6112 reltgt = (uint32_t)reltgt; 6113 break; 6114 } 6115 6116 (void) print_imm(dis, usv, mask, buf, buflen, 6117 DISP, TRY_NEG); 6118 6119 if (op->d86_mode == MODE_RIPREL) 6120 (void) strlcat(buf, "(%rip)", buflen); 6121 break; 6122 } 6123 } 6124 6125 /* 6126 * The symbol lookups may result in false positives, 6127 * particularly on object files, where small numbers may match 6128 * the 0-relative non-relocated addresses of symbols. 6129 */ 6130 6131 lookup = dis->d86_sym_lookup; 6132 if (tgt != 0) { 6133 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 6134 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 6135 (void) strlcat(buf, "\t<", buflen); 6136 curlen = strlen(buf); 6137 lookup(dis->d86_data, tgt, buf + curlen, 6138 buflen - curlen); 6139 (void) strlcat(buf, ">", buflen); 6140 } 6141 6142 /* 6143 * If we printed a negative immediate above, print the 6144 * positive in case our heuristic was unhelpful 6145 */ 6146 if (save_usv) { 6147 (void) strlcat(buf, "\t<", buflen); 6148 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 6149 IMM, POS); 6150 (void) strlcat(buf, ">", buflen); 6151 } 6152 } 6153 6154 if (reltgt != 0) { 6155 /* Print symbol or effective address for reltgt */ 6156 6157 (void) strlcat(buf, "\t<", buflen); 6158 curlen = strlen(buf); 6159 lookup(dis->d86_data, reltgt, buf + curlen, 6160 buflen - curlen); 6161 (void) strlcat(buf, ">", buflen); 6162 } 6163 } 6164 6165 #endif /* DIS_TEXT */ 6166