1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2019 Joyent, Inc. 25 */ 26 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* Copyright (c) 1988 AT&T */ 33 /* All Rights Reserved */ 34 35 #include "dis_tables.h" 36 37 /* BEGIN CSTYLED */ 38 39 /* 40 * Disassembly begins in dis_distable, which is equivalent to the One-byte 41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 42 * decoding loops then traverse out through the other tables as necessary to 43 * decode a given instruction. 44 * 45 * The behavior of this file can be controlled by one of the following flags: 46 * 47 * DIS_TEXT Include text for disassembly 48 * DIS_MEM Include memory-size calculations 49 * 50 * Either or both of these can be defined. 51 * 52 * This file is not, and will never be, cstyled. If anything, the tables should 53 * be taken out another tab stop or two so nothing overlaps. 54 */ 55 56 /* 57 * These functions must be provided for the consumer to do disassembly. 58 */ 59 #ifdef DIS_TEXT 60 extern char *strncpy(char *, const char *, size_t); 61 extern size_t strlen(const char *); 62 extern int strcmp(const char *, const char *); 63 extern int strncmp(const char *, const char *, size_t); 64 extern size_t strlcat(char *, const char *, size_t); 65 #endif 66 67 68 #define TERM 0 /* used to indicate that the 'indirect' */ 69 /* field terminates - no pointer. */ 70 71 /* Used to decode instructions. */ 72 typedef struct instable { 73 struct instable *it_indirect; /* for decode op codes */ 74 uchar_t it_adrmode; 75 #ifdef DIS_TEXT 76 char it_name[NCPS]; 77 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 78 #endif 79 #ifdef DIS_MEM 80 uint_t it_size:16; 81 #endif 82 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 83 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 84 uint_t it_invalid32:1; /* invalid in IA32 */ 85 uint_t it_stackop:1; /* push/pop stack operation */ 86 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ 87 uint_t it_avxsuf:2; /* AVX2/AVX512 suffix rqd. */ 88 uint_t it_vexopmask:1; /* VEX inst. that use opmask */ 89 } instable_t; 90 91 /* 92 * Instruction formats. 93 */ 94 enum { 95 UNKNOWN, 96 MRw, 97 IMlw, 98 IMw, 99 IR, 100 OA, 101 AO, 102 MS, 103 SM, 104 Mv, 105 Mw, 106 M, /* register or memory */ 107 MG9, /* register or memory in group 9 (prefix optional) */ 108 Mb, /* register or memory, always byte sized */ 109 MO, /* memory only (no registers) */ 110 PREF, 111 SWAPGS_RDTSCP, 112 MONITOR_MWAIT, 113 R, 114 RA, 115 SEG, 116 MR, 117 RM, 118 RM_66r, /* RM, but with a required 0x66 prefix */ 119 IA, 120 MA, 121 SD, 122 AD, 123 SA, 124 D, 125 INM, 126 SO, 127 BD, 128 I, 129 P, 130 V, 131 DSHIFT, /* for double shift that has an 8-bit immediate */ 132 U, 133 OVERRIDE, 134 NORM, /* instructions w/o ModR/M byte, no memory access */ 135 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 136 O, /* for call */ 137 JTAB, /* jump table */ 138 IMUL, /* for 186 iimul instr */ 139 CBW, /* so data16 can be evaluated for cbw and variants */ 140 MvI, /* for 186 logicals */ 141 ENTER, /* for 186 enter instr */ 142 RMw, /* for 286 arpl instr */ 143 Ib, /* for push immediate byte */ 144 F, /* for 287 instructions */ 145 FF, /* for 287 instructions */ 146 FFC, /* for 287 instructions */ 147 DM, /* 16-bit data */ 148 AM, /* 16-bit addr */ 149 LSEG, /* for 3-bit seg reg encoding */ 150 MIb, /* for 386 logicals */ 151 SREG, /* for 386 special registers */ 152 PREFIX, /* a REP instruction prefix */ 153 LOCK, /* a LOCK instruction prefix */ 154 INT3, /* The int 3 instruction, which has a fake operand */ 155 INTx, /* The normal int instruction, with explicit int num */ 156 DSHIFTcl, /* for double shift that implicitly uses %cl */ 157 CWD, /* so data16 can be evaluated for cwd and variants */ 158 RET, /* single immediate 16-bit operand */ 159 MOVZ, /* for movs and movz, with different size operands */ 160 CRC32, /* for crc32, with different size operands */ 161 XADDB, /* for xaddb */ 162 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 163 MOVBE, /* movbe instruction */ 164 165 /* 166 * MMX/SIMD addressing modes. 167 */ 168 169 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 170 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 171 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 172 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 173 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 174 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 175 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 176 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 177 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 178 MMOSH, /* Prefixable MMX mm,imm8 */ 179 MM, /* MMX/SIMD-Int mm/mem -> mm */ 180 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 181 MMSH, /* MMX mm,imm8 */ 182 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 183 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 184 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 185 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 186 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 187 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 188 XMMOM, /* Prefixable SIMD xmm -> mem */ 189 XMMOMS, /* Prefixable SIMD mem -> xmm */ 190 XMM, /* SIMD xmm/mem -> xmm */ 191 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 192 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 193 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 194 XMM3P, /* SIMD xmm -> r32,imm8 */ 195 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 196 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 197 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 198 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 199 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 200 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 201 XMMS, /* SIMD xmm -> xmm/mem */ 202 XMMM, /* SIMD mem -> xmm */ 203 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 204 XMMMS, /* SIMD xmm -> mem */ 205 XMM3MX, /* SIMD r32/mem -> xmm */ 206 XMM3MXS, /* SIMD xmm -> r32/mem */ 207 XMMSH, /* SIMD xmm,imm8 */ 208 XMMXM3, /* SIMD xmm/mem -> r32 */ 209 XMMX3, /* SIMD xmm -> r32 */ 210 XMMXMM, /* SIMD xmm/mem -> mm */ 211 XMMMX, /* SIMD mm -> xmm */ 212 XMMXM, /* SIMD xmm -> mm */ 213 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 214 XMM2I, /* SIMD xmm, imm, imm */ 215 XMMFENCE, /* SIMD lfence or mfence */ 216 XMMSFNC, /* SIMD sfence (none or mem) */ 217 FSGS, /* FSGSBASE if reg */ 218 XGETBV_XSETBV, 219 VEX_NONE, /* VEX no operand */ 220 VEX_MO, /* VEX mod_rm -> implicit reg */ 221 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 222 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */ 223 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 224 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 225 VEX_MX, /* VEX mod_rm -> mod_reg */ 226 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 227 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 228 VEX_MR, /* VEX mod_rm -> mod_reg */ 229 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 230 VEX_RX, /* VEX mod_reg -> mod_rm */ 231 VEX_KRR, /* VEX mod_rm -> mod_reg */ 232 VEX_KMR, /* VEX mod_reg -> mod_rm */ 233 VEX_KRM, /* VEX mod_rm -> mod_reg */ 234 VEX_RR, /* VEX mod_rm -> mod_reg */ 235 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 236 VEX_RM, /* VEX mod_reg -> mod_rm */ 237 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */ 238 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 239 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 240 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */ 241 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 242 VMxo, /* VMx instruction with optional prefix */ 243 SVM, /* AMD SVM instructions */ 244 BLS, /* BLSR, BLSMSK, BLSI */ 245 FMA, /* FMA instructions, all VEX_RMrX */ 246 ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */ 247 EVEX_RX, /* EVEX mod_reg -> mod_rm */ 248 EVEX_MX, /* EVEX mod_rm -> mod_reg */ 249 EVEX_RMrX /* EVEX EVEX.vvvv, mod_rm -> mod_reg */ 250 }; 251 252 /* 253 * VEX prefixes 254 */ 255 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 256 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 257 258 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 259 260 /* 261 ** Register numbers for the i386 262 */ 263 #define EAX_REGNO 0 264 #define ECX_REGNO 1 265 #define EDX_REGNO 2 266 #define EBX_REGNO 3 267 #define ESP_REGNO 4 268 #define EBP_REGNO 5 269 #define ESI_REGNO 6 270 #define EDI_REGNO 7 271 272 /* 273 * modes for immediate values 274 */ 275 #define MODE_NONE 0 276 #define MODE_IPREL 1 /* signed IP relative value */ 277 #define MODE_SIGNED 2 /* sign extended immediate */ 278 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 279 #define MODE_OFFSET 4 /* offset part of an address */ 280 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 281 282 /* 283 * The letters used in these macros are: 284 * IND - indirect to another to another table 285 * "T" - means to Terminate indirections (this is the final opcode) 286 * "S" - means "operand length suffix required" 287 * "Sa" - means AVX2 suffix (q/d) required 288 * "Sq" - means AVX512 suffix (q/d) required 289 * "Sd" - means AVX512 suffix (d/s) required 290 * "NS" - means "no suffix" which is the operand length suffix of the opcode 291 * "Z" - means instruction size arg required 292 * "u" - means the opcode is invalid in IA32 but valid in amd64 293 * "x" - means the opcode is invalid in amd64, but not IA32 294 * "y" - means the operand size is always 64 bits in 64 bit mode 295 * "p" - means push/pop stack operation 296 * "vr" - means VEX instruction that operates on normal registers, not fpu 297 * "vo" - means VEX instruction that operates on opmask registers, not fpu 298 */ 299 300 #define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling */ 301 #define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix handling */ 302 #define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix handling */ 303 304 #if defined(DIS_TEXT) && defined(DIS_MEM) 305 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 306 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 307 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 308 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 309 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 310 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 311 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 312 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 313 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 314 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} 315 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} 316 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 317 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 318 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 319 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 320 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 321 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2} 322 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q} 323 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D} 324 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 325 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 326 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 327 #elif defined(DIS_TEXT) 328 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 329 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 330 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 331 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 332 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 333 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 334 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 335 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 336 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 337 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1} 338 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1} 339 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 340 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 341 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 342 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 343 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 344 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2} 345 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q} 346 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5D} 347 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 348 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 349 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 350 #elif defined(DIS_MEM) 351 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 352 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 353 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 354 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 355 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 356 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 357 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 358 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 359 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 360 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1} 361 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1} 362 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 363 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 364 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 365 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 366 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 367 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2} 368 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q} 369 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5D} 370 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 371 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 372 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 373 #else 374 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 375 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 376 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 377 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 378 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 379 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 380 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 381 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 382 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 383 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1} 384 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1} 385 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 386 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 387 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 388 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 389 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 390 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2} 391 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q} 392 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D} 393 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 394 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 395 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 396 #endif 397 398 #ifdef DIS_TEXT 399 /* 400 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 401 */ 402 const char *const dis_addr16[3][8] = { 403 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 404 "(%bx)", 405 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 406 "(%bx)", 407 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 408 "(%bx)", 409 }; 410 411 412 /* 413 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 414 */ 415 const char *const dis_addr32_mode0[16] = { 416 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 417 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 418 }; 419 420 const char *const dis_addr32_mode12[16] = { 421 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 422 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 423 }; 424 425 /* 426 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 427 */ 428 const char *const dis_addr64_mode0[16] = { 429 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 430 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 431 }; 432 const char *const dis_addr64_mode12[16] = { 433 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 434 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 435 }; 436 437 /* 438 * decode for scale from SIB byte 439 */ 440 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 441 442 /* 443 * decode for scale from VSIB byte, note that we always include the scale factor 444 * to match gas. 445 */ 446 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" }; 447 448 /* 449 * register decoding for normal references to registers (ie. not addressing) 450 */ 451 const char *const dis_REG8[16] = { 452 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 453 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 454 }; 455 456 const char *const dis_REG8_REX[16] = { 457 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 458 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 459 }; 460 461 const char *const dis_REG16[16] = { 462 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 463 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 464 }; 465 466 const char *const dis_REG32[16] = { 467 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 468 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 469 }; 470 471 const char *const dis_REG64[16] = { 472 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 473 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 474 }; 475 476 const char *const dis_DEBUGREG[16] = { 477 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 478 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 479 }; 480 481 const char *const dis_CONTROLREG[16] = { 482 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 483 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 484 }; 485 486 const char *const dis_TESTREG[16] = { 487 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 488 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 489 }; 490 491 const char *const dis_MMREG[16] = { 492 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 493 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 494 }; 495 496 const char *const dis_XMMREG[32] = { 497 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 498 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 499 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 500 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 501 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 502 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 503 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 504 "%xmm28", "%xmm29", "%xmm30", "%xmm31", 505 }; 506 507 const char *const dis_YMMREG[32] = { 508 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 509 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 510 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 511 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 512 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 513 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 514 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 515 "%ymm28", "%ymm29", "%ymm30", "%ymm31", 516 }; 517 518 const char *const dis_ZMMREG[32] = { 519 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 520 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 521 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 522 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 523 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 524 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 525 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 526 "%zmm28", "%zmm29", "%zmm30", "%zmm31", 527 }; 528 529 const char *const dis_KOPMASKREG[8] = { 530 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 531 }; 532 533 const char *const dis_SEGREG[16] = { 534 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 535 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 536 }; 537 538 /* 539 * SIMD predicate suffixes 540 */ 541 const char *const dis_PREDSUFFIX[8] = { 542 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 543 }; 544 545 const char *const dis_AVXvgrp7[3][8] = { 546 /*0 1 2 3 4 5 6 7*/ 547 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 548 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 549 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 550 }; 551 552 #endif /* DIS_TEXT */ 553 554 /* 555 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 556 */ 557 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 558 559 /* 560 * "decode table" for pause and clflush instructions 561 */ 562 const instable_t dis_opPause = TNS("pause", NORM); 563 564 /* 565 * "decode table" for wbnoinvd instruction 566 */ 567 const instable_t dis_opWbnoinvd = TNS("wbnoinvd", NORM); 568 569 /* 570 * Decode table for 0x0F00 opcodes 571 */ 572 const instable_t dis_op0F00[8] = { 573 574 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 575 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 576 }; 577 578 579 /* 580 * Decode table for 0x0F01 opcodes 581 */ 582 const instable_t dis_op0F01[8] = { 583 584 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 585 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 586 }; 587 588 /* 589 * Decode table for 0x0F18 opcodes -- SIMD prefetch 590 */ 591 const instable_t dis_op0F18[8] = { 592 593 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 594 /* [4] */ INVALID, INVALID, INVALID, INVALID, 595 }; 596 597 /* 598 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 599 */ 600 const instable_t dis_op0FAE[8] = { 601 /* [0] */ TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS), TNS("stmxcsr",FSGS), 602 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 603 }; 604 605 /* 606 * Decode table for 0xF30FAE opcodes -- FSGSBASE 607 */ 608 const instable_t dis_opF30FAE[8] = { 609 /* [0] */ TNSx("rdfsbase",FSGS), TNSx("rdgsbase",FSGS), TNSx("wrfsbase",FSGS), TNSx("wrgsbase",FSGS), 610 /* [4] */ INVALID, INVALID, INVALID, INVALID, 611 }; 612 613 /* 614 * Decode table for 0x0FBA opcodes 615 */ 616 617 const instable_t dis_op0FBA[8] = { 618 619 /* [0] */ INVALID, INVALID, INVALID, INVALID, 620 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 621 }; 622 623 /* 624 * Decode table for 0x0FC7 opcode (group 9) 625 */ 626 627 const instable_t dis_op0FC7[8] = { 628 629 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9), 630 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9), 631 }; 632 633 /* 634 * Decode table for 0x0FC7 opcode (group 9) mode 3 635 */ 636 637 const instable_t dis_op0FC7m3[8] = { 638 639 /* [0] */ INVALID, INVALID, INVALID, INVALID, 640 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9), 641 }; 642 643 /* 644 * Decode table for 0x0FC7 opcode with 0x66 prefix 645 */ 646 647 const instable_t dis_op660FC7[8] = { 648 649 /* [0] */ INVALID, INVALID, INVALID, INVALID, 650 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 651 }; 652 653 /* 654 * Decode table for 0x0FC7 opcode with 0xF3 prefix 655 */ 656 657 const instable_t dis_opF30FC7[8] = { 658 659 /* [0] */ INVALID, INVALID, INVALID, INVALID, 660 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 661 }; 662 663 /* 664 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 665 * 666 *bit pattern: 0000 1111 1100 1reg 667 */ 668 const instable_t dis_op0FC8[4] = { 669 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 670 }; 671 672 /* 673 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 674 */ 675 const instable_t dis_op0F7123[4][8] = { 676 { 677 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 678 /* .4 */ INVALID, INVALID, INVALID, INVALID, 679 }, { 680 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 681 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 682 }, { 683 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 684 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 685 }, { 686 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 687 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 688 } }; 689 690 /* 691 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 692 */ 693 const instable_t dis_opSIMD7123[32] = { 694 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 695 /* .4 */ INVALID, INVALID, INVALID, INVALID, 696 697 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 698 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 699 700 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 701 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 702 703 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 704 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 705 }; 706 707 /* 708 * SIMD instructions have been wedged into the existing IA32 instruction 709 * set through the use of prefixes. That is, while 0xf0 0x58 may be 710 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 711 * instruction - addss. At present, three prefixes have been coopted in 712 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 713 * following tables are used to provide the prefixed instruction names. 714 * The arrays are sparse, but they're fast. 715 */ 716 717 /* 718 * Decode table for SIMD instructions with the address size (0x66) prefix. 719 */ 720 const instable_t dis_opSIMDdata16[256] = { 721 /* [00] */ INVALID, INVALID, INVALID, INVALID, 722 /* [04] */ INVALID, INVALID, INVALID, INVALID, 723 /* [08] */ INVALID, INVALID, INVALID, INVALID, 724 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 725 726 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 727 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 728 /* [18] */ INVALID, INVALID, INVALID, INVALID, 729 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 730 731 /* [20] */ INVALID, INVALID, INVALID, INVALID, 732 /* [24] */ INVALID, INVALID, INVALID, INVALID, 733 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 734 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 735 736 /* [30] */ INVALID, INVALID, INVALID, INVALID, 737 /* [34] */ INVALID, INVALID, INVALID, INVALID, 738 /* [38] */ INVALID, INVALID, INVALID, INVALID, 739 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 740 741 /* [40] */ INVALID, INVALID, INVALID, INVALID, 742 /* [44] */ INVALID, INVALID, INVALID, INVALID, 743 /* [48] */ INVALID, INVALID, INVALID, INVALID, 744 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 745 746 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 747 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 748 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 749 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 750 751 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 752 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 753 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 754 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 755 756 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 757 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 758 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 759 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 760 761 /* [80] */ INVALID, INVALID, INVALID, INVALID, 762 /* [84] */ INVALID, INVALID, INVALID, INVALID, 763 /* [88] */ INVALID, INVALID, INVALID, INVALID, 764 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 765 766 /* [90] */ INVALID, INVALID, INVALID, INVALID, 767 /* [94] */ INVALID, INVALID, INVALID, INVALID, 768 /* [98] */ INVALID, INVALID, INVALID, INVALID, 769 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 770 771 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 772 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 773 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 774 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 775 776 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 777 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 778 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 779 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 780 781 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 782 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 783 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 784 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 785 786 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 787 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 788 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 789 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 790 791 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 792 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 793 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 794 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 795 796 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 797 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 798 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 799 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 800 }; 801 802 const instable_t dis_opAVX660F[256] = { 803 /* [00] */ INVALID, INVALID, INVALID, INVALID, 804 /* [04] */ INVALID, INVALID, INVALID, INVALID, 805 /* [08] */ INVALID, INVALID, INVALID, INVALID, 806 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 807 808 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 809 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 810 /* [18] */ INVALID, INVALID, INVALID, INVALID, 811 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 812 813 /* [20] */ INVALID, INVALID, INVALID, INVALID, 814 /* [24] */ INVALID, INVALID, INVALID, INVALID, 815 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 816 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 817 818 /* [30] */ INVALID, INVALID, INVALID, INVALID, 819 /* [34] */ INVALID, INVALID, INVALID, INVALID, 820 /* [38] */ INVALID, INVALID, INVALID, INVALID, 821 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 822 823 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 824 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 825 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 826 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 827 828 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 829 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 830 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 831 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 832 833 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 834 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 835 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 836 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 837 838 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 839 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 840 /* [78] */ INVALID, INVALID, INVALID, INVALID, 841 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 842 843 /* [80] */ INVALID, INVALID, INVALID, INVALID, 844 /* [84] */ INVALID, INVALID, INVALID, INVALID, 845 /* [88] */ INVALID, INVALID, INVALID, INVALID, 846 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 847 848 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 849 /* [94] */ INVALID, INVALID, INVALID, INVALID, 850 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 851 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 852 853 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 854 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 855 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 856 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 857 858 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 859 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 860 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 861 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 862 863 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 864 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 865 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 866 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 867 868 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 869 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 870 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 871 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 872 873 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 874 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 875 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 876 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 877 878 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 879 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 880 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 881 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 882 }; 883 884 /* 885 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 886 */ 887 const instable_t dis_opSIMDrepnz[256] = { 888 /* [00] */ INVALID, INVALID, INVALID, INVALID, 889 /* [04] */ INVALID, INVALID, INVALID, INVALID, 890 /* [08] */ INVALID, INVALID, INVALID, INVALID, 891 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 892 893 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID, 894 /* [14] */ INVALID, INVALID, INVALID, INVALID, 895 /* [18] */ INVALID, INVALID, INVALID, INVALID, 896 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 897 898 /* [20] */ INVALID, INVALID, INVALID, INVALID, 899 /* [24] */ INVALID, INVALID, INVALID, INVALID, 900 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 901 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 902 903 /* [30] */ INVALID, INVALID, INVALID, INVALID, 904 /* [34] */ INVALID, INVALID, INVALID, INVALID, 905 /* [38] */ INVALID, INVALID, INVALID, INVALID, 906 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 907 908 /* [40] */ INVALID, INVALID, INVALID, INVALID, 909 /* [44] */ INVALID, INVALID, INVALID, INVALID, 910 /* [48] */ INVALID, INVALID, INVALID, INVALID, 911 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 912 913 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 914 /* [54] */ INVALID, INVALID, INVALID, INVALID, 915 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 916 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 917 918 /* [60] */ INVALID, INVALID, INVALID, INVALID, 919 /* [64] */ INVALID, INVALID, INVALID, INVALID, 920 /* [68] */ INVALID, INVALID, INVALID, INVALID, 921 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 922 923 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 924 /* [74] */ INVALID, INVALID, INVALID, INVALID, 925 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 926 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID, 927 928 /* [80] */ INVALID, INVALID, INVALID, INVALID, 929 /* [84] */ INVALID, INVALID, INVALID, INVALID, 930 /* [88] */ INVALID, INVALID, INVALID, INVALID, 931 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 932 933 /* [90] */ INVALID, INVALID, INVALID, INVALID, 934 /* [94] */ INVALID, INVALID, INVALID, INVALID, 935 /* [98] */ INVALID, INVALID, INVALID, INVALID, 936 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 937 938 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 939 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 940 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 941 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 942 943 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 944 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 945 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 946 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 947 948 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 949 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 950 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 951 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 952 953 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID, 954 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 955 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 956 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 957 958 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 959 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 960 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 961 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 962 963 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID, 964 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 965 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 966 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 967 }; 968 969 const instable_t dis_opAVXF20F[256] = { 970 /* [00] */ INVALID, INVALID, INVALID, INVALID, 971 /* [04] */ INVALID, INVALID, INVALID, INVALID, 972 /* [08] */ INVALID, INVALID, INVALID, INVALID, 973 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 974 975 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 976 /* [14] */ INVALID, INVALID, INVALID, INVALID, 977 /* [18] */ INVALID, INVALID, INVALID, INVALID, 978 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 979 980 /* [20] */ INVALID, INVALID, INVALID, INVALID, 981 /* [24] */ INVALID, INVALID, INVALID, INVALID, 982 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 983 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 984 985 /* [30] */ INVALID, INVALID, INVALID, INVALID, 986 /* [34] */ INVALID, INVALID, INVALID, INVALID, 987 /* [38] */ INVALID, INVALID, INVALID, INVALID, 988 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 989 990 /* [40] */ INVALID, INVALID, INVALID, INVALID, 991 /* [44] */ INVALID, INVALID, INVALID, INVALID, 992 /* [48] */ INVALID, INVALID, INVALID, INVALID, 993 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 994 995 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 996 /* [54] */ INVALID, INVALID, INVALID, INVALID, 997 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 998 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 999 1000 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1001 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1002 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1003 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1004 1005 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 1006 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1008 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 1009 1010 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1011 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1012 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1013 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1014 1015 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 1016 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1017 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1018 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1019 1020 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1021 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1022 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1023 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1024 1025 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1026 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1028 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1029 1030 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 1031 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1033 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1034 1035 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 1036 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1037 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1038 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1039 1040 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1041 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 1042 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1043 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1044 1045 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 1046 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1047 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1048 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1049 }; 1050 1051 const instable_t dis_opAVXF20F3A[256] = { 1052 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1053 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1054 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1055 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1056 1057 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1058 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1059 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1060 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1061 1062 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1063 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1064 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1065 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1066 1067 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1068 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1069 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1070 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1071 1072 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1073 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1074 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1075 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1076 1077 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1078 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1079 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1080 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1081 1082 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1085 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1086 1087 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1090 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1091 1092 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1095 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1096 1097 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1098 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1100 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1101 1102 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1105 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1106 1107 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1108 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1110 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1111 1112 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1115 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1116 1117 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1118 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1119 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1120 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1121 1122 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1123 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1124 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1125 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1126 1127 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID, 1128 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1129 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1130 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1131 }; 1132 1133 const instable_t dis_opAVXF20F38[256] = { 1134 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1135 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1136 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1137 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1138 1139 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1140 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1141 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1142 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1143 1144 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1145 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1146 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1147 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1148 1149 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1150 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1151 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1152 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1153 1154 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1155 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1156 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1157 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1158 1159 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1160 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1161 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1162 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1163 1164 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1165 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1166 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1167 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1168 1169 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1170 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1171 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1172 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1173 1174 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1175 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1176 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1177 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1178 1179 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1180 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1181 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1182 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1183 1184 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1185 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1186 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1187 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1188 1189 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1190 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1191 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1192 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1193 1194 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1195 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1196 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1197 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1198 1199 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1200 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1201 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1202 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1203 1204 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1206 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1207 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1208 1209 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1210 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5), 1211 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1212 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1213 }; 1214 1215 const instable_t dis_opAVXF30F38[256] = { 1216 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1217 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1218 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1219 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1220 1221 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1222 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1223 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1224 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1225 1226 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1227 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1228 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1229 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1230 1231 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1232 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1233 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1234 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1235 1236 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1237 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1238 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1239 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1240 1241 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1242 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1243 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1244 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1245 1246 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1247 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1248 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1250 1251 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1252 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1253 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1254 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1255 1256 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1257 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1258 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1260 1261 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1262 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1263 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1265 1266 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1267 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1268 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1270 1271 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1272 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1273 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1275 1276 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1277 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1278 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1279 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1280 1281 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1282 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1283 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1285 1286 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1287 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1288 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1290 1291 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1292 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5), 1293 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1294 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1295 }; 1296 /* 1297 * Decode table for SIMD instructions with the repz (0xf3) prefix. 1298 */ 1299 const instable_t dis_opSIMDrepz[256] = { 1300 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1301 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1302 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1303 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1304 1305 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID, 1306 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID, 1307 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1308 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1309 1310 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1311 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1312 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 1313 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 1314 1315 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1316 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1317 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1318 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1319 1320 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1321 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1322 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1323 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1324 1325 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 1326 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1327 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 1328 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 1329 1330 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1331 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1332 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1333 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 1334 1335 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1336 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1337 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1338 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1339 1340 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1342 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1343 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1344 1345 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1347 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1348 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1349 1350 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1351 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1352 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1353 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1354 1355 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1356 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1357 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1358 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID, 1359 1360 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1361 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1362 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1363 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1364 1365 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1367 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1368 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1369 1370 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1372 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1373 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1374 1375 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1376 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1377 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1378 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1379 }; 1380 1381 const instable_t dis_opAVXF30F[256] = { 1382 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1383 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1384 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1385 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1386 1387 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1388 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1389 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1390 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1391 1392 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1393 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1394 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1395 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1396 1397 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1398 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1399 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1400 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1401 1402 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1403 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1404 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1405 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1406 1407 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1408 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1409 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1410 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1411 1412 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1413 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1414 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1415 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1416 1417 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1418 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1419 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1420 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1421 1422 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1423 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1424 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1425 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1426 1427 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1428 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1429 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1430 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1431 1432 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1433 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1434 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1435 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1436 1437 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1438 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1439 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1440 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1441 1442 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1443 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1444 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1445 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1446 1447 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1448 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1449 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1450 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1451 1452 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1453 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1454 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1455 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1456 1457 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1458 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1459 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1460 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1461 }; 1462 1463 /* 1464 * Table for instructions with an EVEX prefix. 1465 */ 1466 const instable_t dis_opAVX62[256] = { 1467 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1468 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1469 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1470 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1471 1472 /* [10] */ TSd("vmovup",EVEX_MX), TSd("vmovup",EVEX_RX), INVALID, INVALID, 1473 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1474 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1475 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1476 1477 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1478 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1479 /* [28] */ TSd("vmovap",EVEX_MX), TSd("vmovap",EVEX_RX), INVALID, INVALID, 1480 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1481 1482 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1483 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1484 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1485 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1486 1487 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1488 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1489 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1490 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1491 1492 /* [50] */ TNSZ("vpdpbusd",EVEX_RMrX,16),TNSZ("vpdpbusds",EVEX_RMrX,16),TNSZ("vpdpwssd",EVEX_RMrX,16),TNSZ("vpdpwssds",EVEX_RMrX,16), 1493 /* [54] */ TSd("vandp",EVEX_RMrX), TSd("vandnp",EVEX_RMrX), TSd("vorp",EVEX_RMrX), TSd("vxorp",EVEX_RMrX), 1494 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1495 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1496 1497 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1498 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1499 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1500 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_MX), 1501 1502 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1503 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1504 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1505 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_RX), 1506 1507 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1508 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1509 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1510 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1511 1512 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1513 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1514 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1515 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1516 1517 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1518 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1519 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1520 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1521 1522 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1523 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1524 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1525 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1526 1527 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1528 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1529 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1530 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1531 1532 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1533 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1534 /* [D8] */ INVALID, INVALID, INVALID, TSq("vpand",EVEX_RMrX), 1535 /* [DC] */ INVALID, INVALID, INVALID, TSq("vpandn",EVEX_RMrX), 1536 1537 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1538 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1539 /* [E8] */ INVALID, INVALID, INVALID, TSq("vpor",EVEX_RMrX), 1540 /* [EC] */ INVALID, INVALID, INVALID, TSq("vpxor",EVEX_RMrX), 1541 1542 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1543 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1544 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1545 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1546 }; 1547 1548 /* 1549 * The following two tables are used to encode crc32 and movbe 1550 * since they share the same opcodes. 1551 */ 1552 const instable_t dis_op0F38F0[2] = { 1553 /* [00] */ TNS("crc32b",CRC32), 1554 TS("movbe",MOVBE), 1555 }; 1556 1557 const instable_t dis_op0F38F1[2] = { 1558 /* [00] */ TS("crc32",CRC32), 1559 TS("movbe",MOVBE), 1560 }; 1561 1562 /* 1563 * The following table is used to distinguish between adox and adcx which share 1564 * the same opcodes. 1565 */ 1566 const instable_t dis_op0F38F6[2] = { 1567 /* [00] */ TNS("adcx",ADX), 1568 TNS("adox",ADX), 1569 }; 1570 1571 const instable_t dis_op0F38[256] = { 1572 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1573 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1574 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1575 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1576 1577 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1578 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1579 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1580 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1581 1582 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 1583 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 1584 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 1585 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1586 1587 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 1588 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 1589 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 1590 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 1591 1592 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 1593 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1594 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1595 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1596 1597 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1598 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1599 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1600 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1601 1602 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1604 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1605 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1606 1607 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1608 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1609 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1610 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1611 1612 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID, 1613 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1614 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1615 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1616 1617 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1619 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1620 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1621 1622 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1623 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1624 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1625 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1626 1627 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1628 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1629 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1630 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1631 1632 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1633 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1634 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16), 1635 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, INVALID, 1636 1637 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1638 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1639 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 1640 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 1641 1642 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1643 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1644 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1645 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1646 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1647 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID, 1648 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1649 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1650 }; 1651 1652 const instable_t dis_opAVX660F38[256] = { 1653 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 1654 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 1655 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 1656 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 1657 1658 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 1659 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16), 1660 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 1661 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 1662 1663 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 1664 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 1665 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 1666 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 1667 1668 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 1669 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16), 1670 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 1671 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 1672 1673 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 1674 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16), 1675 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1676 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1677 1678 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1679 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1680 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID, 1681 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1682 1683 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1684 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1685 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1686 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1687 1688 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1689 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1690 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID, 1691 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1692 1693 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1694 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1695 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1696 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID, 1697 1698 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16), 1699 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 1700 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 1701 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16), 1702 1703 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1704 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16), 1705 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16), 1706 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16), 1707 1708 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1709 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16), 1710 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16), 1711 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16), 1712 1713 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1714 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1715 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1716 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1717 1718 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1719 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1720 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 1721 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 1722 1723 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1724 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1725 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1726 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1727 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1728 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5), 1729 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1730 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1731 }; 1732 1733 const instable_t dis_op0F3A[256] = { 1734 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1735 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1736 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 1737 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 1738 1739 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1740 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 1741 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1742 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1743 1744 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 1745 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1746 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1747 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1748 1749 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1750 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1751 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1752 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1753 1754 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 1755 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 1756 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1757 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1758 1759 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1760 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1761 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1762 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1763 1764 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 1765 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1766 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1767 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1768 1769 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1770 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1771 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1772 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1773 1774 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1775 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1776 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1777 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1778 1779 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1780 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1781 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1782 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1783 1784 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1785 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1786 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1787 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1788 1789 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1790 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1791 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1792 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1793 1794 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1795 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1796 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1797 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, INVALID, INVALID, 1798 1799 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1800 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1801 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1802 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 1803 1804 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1805 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1806 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1807 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1808 1809 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1810 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1811 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1812 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1813 }; 1814 1815 const instable_t dis_opAVX660F3A[256] = { 1816 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID, 1817 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 1818 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 1819 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 1820 1821 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1822 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 1823 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 1824 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 1825 1826 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 1827 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1828 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1829 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1830 1831 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI), 1832 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1833 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID, 1834 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1835 1836 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 1837 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID, 1838 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 1839 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 1840 1841 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1842 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1843 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1844 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1845 1846 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 1847 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1848 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1849 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1850 1851 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1852 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1853 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1854 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1855 1856 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1857 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1858 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1859 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1860 1861 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1862 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1863 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1864 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1865 1866 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1867 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1868 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1869 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1870 1871 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1872 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1873 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1874 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1875 1876 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1877 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1878 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1879 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1880 1881 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1882 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1883 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1884 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 1885 1886 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1887 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1888 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1889 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1890 1891 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1892 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1893 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1894 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1895 }; 1896 1897 /* 1898 * Decode table for 0x0F0D which uses the first byte of the mod_rm to 1899 * indicate a sub-code. 1900 */ 1901 const instable_t dis_op0F0D[8] = { 1902 /* [00] */ INVALID, TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID, 1903 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1904 }; 1905 1906 /* 1907 * Decode table for 0x0F opcodes 1908 */ 1909 1910 const instable_t dis_op0F[16][16] = { 1911 { 1912 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 1913 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 1914 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 1915 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID, 1916 }, { 1917 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 1918 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 1919 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 1920 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 1921 }, { 1922 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 1923 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 1924 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 1925 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 1926 }, { 1927 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 1928 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID, 1929 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1930 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1931 }, { 1932 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 1933 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 1934 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 1935 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 1936 }, { 1937 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 1938 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 1939 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 1940 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 1941 }, { 1942 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 1943 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 1944 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 1945 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 1946 }, { 1947 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 1948 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 1949 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 1950 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 1951 }, { 1952 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 1953 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 1954 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 1955 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 1956 }, { 1957 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 1958 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 1959 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 1960 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 1961 }, { 1962 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 1963 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 1964 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 1965 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 1966 }, { 1967 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 1968 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 1969 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 1970 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 1971 }, { 1972 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 1973 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 1974 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1975 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1976 }, { 1977 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 1978 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 1979 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 1980 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 1981 }, { 1982 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 1983 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 1984 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 1985 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 1986 }, { 1987 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 1988 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 1989 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 1990 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 1991 } }; 1992 1993 const instable_t dis_opAVX0F[16][16] = { 1994 { 1995 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1996 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1997 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1998 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1999 }, { 2000 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 2001 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 2002 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2003 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 2004 }, { 2005 /* [20] */ INVALID, INVALID, INVALID, INVALID, 2006 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2007 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 2008 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 2009 }, { 2010 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2011 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2012 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2013 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2014 }, { 2015 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 2016 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 2017 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 2018 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2019 }, { 2020 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 2021 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 2022 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 2023 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 2024 }, { 2025 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2026 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2027 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2028 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2029 }, { 2030 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2031 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 2032 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2033 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2034 }, { 2035 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2036 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2037 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2038 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2039 }, { 2040 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 2041 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2042 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 2043 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2044 }, { 2045 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2046 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2047 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2048 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 2049 }, { 2050 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2051 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2052 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2053 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2054 }, { 2055 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 2056 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 2057 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2058 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2059 }, { 2060 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2061 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2062 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2063 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2064 }, { 2065 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2066 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2067 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2068 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2069 }, { 2070 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5), 2071 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5), 2072 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2073 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2074 } }; 2075 2076 /* 2077 * Decode table for 0x80 opcodes 2078 */ 2079 2080 const instable_t dis_op80[8] = { 2081 2082 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 2083 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 2084 }; 2085 2086 2087 /* 2088 * Decode table for 0x81 opcodes. 2089 */ 2090 2091 const instable_t dis_op81[8] = { 2092 2093 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 2094 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 2095 }; 2096 2097 2098 /* 2099 * Decode table for 0x82 opcodes. 2100 */ 2101 2102 const instable_t dis_op82[8] = { 2103 2104 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 2105 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 2106 }; 2107 /* 2108 * Decode table for 0x83 opcodes. 2109 */ 2110 2111 const instable_t dis_op83[8] = { 2112 2113 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 2114 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 2115 }; 2116 2117 /* 2118 * Decode table for 0xC0 opcodes. 2119 */ 2120 2121 const instable_t dis_opC0[8] = { 2122 2123 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 2124 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 2125 }; 2126 2127 /* 2128 * Decode table for 0xD0 opcodes. 2129 */ 2130 2131 const instable_t dis_opD0[8] = { 2132 2133 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2134 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2135 }; 2136 2137 /* 2138 * Decode table for 0xC1 opcodes. 2139 * 186 instruction set 2140 */ 2141 2142 const instable_t dis_opC1[8] = { 2143 2144 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 2145 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 2146 }; 2147 2148 /* 2149 * Decode table for 0xD1 opcodes. 2150 */ 2151 2152 const instable_t dis_opD1[8] = { 2153 2154 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2155 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 2156 }; 2157 2158 2159 /* 2160 * Decode table for 0xD2 opcodes. 2161 */ 2162 2163 const instable_t dis_opD2[8] = { 2164 2165 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2166 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2167 }; 2168 /* 2169 * Decode table for 0xD3 opcodes. 2170 */ 2171 2172 const instable_t dis_opD3[8] = { 2173 2174 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2175 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 2176 }; 2177 2178 2179 /* 2180 * Decode table for 0xF6 opcodes. 2181 */ 2182 2183 const instable_t dis_opF6[8] = { 2184 2185 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 2186 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 2187 }; 2188 2189 2190 /* 2191 * Decode table for 0xF7 opcodes. 2192 */ 2193 2194 const instable_t dis_opF7[8] = { 2195 2196 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 2197 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 2198 }; 2199 2200 2201 /* 2202 * Decode table for 0xFE opcodes. 2203 */ 2204 2205 const instable_t dis_opFE[8] = { 2206 2207 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 2208 /* [4] */ INVALID, INVALID, INVALID, INVALID, 2209 }; 2210 /* 2211 * Decode table for 0xFF opcodes. 2212 */ 2213 2214 const instable_t dis_opFF[8] = { 2215 2216 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 2217 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 2218 }; 2219 2220 /* for 287 instructions, which are a mess to decode */ 2221 2222 const instable_t dis_opFP1n2[8][8] = { 2223 { 2224 /* bit pattern: 1101 1xxx MODxx xR/M */ 2225 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 2226 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 2227 }, { 2228 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 2229 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 2230 }, { 2231 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 2232 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 2233 }, { 2234 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M), 2235 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 2236 }, { 2237 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 2238 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 2239 }, { 2240 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 2241 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 2242 }, { 2243 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 2244 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 2245 }, { 2246 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2), 2247 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 2248 } }; 2249 2250 const instable_t dis_opFP3[8][8] = { 2251 { 2252 /* bit pattern: 1101 1xxx 11xx xREG */ 2253 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2254 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2255 }, { 2256 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 2257 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 2258 }, { 2259 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 2260 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 2261 }, { 2262 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 2263 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 2264 }, { 2265 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2266 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2267 }, { 2268 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 2269 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 2270 }, { 2271 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 2272 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 2273 }, { 2274 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 2275 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 2276 } }; 2277 2278 const instable_t dis_opFP4[4][8] = { 2279 { 2280 /* bit pattern: 1101 1001 111x xxxx */ 2281 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 2282 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 2283 }, { 2284 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 2285 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 2286 }, { 2287 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 2288 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 2289 }, { 2290 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 2291 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 2292 } }; 2293 2294 const instable_t dis_opFP5[8] = { 2295 /* bit pattern: 1101 1011 111x xxxx */ 2296 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 2297 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 2298 }; 2299 2300 const instable_t dis_opFP6[8] = { 2301 /* bit pattern: 1101 1011 11yy yxxx */ 2302 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 2303 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 2304 }; 2305 2306 const instable_t dis_opFP7[8] = { 2307 /* bit pattern: 1101 1010 11yy yxxx */ 2308 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 2309 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2310 }; 2311 2312 /* 2313 * Main decode table for the op codes. The first two nibbles 2314 * will be used as an index into the table. If there is a 2315 * a need to further decode an instruction, the array to be 2316 * referenced is indicated with the other two entries being 2317 * empty. 2318 */ 2319 2320 const instable_t dis_distable[16][16] = { 2321 { 2322 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 2323 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 2324 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 2325 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 2326 }, { 2327 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 2328 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 2329 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 2330 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 2331 }, { 2332 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 2333 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 2334 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 2335 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 2336 }, { 2337 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 2338 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 2339 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 2340 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 2341 }, { 2342 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2343 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2344 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2345 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2346 }, { 2347 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2348 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2349 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2350 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2351 }, { 2352 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw), 2353 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 2354 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 2355 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 2356 }, { 2357 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 2358 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 2359 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 2360 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 2361 }, { 2362 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 2363 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 2364 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 2365 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 2366 }, { 2367 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2368 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2369 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 2370 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM), 2371 }, { 2372 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 2373 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 2374 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 2375 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 2376 }, { 2377 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2378 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2379 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2380 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2381 }, { 2382 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 2383 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 2384 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 2385 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 2386 }, { 2387 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 2388 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 2389 2390 /* 287 instructions. Note that although the indirect field */ 2391 /* indicates opFP1n2 for further decoding, this is not necessarily */ 2392 /* the case since the opFP arrays are not partitioned according to key1 */ 2393 /* and key2. opFP1n2 is given only to indicate that we haven't */ 2394 /* finished decoding the instruction. */ 2395 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2396 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2397 }, { 2398 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 2399 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 2400 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 2401 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 2402 }, { 2403 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 2404 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 2405 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 2406 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 2407 } }; 2408 2409 /* END CSTYLED */ 2410 2411 /* 2412 * common functions to decode and disassemble an x86 or amd64 instruction 2413 */ 2414 2415 /* 2416 * These are the individual fields of a REX prefix. Note that a REX 2417 * prefix with none of these set is still needed to: 2418 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 2419 * - access the %sil, %dil, %bpl, %spl registers 2420 */ 2421 #define REX_W 0x08 /* 64 bit operand size when set */ 2422 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 2423 #define REX_X 0x02 /* high order bit extension of SIB index field */ 2424 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 2425 2426 /* 2427 * These are the individual fields of a VEX/EVEX prefix. 2428 */ 2429 #define VEX_R 0x08 /* REX.R in 1's complement form */ 2430 #define VEX_X 0x04 /* REX.X in 1's complement form */ 2431 #define VEX_B 0x02 /* REX.B in 1's complement form */ 2432 2433 /* Additional EVEX prefix definitions */ 2434 #define EVEX_R 0x01 /* REX.R' in 1's complement form */ 2435 #define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */ 2436 #define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */ 2437 2438 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 2439 #define VEX_L 0x04 2440 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */ 2441 #define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */ 2442 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 2443 #define VEX_m 0x1F /* VEX m-mmmm field */ 2444 #define EVEX_m 0x3 /* EVEX mm field */ 2445 #define VEX_v 0x78 /* VEX/EVEX register specifier */ 2446 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 2447 2448 /* VEX m-mmmm field, only used by three bytes prefix */ 2449 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 2450 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 2451 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 2452 2453 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 2454 #define VEX_p_66 0x01 2455 #define VEX_p_F3 0x02 2456 #define VEX_p_F2 0x03 2457 2458 /* 2459 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2460 */ 2461 static int isize[] = {1, 2, 4, 4}; 2462 static int isize64[] = {1, 2, 4, 8}; 2463 2464 /* 2465 * Just a bunch of useful macros. 2466 */ 2467 #define WBIT(x) (x & 0x1) /* to get w bit */ 2468 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2469 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2470 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2471 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2472 2473 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2474 2475 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2476 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2477 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2478 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2479 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2480 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2481 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2482 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2483 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2484 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2485 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ 2486 #define ZMM_OPND 11 /* "value" used to indicate a zmm reg */ 2487 2488 /* 2489 * The AVX2 gather instructions are a bit of a mess. While there's a pattern, 2490 * there's not really a consistent scheme that we can use to know what the mode 2491 * is supposed to be for a given type. Various instructions, like VPGATHERDD, 2492 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have 2493 * some registers match VEX_L, but the VSIB is always XMM. 2494 * 2495 * The simplest way to deal with this is to just define a table based on the 2496 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into 2497 * them. 2498 * 2499 * We further have to subdivide this based on the value of VEX_W and the value 2500 * of VEX_L. The array is constructed to be indexed as: 2501 * [opcode - 0x90][VEX_W][VEX_L]. 2502 */ 2503 /* w = 0, 0x90 */ 2504 typedef struct dis_gather_regs { 2505 uint_t dgr_arg0; /* src reg */ 2506 uint_t dgr_arg1; /* vsib reg */ 2507 uint_t dgr_arg2; /* dst reg */ 2508 char *dgr_suffix; /* suffix to append */ 2509 } dis_gather_regs_t; 2510 2511 static dis_gather_regs_t dis_vgather[4][2][2] = { 2512 { 2513 /* op 0x90, W.0 */ 2514 { 2515 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2516 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2517 }, 2518 /* op 0x90, W.1 */ 2519 { 2520 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2521 { YMM_OPND, XMM_OPND, YMM_OPND, "q" } 2522 } 2523 }, 2524 { 2525 /* op 0x91, W.0 */ 2526 { 2527 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2528 { XMM_OPND, YMM_OPND, XMM_OPND, "d" }, 2529 }, 2530 /* op 0x91, W.1 */ 2531 { 2532 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2533 { YMM_OPND, YMM_OPND, YMM_OPND, "q" }, 2534 } 2535 }, 2536 { 2537 /* op 0x92, W.0 */ 2538 { 2539 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2540 { YMM_OPND, YMM_OPND, YMM_OPND, "s" } 2541 }, 2542 /* op 0x92, W.1 */ 2543 { 2544 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2545 { YMM_OPND, XMM_OPND, YMM_OPND, "d" } 2546 } 2547 }, 2548 { 2549 /* op 0x93, W.0 */ 2550 { 2551 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2552 { XMM_OPND, YMM_OPND, XMM_OPND, "s" } 2553 }, 2554 /* op 0x93, W.1 */ 2555 { 2556 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2557 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2558 } 2559 } 2560 }; 2561 2562 /* 2563 * Get the next byte and separate the op code into the high and low nibbles. 2564 */ 2565 static int 2566 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2567 { 2568 int byte; 2569 2570 /* 2571 * x86 instructions have a maximum length of 15 bytes. Bail out if 2572 * we try to read more. 2573 */ 2574 if (x->d86_len >= 15) 2575 return (x->d86_error = 1); 2576 2577 if (x->d86_error) 2578 return (1); 2579 byte = x->d86_get_byte(x->d86_data); 2580 if (byte < 0) 2581 return (x->d86_error = 1); 2582 x->d86_bytes[x->d86_len++] = byte; 2583 *low = byte & 0xf; /* ----xxxx low 4 bits */ 2584 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 2585 return (0); 2586 } 2587 2588 /* 2589 * Get and decode an SIB (scaled index base) byte 2590 */ 2591 static void 2592 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 2593 { 2594 int byte; 2595 2596 if (x->d86_error) 2597 return; 2598 2599 byte = x->d86_get_byte(x->d86_data); 2600 if (byte < 0) { 2601 x->d86_error = 1; 2602 return; 2603 } 2604 x->d86_bytes[x->d86_len++] = byte; 2605 2606 *base = byte & 0x7; 2607 *index = (byte >> 3) & 0x7; 2608 *ss = (byte >> 6) & 0x3; 2609 } 2610 2611 /* 2612 * Get the byte following the op code and separate it into the 2613 * mode, register, and r/m fields. 2614 */ 2615 static void 2616 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 2617 { 2618 if (x->d86_got_modrm == 0) { 2619 if (x->d86_rmindex == -1) 2620 x->d86_rmindex = x->d86_len; 2621 dtrace_get_SIB(x, mode, reg, r_m); 2622 x->d86_got_modrm = 1; 2623 } 2624 } 2625 2626 /* 2627 * Adjust register selection based on any REX prefix bits present. 2628 */ 2629 /*ARGSUSED*/ 2630 static void 2631 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 2632 { 2633 if (reg != NULL && r_m == NULL) { 2634 if (rex_prefix & REX_B) 2635 *reg += 8; 2636 } else { 2637 if (reg != NULL && (REX_R & rex_prefix) != 0) 2638 *reg += 8; 2639 if (r_m != NULL && (REX_B & rex_prefix) != 0) 2640 *r_m += 8; 2641 } 2642 } 2643 2644 /* 2645 * Adjust register selection based on any VEX prefix bits present. 2646 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 2647 */ 2648 /*ARGSUSED*/ 2649 static void 2650 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 2651 { 2652 if (reg != NULL && r_m == NULL) { 2653 if (!(vex_byte1 & VEX_B)) 2654 *reg += 8; 2655 } else { 2656 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 2657 *reg += 8; 2658 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 2659 *r_m += 8; 2660 } 2661 } 2662 2663 /* 2664 * Adjust the instruction mnemonic with the appropriate suffix. 2665 */ 2666 /* ARGSUSED */ 2667 static void 2668 dtrace_evex_mnem_adjust(dis86_t *x, const instable_t *dp, uint_t vex_W, 2669 uint_t evex_byte2) 2670 { 2671 #ifdef DIS_TEXT 2672 /* No adjustments needed for VNNI instructions. */ 2673 if (dp == &dis_opAVX62[0x50] || dp == &dis_opAVX62[0x51] || 2674 dp == &dis_opAVX62[0x52] || dp == &dis_opAVX62[0x53]) { 2675 return; 2676 } 2677 2678 if (dp == &dis_opAVX62[0x7f] || /* vmovdq */ 2679 dp == &dis_opAVX62[0x6f]) { 2680 /* Aligned or Unaligned? */ 2681 if ((evex_byte2 & 0x3) == 0x01) { 2682 (void) strlcat(x->d86_mnem, "a", OPLEN); 2683 (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32", 2684 OPLEN); 2685 } else { 2686 (void) strlcat(x->d86_mnem, "u", OPLEN); 2687 switch (evex_byte2 & 0x81) { 2688 case 0x0: 2689 (void) strlcat(x->d86_mnem, "32", OPLEN); 2690 break; 2691 case 0x1: 2692 (void) strlcat(x->d86_mnem, "8", OPLEN); 2693 break; 2694 case 0x80: 2695 (void) strlcat(x->d86_mnem, "64", OPLEN); 2696 break; 2697 case 0x81: 2698 (void) strlcat(x->d86_mnem, "16", OPLEN); 2699 break; 2700 } 2701 } 2702 } else { 2703 if (dp->it_avxsuf == AVS5Q) { 2704 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 2705 OPLEN); 2706 } else { 2707 (void) strlcat(x->d86_mnem, vex_W != 0 ? "d" : "s", 2708 OPLEN); 2709 } 2710 } 2711 #endif 2712 } 2713 2714 /* 2715 * The following three functions adjust the register selection based on any 2716 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software 2717 * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and 2718 * section 2.6.2 Table 2-31. 2719 */ 2720 static void 2721 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg) 2722 { 2723 if (reg != NULL) { 2724 if ((VEX_R & evex_byte1) == 0) { 2725 *reg += 8; 2726 } 2727 if ((EVEX_R & evex_byte1) == 0) { 2728 *reg += 16; 2729 } 2730 } 2731 } 2732 2733 static void 2734 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m) 2735 { 2736 if (r_m != NULL) { 2737 if ((VEX_B & evex_byte1) == 0) { 2738 *r_m += 8; 2739 } 2740 if ((VEX_X & evex_byte1) == 0) { 2741 *r_m += 16; 2742 } 2743 } 2744 } 2745 2746 /* 2747 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36. 2748 */ 2749 static void 2750 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp) 2751 { 2752 switch (evex_L) { 2753 case 0x0: 2754 *wbitp = XMM_OPND; 2755 break; 2756 case 0x1: 2757 *wbitp = YMM_OPND; 2758 break; 2759 case 0x2: 2760 *wbitp = ZMM_OPND; 2761 break; 2762 } 2763 } 2764 2765 /* 2766 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5. 2767 * This currently only handles a subset of the possibilities. 2768 */ 2769 static void 2770 dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) 2771 { 2772 d86opnd_t *opnd = &x->d86_opnd[opindex]; 2773 2774 if (x->d86_error) 2775 return; 2776 2777 /* Check disp8 bit in the ModR/M byte */ 2778 if ((modrm & 0x80) == 0x80) 2779 return; 2780 2781 /* use evex_L to adjust the value */ 2782 switch (L) { 2783 case 0x0: 2784 opnd->d86_value *= 16; 2785 break; 2786 case 0x1: 2787 opnd->d86_value *= 32; 2788 break; 2789 case 0x2: 2790 opnd->d86_value *= 64; 2791 break; 2792 } 2793 } 2794 2795 /* 2796 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30. 2797 */ 2798 /* ARGSUSED */ 2799 static void 2800 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3) 2801 { 2802 #ifdef DIS_TEXT 2803 char *opnd = x->d86_opnd[tgtop].d86_opnd; 2804 int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; 2805 #endif 2806 if (x->d86_error) 2807 return; 2808 2809 #ifdef DIS_TEXT 2810 if (opmask_reg != 0) { 2811 /* Append the opmask register to operand 1 */ 2812 (void) strlcat(opnd, "{", OPLEN); 2813 (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN); 2814 (void) strlcat(opnd, "}", OPLEN); 2815 } 2816 if ((evex_byte3 & EVEX_ZERO_MASK) != 0) { 2817 /* Append the 'zeroing' modifier to operand 1 */ 2818 (void) strlcat(opnd, "{z}", OPLEN); 2819 } 2820 #endif /* DIS_TEXT */ 2821 } 2822 2823 /* 2824 * Get an immediate operand of the given size, with sign extension. 2825 */ 2826 static void 2827 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 2828 { 2829 int i; 2830 int byte; 2831 int valsize; 2832 2833 if (x->d86_numopnds < opindex + 1) 2834 x->d86_numopnds = opindex + 1; 2835 2836 switch (wbit) { 2837 case BYTE_OPND: 2838 valsize = 1; 2839 break; 2840 case LONG_OPND: 2841 if (x->d86_opnd_size == SIZE16) 2842 valsize = 2; 2843 else if (x->d86_opnd_size == SIZE32) 2844 valsize = 4; 2845 else 2846 valsize = 8; 2847 break; 2848 case MM_OPND: 2849 case XMM_OPND: 2850 case YMM_OPND: 2851 case ZMM_OPND: 2852 case SEG_OPND: 2853 case CONTROL_OPND: 2854 case DEBUG_OPND: 2855 case TEST_OPND: 2856 valsize = size; 2857 break; 2858 case WORD_OPND: 2859 valsize = 2; 2860 break; 2861 } 2862 if (valsize < size) 2863 valsize = size; 2864 2865 if (x->d86_error) 2866 return; 2867 x->d86_opnd[opindex].d86_value = 0; 2868 for (i = 0; i < size; ++i) { 2869 byte = x->d86_get_byte(x->d86_data); 2870 if (byte < 0) { 2871 x->d86_error = 1; 2872 return; 2873 } 2874 x->d86_bytes[x->d86_len++] = byte; 2875 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 2876 } 2877 /* Do sign extension */ 2878 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 2879 for (; i < sizeof (uint64_t); i++) 2880 x->d86_opnd[opindex].d86_value |= 2881 (uint64_t)0xff << (i * 8); 2882 } 2883 #ifdef DIS_TEXT 2884 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2885 x->d86_opnd[opindex].d86_value_size = valsize; 2886 x->d86_imm_bytes += size; 2887 #endif 2888 } 2889 2890 /* 2891 * Get an ip relative operand of the given size, with sign extension. 2892 */ 2893 static void 2894 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 2895 { 2896 dtrace_imm_opnd(x, wbit, size, opindex); 2897 #ifdef DIS_TEXT 2898 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 2899 #endif 2900 } 2901 2902 /* 2903 * Check to see if there is a segment override prefix pending. 2904 * If so, print it in the current 'operand' location and set 2905 * the override flag back to false. 2906 */ 2907 /*ARGSUSED*/ 2908 static void 2909 dtrace_check_override(dis86_t *x, int opindex) 2910 { 2911 #ifdef DIS_TEXT 2912 if (x->d86_seg_prefix) { 2913 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 2914 x->d86_seg_prefix, PFIXLEN); 2915 } 2916 #endif 2917 x->d86_seg_prefix = NULL; 2918 } 2919 2920 2921 /* 2922 * Process a single instruction Register or Memory operand. 2923 * 2924 * mode = addressing mode from ModRM byte 2925 * r_m = r_m (or reg if mode == 3) field from ModRM byte 2926 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 2927 * o = index of operand that we are processing (0, 1 or 2) 2928 * 2929 * the value of reg or r_m must have already been adjusted for any REX prefix. 2930 */ 2931 /*ARGSUSED*/ 2932 static void 2933 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 2934 { 2935 int have_SIB = 0; /* flag presence of scale-index-byte */ 2936 uint_t ss; /* scale-factor from opcode */ 2937 uint_t index; /* index register number */ 2938 uint_t base; /* base register number */ 2939 int dispsize; /* size of displacement in bytes */ 2940 #ifdef DIS_TEXT 2941 char *opnd = x->d86_opnd[opindex].d86_opnd; 2942 #endif 2943 2944 if (x->d86_numopnds < opindex + 1) 2945 x->d86_numopnds = opindex + 1; 2946 2947 if (x->d86_error) 2948 return; 2949 2950 /* 2951 * first handle a simple register 2952 */ 2953 if (mode == REG_ONLY) { 2954 #ifdef DIS_TEXT 2955 switch (wbit) { 2956 case MM_OPND: 2957 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 2958 break; 2959 case XMM_OPND: 2960 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 2961 break; 2962 case YMM_OPND: 2963 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 2964 break; 2965 case ZMM_OPND: 2966 (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN); 2967 break; 2968 case KOPMASK_OPND: 2969 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); 2970 break; 2971 case SEG_OPND: 2972 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 2973 break; 2974 case CONTROL_OPND: 2975 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 2976 break; 2977 case DEBUG_OPND: 2978 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 2979 break; 2980 case TEST_OPND: 2981 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 2982 break; 2983 case BYTE_OPND: 2984 if (x->d86_rex_prefix == 0) 2985 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 2986 else 2987 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 2988 break; 2989 case WORD_OPND: 2990 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2991 break; 2992 case LONG_OPND: 2993 if (x->d86_opnd_size == SIZE16) 2994 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2995 else if (x->d86_opnd_size == SIZE32) 2996 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 2997 else 2998 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 2999 break; 3000 } 3001 #endif /* DIS_TEXT */ 3002 return; 3003 } 3004 3005 /* 3006 * if symbolic representation, skip override prefix, if any 3007 */ 3008 dtrace_check_override(x, opindex); 3009 3010 /* 3011 * Handle 16 bit memory references first, since they decode 3012 * the mode values more simply. 3013 * mode 1 is r_m + 8 bit displacement 3014 * mode 2 is r_m + 16 bit displacement 3015 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 3016 */ 3017 if (x->d86_addr_size == SIZE16) { 3018 if ((mode == 0 && r_m == 6) || mode == 2) 3019 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 3020 else if (mode == 1) 3021 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 3022 #ifdef DIS_TEXT 3023 if (mode == 0 && r_m == 6) 3024 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3025 else if (mode == 0) 3026 x->d86_opnd[opindex].d86_mode = MODE_NONE; 3027 else 3028 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3029 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 3030 #endif 3031 return; 3032 } 3033 3034 /* 3035 * 32 and 64 bit addressing modes are more complex since they 3036 * can involve an SIB (scaled index and base) byte to decode. 3037 */ 3038 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) { 3039 have_SIB = 1; 3040 dtrace_get_SIB(x, &ss, &index, &base); 3041 if (x->d86_error) 3042 return; 3043 if (base != 5 || mode != 0) 3044 if (x->d86_rex_prefix & REX_B) 3045 base += 8; 3046 if (x->d86_rex_prefix & REX_X) 3047 index += 8; 3048 } else { 3049 base = r_m; 3050 } 3051 3052 /* 3053 * Compute the displacement size and get its bytes 3054 */ 3055 dispsize = 0; 3056 3057 if (mode == 1) 3058 dispsize = 1; 3059 else if (mode == 2) 3060 dispsize = 4; 3061 else if ((r_m & 7) == EBP_REGNO || 3062 (have_SIB && (base & 7) == EBP_REGNO)) 3063 dispsize = 4; 3064 3065 if (dispsize > 0) { 3066 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 3067 dispsize, opindex); 3068 if (x->d86_error) 3069 return; 3070 } 3071 3072 #ifdef DIS_TEXT 3073 if (dispsize > 0) 3074 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3075 3076 if (have_SIB == 0) { 3077 if (x->d86_mode == SIZE32) { 3078 if (mode == 0) 3079 (void) strlcat(opnd, dis_addr32_mode0[r_m], 3080 OPLEN); 3081 else 3082 (void) strlcat(opnd, dis_addr32_mode12[r_m], 3083 OPLEN); 3084 } else { 3085 if (mode == 0) { 3086 (void) strlcat(opnd, dis_addr64_mode0[r_m], 3087 OPLEN); 3088 if (r_m == 5) { 3089 x->d86_opnd[opindex].d86_mode = 3090 MODE_RIPREL; 3091 } 3092 } else { 3093 (void) strlcat(opnd, dis_addr64_mode12[r_m], 3094 OPLEN); 3095 } 3096 } 3097 } else { 3098 uint_t need_paren = 0; 3099 char **regs; 3100 char **bregs; 3101 const char *const *sf; 3102 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 3103 regs = (char **)dis_REG32; 3104 else 3105 regs = (char **)dis_REG64; 3106 3107 if (x->d86_vsib != 0) { 3108 if (wbit == YMM_OPND) { /* NOTE this is not addr_size */ 3109 bregs = (char **)dis_YMMREG; 3110 } else if (wbit == XMM_OPND) { 3111 bregs = (char **)dis_XMMREG; 3112 } else { 3113 bregs = (char **)dis_ZMMREG; 3114 } 3115 sf = dis_vscale_factor; 3116 } else { 3117 bregs = regs; 3118 sf = dis_scale_factor; 3119 } 3120 3121 /* 3122 * print the base (if any) 3123 */ 3124 if (base == EBP_REGNO && mode == 0) { 3125 if (index != ESP_REGNO || x->d86_vsib != 0) { 3126 (void) strlcat(opnd, "(", OPLEN); 3127 need_paren = 1; 3128 } 3129 } else { 3130 (void) strlcat(opnd, "(", OPLEN); 3131 (void) strlcat(opnd, regs[base], OPLEN); 3132 need_paren = 1; 3133 } 3134 3135 /* 3136 * print the index (if any) 3137 */ 3138 if (index != ESP_REGNO || x->d86_vsib) { 3139 (void) strlcat(opnd, ",", OPLEN); 3140 (void) strlcat(opnd, bregs[index], OPLEN); 3141 (void) strlcat(opnd, sf[ss], OPLEN); 3142 } else 3143 if (need_paren) 3144 (void) strlcat(opnd, ")", OPLEN); 3145 } 3146 #endif 3147 } 3148 3149 /* 3150 * Operand sequence for standard instruction involving one register 3151 * and one register/memory operand. 3152 * wbit indicates a byte(0) or opnd_size(1) operation 3153 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 3154 */ 3155 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 3156 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3157 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3158 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3159 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 3160 } 3161 3162 /* 3163 * Similar to above, but allows for the two operands to be of different 3164 * classes (ie. wbit). 3165 * wbit is for the r_m operand 3166 * w2 is for the reg operand 3167 */ 3168 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 3169 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3170 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3171 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3172 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 3173 } 3174 3175 /* 3176 * Similar, but for 2 operands plus an immediate. 3177 * vbit indicates direction 3178 * 0 for "opcode imm, r, r_m" or 3179 * 1 for "opcode imm, r_m, r" 3180 */ 3181 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 3182 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3183 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3184 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 3185 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 3186 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3187 } 3188 3189 /* 3190 * Similar, but for 2 operands plus two immediates. 3191 */ 3192 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 3193 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3194 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3195 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3196 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 3197 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3198 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3199 } 3200 3201 /* 3202 * 1 operands plus two immediates. 3203 */ 3204 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 3205 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3206 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3207 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3208 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3209 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3210 } 3211 3212 /* 3213 * Dissassemble a single x86 or amd64 instruction. 3214 * 3215 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 3216 * for interpreting instructions. 3217 * 3218 * returns non-zero for bad opcode 3219 */ 3220 int 3221 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 3222 { 3223 const instable_t *dp; /* decode table being used */ 3224 #ifdef DIS_TEXT 3225 uint_t i; 3226 #endif 3227 #ifdef DIS_MEM 3228 uint_t nomem = 0; 3229 #define NOMEM (nomem = 1) 3230 #else 3231 #define NOMEM /* nothing */ 3232 #endif 3233 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 3234 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 3235 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 3236 uint_t w2; /* wbit value for second operand */ 3237 uint_t vbit; 3238 uint_t mode = 0; /* mode value from ModRM byte */ 3239 uint_t reg; /* reg value from ModRM byte */ 3240 uint_t r_m; /* r_m value from ModRM byte */ 3241 3242 uint_t opcode1; /* high nibble of 1st byte */ 3243 uint_t opcode2; /* low nibble of 1st byte */ 3244 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 3245 uint_t opcode4; /* high nibble of 2nd byte */ 3246 uint_t opcode5; /* low nibble of 2nd byte */ 3247 uint_t opcode6; /* high nibble of 3rd byte */ 3248 uint_t opcode7; /* low nibble of 3rd byte */ 3249 uint_t opcode8; /* high nibble of 4th byte */ 3250 uint_t opcode9; /* low nibble of 4th byte */ 3251 uint_t opcode_bytes = 1; 3252 3253 /* 3254 * legacy prefixes come in 5 flavors, you should have only one of each 3255 */ 3256 uint_t opnd_size_prefix = 0; 3257 uint_t addr_size_prefix = 0; 3258 uint_t segment_prefix = 0; 3259 uint_t lock_prefix = 0; 3260 uint_t rep_prefix = 0; 3261 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 3262 3263 /* 3264 * Intel VEX instruction encoding prefix and fields 3265 */ 3266 3267 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 3268 uint_t vex_prefix = 0; 3269 3270 /* 3271 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 3272 * (for 3 bytes prefix) 3273 */ 3274 uint_t vex_byte1 = 0; 3275 3276 /* 3277 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r. 3278 */ 3279 uint_t evex_byte1 = 0; 3280 uint_t evex_byte2 = 0; 3281 uint_t evex_byte3 = 0; 3282 3283 /* 3284 * For 32-bit mode, it should prefetch the next byte to 3285 * distinguish between AVX and les/lds 3286 */ 3287 uint_t vex_prefetch = 0; 3288 3289 uint_t vex_m = 0; 3290 uint_t vex_v = 0; 3291 uint_t vex_p = 0; 3292 uint_t vex_R = 1; 3293 uint_t vex_X = 1; 3294 uint_t vex_B = 1; 3295 uint_t vex_W = 0; 3296 uint_t vex_L = 0; 3297 uint_t evex_L = 0; 3298 uint_t evex_modrm = 0; 3299 dis_gather_regs_t *vreg; 3300 3301 #ifdef DIS_TEXT 3302 /* Instruction name for BLS* family of instructions */ 3303 char *blsinstr; 3304 #endif 3305 3306 size_t off; 3307 3308 instable_t dp_mmx; 3309 3310 x->d86_len = 0; 3311 x->d86_rmindex = -1; 3312 x->d86_error = 0; 3313 #ifdef DIS_TEXT 3314 x->d86_numopnds = 0; 3315 x->d86_seg_prefix = NULL; 3316 x->d86_mnem[0] = 0; 3317 for (i = 0; i < 4; ++i) { 3318 x->d86_opnd[i].d86_opnd[0] = 0; 3319 x->d86_opnd[i].d86_prefix[0] = 0; 3320 x->d86_opnd[i].d86_value_size = 0; 3321 x->d86_opnd[i].d86_value = 0; 3322 x->d86_opnd[i].d86_mode = MODE_NONE; 3323 } 3324 #endif 3325 x->d86_rex_prefix = 0; 3326 x->d86_got_modrm = 0; 3327 x->d86_memsize = 0; 3328 x->d86_vsib = 0; 3329 3330 if (cpu_mode == SIZE16) { 3331 opnd_size = SIZE16; 3332 addr_size = SIZE16; 3333 } else if (cpu_mode == SIZE32) { 3334 opnd_size = SIZE32; 3335 addr_size = SIZE32; 3336 } else { 3337 opnd_size = SIZE32; 3338 addr_size = SIZE64; 3339 } 3340 3341 /* 3342 * Get one opcode byte and check for zero padding that follows 3343 * jump tables. 3344 */ 3345 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3346 goto error; 3347 3348 if (opcode1 == 0 && opcode2 == 0 && 3349 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 3350 #ifdef DIS_TEXT 3351 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 3352 #endif 3353 goto done; 3354 } 3355 3356 /* 3357 * Gather up legacy x86 prefix bytes. 3358 */ 3359 for (;;) { 3360 uint_t *which_prefix = NULL; 3361 3362 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3363 3364 switch (dp->it_adrmode) { 3365 case PREFIX: 3366 which_prefix = &rep_prefix; 3367 break; 3368 case LOCK: 3369 which_prefix = &lock_prefix; 3370 break; 3371 case OVERRIDE: 3372 which_prefix = &segment_prefix; 3373 #ifdef DIS_TEXT 3374 x->d86_seg_prefix = (char *)dp->it_name; 3375 #endif 3376 if (dp->it_invalid64 && cpu_mode == SIZE64) 3377 goto error; 3378 break; 3379 case AM: 3380 which_prefix = &addr_size_prefix; 3381 break; 3382 case DM: 3383 which_prefix = &opnd_size_prefix; 3384 break; 3385 } 3386 if (which_prefix == NULL) 3387 break; 3388 *which_prefix = (opcode1 << 4) | opcode2; 3389 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3390 goto error; 3391 } 3392 3393 /* 3394 * Handle amd64 mode PREFIX values. 3395 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 3396 * We might have a REX prefix (opcodes 0x40-0x4f) 3397 */ 3398 if (cpu_mode == SIZE64) { 3399 if (segment_prefix != 0x64 && segment_prefix != 0x65) 3400 segment_prefix = 0; 3401 3402 if (opcode1 == 0x4) { 3403 rex_prefix = (opcode1 << 4) | opcode2; 3404 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3405 goto error; 3406 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3407 } else if (opcode1 == 0xC && 3408 (opcode2 == 0x4 || opcode2 == 0x5)) { 3409 /* AVX instructions */ 3410 vex_prefix = (opcode1 << 4) | opcode2; 3411 x->d86_rex_prefix = 0x40; 3412 } 3413 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 3414 /* LDS, LES or AVX */ 3415 dtrace_get_modrm(x, &mode, ®, &r_m); 3416 vex_prefetch = 1; 3417 3418 if (mode == REG_ONLY) { 3419 /* AVX */ 3420 vex_prefix = (opcode1 << 4) | opcode2; 3421 x->d86_rex_prefix = 0x40; 3422 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 3423 opcode4 = ((reg << 3) | r_m) & 0x0F; 3424 } 3425 } 3426 3427 /* 3428 * The EVEX prefix and "bound" instruction share the same first byte. 3429 * "bound" is only valid for 32-bit. For 64-bit this byte begins the 3430 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0. 3431 */ 3432 if (opcode1 == 0x6 && opcode2 == 0x2) { 3433 /* 3434 * An EVEX prefix is 4 bytes long, get the next 3 bytes. 3435 */ 3436 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3437 goto error; 3438 3439 if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) { 3440 /* 3441 * Upper bits in 2nd byte == 0 is 'bound' instn. 3442 * 3443 * We've already read the byte so perform the 3444 * equivalent of dtrace_get_modrm on the byte and set 3445 * the flag to indicate we've already read it. 3446 */ 3447 char b = (opcode4 << 4) | opcode5; 3448 3449 r_m = b & 0x7; 3450 reg = (b >> 3) & 0x7; 3451 mode = (b >> 6) & 0x3; 3452 vex_prefetch = 1; 3453 goto not_avx512; 3454 } 3455 3456 /* check for correct bits being 0 in 2nd byte */ 3457 if ((opcode5 & 0xc) != 0) 3458 goto error; 3459 3460 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3461 goto error; 3462 /* check for correct bit being 1 in 3rd byte */ 3463 if ((opcode7 & 0x4) == 0) 3464 goto error; 3465 3466 if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0) 3467 goto error; 3468 3469 /* Reuse opcode1 & opcode2 to get the real opcode now */ 3470 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3471 goto error; 3472 3473 /* 3474 * We only use the high nibble from the 2nd byte of the prefix 3475 * and save it in the low bits of evex_byte1. This is because 3476 * two of the bits in opcode5 are constant 0 (checked above), 3477 * and the other two bits are captured in vex_m. Also, the VEX 3478 * constants we check in evex_byte1 are against the low bits. 3479 */ 3480 evex_byte1 = opcode4; 3481 evex_byte2 = (opcode6 << 4) | opcode7; 3482 evex_byte3 = (opcode8 << 4) | opcode9; 3483 3484 vex_m = opcode5 & EVEX_m; 3485 vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3; 3486 vex_W = (opcode6 & VEX_W) >> 3; 3487 vex_p = opcode7 & VEX_p; 3488 3489 /* Currently only 3 valid values for evex L'L: 00, 01, 10 */ 3490 evex_L = (opcode8 & EVEX_L) >> 1; 3491 3492 dp = (instable_t *)&dis_opAVX62[(opcode1 << 4) | opcode2]; 3493 } 3494 not_avx512: 3495 3496 if (vex_prefix == VEX_2bytes) { 3497 if (!vex_prefetch) { 3498 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3499 goto error; 3500 } 3501 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 3502 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 3503 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 3504 vex_p = opcode4 & VEX_p; 3505 /* 3506 * The vex.x and vex.b bits are not defined in two bytes 3507 * mode vex prefix, their default values are 1 3508 */ 3509 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 3510 3511 if (vex_R == 0) 3512 x->d86_rex_prefix |= REX_R; 3513 3514 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3515 goto error; 3516 3517 switch (vex_p) { 3518 case VEX_p_66: 3519 dp = (instable_t *) 3520 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 3521 break; 3522 case VEX_p_F3: 3523 dp = (instable_t *) 3524 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 3525 break; 3526 case VEX_p_F2: 3527 dp = (instable_t *) 3528 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 3529 break; 3530 default: 3531 dp = (instable_t *) 3532 &dis_opAVX0F[opcode1][opcode2]; 3533 3534 } 3535 3536 } else if (vex_prefix == VEX_3bytes) { 3537 if (!vex_prefetch) { 3538 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3539 goto error; 3540 } 3541 vex_R = (opcode3 & VEX_R) >> 3; 3542 vex_X = (opcode3 & VEX_X) >> 2; 3543 vex_B = (opcode3 & VEX_B) >> 1; 3544 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 3545 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 3546 3547 if (vex_R == 0) 3548 x->d86_rex_prefix |= REX_R; 3549 if (vex_X == 0) 3550 x->d86_rex_prefix |= REX_X; 3551 if (vex_B == 0) 3552 x->d86_rex_prefix |= REX_B; 3553 3554 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 3555 goto error; 3556 vex_W = (opcode5 & VEX_W) >> 3; 3557 vex_L = (opcode6 & VEX_L) >> 2; 3558 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 3559 vex_p = opcode6 & VEX_p; 3560 3561 if (vex_W) 3562 x->d86_rex_prefix |= REX_W; 3563 3564 /* Only these three vex_m values valid; others are reserved */ 3565 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 3566 (vex_m != VEX_m_0F3A)) 3567 goto error; 3568 3569 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3570 goto error; 3571 3572 switch (vex_p) { 3573 case VEX_p_66: 3574 if (vex_m == VEX_m_0F) { 3575 dp = (instable_t *) 3576 &dis_opAVX660F 3577 [(opcode1 << 4) | opcode2]; 3578 } else if (vex_m == VEX_m_0F38) { 3579 dp = (instable_t *) 3580 &dis_opAVX660F38 3581 [(opcode1 << 4) | opcode2]; 3582 } else if (vex_m == VEX_m_0F3A) { 3583 dp = (instable_t *) 3584 &dis_opAVX660F3A 3585 [(opcode1 << 4) | opcode2]; 3586 } else { 3587 goto error; 3588 } 3589 break; 3590 case VEX_p_F3: 3591 if (vex_m == VEX_m_0F) { 3592 dp = (instable_t *) 3593 &dis_opAVXF30F 3594 [(opcode1 << 4) | opcode2]; 3595 } else if (vex_m == VEX_m_0F38) { 3596 dp = (instable_t *) 3597 &dis_opAVXF30F38 3598 [(opcode1 << 4) | opcode2]; 3599 } else { 3600 goto error; 3601 } 3602 break; 3603 case VEX_p_F2: 3604 if (vex_m == VEX_m_0F) { 3605 dp = (instable_t *) 3606 &dis_opAVXF20F 3607 [(opcode1 << 4) | opcode2]; 3608 } else if (vex_m == VEX_m_0F3A) { 3609 dp = (instable_t *) 3610 &dis_opAVXF20F3A 3611 [(opcode1 << 4) | opcode2]; 3612 } else if (vex_m == VEX_m_0F38) { 3613 dp = (instable_t *) 3614 &dis_opAVXF20F38 3615 [(opcode1 << 4) | opcode2]; 3616 } else { 3617 goto error; 3618 } 3619 break; 3620 default: 3621 dp = (instable_t *) 3622 &dis_opAVX0F[opcode1][opcode2]; 3623 3624 } 3625 } 3626 if (vex_prefix) { 3627 if (dp->it_vexwoxmm) { 3628 wbit = LONG_OPND; 3629 } else if (dp->it_vexopmask) { 3630 wbit = KOPMASK_OPND; 3631 } else { 3632 if (vex_L) { 3633 wbit = YMM_OPND; 3634 } else { 3635 wbit = XMM_OPND; 3636 } 3637 } 3638 } 3639 3640 /* 3641 * Deal with selection of operand and address size now. 3642 * Note that the REX.W bit being set causes opnd_size_prefix to be 3643 * ignored. 3644 */ 3645 if (cpu_mode == SIZE64) { 3646 if ((rex_prefix & REX_W) || vex_W) 3647 opnd_size = SIZE64; 3648 else if (opnd_size_prefix) 3649 opnd_size = SIZE16; 3650 3651 if (addr_size_prefix) 3652 addr_size = SIZE32; 3653 } else if (cpu_mode == SIZE32) { 3654 if (opnd_size_prefix) 3655 opnd_size = SIZE16; 3656 if (addr_size_prefix) 3657 addr_size = SIZE16; 3658 } else { 3659 if (opnd_size_prefix) 3660 opnd_size = SIZE32; 3661 if (addr_size_prefix) 3662 addr_size = SIZE32; 3663 } 3664 /* 3665 * The pause instruction - a repz'd nop. This doesn't fit 3666 * with any of the other prefix goop added for SSE, so we'll 3667 * special-case it here. 3668 */ 3669 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 3670 rep_prefix = 0; 3671 dp = (instable_t *)&dis_opPause; 3672 } 3673 3674 /* 3675 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 3676 * byte so we may need to perform a table indirection. 3677 */ 3678 if (dp->it_indirect == (instable_t *)dis_op0F) { 3679 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3680 goto error; 3681 opcode_bytes = 2; 3682 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 3683 uint_t subcode; 3684 3685 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3686 goto error; 3687 opcode_bytes = 3; 3688 subcode = ((opcode6 & 0x3) << 1) | 3689 ((opcode7 & 0x8) >> 3); 3690 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 3691 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 3692 dp = (instable_t *)&dis_op0FC8[0]; 3693 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 3694 opcode_bytes = 3; 3695 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3696 goto error; 3697 if (opnd_size == SIZE16) 3698 opnd_size = SIZE32; 3699 3700 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 3701 #ifdef DIS_TEXT 3702 if (strcmp(dp->it_name, "INVALID") == 0) 3703 goto error; 3704 #endif 3705 switch (dp->it_adrmode) { 3706 case XMMP: 3707 break; 3708 case XMMP_66r: 3709 case XMMPRM_66r: 3710 case XMM3PM_66r: 3711 if (opnd_size_prefix == 0) { 3712 goto error; 3713 } 3714 3715 break; 3716 case XMMP_66o: 3717 if (opnd_size_prefix == 0) { 3718 /* SSSE3 MMX instructions */ 3719 dp_mmx = *dp; 3720 dp_mmx.it_adrmode = MMOPM_66o; 3721 #ifdef DIS_MEM 3722 dp_mmx.it_size = 8; 3723 #endif 3724 dp = &dp_mmx; 3725 } 3726 break; 3727 default: 3728 goto error; 3729 } 3730 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 3731 opcode_bytes = 3; 3732 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3733 goto error; 3734 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 3735 3736 /* 3737 * Both crc32 and movbe have the same 3rd opcode 3738 * byte of either 0xF0 or 0xF1, so we use another 3739 * indirection to distinguish between the two. 3740 */ 3741 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 3742 dp->it_indirect == (instable_t *)dis_op0F38F1) { 3743 3744 dp = dp->it_indirect; 3745 if (rep_prefix != 0xF2) { 3746 /* It is movbe */ 3747 dp++; 3748 } 3749 } 3750 3751 /* 3752 * The adx family of instructions (adcx and adox) 3753 * continue the classic Intel tradition of abusing 3754 * arbitrary prefixes without actually meaning the 3755 * prefix bit. Therefore, if we find either the 3756 * opnd_size_prefix or rep_prefix we end up zeroing it 3757 * out after making our determination so as to ensure 3758 * that we don't get confused and accidentally print 3759 * repz prefixes and the like on these instructions. 3760 * 3761 * In addition, these instructions are actually much 3762 * closer to AVX instructions in semantics. Importantly, 3763 * they always default to having 32-bit operands. 3764 * However, if the CPU is in 64-bit mode, then and only 3765 * then, does it use REX.w promotes things to 64-bits 3766 * and REX.r allows 64-bit mode to use register r8-r15. 3767 */ 3768 if (dp->it_indirect == (instable_t *)dis_op0F38F6) { 3769 dp = dp->it_indirect; 3770 if (opnd_size_prefix == 0 && 3771 rep_prefix == 0xf3) { 3772 /* It is adox */ 3773 dp++; 3774 } else if (opnd_size_prefix != 0x66 && 3775 rep_prefix != 0) { 3776 /* It isn't adcx */ 3777 goto error; 3778 } 3779 opnd_size_prefix = 0; 3780 rep_prefix = 0; 3781 opnd_size = SIZE32; 3782 if (rex_prefix & REX_W) 3783 opnd_size = SIZE64; 3784 } 3785 3786 #ifdef DIS_TEXT 3787 if (strcmp(dp->it_name, "INVALID") == 0) 3788 goto error; 3789 #endif 3790 switch (dp->it_adrmode) { 3791 case ADX: 3792 case XMM: 3793 break; 3794 case RM_66r: 3795 case XMM_66r: 3796 case XMMM_66r: 3797 if (opnd_size_prefix == 0) { 3798 goto error; 3799 } 3800 break; 3801 case XMM_66o: 3802 if (opnd_size_prefix == 0) { 3803 /* SSSE3 MMX instructions */ 3804 dp_mmx = *dp; 3805 dp_mmx.it_adrmode = MM; 3806 #ifdef DIS_MEM 3807 dp_mmx.it_size = 8; 3808 #endif 3809 dp = &dp_mmx; 3810 } 3811 break; 3812 case CRC32: 3813 if (rep_prefix != 0xF2) { 3814 goto error; 3815 } 3816 rep_prefix = 0; 3817 break; 3818 case MOVBE: 3819 if (rep_prefix != 0x0) { 3820 goto error; 3821 } 3822 break; 3823 default: 3824 goto error; 3825 } 3826 } else if (rep_prefix == 0xf3 && opcode4 == 0 && opcode5 == 9) { 3827 rep_prefix = 0; 3828 dp = (instable_t *)&dis_opWbnoinvd; 3829 } else { 3830 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 3831 } 3832 } 3833 3834 /* 3835 * If still not at a TERM decode entry, then a ModRM byte 3836 * exists and its fields further decode the instruction. 3837 */ 3838 x->d86_got_modrm = 0; 3839 if (dp->it_indirect != TERM) { 3840 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 3841 if (x->d86_error) 3842 goto error; 3843 reg = opcode3; 3844 3845 /* 3846 * decode 287 instructions (D8-DF) from opcodeN 3847 */ 3848 if (opcode1 == 0xD && opcode2 >= 0x8) { 3849 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 3850 dp = (instable_t *)&dis_opFP5[r_m]; 3851 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 3852 dp = (instable_t *)&dis_opFP7[opcode3]; 3853 else if (opcode2 == 0xB && mode == 0x3) 3854 dp = (instable_t *)&dis_opFP6[opcode3]; 3855 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 3856 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 3857 else if (mode == 0x3) 3858 dp = (instable_t *) 3859 &dis_opFP3[opcode2 - 8][opcode3]; 3860 else 3861 dp = (instable_t *) 3862 &dis_opFP1n2[opcode2 - 8][opcode3]; 3863 } else { 3864 dp = (instable_t *)dp->it_indirect + opcode3; 3865 } 3866 } 3867 3868 /* 3869 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 3870 * (sign extend 32bit to 64 bit) 3871 */ 3872 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 3873 opcode1 == 0x6 && opcode2 == 0x3) 3874 dp = (instable_t *)&dis_opMOVSLD; 3875 3876 /* 3877 * at this point we should have a correct (or invalid) opcode 3878 */ 3879 if (cpu_mode == SIZE64 && dp->it_invalid64 || 3880 cpu_mode != SIZE64 && dp->it_invalid32) 3881 goto error; 3882 if (dp->it_indirect != TERM) 3883 goto error; 3884 3885 /* 3886 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do 3887 * need to include UNKNOWN below, as we may have instructions that 3888 * actually have a prefix, but don't exist in any other form. 3889 */ 3890 switch (dp->it_adrmode) { 3891 case UNKNOWN: 3892 case MMO: 3893 case MMOIMPL: 3894 case MMO3P: 3895 case MMOM3: 3896 case MMOMS: 3897 case MMOPM: 3898 case MMOPRM: 3899 case MMOS: 3900 case XMMO: 3901 case XMMOM: 3902 case XMMOMS: 3903 case XMMOPM: 3904 case XMMOS: 3905 case XMMOMX: 3906 case XMMOX3: 3907 case XMMOXMM: 3908 /* 3909 * This is horrible. Some SIMD instructions take the 3910 * form 0x0F 0x?? ..., which is easily decoded using the 3911 * existing tables. Other SIMD instructions use various 3912 * prefix bytes to overload existing instructions. For 3913 * Example, addps is F0, 58, whereas addss is F3 (repz), 3914 * F0, 58. Presumably someone got a raise for this. 3915 * 3916 * If we see one of the instructions which can be 3917 * modified in this way (if we've got one of the SIMDO* 3918 * address modes), we'll check to see if the last prefix 3919 * was a repz. If it was, we strip the prefix from the 3920 * mnemonic, and we indirect using the dis_opSIMDrepz 3921 * table. 3922 */ 3923 3924 /* 3925 * Calculate our offset in dis_op0F 3926 */ 3927 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 3928 goto error; 3929 3930 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3931 sizeof (instable_t); 3932 3933 /* 3934 * Rewrite if this instruction used one of the magic prefixes. 3935 */ 3936 if (rep_prefix) { 3937 if (rep_prefix == 0xf2) 3938 dp = (instable_t *)&dis_opSIMDrepnz[off]; 3939 else 3940 dp = (instable_t *)&dis_opSIMDrepz[off]; 3941 rep_prefix = 0; 3942 } else if (opnd_size_prefix) { 3943 dp = (instable_t *)&dis_opSIMDdata16[off]; 3944 opnd_size_prefix = 0; 3945 if (opnd_size == SIZE16) 3946 opnd_size = SIZE32; 3947 } 3948 break; 3949 3950 case MG9: 3951 /* 3952 * More horribleness: the group 9 (0xF0 0xC7) instructions are 3953 * allowed an optional prefix of 0x66 or 0xF3. This is similar 3954 * to the SIMD business described above, but with a different 3955 * addressing mode (and an indirect table), so we deal with it 3956 * separately (if similarly). 3957 * 3958 * Intel further complicated this with the release of Ivy Bridge 3959 * where they overloaded these instructions based on the ModR/M 3960 * bytes. The VMX instructions have a mode of 0 since they are 3961 * memory instructions but rdrand instructions have a mode of 3962 * 0b11 (REG_ONLY) because they only operate on registers. While 3963 * there are different prefix formats, for now it is sufficient 3964 * to use a single different table. 3965 */ 3966 3967 /* 3968 * Calculate our offset in dis_op0FC7 (the group 9 table) 3969 */ 3970 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 3971 goto error; 3972 3973 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 3974 sizeof (instable_t); 3975 3976 /* 3977 * If we have a mode of 0b11 then we have to rewrite this. 3978 */ 3979 dtrace_get_modrm(x, &mode, ®, &r_m); 3980 if (mode == REG_ONLY) { 3981 dp = (instable_t *)&dis_op0FC7m3[off]; 3982 break; 3983 } 3984 3985 /* 3986 * Rewrite if this instruction used one of the magic prefixes. 3987 */ 3988 if (rep_prefix) { 3989 if (rep_prefix == 0xf3) 3990 dp = (instable_t *)&dis_opF30FC7[off]; 3991 else 3992 goto error; 3993 rep_prefix = 0; 3994 } else if (opnd_size_prefix) { 3995 dp = (instable_t *)&dis_op660FC7[off]; 3996 opnd_size_prefix = 0; 3997 if (opnd_size == SIZE16) 3998 opnd_size = SIZE32; 3999 } else if (reg == 4 || reg == 5) { 4000 /* 4001 * We have xsavec (4) or xsaves (5), so rewrite. 4002 */ 4003 dp = (instable_t *)&dis_op0FC7[reg]; 4004 break; 4005 } 4006 break; 4007 4008 4009 case MMOSH: 4010 /* 4011 * As with the "normal" SIMD instructions, the MMX 4012 * shuffle instructions are overloaded. These 4013 * instructions, however, are special in that they use 4014 * an extra byte, and thus an extra table. As of this 4015 * writing, they only use the opnd_size prefix. 4016 */ 4017 4018 /* 4019 * Calculate our offset in dis_op0F7123 4020 */ 4021 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 4022 sizeof (dis_op0F7123)) 4023 goto error; 4024 4025 if (opnd_size_prefix) { 4026 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 4027 sizeof (instable_t); 4028 dp = (instable_t *)&dis_opSIMD7123[off]; 4029 opnd_size_prefix = 0; 4030 if (opnd_size == SIZE16) 4031 opnd_size = SIZE32; 4032 } 4033 break; 4034 case MRw: 4035 if (rep_prefix) { 4036 if (rep_prefix == 0xf3) { 4037 4038 /* 4039 * Calculate our offset in dis_op0F 4040 */ 4041 if ((uintptr_t)dp - (uintptr_t)dis_op0F > 4042 sizeof (dis_op0F)) 4043 goto error; 4044 4045 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4046 sizeof (instable_t); 4047 4048 dp = (instable_t *)&dis_opSIMDrepz[off]; 4049 rep_prefix = 0; 4050 } else { 4051 goto error; 4052 } 4053 } 4054 break; 4055 case FSGS: 4056 if (rep_prefix == 0xf3) { 4057 if ((uintptr_t)dp - (uintptr_t)dis_op0FAE > 4058 sizeof (dis_op0FAE)) 4059 goto error; 4060 4061 off = ((uintptr_t)dp - (uintptr_t)dis_op0FAE) / 4062 sizeof (instable_t); 4063 dp = (instable_t *)&dis_opF30FAE[off]; 4064 rep_prefix = 0; 4065 } else if (rep_prefix != 0x00) { 4066 goto error; 4067 } 4068 } 4069 4070 /* 4071 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 4072 */ 4073 if (cpu_mode == SIZE64) 4074 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 4075 opnd_size = SIZE64; 4076 4077 #ifdef DIS_TEXT 4078 /* 4079 * At this point most instructions can format the opcode mnemonic 4080 * including the prefixes. 4081 */ 4082 if (lock_prefix) 4083 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 4084 4085 if (rep_prefix == 0xf2) 4086 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 4087 else if (rep_prefix == 0xf3) 4088 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 4089 4090 if (cpu_mode == SIZE64 && addr_size_prefix) 4091 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 4092 4093 if (dp->it_adrmode != CBW && 4094 dp->it_adrmode != CWD && 4095 dp->it_adrmode != XMMSFNC) { 4096 if (strcmp(dp->it_name, "INVALID") == 0) 4097 goto error; 4098 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 4099 if (dp->it_avxsuf == AVS2 && dp->it_suffix) { 4100 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 4101 OPLEN); 4102 } else if (dp->it_vexopmask && dp->it_suffix) { 4103 /* opmask instructions */ 4104 4105 if (opcode1 == 4 && opcode2 == 0xb) { 4106 /* It's a kunpck. */ 4107 if (vex_prefix == VEX_2bytes) { 4108 (void) strlcat(x->d86_mnem, 4109 vex_p == 0 ? "wd" : "bw", OPLEN); 4110 } else { 4111 /* vex_prefix == VEX_3bytes */ 4112 (void) strlcat(x->d86_mnem, 4113 "dq", OPLEN); 4114 } 4115 } else if (opcode1 == 3) { 4116 /* It's a kshift[l|r]. */ 4117 if (vex_W == 0) { 4118 (void) strlcat(x->d86_mnem, 4119 opcode2 == 2 || 4120 opcode2 == 0 ? 4121 "b" : "d", OPLEN); 4122 } else { 4123 /* W == 1 */ 4124 (void) strlcat(x->d86_mnem, 4125 opcode2 == 3 || opcode2 == 1 ? 4126 "q" : "w", OPLEN); 4127 } 4128 } else { 4129 /* if (vex_prefix == VEX_2bytes) { */ 4130 if ((cpu_mode == SIZE64 && opnd_size == 2) || 4131 vex_prefix == VEX_2bytes) { 4132 (void) strlcat(x->d86_mnem, 4133 vex_p == 0 ? "w" : 4134 vex_p == 1 ? "b" : "d", 4135 OPLEN); 4136 } else { 4137 /* vex_prefix == VEX_3bytes */ 4138 (void) strlcat(x->d86_mnem, 4139 vex_p == 1 ? "d" : "q", OPLEN); 4140 } 4141 } 4142 } else if (dp->it_suffix) { 4143 char *types[] = {"", "w", "l", "q"}; 4144 if (opcode_bytes == 2 && opcode4 == 4) { 4145 /* It's a cmovx.yy. Replace the suffix x */ 4146 for (i = 5; i < OPLEN; i++) { 4147 if (x->d86_mnem[i] == '.') 4148 break; 4149 } 4150 x->d86_mnem[i - 1] = *types[opnd_size]; 4151 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 4152 ((opcode6 == 1 && opcode7 == 6) || 4153 (opcode6 == 2 && opcode7 == 2))) { 4154 /* 4155 * To handle PINSRD and PEXTRD 4156 */ 4157 (void) strlcat(x->d86_mnem, "d", OPLEN); 4158 } else if (dp != &dis_distable[0x6][0x2]) { 4159 /* bound instructions (0x62) have no suffix */ 4160 (void) strlcat(x->d86_mnem, types[opnd_size], 4161 OPLEN); 4162 } 4163 } 4164 } 4165 #endif 4166 4167 /* 4168 * Process operands based on the addressing modes. 4169 */ 4170 x->d86_mode = cpu_mode; 4171 /* 4172 * In vex mode the rex_prefix has no meaning 4173 */ 4174 if (!vex_prefix) 4175 x->d86_rex_prefix = rex_prefix; 4176 x->d86_opnd_size = opnd_size; 4177 x->d86_addr_size = addr_size; 4178 vbit = 0; /* initialize for mem/reg -> reg */ 4179 switch (dp->it_adrmode) { 4180 /* 4181 * amd64 instruction to sign extend 32 bit reg/mem operands 4182 * into 64 bit register values 4183 */ 4184 case MOVSXZ: 4185 #ifdef DIS_TEXT 4186 if (rex_prefix == 0) 4187 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 4188 #endif 4189 dtrace_get_modrm(x, &mode, ®, &r_m); 4190 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4191 x->d86_opnd_size = SIZE64; 4192 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4193 x->d86_opnd_size = opnd_size = SIZE32; 4194 wbit = LONG_OPND; 4195 dtrace_get_operand(x, mode, r_m, wbit, 0); 4196 break; 4197 4198 /* 4199 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 4200 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 4201 * wbit lives in 2nd byte, note that operands 4202 * are different sized 4203 */ 4204 case MOVZ: 4205 if (rex_prefix & REX_W) { 4206 /* target register size = 64 bit */ 4207 x->d86_mnem[5] = 'q'; 4208 } 4209 dtrace_get_modrm(x, &mode, ®, &r_m); 4210 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4211 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4212 x->d86_opnd_size = opnd_size = SIZE16; 4213 wbit = WBIT(opcode5); 4214 dtrace_get_operand(x, mode, r_m, wbit, 0); 4215 break; 4216 case CRC32: 4217 opnd_size = SIZE32; 4218 if (rex_prefix & REX_W) 4219 opnd_size = SIZE64; 4220 x->d86_opnd_size = opnd_size; 4221 4222 dtrace_get_modrm(x, &mode, ®, &r_m); 4223 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4224 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4225 wbit = WBIT(opcode7); 4226 if (opnd_size_prefix) 4227 x->d86_opnd_size = opnd_size = SIZE16; 4228 dtrace_get_operand(x, mode, r_m, wbit, 0); 4229 break; 4230 case MOVBE: 4231 opnd_size = SIZE32; 4232 if (rex_prefix & REX_W) 4233 opnd_size = SIZE64; 4234 x->d86_opnd_size = opnd_size; 4235 4236 dtrace_get_modrm(x, &mode, ®, &r_m); 4237 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4238 wbit = WBIT(opcode7); 4239 if (opnd_size_prefix) 4240 x->d86_opnd_size = opnd_size = SIZE16; 4241 if (wbit) { 4242 /* reg -> mem */ 4243 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4244 dtrace_get_operand(x, mode, r_m, wbit, 1); 4245 } else { 4246 /* mem -> reg */ 4247 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4248 dtrace_get_operand(x, mode, r_m, wbit, 0); 4249 } 4250 break; 4251 4252 /* 4253 * imul instruction, with either 8-bit or longer immediate 4254 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 4255 */ 4256 case IMUL: 4257 wbit = LONG_OPND; 4258 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 4259 OPSIZE(opnd_size, opcode2 == 0x9), 1); 4260 break; 4261 4262 /* memory or register operand to register, with 'w' bit */ 4263 case MRw: 4264 case ADX: 4265 wbit = WBIT(opcode2); 4266 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4267 break; 4268 4269 /* register to memory or register operand, with 'w' bit */ 4270 /* arpl happens to fit here also because it is odd */ 4271 case RMw: 4272 if (opcode_bytes == 2) 4273 wbit = WBIT(opcode5); 4274 else 4275 wbit = WBIT(opcode2); 4276 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4277 break; 4278 4279 /* xaddb instruction */ 4280 case XADDB: 4281 wbit = 0; 4282 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4283 break; 4284 4285 /* MMX register to memory or register operand */ 4286 case MMS: 4287 case MMOS: 4288 #ifdef DIS_TEXT 4289 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4290 #else 4291 wbit = LONG_OPND; 4292 #endif 4293 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4294 break; 4295 4296 /* MMX register to memory */ 4297 case MMOMS: 4298 dtrace_get_modrm(x, &mode, ®, &r_m); 4299 if (mode == REG_ONLY) 4300 goto error; 4301 wbit = MM_OPND; 4302 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4303 break; 4304 4305 /* Double shift. Has immediate operand specifying the shift. */ 4306 case DSHIFT: 4307 wbit = LONG_OPND; 4308 dtrace_get_modrm(x, &mode, ®, &r_m); 4309 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4310 dtrace_get_operand(x, mode, r_m, wbit, 2); 4311 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4312 dtrace_imm_opnd(x, wbit, 1, 0); 4313 break; 4314 4315 /* 4316 * Double shift. With no immediate operand, specifies using %cl. 4317 */ 4318 case DSHIFTcl: 4319 wbit = LONG_OPND; 4320 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4321 break; 4322 4323 /* immediate to memory or register operand */ 4324 case IMlw: 4325 wbit = WBIT(opcode2); 4326 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4327 dtrace_get_operand(x, mode, r_m, wbit, 1); 4328 /* 4329 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 4330 */ 4331 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 4332 break; 4333 4334 /* immediate to memory or register operand with the */ 4335 /* 'w' bit present */ 4336 case IMw: 4337 wbit = WBIT(opcode2); 4338 dtrace_get_modrm(x, &mode, ®, &r_m); 4339 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4340 dtrace_get_operand(x, mode, r_m, wbit, 1); 4341 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4342 break; 4343 4344 /* immediate to register with register in low 3 bits */ 4345 /* of op code */ 4346 case IR: 4347 /* w-bit here (with regs) is bit 3 */ 4348 wbit = opcode2 >>3 & 0x1; 4349 reg = REGNO(opcode2); 4350 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4351 mode = REG_ONLY; 4352 r_m = reg; 4353 dtrace_get_operand(x, mode, r_m, wbit, 1); 4354 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 4355 break; 4356 4357 /* MMX immediate shift of register */ 4358 case MMSH: 4359 case MMOSH: 4360 wbit = MM_OPND; 4361 goto mm_shift; /* in next case */ 4362 4363 /* SIMD immediate shift of register */ 4364 case XMMSH: 4365 wbit = XMM_OPND; 4366 mm_shift: 4367 reg = REGNO(opcode7); 4368 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4369 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4370 dtrace_imm_opnd(x, wbit, 1, 0); 4371 NOMEM; 4372 break; 4373 4374 /* accumulator to memory operand */ 4375 case AO: 4376 vbit = 1; 4377 /*FALLTHROUGH*/ 4378 4379 /* memory operand to accumulator */ 4380 case OA: 4381 wbit = WBIT(opcode2); 4382 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 4383 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 4384 #ifdef DIS_TEXT 4385 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 4386 #endif 4387 break; 4388 4389 4390 /* segment register to memory or register operand */ 4391 case SM: 4392 vbit = 1; 4393 /*FALLTHROUGH*/ 4394 4395 /* memory or register operand to segment register */ 4396 case MS: 4397 dtrace_get_modrm(x, &mode, ®, &r_m); 4398 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4399 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 4400 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 4401 break; 4402 4403 /* 4404 * rotate or shift instructions, which may shift by 1 or 4405 * consult the cl register, depending on the 'v' bit 4406 */ 4407 case Mv: 4408 vbit = VBIT(opcode2); 4409 wbit = WBIT(opcode2); 4410 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4411 dtrace_get_operand(x, mode, r_m, wbit, 1); 4412 #ifdef DIS_TEXT 4413 if (vbit) { 4414 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 4415 } else { 4416 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4417 x->d86_opnd[0].d86_value_size = 1; 4418 x->d86_opnd[0].d86_value = 1; 4419 } 4420 #endif 4421 break; 4422 /* 4423 * immediate rotate or shift instructions 4424 */ 4425 case MvI: 4426 wbit = WBIT(opcode2); 4427 normal_imm_mem: 4428 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4429 dtrace_get_operand(x, mode, r_m, wbit, 1); 4430 dtrace_imm_opnd(x, wbit, 1, 0); 4431 break; 4432 4433 /* bit test instructions */ 4434 case MIb: 4435 wbit = LONG_OPND; 4436 goto normal_imm_mem; 4437 4438 /* single memory or register operand with 'w' bit present */ 4439 case Mw: 4440 wbit = WBIT(opcode2); 4441 just_mem: 4442 dtrace_get_modrm(x, &mode, ®, &r_m); 4443 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4444 dtrace_get_operand(x, mode, r_m, wbit, 0); 4445 break; 4446 4447 case SWAPGS_RDTSCP: 4448 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 4449 #ifdef DIS_TEXT 4450 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 4451 #endif 4452 NOMEM; 4453 break; 4454 } else if (mode == 3 && r_m == 1) { 4455 #ifdef DIS_TEXT 4456 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 4457 #endif 4458 NOMEM; 4459 break; 4460 } else if (mode == 3 && r_m == 2) { 4461 #ifdef DIS_TEXT 4462 (void) strncpy(x->d86_mnem, "monitorx", OPLEN); 4463 #endif 4464 NOMEM; 4465 break; 4466 } else if (mode == 3 && r_m == 3) { 4467 #ifdef DIS_TEXT 4468 (void) strncpy(x->d86_mnem, "mwaitx", OPLEN); 4469 #endif 4470 NOMEM; 4471 break; 4472 } else if (mode == 3 && r_m == 4) { 4473 #ifdef DIS_TEXT 4474 (void) strncpy(x->d86_mnem, "clzero", OPLEN); 4475 #endif 4476 NOMEM; 4477 break; 4478 } 4479 4480 /*FALLTHROUGH*/ 4481 4482 /* prefetch instruction - memory operand, but no memory acess */ 4483 case PREF: 4484 NOMEM; 4485 /*FALLTHROUGH*/ 4486 4487 /* single memory or register operand */ 4488 case M: 4489 case MG9: 4490 wbit = LONG_OPND; 4491 goto just_mem; 4492 4493 /* single memory or register byte operand */ 4494 case Mb: 4495 wbit = BYTE_OPND; 4496 goto just_mem; 4497 4498 case VMx: 4499 if (mode == 3) { 4500 #ifdef DIS_TEXT 4501 char *vminstr; 4502 4503 switch (r_m) { 4504 case 1: 4505 vminstr = "vmcall"; 4506 break; 4507 case 2: 4508 vminstr = "vmlaunch"; 4509 break; 4510 case 3: 4511 vminstr = "vmresume"; 4512 break; 4513 case 4: 4514 vminstr = "vmxoff"; 4515 break; 4516 default: 4517 goto error; 4518 } 4519 4520 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 4521 #else 4522 if (r_m < 1 || r_m > 4) 4523 goto error; 4524 #endif 4525 4526 NOMEM; 4527 break; 4528 } 4529 /*FALLTHROUGH*/ 4530 case SVM: 4531 if (mode == 3) { 4532 #if DIS_TEXT 4533 char *vinstr; 4534 4535 switch (r_m) { 4536 case 0: 4537 vinstr = "vmrun"; 4538 break; 4539 case 1: 4540 vinstr = "vmmcall"; 4541 break; 4542 case 2: 4543 vinstr = "vmload"; 4544 break; 4545 case 3: 4546 vinstr = "vmsave"; 4547 break; 4548 case 4: 4549 vinstr = "stgi"; 4550 break; 4551 case 5: 4552 vinstr = "clgi"; 4553 break; 4554 case 6: 4555 vinstr = "skinit"; 4556 break; 4557 case 7: 4558 vinstr = "invlpga"; 4559 break; 4560 } 4561 4562 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 4563 #endif 4564 NOMEM; 4565 break; 4566 } 4567 /*FALLTHROUGH*/ 4568 case MONITOR_MWAIT: 4569 if (mode == 3) { 4570 if (r_m == 0) { 4571 #ifdef DIS_TEXT 4572 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 4573 #endif 4574 NOMEM; 4575 break; 4576 } else if (r_m == 1) { 4577 #ifdef DIS_TEXT 4578 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 4579 #endif 4580 NOMEM; 4581 break; 4582 } else if (r_m == 2) { 4583 #ifdef DIS_TEXT 4584 (void) strncpy(x->d86_mnem, "clac", OPLEN); 4585 #endif 4586 NOMEM; 4587 break; 4588 } else if (r_m == 3) { 4589 #ifdef DIS_TEXT 4590 (void) strncpy(x->d86_mnem, "stac", OPLEN); 4591 #endif 4592 NOMEM; 4593 break; 4594 } else { 4595 goto error; 4596 } 4597 } 4598 /*FALLTHROUGH*/ 4599 case XGETBV_XSETBV: 4600 if (mode == 3) { 4601 if (r_m == 0) { 4602 #ifdef DIS_TEXT 4603 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 4604 #endif 4605 NOMEM; 4606 break; 4607 } else if (r_m == 1) { 4608 #ifdef DIS_TEXT 4609 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 4610 #endif 4611 NOMEM; 4612 break; 4613 } else { 4614 goto error; 4615 } 4616 4617 } 4618 /*FALLTHROUGH*/ 4619 case MO: 4620 /* Similar to M, but only memory (no direct registers) */ 4621 wbit = LONG_OPND; 4622 dtrace_get_modrm(x, &mode, ®, &r_m); 4623 if (mode == 3) 4624 goto error; 4625 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4626 dtrace_get_operand(x, mode, r_m, wbit, 0); 4627 break; 4628 4629 /* move special register to register or reverse if vbit */ 4630 case SREG: 4631 switch (opcode5) { 4632 4633 case 2: 4634 vbit = 1; 4635 /*FALLTHROUGH*/ 4636 case 0: 4637 wbit = CONTROL_OPND; 4638 break; 4639 4640 case 3: 4641 vbit = 1; 4642 /*FALLTHROUGH*/ 4643 case 1: 4644 wbit = DEBUG_OPND; 4645 break; 4646 4647 case 6: 4648 vbit = 1; 4649 /*FALLTHROUGH*/ 4650 case 4: 4651 wbit = TEST_OPND; 4652 break; 4653 4654 } 4655 dtrace_get_modrm(x, &mode, ®, &r_m); 4656 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4657 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 4658 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 4659 NOMEM; 4660 break; 4661 4662 /* 4663 * single register operand with register in the low 3 4664 * bits of op code 4665 */ 4666 case R: 4667 if (opcode_bytes == 2) 4668 reg = REGNO(opcode5); 4669 else 4670 reg = REGNO(opcode2); 4671 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4672 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4673 NOMEM; 4674 break; 4675 4676 /* 4677 * register to accumulator with register in the low 3 4678 * bits of op code, xchg instructions 4679 */ 4680 case RA: 4681 NOMEM; 4682 reg = REGNO(opcode2); 4683 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4684 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4685 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 4686 break; 4687 4688 /* 4689 * single segment register operand, with register in 4690 * bits 3-4 of op code byte 4691 */ 4692 case SEG: 4693 NOMEM; 4694 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 4695 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4696 break; 4697 4698 /* 4699 * single segment register operand, with register in 4700 * bits 3-5 of op code 4701 */ 4702 case LSEG: 4703 NOMEM; 4704 /* long seg reg from opcode */ 4705 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 4706 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4707 break; 4708 4709 /* memory or register operand to register */ 4710 case MR: 4711 if (vex_prefetch) 4712 x->d86_got_modrm = 1; 4713 wbit = LONG_OPND; 4714 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4715 break; 4716 4717 case RM: 4718 case RM_66r: 4719 if (vex_prefetch) 4720 x->d86_got_modrm = 1; 4721 wbit = LONG_OPND; 4722 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4723 break; 4724 4725 /* MMX/SIMD-Int memory or mm reg to mm reg */ 4726 case MM: 4727 case MMO: 4728 #ifdef DIS_TEXT 4729 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4730 #else 4731 wbit = LONG_OPND; 4732 #endif 4733 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4734 break; 4735 4736 case MMOIMPL: 4737 #ifdef DIS_TEXT 4738 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4739 #else 4740 wbit = LONG_OPND; 4741 #endif 4742 dtrace_get_modrm(x, &mode, ®, &r_m); 4743 if (mode != REG_ONLY) 4744 goto error; 4745 4746 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4747 dtrace_get_operand(x, mode, r_m, wbit, 0); 4748 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 4749 mode = 0; /* change for memory access size... */ 4750 break; 4751 4752 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 4753 case MMO3P: 4754 wbit = MM_OPND; 4755 goto xmm3p; 4756 case XMM3P: 4757 wbit = XMM_OPND; 4758 xmm3p: 4759 dtrace_get_modrm(x, &mode, ®, &r_m); 4760 if (mode != REG_ONLY) 4761 goto error; 4762 4763 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 4764 1); 4765 NOMEM; 4766 break; 4767 4768 case XMM3PM_66r: 4769 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 4770 1, 0); 4771 break; 4772 4773 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 4774 case MMOPRM: 4775 wbit = LONG_OPND; 4776 w2 = MM_OPND; 4777 goto xmmprm; 4778 case XMMPRM: 4779 case XMMPRM_66r: 4780 wbit = LONG_OPND; 4781 w2 = XMM_OPND; 4782 xmmprm: 4783 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 4784 break; 4785 4786 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 4787 case MMOPM: 4788 case MMOPM_66o: 4789 wbit = w2 = MM_OPND; 4790 goto xmmprm; 4791 4792 /* MMX/SIMD-Int mm reg to r32 */ 4793 case MMOM3: 4794 NOMEM; 4795 dtrace_get_modrm(x, &mode, ®, &r_m); 4796 if (mode != REG_ONLY) 4797 goto error; 4798 wbit = MM_OPND; 4799 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4800 break; 4801 4802 /* SIMD memory or xmm reg operand to xmm reg */ 4803 case XMM: 4804 case XMM_66o: 4805 case XMM_66r: 4806 case XMMO: 4807 case XMMXIMPL: 4808 wbit = XMM_OPND; 4809 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4810 4811 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 4812 goto error; 4813 4814 #ifdef DIS_TEXT 4815 /* 4816 * movlps and movhlps share opcodes. They differ in the 4817 * addressing modes allowed for their operands. 4818 * movhps and movlhps behave similarly. 4819 */ 4820 if (mode == REG_ONLY) { 4821 if (strcmp(dp->it_name, "movlps") == 0) 4822 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 4823 else if (strcmp(dp->it_name, "movhps") == 0) 4824 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4825 } 4826 #endif 4827 if (dp->it_adrmode == XMMXIMPL) 4828 mode = 0; /* change for memory access size... */ 4829 break; 4830 4831 /* SIMD xmm reg to memory or xmm reg */ 4832 case XMMS: 4833 case XMMOS: 4834 case XMMMS: 4835 case XMMOMS: 4836 dtrace_get_modrm(x, &mode, ®, &r_m); 4837 #ifdef DIS_TEXT 4838 if ((strcmp(dp->it_name, "movlps") == 0 || 4839 strcmp(dp->it_name, "movhps") == 0 || 4840 strcmp(dp->it_name, "movntps") == 0) && 4841 mode == REG_ONLY) 4842 goto error; 4843 #endif 4844 wbit = XMM_OPND; 4845 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4846 break; 4847 4848 /* SIMD memory to xmm reg */ 4849 case XMMM: 4850 case XMMM_66r: 4851 case XMMOM: 4852 wbit = XMM_OPND; 4853 dtrace_get_modrm(x, &mode, ®, &r_m); 4854 #ifdef DIS_TEXT 4855 if (mode == REG_ONLY) { 4856 if (strcmp(dp->it_name, "movhps") == 0) 4857 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4858 else 4859 goto error; 4860 } 4861 #endif 4862 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4863 break; 4864 4865 /* SIMD memory or r32 to xmm reg */ 4866 case XMM3MX: 4867 wbit = LONG_OPND; 4868 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4869 break; 4870 4871 case XMM3MXS: 4872 wbit = LONG_OPND; 4873 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4874 break; 4875 4876 /* SIMD memory or mm reg to xmm reg */ 4877 case XMMOMX: 4878 /* SIMD mm to xmm */ 4879 case XMMMX: 4880 wbit = MM_OPND; 4881 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4882 break; 4883 4884 /* SIMD memory or xmm reg to mm reg */ 4885 case XMMXMM: 4886 case XMMOXMM: 4887 case XMMXM: 4888 wbit = XMM_OPND; 4889 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4890 break; 4891 4892 4893 /* SIMD memory or xmm reg to r32 */ 4894 case XMMXM3: 4895 wbit = XMM_OPND; 4896 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4897 break; 4898 4899 /* SIMD xmm to r32 */ 4900 case XMMX3: 4901 case XMMOX3: 4902 dtrace_get_modrm(x, &mode, ®, &r_m); 4903 if (mode != REG_ONLY) 4904 goto error; 4905 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4906 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 4907 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4908 NOMEM; 4909 break; 4910 4911 /* SIMD predicated memory or xmm reg with/to xmm reg */ 4912 case XMMP: 4913 case XMMP_66r: 4914 case XMMP_66o: 4915 case XMMOPM: 4916 wbit = XMM_OPND; 4917 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 4918 1); 4919 4920 #ifdef DIS_TEXT 4921 /* 4922 * cmpps and cmpss vary their instruction name based 4923 * on the value of imm8. Other XMMP instructions, 4924 * such as shufps, require explicit specification of 4925 * the predicate. 4926 */ 4927 if (dp->it_name[0] == 'c' && 4928 dp->it_name[1] == 'm' && 4929 dp->it_name[2] == 'p' && 4930 strlen(dp->it_name) == 5) { 4931 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 4932 4933 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 4934 goto error; 4935 4936 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 4937 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 4938 OPLEN); 4939 (void) strlcat(x->d86_mnem, 4940 dp->it_name + strlen(dp->it_name) - 2, 4941 OPLEN); 4942 x->d86_opnd[0] = x->d86_opnd[1]; 4943 x->d86_opnd[1] = x->d86_opnd[2]; 4944 x->d86_numopnds = 2; 4945 } 4946 4947 /* 4948 * The pclmulqdq instruction has a series of alternate names for 4949 * various encodings of the immediate byte. As such, if we 4950 * happen to find it and the immediate value matches, we'll 4951 * rewrite the mnemonic. 4952 */ 4953 if (strcmp(dp->it_name, "pclmulqdq") == 0) { 4954 boolean_t changed = B_TRUE; 4955 switch (x->d86_opnd[0].d86_value) { 4956 case 0x00: 4957 (void) strncpy(x->d86_mnem, "pclmullqlqdq", 4958 OPLEN); 4959 break; 4960 case 0x01: 4961 (void) strncpy(x->d86_mnem, "pclmulhqlqdq", 4962 OPLEN); 4963 break; 4964 case 0x10: 4965 (void) strncpy(x->d86_mnem, "pclmullqhqdq", 4966 OPLEN); 4967 break; 4968 case 0x11: 4969 (void) strncpy(x->d86_mnem, "pclmulhqhqdq", 4970 OPLEN); 4971 break; 4972 default: 4973 changed = B_FALSE; 4974 break; 4975 } 4976 4977 if (changed == B_TRUE) { 4978 x->d86_opnd[0].d86_value_size = 0; 4979 x->d86_opnd[0] = x->d86_opnd[1]; 4980 x->d86_opnd[1] = x->d86_opnd[2]; 4981 x->d86_numopnds = 2; 4982 } 4983 } 4984 #endif 4985 break; 4986 4987 case XMMX2I: 4988 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 4989 1); 4990 NOMEM; 4991 break; 4992 4993 case XMM2I: 4994 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 4995 NOMEM; 4996 break; 4997 4998 /* immediate operand to accumulator */ 4999 case IA: 5000 wbit = WBIT(opcode2); 5001 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5002 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 5003 NOMEM; 5004 break; 5005 5006 /* memory or register operand to accumulator */ 5007 case MA: 5008 wbit = WBIT(opcode2); 5009 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5010 dtrace_get_operand(x, mode, r_m, wbit, 0); 5011 break; 5012 5013 /* si register to di register used to reference memory */ 5014 case SD: 5015 #ifdef DIS_TEXT 5016 dtrace_check_override(x, 0); 5017 x->d86_numopnds = 2; 5018 if (addr_size == SIZE64) { 5019 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5020 OPLEN); 5021 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5022 OPLEN); 5023 } else if (addr_size == SIZE32) { 5024 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5025 OPLEN); 5026 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5027 OPLEN); 5028 } else { 5029 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5030 OPLEN); 5031 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5032 OPLEN); 5033 } 5034 #endif 5035 wbit = LONG_OPND; 5036 break; 5037 5038 /* accumulator to di register */ 5039 case AD: 5040 wbit = WBIT(opcode2); 5041 #ifdef DIS_TEXT 5042 dtrace_check_override(x, 1); 5043 x->d86_numopnds = 2; 5044 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 5045 if (addr_size == SIZE64) 5046 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5047 OPLEN); 5048 else if (addr_size == SIZE32) 5049 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5050 OPLEN); 5051 else 5052 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5053 OPLEN); 5054 #endif 5055 break; 5056 5057 /* si register to accumulator */ 5058 case SA: 5059 wbit = WBIT(opcode2); 5060 #ifdef DIS_TEXT 5061 dtrace_check_override(x, 0); 5062 x->d86_numopnds = 2; 5063 if (addr_size == SIZE64) 5064 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5065 OPLEN); 5066 else if (addr_size == SIZE32) 5067 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5068 OPLEN); 5069 else 5070 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5071 OPLEN); 5072 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5073 #endif 5074 break; 5075 5076 /* 5077 * single operand, a 16/32 bit displacement 5078 */ 5079 case D: 5080 wbit = LONG_OPND; 5081 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5082 NOMEM; 5083 break; 5084 5085 /* jmp/call indirect to memory or register operand */ 5086 case INM: 5087 #ifdef DIS_TEXT 5088 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 5089 #endif 5090 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5091 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5092 wbit = LONG_OPND; 5093 break; 5094 5095 /* 5096 * for long jumps and long calls -- a new code segment 5097 * register and an offset in IP -- stored in object 5098 * code in reverse order. Note - not valid in amd64 5099 */ 5100 case SO: 5101 dtrace_check_override(x, 1); 5102 wbit = LONG_OPND; 5103 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 5104 #ifdef DIS_TEXT 5105 x->d86_opnd[1].d86_mode = MODE_SIGNED; 5106 #endif 5107 /* will now get segment operand */ 5108 dtrace_imm_opnd(x, wbit, 2, 0); 5109 break; 5110 5111 /* 5112 * jmp/call. single operand, 8 bit displacement. 5113 * added to current EIP in 'compofff' 5114 */ 5115 case BD: 5116 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 5117 NOMEM; 5118 break; 5119 5120 /* single 32/16 bit immediate operand */ 5121 case I: 5122 wbit = LONG_OPND; 5123 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5124 break; 5125 5126 /* single 8 bit immediate operand */ 5127 case Ib: 5128 wbit = LONG_OPND; 5129 dtrace_imm_opnd(x, wbit, 1, 0); 5130 break; 5131 5132 case ENTER: 5133 wbit = LONG_OPND; 5134 dtrace_imm_opnd(x, wbit, 2, 0); 5135 dtrace_imm_opnd(x, wbit, 1, 1); 5136 switch (opnd_size) { 5137 case SIZE64: 5138 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 5139 break; 5140 case SIZE32: 5141 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 5142 break; 5143 case SIZE16: 5144 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 5145 break; 5146 } 5147 5148 break; 5149 5150 /* 16-bit immediate operand */ 5151 case RET: 5152 wbit = LONG_OPND; 5153 dtrace_imm_opnd(x, wbit, 2, 0); 5154 break; 5155 5156 /* single 8 bit port operand */ 5157 case P: 5158 dtrace_check_override(x, 0); 5159 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5160 NOMEM; 5161 break; 5162 5163 /* single operand, dx register (variable port instruction) */ 5164 case V: 5165 x->d86_numopnds = 1; 5166 dtrace_check_override(x, 0); 5167 #ifdef DIS_TEXT 5168 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 5169 #endif 5170 NOMEM; 5171 break; 5172 5173 /* 5174 * The int instruction, which has two forms: 5175 * int 3 (breakpoint) or 5176 * int n, where n is indicated in the subsequent 5177 * byte (format Ib). The int 3 instruction (opcode 0xCC), 5178 * where, although the 3 looks like an operand, 5179 * it is implied by the opcode. It must be converted 5180 * to the correct base and output. 5181 */ 5182 case INT3: 5183 #ifdef DIS_TEXT 5184 x->d86_numopnds = 1; 5185 x->d86_opnd[0].d86_mode = MODE_SIGNED; 5186 x->d86_opnd[0].d86_value_size = 1; 5187 x->d86_opnd[0].d86_value = 3; 5188 #endif 5189 NOMEM; 5190 break; 5191 5192 /* single 8 bit immediate operand */ 5193 case INTx: 5194 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5195 NOMEM; 5196 break; 5197 5198 /* an unused byte must be discarded */ 5199 case U: 5200 if (x->d86_get_byte(x->d86_data) < 0) 5201 goto error; 5202 x->d86_len++; 5203 NOMEM; 5204 break; 5205 5206 case CBW: 5207 #ifdef DIS_TEXT 5208 if (opnd_size == SIZE16) 5209 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 5210 else if (opnd_size == SIZE32) 5211 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 5212 else 5213 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 5214 #endif 5215 wbit = LONG_OPND; 5216 NOMEM; 5217 break; 5218 5219 case CWD: 5220 #ifdef DIS_TEXT 5221 if (opnd_size == SIZE16) 5222 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 5223 else if (opnd_size == SIZE32) 5224 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 5225 else 5226 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 5227 #endif 5228 wbit = LONG_OPND; 5229 NOMEM; 5230 break; 5231 5232 case XMMSFNC: 5233 /* 5234 * sfence is sfence if mode is REG_ONLY. If mode isn't 5235 * REG_ONLY, mnemonic should be 'clflush'. 5236 */ 5237 dtrace_get_modrm(x, &mode, ®, &r_m); 5238 5239 /* sfence doesn't take operands */ 5240 if (mode != REG_ONLY) { 5241 if (opnd_size_prefix == 0x66) { 5242 #ifdef DIS_TEXT 5243 (void) strlcat(x->d86_mnem, "clflushopt", 5244 OPLEN); 5245 #endif 5246 } else if (opnd_size_prefix == 0) { 5247 #ifdef DIS_TEXT 5248 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 5249 #endif 5250 } else { 5251 /* Unknown instruction */ 5252 goto error; 5253 } 5254 5255 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5256 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5257 NOMEM; 5258 #ifdef DIS_TEXT 5259 } else { 5260 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 5261 #endif 5262 } 5263 break; 5264 5265 case FSGS: 5266 /* 5267 * The FSGSBASE instructions are taken only when the mode is set 5268 * to registers. They share opcodes with instructions like 5269 * fxrstor, stmxcsr, etc. We handle the repz prefix earlier. 5270 */ 5271 wbit = WBIT(opcode2); 5272 dtrace_get_modrm(x, &mode, ®, &r_m); 5273 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5274 dtrace_get_operand(x, mode, r_m, wbit, 0); 5275 if (mode == REG_ONLY) { 5276 NOMEM; 5277 } 5278 break; 5279 5280 /* 5281 * no disassembly, the mnemonic was all there was so go on 5282 */ 5283 case NORM: 5284 if (dp->it_invalid32 && cpu_mode != SIZE64) 5285 goto error; 5286 NOMEM; 5287 /*FALLTHROUGH*/ 5288 case IMPLMEM: 5289 break; 5290 5291 case XMMFENCE: 5292 /* 5293 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but 5294 * differ in mode and reg. 5295 */ 5296 dtrace_get_modrm(x, &mode, ®, &r_m); 5297 5298 if (mode == REG_ONLY) { 5299 /* 5300 * Only the following exact byte sequences are allowed: 5301 * 5302 * 0f ae e8 lfence 5303 * 0f ae f0 mfence 5304 */ 5305 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 5306 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 5307 goto error; 5308 } else { 5309 #ifdef DIS_TEXT 5310 if (reg == 5) { 5311 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 5312 } else if (reg == 6) { 5313 if (opnd_size_prefix == 0x66) { 5314 (void) strncpy(x->d86_mnem, "clwb", 5315 OPLEN); 5316 } else if (opnd_size_prefix == 0x00) { 5317 (void) strncpy(x->d86_mnem, "xsaveopt", 5318 OPLEN); 5319 } else { 5320 goto error; 5321 } 5322 } else { 5323 goto error; 5324 } 5325 #endif 5326 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5327 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5328 } 5329 break; 5330 5331 /* float reg */ 5332 case F: 5333 #ifdef DIS_TEXT 5334 x->d86_numopnds = 1; 5335 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 5336 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 5337 #endif 5338 NOMEM; 5339 break; 5340 5341 /* float reg to float reg, with ret bit present */ 5342 case FF: 5343 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 5344 /*FALLTHROUGH*/ 5345 case FFC: /* case for vbit always = 0 */ 5346 #ifdef DIS_TEXT 5347 x->d86_numopnds = 2; 5348 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 5349 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 5350 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 5351 #endif 5352 NOMEM; 5353 break; 5354 5355 /* AVX instructions */ 5356 case VEX_MO: 5357 /* op(ModR/M.r/m) */ 5358 x->d86_numopnds = 1; 5359 dtrace_get_modrm(x, &mode, ®, &r_m); 5360 #ifdef DIS_TEXT 5361 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 5362 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 5363 #endif 5364 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5365 dtrace_get_operand(x, mode, r_m, wbit, 0); 5366 break; 5367 case VEX_RMrX: 5368 case FMA: 5369 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 5370 x->d86_numopnds = 3; 5371 dtrace_get_modrm(x, &mode, ®, &r_m); 5372 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5373 5374 /* 5375 * In classic Intel fashion, the opcodes for all of the FMA 5376 * instructions all have two possible mnemonics which vary by 5377 * one letter, which is selected based on the value of the wbit. 5378 * When wbit is one, they have the 'd' suffix and when 'wbit' is 5379 * 0, they have the 's' suffix. Otherwise, the FMA instructions 5380 * are all a standard VEX_RMrX. 5381 */ 5382 #ifdef DIS_TEXT 5383 if (dp->it_adrmode == FMA) { 5384 size_t len = strlen(dp->it_name); 5385 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5386 if (len + 1 < OPLEN) { 5387 (void) strncpy(x->d86_mnem + len, 5388 vex_W != 0 ? "d" : "s", OPLEN - len); 5389 } 5390 } 5391 #endif 5392 5393 if (mode != REG_ONLY) { 5394 if ((dp == &dis_opAVXF20F[0x10]) || 5395 (dp == &dis_opAVXF30F[0x10])) { 5396 /* vmovsd <m64>, <xmm> */ 5397 /* or vmovss <m64>, <xmm> */ 5398 x->d86_numopnds = 2; 5399 goto L_VEX_MX; 5400 } 5401 } 5402 5403 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5404 /* 5405 * VEX prefix uses the 1's complement form to encode the 5406 * XMM/YMM regs 5407 */ 5408 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5409 5410 if ((dp == &dis_opAVXF20F[0x2A]) || 5411 (dp == &dis_opAVXF30F[0x2A])) { 5412 /* 5413 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 5414 * <xmm>, <xmm> 5415 */ 5416 wbit = LONG_OPND; 5417 } 5418 #ifdef DIS_TEXT 5419 else if ((mode == REG_ONLY) && 5420 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 5421 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 5422 } else if ((mode == REG_ONLY) && 5423 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 5424 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 5425 } 5426 #endif 5427 dtrace_get_operand(x, mode, r_m, wbit, 0); 5428 5429 break; 5430 5431 case VEX_VRMrX: 5432 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */ 5433 x->d86_numopnds = 3; 5434 dtrace_get_modrm(x, &mode, ®, &r_m); 5435 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5436 5437 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5438 /* 5439 * VEX prefix uses the 1's complement form to encode the 5440 * XMM/YMM regs 5441 */ 5442 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0); 5443 5444 dtrace_get_operand(x, mode, r_m, wbit, 1); 5445 break; 5446 5447 case VEX_SbVM: 5448 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */ 5449 x->d86_numopnds = 3; 5450 x->d86_vsib = 1; 5451 5452 /* 5453 * All instructions that use VSIB are currently a mess. See the 5454 * comment around the dis_gather_regs_t structure definition. 5455 */ 5456 5457 vreg = &dis_vgather[opcode2][vex_W][vex_L]; 5458 5459 #ifdef DIS_TEXT 5460 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5461 (void) strlcat(x->d86_mnem + strlen(dp->it_name), 5462 vreg->dgr_suffix, OPLEN - strlen(dp->it_name)); 5463 #endif 5464 5465 dtrace_get_modrm(x, &mode, ®, &r_m); 5466 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5467 5468 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2); 5469 /* 5470 * VEX prefix uses the 1's complement form to encode the 5471 * XMM/YMM regs 5472 */ 5473 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0, 5474 0); 5475 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1); 5476 break; 5477 5478 case VEX_RRX: 5479 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5480 x->d86_numopnds = 3; 5481 5482 dtrace_get_modrm(x, &mode, ®, &r_m); 5483 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5484 5485 if (mode != REG_ONLY) { 5486 if ((dp == &dis_opAVXF20F[0x11]) || 5487 (dp == &dis_opAVXF30F[0x11])) { 5488 /* vmovsd <xmm>, <m64> */ 5489 /* or vmovss <xmm>, <m64> */ 5490 x->d86_numopnds = 2; 5491 goto L_VEX_RM; 5492 } 5493 } 5494 5495 dtrace_get_operand(x, mode, r_m, wbit, 2); 5496 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5497 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5498 break; 5499 5500 case VEX_RMRX: 5501 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 5502 x->d86_numopnds = 4; 5503 5504 dtrace_get_modrm(x, &mode, ®, &r_m); 5505 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5506 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 5507 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5508 if (dp == &dis_opAVX660F3A[0x18]) { 5509 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 5510 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 5511 } else if ((dp == &dis_opAVX660F3A[0x20]) || 5512 (dp == & dis_opAVX660F[0xC4])) { 5513 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 5514 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 5515 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5516 } else if (dp == &dis_opAVX660F3A[0x22]) { 5517 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 5518 #ifdef DIS_TEXT 5519 if (vex_W) 5520 x->d86_mnem[6] = 'q'; 5521 #endif 5522 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5523 } else { 5524 dtrace_get_operand(x, mode, r_m, wbit, 1); 5525 } 5526 5527 /* one byte immediate number */ 5528 dtrace_imm_opnd(x, wbit, 1, 0); 5529 5530 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 5531 if ((dp == &dis_opAVX660F3A[0x4A]) || 5532 (dp == &dis_opAVX660F3A[0x4B]) || 5533 (dp == &dis_opAVX660F3A[0x4C])) { 5534 #ifdef DIS_TEXT 5535 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 5536 #endif 5537 x->d86_opnd[0].d86_mode = MODE_NONE; 5538 #ifdef DIS_TEXT 5539 if (vex_L) 5540 (void) strncpy(x->d86_opnd[0].d86_opnd, 5541 dis_YMMREG[regnum], OPLEN); 5542 else 5543 (void) strncpy(x->d86_opnd[0].d86_opnd, 5544 dis_XMMREG[regnum], OPLEN); 5545 #endif 5546 } 5547 break; 5548 5549 case VEX_MX: 5550 /* ModR/M.reg := op(ModR/M.rm) */ 5551 x->d86_numopnds = 2; 5552 5553 dtrace_get_modrm(x, &mode, ®, &r_m); 5554 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5555 L_VEX_MX: 5556 5557 if ((dp == &dis_opAVXF20F[0xE6]) || 5558 (dp == &dis_opAVX660F[0x5A]) || 5559 (dp == &dis_opAVX660F[0xE6])) { 5560 /* vcvtpd2dq <ymm>, <xmm> */ 5561 /* or vcvtpd2ps <ymm>, <xmm> */ 5562 /* or vcvttpd2dq <ymm>, <xmm> */ 5563 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 5564 dtrace_get_operand(x, mode, r_m, wbit, 0); 5565 } else if ((dp == &dis_opAVXF30F[0xE6]) || 5566 (dp == &dis_opAVX0F[0x5][0xA]) || 5567 (dp == &dis_opAVX660F38[0x13]) || 5568 (dp == &dis_opAVX660F38[0x18]) || 5569 (dp == &dis_opAVX660F38[0x19]) || 5570 (dp == &dis_opAVX660F38[0x58]) || 5571 (dp == &dis_opAVX660F38[0x78]) || 5572 (dp == &dis_opAVX660F38[0x79]) || 5573 (dp == &dis_opAVX660F38[0x59])) { 5574 /* vcvtdq2pd <xmm>, <ymm> */ 5575 /* or vcvtps2pd <xmm>, <ymm> */ 5576 /* or vcvtph2ps <xmm>, <ymm> */ 5577 /* or vbroadcasts* <xmm>, <ymm> */ 5578 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5579 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 5580 } else if (dp == &dis_opAVX660F[0x6E]) { 5581 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5582 #ifdef DIS_TEXT 5583 if (vex_W) 5584 x->d86_mnem[4] = 'q'; 5585 #endif 5586 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5587 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5588 } else { 5589 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5590 dtrace_get_operand(x, mode, r_m, wbit, 0); 5591 } 5592 5593 break; 5594 5595 case VEX_MXI: 5596 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 5597 x->d86_numopnds = 3; 5598 5599 dtrace_get_modrm(x, &mode, ®, &r_m); 5600 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5601 5602 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5603 dtrace_get_operand(x, mode, r_m, wbit, 1); 5604 5605 /* one byte immediate number */ 5606 dtrace_imm_opnd(x, wbit, 1, 0); 5607 break; 5608 5609 case VEX_XXI: 5610 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 5611 x->d86_numopnds = 3; 5612 5613 dtrace_get_modrm(x, &mode, ®, &r_m); 5614 #ifdef DIS_TEXT 5615 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 5616 OPLEN); 5617 #endif 5618 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5619 5620 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5621 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 5622 5623 /* one byte immediate number */ 5624 dtrace_imm_opnd(x, wbit, 1, 0); 5625 break; 5626 5627 case VEX_MR: 5628 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 5629 if (dp == &dis_opAVX660F[0xC5]) { 5630 /* vpextrw <imm8>, <xmm>, <reg> */ 5631 x->d86_numopnds = 2; 5632 vbit = 2; 5633 } else { 5634 x->d86_numopnds = 2; 5635 vbit = 1; 5636 } 5637 5638 dtrace_get_modrm(x, &mode, ®, &r_m); 5639 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5640 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 5641 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 5642 5643 if (vbit == 2) 5644 dtrace_imm_opnd(x, wbit, 1, 0); 5645 5646 break; 5647 5648 case VEX_KMR: 5649 /* opmask: mod_rm := %k */ 5650 x->d86_numopnds = 2; 5651 dtrace_get_modrm(x, &mode, ®, &r_m); 5652 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5653 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5654 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5655 break; 5656 5657 case VEX_KRM: 5658 /* opmask: mod_reg := mod_rm */ 5659 x->d86_numopnds = 2; 5660 dtrace_get_modrm(x, &mode, ®, &r_m); 5661 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5662 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5663 if (mode == REG_ONLY) { 5664 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0); 5665 } else { 5666 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5667 } 5668 break; 5669 5670 case VEX_KRR: 5671 /* opmask: mod_reg := mod_rm */ 5672 x->d86_numopnds = 2; 5673 dtrace_get_modrm(x, &mode, ®, &r_m); 5674 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5675 dtrace_get_operand(x, mode, reg, wbit, 1); 5676 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0); 5677 break; 5678 5679 case VEX_RRI: 5680 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 5681 x->d86_numopnds = 2; 5682 5683 dtrace_get_modrm(x, &mode, ®, &r_m); 5684 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5685 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5686 dtrace_get_operand(x, mode, r_m, wbit, 0); 5687 break; 5688 5689 case VEX_RX: 5690 /* ModR/M.rm := op(ModR/M.reg) */ 5691 /* vextractf128 || vcvtps2ph */ 5692 if (dp == &dis_opAVX660F3A[0x19] || 5693 dp == &dis_opAVX660F3A[0x1d]) { 5694 x->d86_numopnds = 3; 5695 5696 dtrace_get_modrm(x, &mode, ®, &r_m); 5697 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5698 5699 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5700 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5701 5702 /* one byte immediate number */ 5703 dtrace_imm_opnd(x, wbit, 1, 0); 5704 break; 5705 } 5706 5707 x->d86_numopnds = 2; 5708 5709 dtrace_get_modrm(x, &mode, ®, &r_m); 5710 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5711 dtrace_get_operand(x, mode, r_m, wbit, 1); 5712 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5713 break; 5714 5715 case VEX_RR: 5716 /* ModR/M.rm := op(ModR/M.reg) */ 5717 x->d86_numopnds = 2; 5718 5719 dtrace_get_modrm(x, &mode, ®, &r_m); 5720 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5721 5722 if (dp == &dis_opAVX660F[0x7E]) { 5723 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5724 #ifdef DIS_TEXT 5725 if (vex_W) 5726 x->d86_mnem[4] = 'q'; 5727 #endif 5728 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5729 } else 5730 dtrace_get_operand(x, mode, r_m, wbit, 1); 5731 5732 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5733 break; 5734 5735 case VEX_RRi: 5736 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5737 x->d86_numopnds = 3; 5738 5739 dtrace_get_modrm(x, &mode, ®, &r_m); 5740 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5741 5742 #ifdef DIS_TEXT 5743 if (dp == &dis_opAVX660F3A[0x16]) { 5744 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 5745 if (vex_W) 5746 x->d86_mnem[6] = 'q'; 5747 } 5748 #endif 5749 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5750 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5751 5752 /* one byte immediate number */ 5753 dtrace_imm_opnd(x, wbit, 1, 0); 5754 break; 5755 case VEX_RIM: 5756 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5757 x->d86_numopnds = 3; 5758 5759 dtrace_get_modrm(x, &mode, ®, &r_m); 5760 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5761 5762 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5763 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5764 /* one byte immediate number */ 5765 dtrace_imm_opnd(x, wbit, 1, 0); 5766 break; 5767 5768 case VEX_RM: 5769 /* ModR/M.rm := op(ModR/M.reg) */ 5770 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 5771 x->d86_numopnds = 3; 5772 5773 dtrace_get_modrm(x, &mode, ®, &r_m); 5774 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5775 5776 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5777 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5778 /* one byte immediate number */ 5779 dtrace_imm_opnd(x, wbit, 1, 0); 5780 break; 5781 } 5782 x->d86_numopnds = 2; 5783 5784 dtrace_get_modrm(x, &mode, ®, &r_m); 5785 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5786 L_VEX_RM: 5787 vbit = 1; 5788 dtrace_get_operand(x, mode, r_m, wbit, vbit); 5789 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 5790 5791 break; 5792 5793 case VEX_RRM: 5794 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5795 x->d86_numopnds = 3; 5796 5797 dtrace_get_modrm(x, &mode, ®, &r_m); 5798 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5799 dtrace_get_operand(x, mode, r_m, wbit, 2); 5800 /* VEX use the 1's complement form encode the XMM/YMM regs */ 5801 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5802 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5803 break; 5804 5805 case VEX_RMX: 5806 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 5807 x->d86_numopnds = 3; 5808 5809 dtrace_get_modrm(x, &mode, ®, &r_m); 5810 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5811 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5812 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5813 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 5814 break; 5815 5816 case VEX_NONE: 5817 #ifdef DIS_TEXT 5818 if (vex_L) 5819 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 5820 #endif 5821 break; 5822 case BLS: { 5823 5824 /* 5825 * The BLS instructions are VEX instructions that are based on 5826 * VEX.0F38.F3; however, they are considered special group 17 5827 * and like everything else, they use the bits in 3-5 of the 5828 * MOD R/M to determine the sub instruction. Unlike many others 5829 * like the VMX instructions, these are valid both for memory 5830 * and register forms. 5831 */ 5832 5833 dtrace_get_modrm(x, &mode, ®, &r_m); 5834 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5835 5836 switch (reg) { 5837 case 1: 5838 #ifdef DIS_TEXT 5839 blsinstr = "blsr"; 5840 #endif 5841 break; 5842 case 2: 5843 #ifdef DIS_TEXT 5844 blsinstr = "blsmsk"; 5845 #endif 5846 break; 5847 case 3: 5848 #ifdef DIS_TEXT 5849 blsinstr = "blsi"; 5850 #endif 5851 break; 5852 default: 5853 goto error; 5854 } 5855 5856 x->d86_numopnds = 2; 5857 #ifdef DIS_TEXT 5858 (void) strncpy(x->d86_mnem, blsinstr, OPLEN); 5859 #endif 5860 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5861 dtrace_get_operand(x, mode, r_m, wbit, 0); 5862 break; 5863 } 5864 case EVEX_MX: 5865 /* ModR/M.reg := op(ModR/M.rm) */ 5866 x->d86_numopnds = 2; 5867 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5868 dtrace_get_modrm(x, &mode, ®, &r_m); 5869 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5870 dtrace_evex_adjust_reg(evex_byte1, ®); 5871 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5872 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5873 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5874 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 5875 dtrace_get_operand(x, mode, r_m, wbit, 0); 5876 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 5877 break; 5878 case EVEX_RX: 5879 /* ModR/M.rm := op(ModR/M.reg) */ 5880 x->d86_numopnds = 2; 5881 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5882 dtrace_get_modrm(x, &mode, ®, &r_m); 5883 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5884 dtrace_evex_adjust_reg(evex_byte1, ®); 5885 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5886 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5887 dtrace_get_operand(x, mode, r_m, wbit, 1); 5888 dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); 5889 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 5890 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5891 break; 5892 case EVEX_RMrX: 5893 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */ 5894 x->d86_numopnds = 3; 5895 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5896 dtrace_get_modrm(x, &mode, ®, &r_m); 5897 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5898 dtrace_evex_adjust_reg(evex_byte1, ®); 5899 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5900 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5901 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5902 /* 5903 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 5904 * register specifier). The EVEX prefix handling uses the vex_v 5905 * variable for these bits. 5906 */ 5907 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5908 dtrace_get_operand(x, mode, r_m, wbit, 0); 5909 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 5910 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); 5911 break; 5912 /* an invalid op code */ 5913 case AM: 5914 case DM: 5915 case OVERRIDE: 5916 case PREFIX: 5917 case UNKNOWN: 5918 NOMEM; 5919 default: 5920 goto error; 5921 } /* end switch */ 5922 if (x->d86_error) 5923 goto error; 5924 5925 done: 5926 #ifdef DIS_MEM 5927 /* 5928 * compute the size of any memory accessed by the instruction 5929 */ 5930 if (x->d86_memsize != 0) { 5931 return (0); 5932 } else if (dp->it_stackop) { 5933 switch (opnd_size) { 5934 case SIZE16: 5935 x->d86_memsize = 2; 5936 break; 5937 case SIZE32: 5938 x->d86_memsize = 4; 5939 break; 5940 case SIZE64: 5941 x->d86_memsize = 8; 5942 break; 5943 } 5944 } else if (nomem || mode == REG_ONLY) { 5945 x->d86_memsize = 0; 5946 5947 } else if (dp->it_size != 0) { 5948 /* 5949 * In 64 bit mode descriptor table entries 5950 * go up to 10 bytes and popf/pushf are always 8 bytes 5951 */ 5952 if (x->d86_mode == SIZE64 && dp->it_size == 6) 5953 x->d86_memsize = 10; 5954 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 5955 (opcode2 == 0xc || opcode2 == 0xd)) 5956 x->d86_memsize = 8; 5957 else 5958 x->d86_memsize = dp->it_size; 5959 5960 } else if (wbit == 0) { 5961 x->d86_memsize = 1; 5962 5963 } else if (wbit == LONG_OPND) { 5964 if (opnd_size == SIZE64) 5965 x->d86_memsize = 8; 5966 else if (opnd_size == SIZE32) 5967 x->d86_memsize = 4; 5968 else 5969 x->d86_memsize = 2; 5970 5971 } else if (wbit == SEG_OPND) { 5972 x->d86_memsize = 4; 5973 5974 } else { 5975 x->d86_memsize = 8; 5976 } 5977 #endif 5978 return (0); 5979 5980 error: 5981 #ifdef DIS_TEXT 5982 (void) strlcat(x->d86_mnem, "undef", OPLEN); 5983 #endif 5984 return (1); 5985 } 5986 5987 #ifdef DIS_TEXT 5988 5989 /* 5990 * Some instructions should have immediate operands printed 5991 * as unsigned integers. We compare against this table. 5992 */ 5993 static char *unsigned_ops[] = { 5994 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 5995 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 5996 0 5997 }; 5998 5999 6000 static int 6001 isunsigned_op(char *opcode) 6002 { 6003 char *where; 6004 int i; 6005 int is_unsigned = 0; 6006 6007 /* 6008 * Work back to start of last mnemonic, since we may have 6009 * prefixes on some opcodes. 6010 */ 6011 where = opcode + strlen(opcode) - 1; 6012 while (where > opcode && *where != ' ') 6013 --where; 6014 if (*where == ' ') 6015 ++where; 6016 6017 for (i = 0; unsigned_ops[i]; ++i) { 6018 if (strncmp(where, unsigned_ops[i], 6019 strlen(unsigned_ops[i]))) 6020 continue; 6021 is_unsigned = 1; 6022 break; 6023 } 6024 return (is_unsigned); 6025 } 6026 6027 /* 6028 * Print a numeric immediate into end of buf, maximum length buflen. 6029 * The immediate may be an address or a displacement. Mask is set 6030 * for address size. If the immediate is a "small negative", or 6031 * if it's a negative displacement of any magnitude, print as -<absval>. 6032 * Respect the "octal" flag. "Small negative" is defined as "in the 6033 * interval [NEG_LIMIT, 0)". 6034 * 6035 * Also, "isunsigned_op()" instructions never print negatives. 6036 * 6037 * Return whether we decided to print a negative value or not. 6038 */ 6039 6040 #define NEG_LIMIT -255 6041 enum {IMM, DISP}; 6042 enum {POS, TRY_NEG}; 6043 6044 static int 6045 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 6046 size_t buflen, int disp, int try_neg) 6047 { 6048 int curlen; 6049 int64_t sv = (int64_t)usv; 6050 int octal = dis->d86_flags & DIS_F_OCTAL; 6051 6052 curlen = strlen(buf); 6053 6054 if (try_neg == TRY_NEG && sv < 0 && 6055 (disp || sv >= NEG_LIMIT) && 6056 !isunsigned_op(dis->d86_mnem)) { 6057 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6058 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 6059 return (1); 6060 } else { 6061 if (disp == DISP) 6062 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6063 octal ? "+0%llo" : "+0x%llx", usv & mask); 6064 else 6065 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6066 octal ? "0%llo" : "0x%llx", usv & mask); 6067 return (0); 6068 6069 } 6070 } 6071 6072 6073 static int 6074 log2(int size) 6075 { 6076 switch (size) { 6077 case 1: return (0); 6078 case 2: return (1); 6079 case 4: return (2); 6080 case 8: return (3); 6081 } 6082 return (0); 6083 } 6084 6085 /* ARGSUSED */ 6086 void 6087 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 6088 size_t buflen) 6089 { 6090 uint64_t reltgt = 0; 6091 uint64_t tgt = 0; 6092 int curlen; 6093 int (*lookup)(void *, uint64_t, char *, size_t); 6094 int i; 6095 int64_t sv; 6096 uint64_t usv, mask, save_mask, save_usv; 6097 static uint64_t masks[] = 6098 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 6099 save_usv = 0; 6100 6101 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 6102 6103 /* 6104 * For PC-relative jumps, the pc is really the next pc after executing 6105 * this instruction, so increment it appropriately. 6106 */ 6107 pc += dis->d86_len; 6108 6109 for (i = 0; i < dis->d86_numopnds; i++) { 6110 d86opnd_t *op = &dis->d86_opnd[i]; 6111 6112 if (i != 0) 6113 (void) strlcat(buf, ",", buflen); 6114 6115 (void) strlcat(buf, op->d86_prefix, buflen); 6116 6117 /* 6118 * sv is for the signed, possibly-truncated immediate or 6119 * displacement; usv retains the original size and 6120 * unsignedness for symbol lookup. 6121 */ 6122 6123 sv = usv = op->d86_value; 6124 6125 /* 6126 * About masks: for immediates that represent 6127 * addresses, the appropriate display size is 6128 * the effective address size of the instruction. 6129 * This includes MODE_OFFSET, MODE_IPREL, and 6130 * MODE_RIPREL. Immediates that are simply 6131 * immediate values should display in the operand's 6132 * size, however, since they don't represent addresses. 6133 */ 6134 6135 /* d86_addr_size is SIZEnn, which is log2(real size) */ 6136 mask = masks[dis->d86_addr_size]; 6137 6138 /* d86_value_size and d86_imm_bytes are in bytes */ 6139 if (op->d86_mode == MODE_SIGNED || 6140 op->d86_mode == MODE_IMPLIED) 6141 mask = masks[log2(op->d86_value_size)]; 6142 6143 switch (op->d86_mode) { 6144 6145 case MODE_NONE: 6146 6147 (void) strlcat(buf, op->d86_opnd, buflen); 6148 break; 6149 6150 case MODE_SIGNED: 6151 case MODE_IMPLIED: 6152 case MODE_OFFSET: 6153 6154 tgt = usv; 6155 6156 if (dis->d86_seg_prefix) 6157 (void) strlcat(buf, dis->d86_seg_prefix, 6158 buflen); 6159 6160 if (op->d86_mode == MODE_SIGNED || 6161 op->d86_mode == MODE_IMPLIED) { 6162 (void) strlcat(buf, "$", buflen); 6163 } 6164 6165 if (print_imm(dis, usv, mask, buf, buflen, 6166 IMM, TRY_NEG) && 6167 (op->d86_mode == MODE_SIGNED || 6168 op->d86_mode == MODE_IMPLIED)) { 6169 6170 /* 6171 * We printed a negative value for an 6172 * immediate that wasn't a 6173 * displacement. Note that fact so we can 6174 * print the positive value as an 6175 * annotation. 6176 */ 6177 6178 save_usv = usv; 6179 save_mask = mask; 6180 } 6181 (void) strlcat(buf, op->d86_opnd, buflen); 6182 6183 break; 6184 6185 case MODE_IPREL: 6186 case MODE_RIPREL: 6187 6188 reltgt = pc + sv; 6189 6190 switch (mode) { 6191 case SIZE16: 6192 reltgt = (uint16_t)reltgt; 6193 break; 6194 case SIZE32: 6195 reltgt = (uint32_t)reltgt; 6196 break; 6197 } 6198 6199 (void) print_imm(dis, usv, mask, buf, buflen, 6200 DISP, TRY_NEG); 6201 6202 if (op->d86_mode == MODE_RIPREL) 6203 (void) strlcat(buf, "(%rip)", buflen); 6204 break; 6205 } 6206 } 6207 6208 /* 6209 * The symbol lookups may result in false positives, 6210 * particularly on object files, where small numbers may match 6211 * the 0-relative non-relocated addresses of symbols. 6212 */ 6213 6214 lookup = dis->d86_sym_lookup; 6215 if (tgt != 0) { 6216 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 6217 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 6218 (void) strlcat(buf, "\t<", buflen); 6219 curlen = strlen(buf); 6220 lookup(dis->d86_data, tgt, buf + curlen, 6221 buflen - curlen); 6222 (void) strlcat(buf, ">", buflen); 6223 } 6224 6225 /* 6226 * If we printed a negative immediate above, print the 6227 * positive in case our heuristic was unhelpful 6228 */ 6229 if (save_usv) { 6230 (void) strlcat(buf, "\t<", buflen); 6231 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 6232 IMM, POS); 6233 (void) strlcat(buf, ">", buflen); 6234 } 6235 } 6236 6237 if (reltgt != 0) { 6238 /* Print symbol or effective address for reltgt */ 6239 6240 (void) strlcat(buf, "\t<", buflen); 6241 curlen = strlen(buf); 6242 lookup(dis->d86_data, reltgt, buf + curlen, 6243 buflen - curlen); 6244 (void) strlcat(buf, ">", buflen); 6245 } 6246 } 6247 6248 #endif /* DIS_TEXT */ 6249