1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2019, Joyent, Inc. 25 */ 26 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 32 /* Copyright (c) 1988 AT&T */ 33 /* All Rights Reserved */ 34 35 #include "dis_tables.h" 36 37 /* BEGIN CSTYLED */ 38 39 /* 40 * Disassembly begins in dis_distable, which is equivalent to the One-byte 41 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 42 * decoding loops then traverse out through the other tables as necessary to 43 * decode a given instruction. 44 * 45 * The behavior of this file can be controlled by one of the following flags: 46 * 47 * DIS_TEXT Include text for disassembly 48 * DIS_MEM Include memory-size calculations 49 * 50 * Either or both of these can be defined. 51 * 52 * This file is not, and will never be, cstyled. If anything, the tables should 53 * be taken out another tab stop or two so nothing overlaps. 54 */ 55 56 /* 57 * These functions must be provided for the consumer to do disassembly. 58 */ 59 #ifdef DIS_TEXT 60 extern char *strncpy(char *, const char *, size_t); 61 extern size_t strlen(const char *); 62 extern int strcmp(const char *, const char *); 63 extern int strncmp(const char *, const char *, size_t); 64 extern size_t strlcat(char *, const char *, size_t); 65 #endif 66 67 68 #define TERM 0 /* used to indicate that the 'indirect' */ 69 /* field terminates - no pointer. */ 70 71 /* Used to decode instructions. */ 72 typedef struct instable { 73 struct instable *it_indirect; /* for decode op codes */ 74 uchar_t it_adrmode; 75 #ifdef DIS_TEXT 76 char it_name[NCPS]; 77 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 78 #endif 79 #ifdef DIS_MEM 80 uint_t it_size:16; 81 #endif 82 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 83 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 84 uint_t it_invalid32:1; /* invalid in IA32 */ 85 uint_t it_stackop:1; /* push/pop stack operation */ 86 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ 87 uint_t it_avxsuf:2; /* AVX2/AVX512 suffix rqd. */ 88 uint_t it_vexopmask:1; /* VEX inst. that use opmask */ 89 } instable_t; 90 91 /* 92 * Instruction formats. 93 */ 94 enum { 95 UNKNOWN, 96 MRw, 97 IMlw, 98 IMw, 99 IR, 100 OA, 101 AO, 102 MS, 103 SM, 104 Mv, 105 Mw, 106 M, /* register or memory */ 107 MG9, /* register or memory in group 9 (prefix optional) */ 108 Mb, /* register or memory, always byte sized */ 109 MO, /* memory only (no registers) */ 110 PREF, 111 SWAPGS_RDTSCP, 112 MONITOR_MWAIT, 113 R, 114 RA, 115 SEG, 116 MR, 117 RM, 118 RM_66r, /* RM, but with a required 0x66 prefix */ 119 IA, 120 MA, 121 SD, 122 AD, 123 SA, 124 D, 125 INM, 126 SO, 127 BD, 128 I, 129 P, 130 V, 131 DSHIFT, /* for double shift that has an 8-bit immediate */ 132 U, 133 OVERRIDE, 134 NORM, /* instructions w/o ModR/M byte, no memory access */ 135 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 136 O, /* for call */ 137 JTAB, /* jump table */ 138 IMUL, /* for 186 iimul instr */ 139 CBW, /* so data16 can be evaluated for cbw and variants */ 140 MvI, /* for 186 logicals */ 141 ENTER, /* for 186 enter instr */ 142 RMw, /* for 286 arpl instr */ 143 Ib, /* for push immediate byte */ 144 F, /* for 287 instructions */ 145 FF, /* for 287 instructions */ 146 FFC, /* for 287 instructions */ 147 DM, /* 16-bit data */ 148 AM, /* 16-bit addr */ 149 LSEG, /* for 3-bit seg reg encoding */ 150 MIb, /* for 386 logicals */ 151 SREG, /* for 386 special registers */ 152 PREFIX, /* a REP instruction prefix */ 153 LOCK, /* a LOCK instruction prefix */ 154 INT3, /* The int 3 instruction, which has a fake operand */ 155 INTx, /* The normal int instruction, with explicit int num */ 156 DSHIFTcl, /* for double shift that implicitly uses %cl */ 157 CWD, /* so data16 can be evaluated for cwd and variants */ 158 RET, /* single immediate 16-bit operand */ 159 MOVZ, /* for movs and movz, with different size operands */ 160 CRC32, /* for crc32, with different size operands */ 161 XADDB, /* for xaddb */ 162 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 163 MOVBE, /* movbe instruction */ 164 165 /* 166 * MMX/SIMD addressing modes. 167 */ 168 169 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 170 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 171 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 172 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 173 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 174 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 175 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 176 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 177 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 178 MMOSH, /* Prefixable MMX mm,imm8 */ 179 MM, /* MMX/SIMD-Int mm/mem -> mm */ 180 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 181 MMSH, /* MMX mm,imm8 */ 182 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 183 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 184 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 185 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 186 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 187 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 188 XMMOM, /* Prefixable SIMD xmm -> mem */ 189 XMMOMS, /* Prefixable SIMD mem -> xmm */ 190 XMM, /* SIMD xmm/mem -> xmm */ 191 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 192 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 193 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 194 XMM3P, /* SIMD xmm -> r32,imm8 */ 195 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 196 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 197 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 198 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 199 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 200 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 201 XMMS, /* SIMD xmm -> xmm/mem */ 202 XMMM, /* SIMD mem -> xmm */ 203 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 204 XMMMS, /* SIMD xmm -> mem */ 205 XMM3MX, /* SIMD r32/mem -> xmm */ 206 XMM3MXS, /* SIMD xmm -> r32/mem */ 207 XMMSH, /* SIMD xmm,imm8 */ 208 XMMXM3, /* SIMD xmm/mem -> r32 */ 209 XMMX3, /* SIMD xmm -> r32 */ 210 XMMXMM, /* SIMD xmm/mem -> mm */ 211 XMMMX, /* SIMD mm -> xmm */ 212 XMMXM, /* SIMD xmm -> mm */ 213 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 214 XMM2I, /* SIMD xmm, imm, imm */ 215 XMMFENCE, /* SIMD lfence or mfence */ 216 XMMSFNC, /* SIMD sfence (none or mem) */ 217 FSGS, /* FSGSBASE if reg */ 218 XGETBV_XSETBV, 219 VEX_NONE, /* VEX no operand */ 220 VEX_MO, /* VEX mod_rm -> implicit reg */ 221 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 222 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */ 223 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 224 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 225 VEX_MX, /* VEX mod_rm -> mod_reg */ 226 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 227 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 228 VEX_MR, /* VEX mod_rm -> mod_reg */ 229 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 230 VEX_RX, /* VEX mod_reg -> mod_rm */ 231 VEX_KRR, /* VEX mod_rm -> mod_reg */ 232 VEX_KMR, /* VEX mod_reg -> mod_rm */ 233 VEX_KRM, /* VEX mod_rm -> mod_reg */ 234 VEX_RR, /* VEX mod_rm -> mod_reg */ 235 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 236 VEX_RM, /* VEX mod_reg -> mod_rm */ 237 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */ 238 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 239 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 240 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */ 241 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 242 VMxo, /* VMx instruction with optional prefix */ 243 SVM, /* AMD SVM instructions */ 244 BLS, /* BLSR, BLSMSK, BLSI */ 245 FMA, /* FMA instructions, all VEX_RMrX */ 246 ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */ 247 EVEX_RX, /* EVEX mod_reg -> mod_rm */ 248 EVEX_MX, /* EVEX mod_rm -> mod_reg */ 249 EVEX_RMrX /* EVEX EVEX.vvvv, mod_rm -> mod_reg */ 250 }; 251 252 /* 253 * VEX prefixes 254 */ 255 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 256 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 257 258 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 259 260 /* 261 ** Register numbers for the i386 262 */ 263 #define EAX_REGNO 0 264 #define ECX_REGNO 1 265 #define EDX_REGNO 2 266 #define EBX_REGNO 3 267 #define ESP_REGNO 4 268 #define EBP_REGNO 5 269 #define ESI_REGNO 6 270 #define EDI_REGNO 7 271 272 /* 273 * modes for immediate values 274 */ 275 #define MODE_NONE 0 276 #define MODE_IPREL 1 /* signed IP relative value */ 277 #define MODE_SIGNED 2 /* sign extended immediate */ 278 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 279 #define MODE_OFFSET 4 /* offset part of an address */ 280 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 281 282 /* 283 * The letters used in these macros are: 284 * IND - indirect to another to another table 285 * "T" - means to Terminate indirections (this is the final opcode) 286 * "S" - means "operand length suffix required" 287 * "Sa" - means AVX2 suffix (q/d) required 288 * "Sq" - means AVX512 suffix (q/d) required 289 * "Sd" - means AVX512 suffix (d/s) required 290 * "NS" - means "no suffix" which is the operand length suffix of the opcode 291 * "Z" - means instruction size arg required 292 * "u" - means the opcode is invalid in IA32 but valid in amd64 293 * "x" - means the opcode is invalid in amd64, but not IA32 294 * "y" - means the operand size is always 64 bits in 64 bit mode 295 * "p" - means push/pop stack operation 296 * "vr" - means VEX instruction that operates on normal registers, not fpu 297 * "vo" - means VEX instruction that operates on opmask registers, not fpu 298 */ 299 300 #define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling */ 301 #define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix handling */ 302 #define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix handling */ 303 304 #if defined(DIS_TEXT) && defined(DIS_MEM) 305 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 306 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 307 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 308 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 309 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 310 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 311 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 312 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 313 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 314 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} 315 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} 316 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 317 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 318 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 319 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 320 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 321 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2} 322 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q} 323 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D} 324 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 325 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 326 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 327 #elif defined(DIS_TEXT) 328 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 329 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 330 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 331 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 332 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 333 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 334 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 335 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 336 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 337 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1} 338 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1} 339 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 340 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 341 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 342 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 343 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 344 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2} 345 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q} 346 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5D} 347 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 348 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 349 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 350 #elif defined(DIS_MEM) 351 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 352 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 353 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 354 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 355 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 356 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 357 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 358 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 359 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 360 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1} 361 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1} 362 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 363 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 364 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 365 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 366 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 367 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2} 368 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q} 369 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5D} 370 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 371 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 372 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 373 #else 374 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 375 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 376 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 377 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 378 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 379 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 380 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 381 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 382 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 383 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1} 384 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1} 385 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 386 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 387 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 388 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 389 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 390 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2} 391 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q} 392 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D} 393 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 394 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 395 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 396 #endif 397 398 #ifdef DIS_TEXT 399 /* 400 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 401 */ 402 const char *const dis_addr16[3][8] = { 403 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 404 "(%bx)", 405 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 406 "(%bx)", 407 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 408 "(%bx)", 409 }; 410 411 412 /* 413 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 414 */ 415 const char *const dis_addr32_mode0[16] = { 416 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 417 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 418 }; 419 420 const char *const dis_addr32_mode12[16] = { 421 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 422 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 423 }; 424 425 /* 426 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 427 */ 428 const char *const dis_addr64_mode0[16] = { 429 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 430 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 431 }; 432 const char *const dis_addr64_mode12[16] = { 433 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 434 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 435 }; 436 437 /* 438 * decode for scale from SIB byte 439 */ 440 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 441 442 /* 443 * decode for scale from VSIB byte, note that we always include the scale factor 444 * to match gas. 445 */ 446 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" }; 447 448 /* 449 * register decoding for normal references to registers (ie. not addressing) 450 */ 451 const char *const dis_REG8[16] = { 452 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 453 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 454 }; 455 456 const char *const dis_REG8_REX[16] = { 457 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 458 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 459 }; 460 461 const char *const dis_REG16[16] = { 462 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 463 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 464 }; 465 466 const char *const dis_REG32[16] = { 467 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 468 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 469 }; 470 471 const char *const dis_REG64[16] = { 472 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 473 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 474 }; 475 476 const char *const dis_DEBUGREG[16] = { 477 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 478 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 479 }; 480 481 const char *const dis_CONTROLREG[16] = { 482 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 483 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 484 }; 485 486 const char *const dis_TESTREG[16] = { 487 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 488 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 489 }; 490 491 const char *const dis_MMREG[16] = { 492 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 493 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 494 }; 495 496 const char *const dis_XMMREG[32] = { 497 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 498 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 499 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 500 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 501 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 502 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 503 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 504 "%xmm28", "%xmm29", "%xmm30", "%xmm31", 505 }; 506 507 const char *const dis_YMMREG[32] = { 508 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 509 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 510 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 511 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 512 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 513 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 514 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 515 "%ymm28", "%ymm29", "%ymm30", "%ymm31", 516 }; 517 518 const char *const dis_ZMMREG[32] = { 519 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 520 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 521 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 522 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 523 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 524 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 525 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 526 "%zmm28", "%zmm29", "%zmm30", "%zmm31", 527 }; 528 529 const char *const dis_KOPMASKREG[8] = { 530 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 531 }; 532 533 const char *const dis_SEGREG[16] = { 534 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 535 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 536 }; 537 538 /* 539 * SIMD predicate suffixes 540 */ 541 const char *const dis_PREDSUFFIX[8] = { 542 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 543 }; 544 545 const char *const dis_AVXvgrp7[3][8] = { 546 /*0 1 2 3 4 5 6 7*/ 547 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 548 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 549 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 550 }; 551 552 #endif /* DIS_TEXT */ 553 554 /* 555 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 556 */ 557 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 558 559 /* 560 * "decode table" for pause and clflush instructions 561 */ 562 const instable_t dis_opPause = TNS("pause", NORM); 563 564 /* 565 * Decode table for 0x0F00 opcodes 566 */ 567 const instable_t dis_op0F00[8] = { 568 569 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 570 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 571 }; 572 573 574 /* 575 * Decode table for 0x0F01 opcodes 576 */ 577 const instable_t dis_op0F01[8] = { 578 579 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 580 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 581 }; 582 583 /* 584 * Decode table for 0x0F18 opcodes -- SIMD prefetch 585 */ 586 const instable_t dis_op0F18[8] = { 587 588 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 589 /* [4] */ INVALID, INVALID, INVALID, INVALID, 590 }; 591 592 /* 593 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 594 */ 595 const instable_t dis_op0FAE[8] = { 596 /* [0] */ TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS), TNS("stmxcsr",FSGS), 597 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 598 }; 599 600 /* 601 * Decode table for 0xF30FAE opcodes -- FSGSBASE 602 */ 603 const instable_t dis_opF30FAE[8] = { 604 /* [0] */ TNSx("rdfsbase",FSGS), TNSx("rdgsbase",FSGS), TNSx("wrfsbase",FSGS), TNSx("wrgsbase",FSGS), 605 /* [4] */ INVALID, INVALID, INVALID, INVALID, 606 }; 607 608 /* 609 * Decode table for 0x0FBA opcodes 610 */ 611 612 const instable_t dis_op0FBA[8] = { 613 614 /* [0] */ INVALID, INVALID, INVALID, INVALID, 615 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 616 }; 617 618 /* 619 * Decode table for 0x0FC7 opcode (group 9) 620 */ 621 622 const instable_t dis_op0FC7[8] = { 623 624 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9), 625 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9), 626 }; 627 628 /* 629 * Decode table for 0x0FC7 opcode (group 9) mode 3 630 */ 631 632 const instable_t dis_op0FC7m3[8] = { 633 634 /* [0] */ INVALID, INVALID, INVALID, INVALID, 635 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9), 636 }; 637 638 /* 639 * Decode table for 0x0FC7 opcode with 0x66 prefix 640 */ 641 642 const instable_t dis_op660FC7[8] = { 643 644 /* [0] */ INVALID, INVALID, INVALID, INVALID, 645 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 646 }; 647 648 /* 649 * Decode table for 0x0FC7 opcode with 0xF3 prefix 650 */ 651 652 const instable_t dis_opF30FC7[8] = { 653 654 /* [0] */ INVALID, INVALID, INVALID, INVALID, 655 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 656 }; 657 658 /* 659 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 660 * 661 *bit pattern: 0000 1111 1100 1reg 662 */ 663 const instable_t dis_op0FC8[4] = { 664 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 665 }; 666 667 /* 668 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 669 */ 670 const instable_t dis_op0F7123[4][8] = { 671 { 672 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 673 /* .4 */ INVALID, INVALID, INVALID, INVALID, 674 }, { 675 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 676 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 677 }, { 678 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 679 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 680 }, { 681 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 682 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 683 } }; 684 685 /* 686 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 687 */ 688 const instable_t dis_opSIMD7123[32] = { 689 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 690 /* .4 */ INVALID, INVALID, INVALID, INVALID, 691 692 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 693 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 694 695 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 696 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 697 698 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 699 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 700 }; 701 702 /* 703 * SIMD instructions have been wedged into the existing IA32 instruction 704 * set through the use of prefixes. That is, while 0xf0 0x58 may be 705 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 706 * instruction - addss. At present, three prefixes have been coopted in 707 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 708 * following tables are used to provide the prefixed instruction names. 709 * The arrays are sparse, but they're fast. 710 */ 711 712 /* 713 * Decode table for SIMD instructions with the address size (0x66) prefix. 714 */ 715 const instable_t dis_opSIMDdata16[256] = { 716 /* [00] */ INVALID, INVALID, INVALID, INVALID, 717 /* [04] */ INVALID, INVALID, INVALID, INVALID, 718 /* [08] */ INVALID, INVALID, INVALID, INVALID, 719 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 720 721 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 722 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 723 /* [18] */ INVALID, INVALID, INVALID, INVALID, 724 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 725 726 /* [20] */ INVALID, INVALID, INVALID, INVALID, 727 /* [24] */ INVALID, INVALID, INVALID, INVALID, 728 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 729 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 730 731 /* [30] */ INVALID, INVALID, INVALID, INVALID, 732 /* [34] */ INVALID, INVALID, INVALID, INVALID, 733 /* [38] */ INVALID, INVALID, INVALID, INVALID, 734 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 735 736 /* [40] */ INVALID, INVALID, INVALID, INVALID, 737 /* [44] */ INVALID, INVALID, INVALID, INVALID, 738 /* [48] */ INVALID, INVALID, INVALID, INVALID, 739 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 740 741 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 742 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 743 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 744 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 745 746 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 747 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 748 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 749 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 750 751 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 752 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 753 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 754 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 755 756 /* [80] */ INVALID, INVALID, INVALID, INVALID, 757 /* [84] */ INVALID, INVALID, INVALID, INVALID, 758 /* [88] */ INVALID, INVALID, INVALID, INVALID, 759 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 760 761 /* [90] */ INVALID, INVALID, INVALID, INVALID, 762 /* [94] */ INVALID, INVALID, INVALID, INVALID, 763 /* [98] */ INVALID, INVALID, INVALID, INVALID, 764 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 765 766 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 767 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 768 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 769 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 770 771 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 772 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 773 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 774 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 775 776 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 777 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 778 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 779 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 780 781 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 782 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 783 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 784 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 785 786 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 787 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 788 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 789 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 790 791 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 792 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 793 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 794 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 795 }; 796 797 const instable_t dis_opAVX660F[256] = { 798 /* [00] */ INVALID, INVALID, INVALID, INVALID, 799 /* [04] */ INVALID, INVALID, INVALID, INVALID, 800 /* [08] */ INVALID, INVALID, INVALID, INVALID, 801 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 802 803 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 804 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 805 /* [18] */ INVALID, INVALID, INVALID, INVALID, 806 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 807 808 /* [20] */ INVALID, INVALID, INVALID, INVALID, 809 /* [24] */ INVALID, INVALID, INVALID, INVALID, 810 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 811 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 812 813 /* [30] */ INVALID, INVALID, INVALID, INVALID, 814 /* [34] */ INVALID, INVALID, INVALID, INVALID, 815 /* [38] */ INVALID, INVALID, INVALID, INVALID, 816 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 817 818 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 819 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 820 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 821 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 822 823 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 824 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 825 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 826 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 827 828 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 829 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 830 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 831 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 832 833 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 834 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 835 /* [78] */ INVALID, INVALID, INVALID, INVALID, 836 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 837 838 /* [80] */ INVALID, INVALID, INVALID, INVALID, 839 /* [84] */ INVALID, INVALID, INVALID, INVALID, 840 /* [88] */ INVALID, INVALID, INVALID, INVALID, 841 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 842 843 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 844 /* [94] */ INVALID, INVALID, INVALID, INVALID, 845 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 846 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 847 848 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 849 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 850 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 851 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 852 853 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 854 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 855 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 856 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 857 858 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 859 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 860 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 861 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 862 863 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 864 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 865 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 866 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 867 868 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 869 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 870 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 871 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 872 873 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 874 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 875 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 876 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 877 }; 878 879 /* 880 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 881 */ 882 const instable_t dis_opSIMDrepnz[256] = { 883 /* [00] */ INVALID, INVALID, INVALID, INVALID, 884 /* [04] */ INVALID, INVALID, INVALID, INVALID, 885 /* [08] */ INVALID, INVALID, INVALID, INVALID, 886 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 887 888 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID, 889 /* [14] */ INVALID, INVALID, INVALID, INVALID, 890 /* [18] */ INVALID, INVALID, INVALID, INVALID, 891 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 892 893 /* [20] */ INVALID, INVALID, INVALID, INVALID, 894 /* [24] */ INVALID, INVALID, INVALID, INVALID, 895 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 896 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 897 898 /* [30] */ INVALID, INVALID, INVALID, INVALID, 899 /* [34] */ INVALID, INVALID, INVALID, INVALID, 900 /* [38] */ INVALID, INVALID, INVALID, INVALID, 901 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 902 903 /* [40] */ INVALID, INVALID, INVALID, INVALID, 904 /* [44] */ INVALID, INVALID, INVALID, INVALID, 905 /* [48] */ INVALID, INVALID, INVALID, INVALID, 906 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 907 908 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 909 /* [54] */ INVALID, INVALID, INVALID, INVALID, 910 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 911 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 912 913 /* [60] */ INVALID, INVALID, INVALID, INVALID, 914 /* [64] */ INVALID, INVALID, INVALID, INVALID, 915 /* [68] */ INVALID, INVALID, INVALID, INVALID, 916 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 917 918 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 919 /* [74] */ INVALID, INVALID, INVALID, INVALID, 920 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 921 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID, 922 923 /* [80] */ INVALID, INVALID, INVALID, INVALID, 924 /* [84] */ INVALID, INVALID, INVALID, INVALID, 925 /* [88] */ INVALID, INVALID, INVALID, INVALID, 926 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 927 928 /* [90] */ INVALID, INVALID, INVALID, INVALID, 929 /* [94] */ INVALID, INVALID, INVALID, INVALID, 930 /* [98] */ INVALID, INVALID, INVALID, INVALID, 931 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 932 933 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 934 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 935 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 936 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 937 938 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 939 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 940 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 941 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 942 943 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 944 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 945 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 946 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 947 948 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID, 949 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 950 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 951 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 952 953 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 954 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 955 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 956 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 957 958 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID, 959 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 960 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 961 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 962 }; 963 964 const instable_t dis_opAVXF20F[256] = { 965 /* [00] */ INVALID, INVALID, INVALID, INVALID, 966 /* [04] */ INVALID, INVALID, INVALID, INVALID, 967 /* [08] */ INVALID, INVALID, INVALID, INVALID, 968 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 969 970 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 971 /* [14] */ INVALID, INVALID, INVALID, INVALID, 972 /* [18] */ INVALID, INVALID, INVALID, INVALID, 973 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 974 975 /* [20] */ INVALID, INVALID, INVALID, INVALID, 976 /* [24] */ INVALID, INVALID, INVALID, INVALID, 977 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 978 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 979 980 /* [30] */ INVALID, INVALID, INVALID, INVALID, 981 /* [34] */ INVALID, INVALID, INVALID, INVALID, 982 /* [38] */ INVALID, INVALID, INVALID, INVALID, 983 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 984 985 /* [40] */ INVALID, INVALID, INVALID, INVALID, 986 /* [44] */ INVALID, INVALID, INVALID, INVALID, 987 /* [48] */ INVALID, INVALID, INVALID, INVALID, 988 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 989 990 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 991 /* [54] */ INVALID, INVALID, INVALID, INVALID, 992 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 993 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 994 995 /* [60] */ INVALID, INVALID, INVALID, INVALID, 996 /* [64] */ INVALID, INVALID, INVALID, INVALID, 997 /* [68] */ INVALID, INVALID, INVALID, INVALID, 998 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 999 1000 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 1001 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1002 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1003 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 1004 1005 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1006 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1008 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1009 1010 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 1011 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1012 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1013 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1014 1015 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1016 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1017 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1018 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1019 1020 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1021 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1022 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1023 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1024 1025 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 1026 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1028 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1029 1030 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 1031 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1033 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1034 1035 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1036 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 1037 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1038 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1039 1040 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 1041 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1042 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1043 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1044 }; 1045 1046 const instable_t dis_opAVXF20F3A[256] = { 1047 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1048 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1049 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1050 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1051 1052 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1053 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1054 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1055 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1056 1057 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1058 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1059 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1060 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1061 1062 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1063 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1064 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1065 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1066 1067 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1068 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1069 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1070 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1071 1072 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1073 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1074 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1075 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1076 1077 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1078 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1079 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1080 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1081 1082 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1085 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1086 1087 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1090 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1091 1092 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1095 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1096 1097 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1098 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1100 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1101 1102 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1105 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1106 1107 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1108 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1110 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1111 1112 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1115 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1116 1117 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1118 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1119 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1120 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1121 1122 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID, 1123 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1124 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1125 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1126 }; 1127 1128 const instable_t dis_opAVXF20F38[256] = { 1129 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1130 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1131 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1132 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1133 1134 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1135 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1136 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1137 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1138 1139 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1140 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1141 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1142 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1143 1144 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1145 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1146 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1147 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1148 1149 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1150 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1151 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1152 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1153 1154 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1155 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1156 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1157 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1158 1159 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1160 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1161 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1162 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1163 1164 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1165 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1166 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1167 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1168 1169 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1170 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1171 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1172 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1173 1174 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1175 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1176 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1177 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1178 1179 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1180 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1181 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1182 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1183 1184 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1185 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1186 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1187 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1188 1189 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1190 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1191 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1192 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1193 1194 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1195 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1196 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1197 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1198 1199 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1200 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1201 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1202 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1203 1204 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5), 1206 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1207 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1208 }; 1209 1210 const instable_t dis_opAVXF30F38[256] = { 1211 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1212 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1213 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1214 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1215 1216 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1217 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1218 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1219 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1220 1221 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1222 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1223 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1224 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1225 1226 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1227 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1228 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1229 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1230 1231 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1232 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1233 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1234 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1235 1236 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1237 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1238 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1239 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1240 1241 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1242 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1243 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1244 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1245 1246 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1247 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1248 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1250 1251 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1252 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1253 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1254 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1255 1256 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1257 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1258 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1260 1261 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1262 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1263 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1265 1266 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1267 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1268 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1270 1271 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1272 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1273 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1275 1276 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1277 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1278 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1279 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1280 1281 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1282 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1283 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1285 1286 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1287 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5), 1288 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1290 }; 1291 /* 1292 * Decode table for SIMD instructions with the repz (0xf3) prefix. 1293 */ 1294 const instable_t dis_opSIMDrepz[256] = { 1295 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1296 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1297 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1298 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1299 1300 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID, 1301 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID, 1302 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1303 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1304 1305 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1306 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1307 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 1308 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 1309 1310 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1311 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1312 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1313 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1314 1315 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1316 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1317 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1318 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1319 1320 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 1321 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1322 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 1323 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 1324 1325 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1326 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1327 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1328 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 1329 1330 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1331 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1332 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1333 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1334 1335 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1336 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1337 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1338 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1339 1340 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1342 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1343 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1344 1345 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1347 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1348 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1349 1350 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1351 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1352 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1353 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID, 1354 1355 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1356 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1357 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1358 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1359 1360 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1361 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1362 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1363 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1364 1365 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1367 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1368 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1369 1370 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1372 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1373 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1374 }; 1375 1376 const instable_t dis_opAVXF30F[256] = { 1377 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1378 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1379 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1380 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1381 1382 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1383 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1384 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1385 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1386 1387 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1388 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1389 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1390 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1391 1392 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1393 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1394 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1395 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1396 1397 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1398 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1399 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1400 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1401 1402 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1403 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1404 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1405 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1406 1407 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1408 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1409 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1410 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1411 1412 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1413 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1414 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1415 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1416 1417 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1418 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1419 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1420 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1421 1422 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1423 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1424 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1425 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1426 1427 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1428 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1429 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1430 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1431 1432 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1433 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1434 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1435 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1436 1437 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1438 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1439 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1440 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1441 1442 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1443 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1444 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1445 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1446 1447 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1448 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1449 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1450 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1451 1452 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1453 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1454 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1455 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1456 }; 1457 1458 /* 1459 * Table for instructions with an EVEX prefix. 1460 */ 1461 const instable_t dis_opAVX62[256] = { 1462 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1463 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1464 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1465 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1466 1467 /* [10] */ TSd("vmovup",EVEX_MX), TSd("vmovup",EVEX_RX), INVALID, INVALID, 1468 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1469 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1470 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1471 1472 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1473 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1474 /* [28] */ TSd("vmovap",EVEX_MX), TSd("vmovap",EVEX_RX), INVALID, INVALID, 1475 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1476 1477 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1478 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1479 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1480 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1481 1482 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1483 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1484 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1485 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1486 1487 /* [50] */ TNSZ("vpdpbusd",EVEX_RMrX,16),TNSZ("vpdpbusds",EVEX_RMrX,16),TNSZ("vpdpwssd",EVEX_RMrX,16),TNSZ("vpdpwssds",EVEX_RMrX,16), 1488 /* [54] */ TSd("vandp",EVEX_RMrX), TSd("vandnp",EVEX_RMrX), TSd("vorp",EVEX_RMrX), TSd("vxorp",EVEX_RMrX), 1489 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1490 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1491 1492 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1493 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1494 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1495 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_MX), 1496 1497 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1498 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1499 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1500 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdq",EVEX_RX), 1501 1502 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1503 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1504 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1505 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1506 1507 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1508 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1509 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1510 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1511 1512 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1513 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1514 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1515 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1516 1517 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1518 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1519 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1520 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1521 1522 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1523 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1524 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1525 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1526 1527 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1528 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1529 /* [D8] */ INVALID, INVALID, INVALID, TSq("vpand",EVEX_RMrX), 1530 /* [DC] */ INVALID, INVALID, INVALID, TSq("vpandn",EVEX_RMrX), 1531 1532 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1533 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1534 /* [E8] */ INVALID, INVALID, INVALID, TSq("vpor",EVEX_RMrX), 1535 /* [EC] */ INVALID, INVALID, INVALID, TSq("vpxor",EVEX_RMrX), 1536 1537 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1538 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1539 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1540 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1541 }; 1542 1543 /* 1544 * The following two tables are used to encode crc32 and movbe 1545 * since they share the same opcodes. 1546 */ 1547 const instable_t dis_op0F38F0[2] = { 1548 /* [00] */ TNS("crc32b",CRC32), 1549 TS("movbe",MOVBE), 1550 }; 1551 1552 const instable_t dis_op0F38F1[2] = { 1553 /* [00] */ TS("crc32",CRC32), 1554 TS("movbe",MOVBE), 1555 }; 1556 1557 /* 1558 * The following table is used to distinguish between adox and adcx which share 1559 * the same opcodes. 1560 */ 1561 const instable_t dis_op0F38F6[2] = { 1562 /* [00] */ TNS("adcx",ADX), 1563 TNS("adox",ADX), 1564 }; 1565 1566 const instable_t dis_op0F38[256] = { 1567 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1568 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1569 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 1570 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1571 1572 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 1573 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 1574 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1575 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 1576 1577 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 1578 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 1579 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 1580 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1581 1582 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 1583 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 1584 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 1585 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 1586 1587 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 1588 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1589 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1590 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1591 1592 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1593 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1594 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1595 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1596 1597 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1598 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1599 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1600 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1601 1602 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1604 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1605 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1606 1607 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID, 1608 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1609 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1610 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1611 1612 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1613 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1614 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1615 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1616 1617 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1619 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1620 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1621 1622 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1623 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1624 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1625 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1626 1627 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1628 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1629 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16), 1630 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, INVALID, 1631 1632 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1633 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1634 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 1635 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 1636 1637 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1638 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1639 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1640 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1641 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1642 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID, 1643 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1644 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1645 }; 1646 1647 const instable_t dis_opAVX660F38[256] = { 1648 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 1649 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 1650 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 1651 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 1652 1653 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 1654 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16), 1655 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 1656 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 1657 1658 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 1659 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 1660 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 1661 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 1662 1663 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 1664 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16), 1665 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 1666 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 1667 1668 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 1669 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16), 1670 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1671 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1672 1673 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1674 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1675 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID, 1676 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1677 1678 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1679 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1680 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1681 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1682 1683 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1684 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1685 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID, 1686 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1687 1688 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1689 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1690 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1691 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID, 1692 1693 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16), 1694 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 1695 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 1696 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16), 1697 1698 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1699 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16), 1700 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16), 1701 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16), 1702 1703 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1704 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16), 1705 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16), 1706 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16), 1707 1708 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1709 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1710 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1711 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1712 1713 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1714 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1715 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 1716 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 1717 1718 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1719 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1720 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1721 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1722 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 1723 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5), 1724 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1725 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1726 }; 1727 1728 const instable_t dis_op0F3A[256] = { 1729 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1730 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1731 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 1732 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 1733 1734 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1735 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 1736 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1737 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1738 1739 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 1740 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1741 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1742 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1743 1744 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1745 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1746 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1747 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1748 1749 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 1750 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 1751 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1752 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1753 1754 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1755 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1756 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1757 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1758 1759 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 1760 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1761 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1762 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1763 1764 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1765 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1766 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1767 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1768 1769 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1770 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1771 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1772 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1773 1774 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1775 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1776 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1777 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1778 1779 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1780 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1781 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1782 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1783 1784 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1785 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1786 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1787 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1788 1789 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1790 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1791 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1792 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, INVALID, INVALID, 1793 1794 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1795 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1796 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1797 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 1798 1799 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1800 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1801 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1802 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1803 1804 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1805 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1806 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1807 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1808 }; 1809 1810 const instable_t dis_opAVX660F3A[256] = { 1811 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID, 1812 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 1813 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 1814 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 1815 1816 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1817 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 1818 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 1819 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 1820 1821 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 1822 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1823 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1824 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1825 1826 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI), 1827 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1828 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID, 1829 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1830 1831 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 1832 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID, 1833 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 1834 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 1835 1836 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1837 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1838 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1839 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1840 1841 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 1842 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1843 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1844 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1845 1846 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1847 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1848 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1849 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1850 1851 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1852 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1853 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1854 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1855 1856 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1857 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1858 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1859 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1860 1861 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1862 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1863 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1864 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1865 1866 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1867 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1868 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1869 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1870 1871 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1872 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1873 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1874 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1875 1876 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1877 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1878 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1879 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 1880 1881 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1882 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1883 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1884 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1885 1886 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1887 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1888 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1889 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1890 }; 1891 1892 /* 1893 * Decode table for 0x0F0D which uses the first byte of the mod_rm to 1894 * indicate a sub-code. 1895 */ 1896 const instable_t dis_op0F0D[8] = { 1897 /* [00] */ INVALID, TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID, 1898 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1899 }; 1900 1901 /* 1902 * Decode table for 0x0F opcodes 1903 */ 1904 1905 const instable_t dis_op0F[16][16] = { 1906 { 1907 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 1908 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 1909 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 1910 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID, 1911 }, { 1912 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 1913 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 1914 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 1915 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 1916 }, { 1917 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 1918 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 1919 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 1920 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 1921 }, { 1922 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 1923 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID, 1924 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1925 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1926 }, { 1927 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 1928 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 1929 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 1930 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 1931 }, { 1932 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 1933 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 1934 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 1935 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 1936 }, { 1937 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 1938 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 1939 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 1940 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 1941 }, { 1942 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 1943 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 1944 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 1945 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 1946 }, { 1947 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 1948 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 1949 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 1950 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 1951 }, { 1952 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 1953 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 1954 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 1955 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 1956 }, { 1957 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 1958 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 1959 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 1960 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 1961 }, { 1962 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 1963 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 1964 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 1965 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 1966 }, { 1967 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 1968 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 1969 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1970 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1971 }, { 1972 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 1973 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 1974 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 1975 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 1976 }, { 1977 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 1978 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 1979 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 1980 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 1981 }, { 1982 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 1983 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 1984 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 1985 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 1986 } }; 1987 1988 const instable_t dis_opAVX0F[16][16] = { 1989 { 1990 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1991 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1992 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1993 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1994 }, { 1995 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 1996 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 1997 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1998 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1999 }, { 2000 /* [20] */ INVALID, INVALID, INVALID, INVALID, 2001 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2002 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 2003 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 2004 }, { 2005 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2006 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2007 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2008 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2009 }, { 2010 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 2011 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 2012 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 2013 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2014 }, { 2015 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 2016 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 2017 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 2018 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 2019 }, { 2020 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2021 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2022 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2023 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2024 }, { 2025 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2026 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 2027 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2028 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2029 }, { 2030 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2031 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2032 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2033 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2034 }, { 2035 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 2036 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2037 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 2038 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2039 }, { 2040 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2041 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2042 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2043 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 2044 }, { 2045 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2046 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2047 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2048 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2049 }, { 2050 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 2051 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 2052 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2053 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2054 }, { 2055 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2056 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2057 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2058 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2059 }, { 2060 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2061 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2062 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2063 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2064 }, { 2065 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5), 2066 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5), 2067 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2068 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2069 } }; 2070 2071 /* 2072 * Decode table for 0x80 opcodes 2073 */ 2074 2075 const instable_t dis_op80[8] = { 2076 2077 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 2078 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 2079 }; 2080 2081 2082 /* 2083 * Decode table for 0x81 opcodes. 2084 */ 2085 2086 const instable_t dis_op81[8] = { 2087 2088 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 2089 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 2090 }; 2091 2092 2093 /* 2094 * Decode table for 0x82 opcodes. 2095 */ 2096 2097 const instable_t dis_op82[8] = { 2098 2099 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 2100 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 2101 }; 2102 /* 2103 * Decode table for 0x83 opcodes. 2104 */ 2105 2106 const instable_t dis_op83[8] = { 2107 2108 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 2109 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 2110 }; 2111 2112 /* 2113 * Decode table for 0xC0 opcodes. 2114 */ 2115 2116 const instable_t dis_opC0[8] = { 2117 2118 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 2119 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 2120 }; 2121 2122 /* 2123 * Decode table for 0xD0 opcodes. 2124 */ 2125 2126 const instable_t dis_opD0[8] = { 2127 2128 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2129 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2130 }; 2131 2132 /* 2133 * Decode table for 0xC1 opcodes. 2134 * 186 instruction set 2135 */ 2136 2137 const instable_t dis_opC1[8] = { 2138 2139 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 2140 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 2141 }; 2142 2143 /* 2144 * Decode table for 0xD1 opcodes. 2145 */ 2146 2147 const instable_t dis_opD1[8] = { 2148 2149 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2150 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 2151 }; 2152 2153 2154 /* 2155 * Decode table for 0xD2 opcodes. 2156 */ 2157 2158 const instable_t dis_opD2[8] = { 2159 2160 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2161 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2162 }; 2163 /* 2164 * Decode table for 0xD3 opcodes. 2165 */ 2166 2167 const instable_t dis_opD3[8] = { 2168 2169 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2170 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 2171 }; 2172 2173 2174 /* 2175 * Decode table for 0xF6 opcodes. 2176 */ 2177 2178 const instable_t dis_opF6[8] = { 2179 2180 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 2181 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 2182 }; 2183 2184 2185 /* 2186 * Decode table for 0xF7 opcodes. 2187 */ 2188 2189 const instable_t dis_opF7[8] = { 2190 2191 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 2192 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 2193 }; 2194 2195 2196 /* 2197 * Decode table for 0xFE opcodes. 2198 */ 2199 2200 const instable_t dis_opFE[8] = { 2201 2202 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 2203 /* [4] */ INVALID, INVALID, INVALID, INVALID, 2204 }; 2205 /* 2206 * Decode table for 0xFF opcodes. 2207 */ 2208 2209 const instable_t dis_opFF[8] = { 2210 2211 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 2212 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 2213 }; 2214 2215 /* for 287 instructions, which are a mess to decode */ 2216 2217 const instable_t dis_opFP1n2[8][8] = { 2218 { 2219 /* bit pattern: 1101 1xxx MODxx xR/M */ 2220 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 2221 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 2222 }, { 2223 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 2224 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 2225 }, { 2226 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 2227 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 2228 }, { 2229 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M), 2230 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 2231 }, { 2232 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 2233 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 2234 }, { 2235 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 2236 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 2237 }, { 2238 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 2239 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 2240 }, { 2241 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2), 2242 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 2243 } }; 2244 2245 const instable_t dis_opFP3[8][8] = { 2246 { 2247 /* bit pattern: 1101 1xxx 11xx xREG */ 2248 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2249 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2250 }, { 2251 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 2252 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 2253 }, { 2254 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 2255 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 2256 }, { 2257 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 2258 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 2259 }, { 2260 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2261 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2262 }, { 2263 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 2264 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 2265 }, { 2266 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 2267 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 2268 }, { 2269 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 2270 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 2271 } }; 2272 2273 const instable_t dis_opFP4[4][8] = { 2274 { 2275 /* bit pattern: 1101 1001 111x xxxx */ 2276 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 2277 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 2278 }, { 2279 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 2280 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 2281 }, { 2282 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 2283 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 2284 }, { 2285 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 2286 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 2287 } }; 2288 2289 const instable_t dis_opFP5[8] = { 2290 /* bit pattern: 1101 1011 111x xxxx */ 2291 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 2292 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 2293 }; 2294 2295 const instable_t dis_opFP6[8] = { 2296 /* bit pattern: 1101 1011 11yy yxxx */ 2297 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 2298 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 2299 }; 2300 2301 const instable_t dis_opFP7[8] = { 2302 /* bit pattern: 1101 1010 11yy yxxx */ 2303 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 2304 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2305 }; 2306 2307 /* 2308 * Main decode table for the op codes. The first two nibbles 2309 * will be used as an index into the table. If there is a 2310 * a need to further decode an instruction, the array to be 2311 * referenced is indicated with the other two entries being 2312 * empty. 2313 */ 2314 2315 const instable_t dis_distable[16][16] = { 2316 { 2317 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 2318 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 2319 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 2320 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 2321 }, { 2322 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 2323 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 2324 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 2325 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 2326 }, { 2327 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 2328 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 2329 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 2330 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 2331 }, { 2332 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 2333 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 2334 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 2335 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 2336 }, { 2337 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2338 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2339 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2340 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2341 }, { 2342 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2343 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2344 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2345 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2346 }, { 2347 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw), 2348 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 2349 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 2350 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 2351 }, { 2352 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 2353 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 2354 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 2355 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 2356 }, { 2357 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 2358 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 2359 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 2360 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 2361 }, { 2362 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2363 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2364 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 2365 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM), 2366 }, { 2367 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 2368 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 2369 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 2370 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 2371 }, { 2372 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2373 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2374 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2375 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2376 }, { 2377 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 2378 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 2379 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 2380 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 2381 }, { 2382 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 2383 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 2384 2385 /* 287 instructions. Note that although the indirect field */ 2386 /* indicates opFP1n2 for further decoding, this is not necessarily */ 2387 /* the case since the opFP arrays are not partitioned according to key1 */ 2388 /* and key2. opFP1n2 is given only to indicate that we haven't */ 2389 /* finished decoding the instruction. */ 2390 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2391 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2392 }, { 2393 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 2394 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 2395 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 2396 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 2397 }, { 2398 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 2399 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 2400 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 2401 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 2402 } }; 2403 2404 /* END CSTYLED */ 2405 2406 /* 2407 * common functions to decode and disassemble an x86 or amd64 instruction 2408 */ 2409 2410 /* 2411 * These are the individual fields of a REX prefix. Note that a REX 2412 * prefix with none of these set is still needed to: 2413 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 2414 * - access the %sil, %dil, %bpl, %spl registers 2415 */ 2416 #define REX_W 0x08 /* 64 bit operand size when set */ 2417 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 2418 #define REX_X 0x02 /* high order bit extension of SIB index field */ 2419 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 2420 2421 /* 2422 * These are the individual fields of a VEX/EVEX prefix. 2423 */ 2424 #define VEX_R 0x08 /* REX.R in 1's complement form */ 2425 #define VEX_X 0x04 /* REX.X in 1's complement form */ 2426 #define VEX_B 0x02 /* REX.B in 1's complement form */ 2427 2428 /* Additional EVEX prefix definitions */ 2429 #define EVEX_R 0x01 /* REX.R' in 1's complement form */ 2430 #define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */ 2431 #define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */ 2432 2433 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 2434 #define VEX_L 0x04 2435 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */ 2436 #define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */ 2437 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 2438 #define VEX_m 0x1F /* VEX m-mmmm field */ 2439 #define EVEX_m 0x3 /* EVEX mm field */ 2440 #define VEX_v 0x78 /* VEX/EVEX register specifier */ 2441 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 2442 2443 /* VEX m-mmmm field, only used by three bytes prefix */ 2444 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 2445 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 2446 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 2447 2448 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 2449 #define VEX_p_66 0x01 2450 #define VEX_p_F3 0x02 2451 #define VEX_p_F2 0x03 2452 2453 /* 2454 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2455 */ 2456 static int isize[] = {1, 2, 4, 4}; 2457 static int isize64[] = {1, 2, 4, 8}; 2458 2459 /* 2460 * Just a bunch of useful macros. 2461 */ 2462 #define WBIT(x) (x & 0x1) /* to get w bit */ 2463 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2464 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2465 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2466 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2467 2468 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2469 2470 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2471 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2472 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2473 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2474 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2475 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2476 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2477 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2478 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2479 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2480 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ 2481 #define ZMM_OPND 11 /* "value" used to indicate a zmm reg */ 2482 2483 /* 2484 * The AVX2 gather instructions are a bit of a mess. While there's a pattern, 2485 * there's not really a consistent scheme that we can use to know what the mode 2486 * is supposed to be for a given type. Various instructions, like VPGATHERDD, 2487 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have 2488 * some registers match VEX_L, but the VSIB is always XMM. 2489 * 2490 * The simplest way to deal with this is to just define a table based on the 2491 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into 2492 * them. 2493 * 2494 * We further have to subdivide this based on the value of VEX_W and the value 2495 * of VEX_L. The array is constructed to be indexed as: 2496 * [opcode - 0x90][VEX_W][VEX_L]. 2497 */ 2498 /* w = 0, 0x90 */ 2499 typedef struct dis_gather_regs { 2500 uint_t dgr_arg0; /* src reg */ 2501 uint_t dgr_arg1; /* vsib reg */ 2502 uint_t dgr_arg2; /* dst reg */ 2503 char *dgr_suffix; /* suffix to append */ 2504 } dis_gather_regs_t; 2505 2506 static dis_gather_regs_t dis_vgather[4][2][2] = { 2507 { 2508 /* op 0x90, W.0 */ 2509 { 2510 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2511 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2512 }, 2513 /* op 0x90, W.1 */ 2514 { 2515 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2516 { YMM_OPND, XMM_OPND, YMM_OPND, "q" } 2517 } 2518 }, 2519 { 2520 /* op 0x91, W.0 */ 2521 { 2522 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2523 { XMM_OPND, YMM_OPND, XMM_OPND, "d" }, 2524 }, 2525 /* op 0x91, W.1 */ 2526 { 2527 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2528 { YMM_OPND, YMM_OPND, YMM_OPND, "q" }, 2529 } 2530 }, 2531 { 2532 /* op 0x92, W.0 */ 2533 { 2534 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2535 { YMM_OPND, YMM_OPND, YMM_OPND, "s" } 2536 }, 2537 /* op 0x92, W.1 */ 2538 { 2539 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2540 { YMM_OPND, XMM_OPND, YMM_OPND, "d" } 2541 } 2542 }, 2543 { 2544 /* op 0x93, W.0 */ 2545 { 2546 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2547 { XMM_OPND, YMM_OPND, XMM_OPND, "s" } 2548 }, 2549 /* op 0x93, W.1 */ 2550 { 2551 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2552 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2553 } 2554 } 2555 }; 2556 2557 /* 2558 * Get the next byte and separate the op code into the high and low nibbles. 2559 */ 2560 static int 2561 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2562 { 2563 int byte; 2564 2565 /* 2566 * x86 instructions have a maximum length of 15 bytes. Bail out if 2567 * we try to read more. 2568 */ 2569 if (x->d86_len >= 15) 2570 return (x->d86_error = 1); 2571 2572 if (x->d86_error) 2573 return (1); 2574 byte = x->d86_get_byte(x->d86_data); 2575 if (byte < 0) 2576 return (x->d86_error = 1); 2577 x->d86_bytes[x->d86_len++] = byte; 2578 *low = byte & 0xf; /* ----xxxx low 4 bits */ 2579 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 2580 return (0); 2581 } 2582 2583 /* 2584 * Get and decode an SIB (scaled index base) byte 2585 */ 2586 static void 2587 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 2588 { 2589 int byte; 2590 2591 if (x->d86_error) 2592 return; 2593 2594 byte = x->d86_get_byte(x->d86_data); 2595 if (byte < 0) { 2596 x->d86_error = 1; 2597 return; 2598 } 2599 x->d86_bytes[x->d86_len++] = byte; 2600 2601 *base = byte & 0x7; 2602 *index = (byte >> 3) & 0x7; 2603 *ss = (byte >> 6) & 0x3; 2604 } 2605 2606 /* 2607 * Get the byte following the op code and separate it into the 2608 * mode, register, and r/m fields. 2609 */ 2610 static void 2611 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 2612 { 2613 if (x->d86_got_modrm == 0) { 2614 if (x->d86_rmindex == -1) 2615 x->d86_rmindex = x->d86_len; 2616 dtrace_get_SIB(x, mode, reg, r_m); 2617 x->d86_got_modrm = 1; 2618 } 2619 } 2620 2621 /* 2622 * Adjust register selection based on any REX prefix bits present. 2623 */ 2624 /*ARGSUSED*/ 2625 static void 2626 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 2627 { 2628 if (reg != NULL && r_m == NULL) { 2629 if (rex_prefix & REX_B) 2630 *reg += 8; 2631 } else { 2632 if (reg != NULL && (REX_R & rex_prefix) != 0) 2633 *reg += 8; 2634 if (r_m != NULL && (REX_B & rex_prefix) != 0) 2635 *r_m += 8; 2636 } 2637 } 2638 2639 /* 2640 * Adjust register selection based on any VEX prefix bits present. 2641 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 2642 */ 2643 /*ARGSUSED*/ 2644 static void 2645 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 2646 { 2647 if (reg != NULL && r_m == NULL) { 2648 if (!(vex_byte1 & VEX_B)) 2649 *reg += 8; 2650 } else { 2651 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 2652 *reg += 8; 2653 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 2654 *r_m += 8; 2655 } 2656 } 2657 2658 /* 2659 * Adjust the instruction mnemonic with the appropriate suffix. 2660 */ 2661 /* ARGSUSED */ 2662 static void 2663 dtrace_evex_mnem_adjust(dis86_t *x, instable_t *dp, uint_t vex_W, 2664 uint_t evex_byte2) 2665 { 2666 #ifdef DIS_TEXT 2667 /* No adjustments needed for VNNI instructions. */ 2668 if (dp == &dis_opAVX62[0x50] || dp == &dis_opAVX62[0x51] || 2669 dp == &dis_opAVX62[0x52] || dp == &dis_opAVX62[0x53]) { 2670 return; 2671 } 2672 2673 if (dp == &dis_opAVX62[0x7f] || /* vmovdq */ 2674 dp == &dis_opAVX62[0x6f]) { 2675 /* Aligned or Unaligned? */ 2676 if ((evex_byte2 & 0x3) == 0x01) { 2677 (void) strlcat(x->d86_mnem, "a", OPLEN); 2678 (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32", 2679 OPLEN); 2680 } else { 2681 (void) strlcat(x->d86_mnem, "u", OPLEN); 2682 switch (evex_byte2 & 0x81) { 2683 case 0x0: 2684 (void) strlcat(x->d86_mnem, "32", OPLEN); 2685 break; 2686 case 0x1: 2687 (void) strlcat(x->d86_mnem, "8", OPLEN); 2688 break; 2689 case 0x80: 2690 (void) strlcat(x->d86_mnem, "64", OPLEN); 2691 break; 2692 case 0x81: 2693 (void) strlcat(x->d86_mnem, "16", OPLEN); 2694 break; 2695 } 2696 } 2697 } else { 2698 if (dp->it_avxsuf == AVS5Q) { 2699 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 2700 OPLEN); 2701 } else { 2702 (void) strlcat(x->d86_mnem, vex_W != 0 ? "d" : "s", 2703 OPLEN); 2704 } 2705 } 2706 #endif 2707 } 2708 2709 /* 2710 * The following three functions adjust the register selection based on any 2711 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software 2712 * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and 2713 * section 2.6.2 Table 2-31. 2714 */ 2715 static void 2716 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg) 2717 { 2718 if (reg != NULL) { 2719 if ((VEX_R & evex_byte1) == 0) { 2720 *reg += 8; 2721 } 2722 if ((EVEX_R & evex_byte1) == 0) { 2723 *reg += 16; 2724 } 2725 } 2726 } 2727 2728 static void 2729 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m) 2730 { 2731 if (r_m != NULL) { 2732 if ((VEX_B & evex_byte1) == 0) { 2733 *r_m += 8; 2734 } 2735 if ((VEX_X & evex_byte1) == 0) { 2736 *r_m += 16; 2737 } 2738 } 2739 } 2740 2741 /* 2742 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36. 2743 */ 2744 static void 2745 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp) 2746 { 2747 switch (evex_L) { 2748 case 0x0: 2749 *wbitp = XMM_OPND; 2750 break; 2751 case 0x1: 2752 *wbitp = YMM_OPND; 2753 break; 2754 case 0x2: 2755 *wbitp = ZMM_OPND; 2756 break; 2757 } 2758 } 2759 2760 /* 2761 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5. 2762 * This currently only handles a subset of the possibilities. 2763 */ 2764 static void 2765 dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) 2766 { 2767 d86opnd_t *opnd = &x->d86_opnd[opindex]; 2768 2769 if (x->d86_error) 2770 return; 2771 2772 /* Check disp8 bit in the ModR/M byte */ 2773 if ((modrm & 0x80) == 0x80) 2774 return; 2775 2776 /* use evex_L to adjust the value */ 2777 switch (L) { 2778 case 0x0: 2779 opnd->d86_value *= 16; 2780 break; 2781 case 0x1: 2782 opnd->d86_value *= 32; 2783 break; 2784 case 0x2: 2785 opnd->d86_value *= 64; 2786 break; 2787 } 2788 } 2789 2790 /* 2791 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30. 2792 */ 2793 /* ARGSUSED */ 2794 static void 2795 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3) 2796 { 2797 #ifdef DIS_TEXT 2798 char *opnd = x->d86_opnd[tgtop].d86_opnd; 2799 int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; 2800 #endif 2801 if (x->d86_error) 2802 return; 2803 2804 #ifdef DIS_TEXT 2805 if (opmask_reg != 0) { 2806 /* Append the opmask register to operand 1 */ 2807 (void) strlcat(opnd, "{", OPLEN); 2808 (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN); 2809 (void) strlcat(opnd, "}", OPLEN); 2810 } 2811 if ((evex_byte3 & EVEX_ZERO_MASK) != 0) { 2812 /* Append the 'zeroing' modifier to operand 1 */ 2813 (void) strlcat(opnd, "{z}", OPLEN); 2814 } 2815 #endif /* DIS_TEXT */ 2816 } 2817 2818 /* 2819 * Get an immediate operand of the given size, with sign extension. 2820 */ 2821 static void 2822 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 2823 { 2824 int i; 2825 int byte; 2826 int valsize; 2827 2828 if (x->d86_numopnds < opindex + 1) 2829 x->d86_numopnds = opindex + 1; 2830 2831 switch (wbit) { 2832 case BYTE_OPND: 2833 valsize = 1; 2834 break; 2835 case LONG_OPND: 2836 if (x->d86_opnd_size == SIZE16) 2837 valsize = 2; 2838 else if (x->d86_opnd_size == SIZE32) 2839 valsize = 4; 2840 else 2841 valsize = 8; 2842 break; 2843 case MM_OPND: 2844 case XMM_OPND: 2845 case YMM_OPND: 2846 case ZMM_OPND: 2847 case SEG_OPND: 2848 case CONTROL_OPND: 2849 case DEBUG_OPND: 2850 case TEST_OPND: 2851 valsize = size; 2852 break; 2853 case WORD_OPND: 2854 valsize = 2; 2855 break; 2856 } 2857 if (valsize < size) 2858 valsize = size; 2859 2860 if (x->d86_error) 2861 return; 2862 x->d86_opnd[opindex].d86_value = 0; 2863 for (i = 0; i < size; ++i) { 2864 byte = x->d86_get_byte(x->d86_data); 2865 if (byte < 0) { 2866 x->d86_error = 1; 2867 return; 2868 } 2869 x->d86_bytes[x->d86_len++] = byte; 2870 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 2871 } 2872 /* Do sign extension */ 2873 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 2874 for (; i < sizeof (uint64_t); i++) 2875 x->d86_opnd[opindex].d86_value |= 2876 (uint64_t)0xff << (i * 8); 2877 } 2878 #ifdef DIS_TEXT 2879 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 2880 x->d86_opnd[opindex].d86_value_size = valsize; 2881 x->d86_imm_bytes += size; 2882 #endif 2883 } 2884 2885 /* 2886 * Get an ip relative operand of the given size, with sign extension. 2887 */ 2888 static void 2889 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 2890 { 2891 dtrace_imm_opnd(x, wbit, size, opindex); 2892 #ifdef DIS_TEXT 2893 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 2894 #endif 2895 } 2896 2897 /* 2898 * Check to see if there is a segment override prefix pending. 2899 * If so, print it in the current 'operand' location and set 2900 * the override flag back to false. 2901 */ 2902 /*ARGSUSED*/ 2903 static void 2904 dtrace_check_override(dis86_t *x, int opindex) 2905 { 2906 #ifdef DIS_TEXT 2907 if (x->d86_seg_prefix) { 2908 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 2909 x->d86_seg_prefix, PFIXLEN); 2910 } 2911 #endif 2912 x->d86_seg_prefix = NULL; 2913 } 2914 2915 2916 /* 2917 * Process a single instruction Register or Memory operand. 2918 * 2919 * mode = addressing mode from ModRM byte 2920 * r_m = r_m (or reg if mode == 3) field from ModRM byte 2921 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 2922 * o = index of operand that we are processing (0, 1 or 2) 2923 * 2924 * the value of reg or r_m must have already been adjusted for any REX prefix. 2925 */ 2926 /*ARGSUSED*/ 2927 static void 2928 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 2929 { 2930 int have_SIB = 0; /* flag presence of scale-index-byte */ 2931 uint_t ss; /* scale-factor from opcode */ 2932 uint_t index; /* index register number */ 2933 uint_t base; /* base register number */ 2934 int dispsize; /* size of displacement in bytes */ 2935 #ifdef DIS_TEXT 2936 char *opnd = x->d86_opnd[opindex].d86_opnd; 2937 #endif 2938 2939 if (x->d86_numopnds < opindex + 1) 2940 x->d86_numopnds = opindex + 1; 2941 2942 if (x->d86_error) 2943 return; 2944 2945 /* 2946 * first handle a simple register 2947 */ 2948 if (mode == REG_ONLY) { 2949 #ifdef DIS_TEXT 2950 switch (wbit) { 2951 case MM_OPND: 2952 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 2953 break; 2954 case XMM_OPND: 2955 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 2956 break; 2957 case YMM_OPND: 2958 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 2959 break; 2960 case ZMM_OPND: 2961 (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN); 2962 break; 2963 case KOPMASK_OPND: 2964 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); 2965 break; 2966 case SEG_OPND: 2967 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 2968 break; 2969 case CONTROL_OPND: 2970 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 2971 break; 2972 case DEBUG_OPND: 2973 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 2974 break; 2975 case TEST_OPND: 2976 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 2977 break; 2978 case BYTE_OPND: 2979 if (x->d86_rex_prefix == 0) 2980 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 2981 else 2982 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 2983 break; 2984 case WORD_OPND: 2985 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2986 break; 2987 case LONG_OPND: 2988 if (x->d86_opnd_size == SIZE16) 2989 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 2990 else if (x->d86_opnd_size == SIZE32) 2991 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 2992 else 2993 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 2994 break; 2995 } 2996 #endif /* DIS_TEXT */ 2997 return; 2998 } 2999 3000 /* 3001 * if symbolic representation, skip override prefix, if any 3002 */ 3003 dtrace_check_override(x, opindex); 3004 3005 /* 3006 * Handle 16 bit memory references first, since they decode 3007 * the mode values more simply. 3008 * mode 1 is r_m + 8 bit displacement 3009 * mode 2 is r_m + 16 bit displacement 3010 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 3011 */ 3012 if (x->d86_addr_size == SIZE16) { 3013 if ((mode == 0 && r_m == 6) || mode == 2) 3014 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 3015 else if (mode == 1) 3016 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 3017 #ifdef DIS_TEXT 3018 if (mode == 0 && r_m == 6) 3019 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3020 else if (mode == 0) 3021 x->d86_opnd[opindex].d86_mode = MODE_NONE; 3022 else 3023 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3024 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 3025 #endif 3026 return; 3027 } 3028 3029 /* 3030 * 32 and 64 bit addressing modes are more complex since they 3031 * can involve an SIB (scaled index and base) byte to decode. 3032 */ 3033 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8) { 3034 have_SIB = 1; 3035 dtrace_get_SIB(x, &ss, &index, &base); 3036 if (x->d86_error) 3037 return; 3038 if (base != 5 || mode != 0) 3039 if (x->d86_rex_prefix & REX_B) 3040 base += 8; 3041 if (x->d86_rex_prefix & REX_X) 3042 index += 8; 3043 } else { 3044 base = r_m; 3045 } 3046 3047 /* 3048 * Compute the displacement size and get its bytes 3049 */ 3050 dispsize = 0; 3051 3052 if (mode == 1) 3053 dispsize = 1; 3054 else if (mode == 2) 3055 dispsize = 4; 3056 else if ((r_m & 7) == EBP_REGNO || 3057 (have_SIB && (base & 7) == EBP_REGNO)) 3058 dispsize = 4; 3059 3060 if (dispsize > 0) { 3061 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 3062 dispsize, opindex); 3063 if (x->d86_error) 3064 return; 3065 } 3066 3067 #ifdef DIS_TEXT 3068 if (dispsize > 0) 3069 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3070 3071 if (have_SIB == 0) { 3072 if (x->d86_mode == SIZE32) { 3073 if (mode == 0) 3074 (void) strlcat(opnd, dis_addr32_mode0[r_m], 3075 OPLEN); 3076 else 3077 (void) strlcat(opnd, dis_addr32_mode12[r_m], 3078 OPLEN); 3079 } else { 3080 if (mode == 0) { 3081 (void) strlcat(opnd, dis_addr64_mode0[r_m], 3082 OPLEN); 3083 if (r_m == 5) { 3084 x->d86_opnd[opindex].d86_mode = 3085 MODE_RIPREL; 3086 } 3087 } else { 3088 (void) strlcat(opnd, dis_addr64_mode12[r_m], 3089 OPLEN); 3090 } 3091 } 3092 } else { 3093 uint_t need_paren = 0; 3094 char **regs; 3095 char **bregs; 3096 const char *const *sf; 3097 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 3098 regs = (char **)dis_REG32; 3099 else 3100 regs = (char **)dis_REG64; 3101 3102 if (x->d86_vsib != 0) { 3103 if (wbit == YMM_OPND) { /* NOTE this is not addr_size */ 3104 bregs = (char **)dis_YMMREG; 3105 } else if (wbit == XMM_OPND) { 3106 bregs = (char **)dis_XMMREG; 3107 } else { 3108 bregs = (char **)dis_ZMMREG; 3109 } 3110 sf = dis_vscale_factor; 3111 } else { 3112 bregs = regs; 3113 sf = dis_scale_factor; 3114 } 3115 3116 /* 3117 * print the base (if any) 3118 */ 3119 if (base == EBP_REGNO && mode == 0) { 3120 if (index != ESP_REGNO || x->d86_vsib != 0) { 3121 (void) strlcat(opnd, "(", OPLEN); 3122 need_paren = 1; 3123 } 3124 } else { 3125 (void) strlcat(opnd, "(", OPLEN); 3126 (void) strlcat(opnd, regs[base], OPLEN); 3127 need_paren = 1; 3128 } 3129 3130 /* 3131 * print the index (if any) 3132 */ 3133 if (index != ESP_REGNO || x->d86_vsib) { 3134 (void) strlcat(opnd, ",", OPLEN); 3135 (void) strlcat(opnd, bregs[index], OPLEN); 3136 (void) strlcat(opnd, sf[ss], OPLEN); 3137 } else 3138 if (need_paren) 3139 (void) strlcat(opnd, ")", OPLEN); 3140 } 3141 #endif 3142 } 3143 3144 /* 3145 * Operand sequence for standard instruction involving one register 3146 * and one register/memory operand. 3147 * wbit indicates a byte(0) or opnd_size(1) operation 3148 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 3149 */ 3150 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 3151 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3152 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3153 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3154 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 3155 } 3156 3157 /* 3158 * Similar to above, but allows for the two operands to be of different 3159 * classes (ie. wbit). 3160 * wbit is for the r_m operand 3161 * w2 is for the reg operand 3162 */ 3163 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 3164 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3165 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3166 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3167 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 3168 } 3169 3170 /* 3171 * Similar, but for 2 operands plus an immediate. 3172 * vbit indicates direction 3173 * 0 for "opcode imm, r, r_m" or 3174 * 1 for "opcode imm, r_m, r" 3175 */ 3176 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 3177 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3178 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3179 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 3180 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 3181 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3182 } 3183 3184 /* 3185 * Similar, but for 2 operands plus two immediates. 3186 */ 3187 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 3188 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3189 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3190 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3191 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 3192 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3193 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3194 } 3195 3196 /* 3197 * 1 operands plus two immediates. 3198 */ 3199 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 3200 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3201 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3202 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3203 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3204 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3205 } 3206 3207 /* 3208 * Dissassemble a single x86 or amd64 instruction. 3209 * 3210 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 3211 * for interpreting instructions. 3212 * 3213 * returns non-zero for bad opcode 3214 */ 3215 int 3216 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 3217 { 3218 instable_t *dp; /* decode table being used */ 3219 #ifdef DIS_TEXT 3220 uint_t i; 3221 #endif 3222 #ifdef DIS_MEM 3223 uint_t nomem = 0; 3224 #define NOMEM (nomem = 1) 3225 #else 3226 #define NOMEM /* nothing */ 3227 #endif 3228 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 3229 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 3230 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 3231 uint_t w2; /* wbit value for second operand */ 3232 uint_t vbit; 3233 uint_t mode = 0; /* mode value from ModRM byte */ 3234 uint_t reg; /* reg value from ModRM byte */ 3235 uint_t r_m; /* r_m value from ModRM byte */ 3236 3237 uint_t opcode1; /* high nibble of 1st byte */ 3238 uint_t opcode2; /* low nibble of 1st byte */ 3239 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 3240 uint_t opcode4; /* high nibble of 2nd byte */ 3241 uint_t opcode5; /* low nibble of 2nd byte */ 3242 uint_t opcode6; /* high nibble of 3rd byte */ 3243 uint_t opcode7; /* low nibble of 3rd byte */ 3244 uint_t opcode8; /* high nibble of 4th byte */ 3245 uint_t opcode9; /* low nibble of 4th byte */ 3246 uint_t opcode_bytes = 1; 3247 3248 /* 3249 * legacy prefixes come in 5 flavors, you should have only one of each 3250 */ 3251 uint_t opnd_size_prefix = 0; 3252 uint_t addr_size_prefix = 0; 3253 uint_t segment_prefix = 0; 3254 uint_t lock_prefix = 0; 3255 uint_t rep_prefix = 0; 3256 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 3257 3258 /* 3259 * Intel VEX instruction encoding prefix and fields 3260 */ 3261 3262 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 3263 uint_t vex_prefix = 0; 3264 3265 /* 3266 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 3267 * (for 3 bytes prefix) 3268 */ 3269 uint_t vex_byte1 = 0; 3270 3271 /* 3272 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r. 3273 */ 3274 uint_t evex_byte1 = 0; 3275 uint_t evex_byte2 = 0; 3276 uint_t evex_byte3 = 0; 3277 3278 /* 3279 * For 32-bit mode, it should prefetch the next byte to 3280 * distinguish between AVX and les/lds 3281 */ 3282 uint_t vex_prefetch = 0; 3283 3284 uint_t vex_m = 0; 3285 uint_t vex_v = 0; 3286 uint_t vex_p = 0; 3287 uint_t vex_R = 1; 3288 uint_t vex_X = 1; 3289 uint_t vex_B = 1; 3290 uint_t vex_W = 0; 3291 uint_t vex_L = 0; 3292 uint_t evex_L = 0; 3293 uint_t evex_modrm = 0; 3294 dis_gather_regs_t *vreg; 3295 3296 #ifdef DIS_TEXT 3297 /* Instruction name for BLS* family of instructions */ 3298 char *blsinstr; 3299 #endif 3300 3301 size_t off; 3302 3303 instable_t dp_mmx; 3304 3305 x->d86_len = 0; 3306 x->d86_rmindex = -1; 3307 x->d86_error = 0; 3308 #ifdef DIS_TEXT 3309 x->d86_numopnds = 0; 3310 x->d86_seg_prefix = NULL; 3311 x->d86_mnem[0] = 0; 3312 for (i = 0; i < 4; ++i) { 3313 x->d86_opnd[i].d86_opnd[0] = 0; 3314 x->d86_opnd[i].d86_prefix[0] = 0; 3315 x->d86_opnd[i].d86_value_size = 0; 3316 x->d86_opnd[i].d86_value = 0; 3317 x->d86_opnd[i].d86_mode = MODE_NONE; 3318 } 3319 #endif 3320 x->d86_rex_prefix = 0; 3321 x->d86_got_modrm = 0; 3322 x->d86_memsize = 0; 3323 x->d86_vsib = 0; 3324 3325 if (cpu_mode == SIZE16) { 3326 opnd_size = SIZE16; 3327 addr_size = SIZE16; 3328 } else if (cpu_mode == SIZE32) { 3329 opnd_size = SIZE32; 3330 addr_size = SIZE32; 3331 } else { 3332 opnd_size = SIZE32; 3333 addr_size = SIZE64; 3334 } 3335 3336 /* 3337 * Get one opcode byte and check for zero padding that follows 3338 * jump tables. 3339 */ 3340 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3341 goto error; 3342 3343 if (opcode1 == 0 && opcode2 == 0 && 3344 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 3345 #ifdef DIS_TEXT 3346 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 3347 #endif 3348 goto done; 3349 } 3350 3351 /* 3352 * Gather up legacy x86 prefix bytes. 3353 */ 3354 for (;;) { 3355 uint_t *which_prefix = NULL; 3356 3357 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3358 3359 switch (dp->it_adrmode) { 3360 case PREFIX: 3361 which_prefix = &rep_prefix; 3362 break; 3363 case LOCK: 3364 which_prefix = &lock_prefix; 3365 break; 3366 case OVERRIDE: 3367 which_prefix = &segment_prefix; 3368 #ifdef DIS_TEXT 3369 x->d86_seg_prefix = (char *)dp->it_name; 3370 #endif 3371 if (dp->it_invalid64 && cpu_mode == SIZE64) 3372 goto error; 3373 break; 3374 case AM: 3375 which_prefix = &addr_size_prefix; 3376 break; 3377 case DM: 3378 which_prefix = &opnd_size_prefix; 3379 break; 3380 } 3381 if (which_prefix == NULL) 3382 break; 3383 *which_prefix = (opcode1 << 4) | opcode2; 3384 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3385 goto error; 3386 } 3387 3388 /* 3389 * Handle amd64 mode PREFIX values. 3390 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 3391 * We might have a REX prefix (opcodes 0x40-0x4f) 3392 */ 3393 if (cpu_mode == SIZE64) { 3394 if (segment_prefix != 0x64 && segment_prefix != 0x65) 3395 segment_prefix = 0; 3396 3397 if (opcode1 == 0x4) { 3398 rex_prefix = (opcode1 << 4) | opcode2; 3399 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3400 goto error; 3401 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3402 } else if (opcode1 == 0xC && 3403 (opcode2 == 0x4 || opcode2 == 0x5)) { 3404 /* AVX instructions */ 3405 vex_prefix = (opcode1 << 4) | opcode2; 3406 x->d86_rex_prefix = 0x40; 3407 } 3408 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 3409 /* LDS, LES or AVX */ 3410 dtrace_get_modrm(x, &mode, ®, &r_m); 3411 vex_prefetch = 1; 3412 3413 if (mode == REG_ONLY) { 3414 /* AVX */ 3415 vex_prefix = (opcode1 << 4) | opcode2; 3416 x->d86_rex_prefix = 0x40; 3417 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 3418 opcode4 = ((reg << 3) | r_m) & 0x0F; 3419 } 3420 } 3421 3422 /* 3423 * The EVEX prefix and "bound" instruction share the same first byte. 3424 * "bound" is only valid for 32-bit. For 64-bit this byte begins the 3425 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0. 3426 */ 3427 if (opcode1 == 0x6 && opcode2 == 0x2) { 3428 /* 3429 * An EVEX prefix is 4 bytes long, get the next 3 bytes. 3430 */ 3431 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3432 goto error; 3433 3434 if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) { 3435 /* 3436 * Upper bits in 2nd byte == 0 is 'bound' instn. 3437 * 3438 * We've already read the byte so perform the 3439 * equivalent of dtrace_get_modrm on the byte and set 3440 * the flag to indicate we've already read it. 3441 */ 3442 char b = (opcode4 << 4) | opcode5; 3443 3444 r_m = b & 0x7; 3445 reg = (b >> 3) & 0x7; 3446 mode = (b >> 6) & 0x3; 3447 vex_prefetch = 1; 3448 goto not_avx512; 3449 } 3450 3451 /* check for correct bits being 0 in 2nd byte */ 3452 if ((opcode5 & 0xc) != 0) 3453 goto error; 3454 3455 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3456 goto error; 3457 /* check for correct bit being 1 in 3rd byte */ 3458 if ((opcode7 & 0x4) == 0) 3459 goto error; 3460 3461 if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0) 3462 goto error; 3463 3464 /* Reuse opcode1 & opcode2 to get the real opcode now */ 3465 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3466 goto error; 3467 3468 /* 3469 * We only use the high nibble from the 2nd byte of the prefix 3470 * and save it in the low bits of evex_byte1. This is because 3471 * two of the bits in opcode5 are constant 0 (checked above), 3472 * and the other two bits are captured in vex_m. Also, the VEX 3473 * constants we check in evex_byte1 are against the low bits. 3474 */ 3475 evex_byte1 = opcode4; 3476 evex_byte2 = (opcode6 << 4) | opcode7; 3477 evex_byte3 = (opcode8 << 4) | opcode9; 3478 3479 vex_m = opcode5 & EVEX_m; 3480 vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3; 3481 vex_W = (opcode6 & VEX_W) >> 3; 3482 vex_p = opcode7 & VEX_p; 3483 3484 /* Currently only 3 valid values for evex L'L: 00, 01, 10 */ 3485 evex_L = (opcode8 & EVEX_L) >> 1; 3486 3487 dp = (instable_t *)&dis_opAVX62[(opcode1 << 4) | opcode2]; 3488 } 3489 not_avx512: 3490 3491 if (vex_prefix == VEX_2bytes) { 3492 if (!vex_prefetch) { 3493 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3494 goto error; 3495 } 3496 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 3497 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 3498 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 3499 vex_p = opcode4 & VEX_p; 3500 /* 3501 * The vex.x and vex.b bits are not defined in two bytes 3502 * mode vex prefix, their default values are 1 3503 */ 3504 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 3505 3506 if (vex_R == 0) 3507 x->d86_rex_prefix |= REX_R; 3508 3509 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3510 goto error; 3511 3512 switch (vex_p) { 3513 case VEX_p_66: 3514 dp = (instable_t *) 3515 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 3516 break; 3517 case VEX_p_F3: 3518 dp = (instable_t *) 3519 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 3520 break; 3521 case VEX_p_F2: 3522 dp = (instable_t *) 3523 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 3524 break; 3525 default: 3526 dp = (instable_t *) 3527 &dis_opAVX0F[opcode1][opcode2]; 3528 3529 } 3530 3531 } else if (vex_prefix == VEX_3bytes) { 3532 if (!vex_prefetch) { 3533 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3534 goto error; 3535 } 3536 vex_R = (opcode3 & VEX_R) >> 3; 3537 vex_X = (opcode3 & VEX_X) >> 2; 3538 vex_B = (opcode3 & VEX_B) >> 1; 3539 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 3540 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 3541 3542 if (vex_R == 0) 3543 x->d86_rex_prefix |= REX_R; 3544 if (vex_X == 0) 3545 x->d86_rex_prefix |= REX_X; 3546 if (vex_B == 0) 3547 x->d86_rex_prefix |= REX_B; 3548 3549 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 3550 goto error; 3551 vex_W = (opcode5 & VEX_W) >> 3; 3552 vex_L = (opcode6 & VEX_L) >> 2; 3553 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 3554 vex_p = opcode6 & VEX_p; 3555 3556 if (vex_W) 3557 x->d86_rex_prefix |= REX_W; 3558 3559 /* Only these three vex_m values valid; others are reserved */ 3560 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 3561 (vex_m != VEX_m_0F3A)) 3562 goto error; 3563 3564 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3565 goto error; 3566 3567 switch (vex_p) { 3568 case VEX_p_66: 3569 if (vex_m == VEX_m_0F) { 3570 dp = (instable_t *) 3571 &dis_opAVX660F 3572 [(opcode1 << 4) | opcode2]; 3573 } else if (vex_m == VEX_m_0F38) { 3574 dp = (instable_t *) 3575 &dis_opAVX660F38 3576 [(opcode1 << 4) | opcode2]; 3577 } else if (vex_m == VEX_m_0F3A) { 3578 dp = (instable_t *) 3579 &dis_opAVX660F3A 3580 [(opcode1 << 4) | opcode2]; 3581 } else { 3582 goto error; 3583 } 3584 break; 3585 case VEX_p_F3: 3586 if (vex_m == VEX_m_0F) { 3587 dp = (instable_t *) 3588 &dis_opAVXF30F 3589 [(opcode1 << 4) | opcode2]; 3590 } else if (vex_m == VEX_m_0F38) { 3591 dp = (instable_t *) 3592 &dis_opAVXF30F38 3593 [(opcode1 << 4) | opcode2]; 3594 } else { 3595 goto error; 3596 } 3597 break; 3598 case VEX_p_F2: 3599 if (vex_m == VEX_m_0F) { 3600 dp = (instable_t *) 3601 &dis_opAVXF20F 3602 [(opcode1 << 4) | opcode2]; 3603 } else if (vex_m == VEX_m_0F3A) { 3604 dp = (instable_t *) 3605 &dis_opAVXF20F3A 3606 [(opcode1 << 4) | opcode2]; 3607 } else if (vex_m == VEX_m_0F38) { 3608 dp = (instable_t *) 3609 &dis_opAVXF20F38 3610 [(opcode1 << 4) | opcode2]; 3611 } else { 3612 goto error; 3613 } 3614 break; 3615 default: 3616 dp = (instable_t *) 3617 &dis_opAVX0F[opcode1][opcode2]; 3618 3619 } 3620 } 3621 if (vex_prefix) { 3622 if (dp->it_vexwoxmm) { 3623 wbit = LONG_OPND; 3624 } else if (dp->it_vexopmask) { 3625 wbit = KOPMASK_OPND; 3626 } else { 3627 if (vex_L) { 3628 wbit = YMM_OPND; 3629 } else { 3630 wbit = XMM_OPND; 3631 } 3632 } 3633 } 3634 3635 /* 3636 * Deal with selection of operand and address size now. 3637 * Note that the REX.W bit being set causes opnd_size_prefix to be 3638 * ignored. 3639 */ 3640 if (cpu_mode == SIZE64) { 3641 if ((rex_prefix & REX_W) || vex_W) 3642 opnd_size = SIZE64; 3643 else if (opnd_size_prefix) 3644 opnd_size = SIZE16; 3645 3646 if (addr_size_prefix) 3647 addr_size = SIZE32; 3648 } else if (cpu_mode == SIZE32) { 3649 if (opnd_size_prefix) 3650 opnd_size = SIZE16; 3651 if (addr_size_prefix) 3652 addr_size = SIZE16; 3653 } else { 3654 if (opnd_size_prefix) 3655 opnd_size = SIZE32; 3656 if (addr_size_prefix) 3657 addr_size = SIZE32; 3658 } 3659 /* 3660 * The pause instruction - a repz'd nop. This doesn't fit 3661 * with any of the other prefix goop added for SSE, so we'll 3662 * special-case it here. 3663 */ 3664 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 3665 rep_prefix = 0; 3666 dp = (instable_t *)&dis_opPause; 3667 } 3668 3669 /* 3670 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 3671 * byte so we may need to perform a table indirection. 3672 */ 3673 if (dp->it_indirect == (instable_t *)dis_op0F) { 3674 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3675 goto error; 3676 opcode_bytes = 2; 3677 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 3678 uint_t subcode; 3679 3680 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3681 goto error; 3682 opcode_bytes = 3; 3683 subcode = ((opcode6 & 0x3) << 1) | 3684 ((opcode7 & 0x8) >> 3); 3685 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 3686 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 3687 dp = (instable_t *)&dis_op0FC8[0]; 3688 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 3689 opcode_bytes = 3; 3690 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3691 goto error; 3692 if (opnd_size == SIZE16) 3693 opnd_size = SIZE32; 3694 3695 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 3696 #ifdef DIS_TEXT 3697 if (strcmp(dp->it_name, "INVALID") == 0) 3698 goto error; 3699 #endif 3700 switch (dp->it_adrmode) { 3701 case XMMP: 3702 break; 3703 case XMMP_66r: 3704 case XMMPRM_66r: 3705 case XMM3PM_66r: 3706 if (opnd_size_prefix == 0) { 3707 goto error; 3708 } 3709 3710 break; 3711 case XMMP_66o: 3712 if (opnd_size_prefix == 0) { 3713 /* SSSE3 MMX instructions */ 3714 dp_mmx = *dp; 3715 dp = &dp_mmx; 3716 dp->it_adrmode = MMOPM_66o; 3717 #ifdef DIS_MEM 3718 dp->it_size = 8; 3719 #endif 3720 } 3721 break; 3722 default: 3723 goto error; 3724 } 3725 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 3726 opcode_bytes = 3; 3727 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3728 goto error; 3729 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 3730 3731 /* 3732 * Both crc32 and movbe have the same 3rd opcode 3733 * byte of either 0xF0 or 0xF1, so we use another 3734 * indirection to distinguish between the two. 3735 */ 3736 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 3737 dp->it_indirect == (instable_t *)dis_op0F38F1) { 3738 3739 dp = dp->it_indirect; 3740 if (rep_prefix != 0xF2) { 3741 /* It is movbe */ 3742 dp++; 3743 } 3744 } 3745 3746 /* 3747 * The adx family of instructions (adcx and adox) 3748 * continue the classic Intel tradition of abusing 3749 * arbitrary prefixes without actually meaning the 3750 * prefix bit. Therefore, if we find either the 3751 * opnd_size_prefix or rep_prefix we end up zeroing it 3752 * out after making our determination so as to ensure 3753 * that we don't get confused and accidentally print 3754 * repz prefixes and the like on these instructions. 3755 * 3756 * In addition, these instructions are actually much 3757 * closer to AVX instructions in semantics. Importantly, 3758 * they always default to having 32-bit operands. 3759 * However, if the CPU is in 64-bit mode, then and only 3760 * then, does it use REX.w promotes things to 64-bits 3761 * and REX.r allows 64-bit mode to use register r8-r15. 3762 */ 3763 if (dp->it_indirect == (instable_t *)dis_op0F38F6) { 3764 dp = dp->it_indirect; 3765 if (opnd_size_prefix == 0 && 3766 rep_prefix == 0xf3) { 3767 /* It is adox */ 3768 dp++; 3769 } else if (opnd_size_prefix != 0x66 && 3770 rep_prefix != 0) { 3771 /* It isn't adcx */ 3772 goto error; 3773 } 3774 opnd_size_prefix = 0; 3775 rep_prefix = 0; 3776 opnd_size = SIZE32; 3777 if (rex_prefix & REX_W) 3778 opnd_size = SIZE64; 3779 } 3780 3781 #ifdef DIS_TEXT 3782 if (strcmp(dp->it_name, "INVALID") == 0) 3783 goto error; 3784 #endif 3785 switch (dp->it_adrmode) { 3786 case ADX: 3787 case XMM: 3788 break; 3789 case RM_66r: 3790 case XMM_66r: 3791 case XMMM_66r: 3792 if (opnd_size_prefix == 0) { 3793 goto error; 3794 } 3795 break; 3796 case XMM_66o: 3797 if (opnd_size_prefix == 0) { 3798 /* SSSE3 MMX instructions */ 3799 dp_mmx = *dp; 3800 dp = &dp_mmx; 3801 dp->it_adrmode = MM; 3802 #ifdef DIS_MEM 3803 dp->it_size = 8; 3804 #endif 3805 } 3806 break; 3807 case CRC32: 3808 if (rep_prefix != 0xF2) { 3809 goto error; 3810 } 3811 rep_prefix = 0; 3812 break; 3813 case MOVBE: 3814 if (rep_prefix != 0x0) { 3815 goto error; 3816 } 3817 break; 3818 default: 3819 goto error; 3820 } 3821 } else { 3822 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 3823 } 3824 } 3825 3826 /* 3827 * If still not at a TERM decode entry, then a ModRM byte 3828 * exists and its fields further decode the instruction. 3829 */ 3830 x->d86_got_modrm = 0; 3831 if (dp->it_indirect != TERM) { 3832 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 3833 if (x->d86_error) 3834 goto error; 3835 reg = opcode3; 3836 3837 /* 3838 * decode 287 instructions (D8-DF) from opcodeN 3839 */ 3840 if (opcode1 == 0xD && opcode2 >= 0x8) { 3841 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 3842 dp = (instable_t *)&dis_opFP5[r_m]; 3843 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 3844 dp = (instable_t *)&dis_opFP7[opcode3]; 3845 else if (opcode2 == 0xB && mode == 0x3) 3846 dp = (instable_t *)&dis_opFP6[opcode3]; 3847 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 3848 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 3849 else if (mode == 0x3) 3850 dp = (instable_t *) 3851 &dis_opFP3[opcode2 - 8][opcode3]; 3852 else 3853 dp = (instable_t *) 3854 &dis_opFP1n2[opcode2 - 8][opcode3]; 3855 } else { 3856 dp = (instable_t *)dp->it_indirect + opcode3; 3857 } 3858 } 3859 3860 /* 3861 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 3862 * (sign extend 32bit to 64 bit) 3863 */ 3864 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 3865 opcode1 == 0x6 && opcode2 == 0x3) 3866 dp = (instable_t *)&dis_opMOVSLD; 3867 3868 /* 3869 * at this point we should have a correct (or invalid) opcode 3870 */ 3871 if (cpu_mode == SIZE64 && dp->it_invalid64 || 3872 cpu_mode != SIZE64 && dp->it_invalid32) 3873 goto error; 3874 if (dp->it_indirect != TERM) 3875 goto error; 3876 3877 /* 3878 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do 3879 * need to include UNKNOWN below, as we may have instructions that 3880 * actually have a prefix, but don't exist in any other form. 3881 */ 3882 switch (dp->it_adrmode) { 3883 case UNKNOWN: 3884 case MMO: 3885 case MMOIMPL: 3886 case MMO3P: 3887 case MMOM3: 3888 case MMOMS: 3889 case MMOPM: 3890 case MMOPRM: 3891 case MMOS: 3892 case XMMO: 3893 case XMMOM: 3894 case XMMOMS: 3895 case XMMOPM: 3896 case XMMOS: 3897 case XMMOMX: 3898 case XMMOX3: 3899 case XMMOXMM: 3900 /* 3901 * This is horrible. Some SIMD instructions take the 3902 * form 0x0F 0x?? ..., which is easily decoded using the 3903 * existing tables. Other SIMD instructions use various 3904 * prefix bytes to overload existing instructions. For 3905 * Example, addps is F0, 58, whereas addss is F3 (repz), 3906 * F0, 58. Presumably someone got a raise for this. 3907 * 3908 * If we see one of the instructions which can be 3909 * modified in this way (if we've got one of the SIMDO* 3910 * address modes), we'll check to see if the last prefix 3911 * was a repz. If it was, we strip the prefix from the 3912 * mnemonic, and we indirect using the dis_opSIMDrepz 3913 * table. 3914 */ 3915 3916 /* 3917 * Calculate our offset in dis_op0F 3918 */ 3919 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 3920 goto error; 3921 3922 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 3923 sizeof (instable_t); 3924 3925 /* 3926 * Rewrite if this instruction used one of the magic prefixes. 3927 */ 3928 if (rep_prefix) { 3929 if (rep_prefix == 0xf2) 3930 dp = (instable_t *)&dis_opSIMDrepnz[off]; 3931 else 3932 dp = (instable_t *)&dis_opSIMDrepz[off]; 3933 rep_prefix = 0; 3934 } else if (opnd_size_prefix) { 3935 dp = (instable_t *)&dis_opSIMDdata16[off]; 3936 opnd_size_prefix = 0; 3937 if (opnd_size == SIZE16) 3938 opnd_size = SIZE32; 3939 } 3940 break; 3941 3942 case MG9: 3943 /* 3944 * More horribleness: the group 9 (0xF0 0xC7) instructions are 3945 * allowed an optional prefix of 0x66 or 0xF3. This is similar 3946 * to the SIMD business described above, but with a different 3947 * addressing mode (and an indirect table), so we deal with it 3948 * separately (if similarly). 3949 * 3950 * Intel further complicated this with the release of Ivy Bridge 3951 * where they overloaded these instructions based on the ModR/M 3952 * bytes. The VMX instructions have a mode of 0 since they are 3953 * memory instructions but rdrand instructions have a mode of 3954 * 0b11 (REG_ONLY) because they only operate on registers. While 3955 * there are different prefix formats, for now it is sufficient 3956 * to use a single different table. 3957 */ 3958 3959 /* 3960 * Calculate our offset in dis_op0FC7 (the group 9 table) 3961 */ 3962 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 3963 goto error; 3964 3965 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 3966 sizeof (instable_t); 3967 3968 /* 3969 * If we have a mode of 0b11 then we have to rewrite this. 3970 */ 3971 dtrace_get_modrm(x, &mode, ®, &r_m); 3972 if (mode == REG_ONLY) { 3973 dp = (instable_t *)&dis_op0FC7m3[off]; 3974 break; 3975 } 3976 3977 /* 3978 * Rewrite if this instruction used one of the magic prefixes. 3979 */ 3980 if (rep_prefix) { 3981 if (rep_prefix == 0xf3) 3982 dp = (instable_t *)&dis_opF30FC7[off]; 3983 else 3984 goto error; 3985 rep_prefix = 0; 3986 } else if (opnd_size_prefix) { 3987 dp = (instable_t *)&dis_op660FC7[off]; 3988 opnd_size_prefix = 0; 3989 if (opnd_size == SIZE16) 3990 opnd_size = SIZE32; 3991 } else if (reg == 4 || reg == 5) { 3992 /* 3993 * We have xsavec (4) or xsaves (5), so rewrite. 3994 */ 3995 dp = (instable_t *)&dis_op0FC7[reg]; 3996 break; 3997 } 3998 break; 3999 4000 4001 case MMOSH: 4002 /* 4003 * As with the "normal" SIMD instructions, the MMX 4004 * shuffle instructions are overloaded. These 4005 * instructions, however, are special in that they use 4006 * an extra byte, and thus an extra table. As of this 4007 * writing, they only use the opnd_size prefix. 4008 */ 4009 4010 /* 4011 * Calculate our offset in dis_op0F7123 4012 */ 4013 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 4014 sizeof (dis_op0F7123)) 4015 goto error; 4016 4017 if (opnd_size_prefix) { 4018 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 4019 sizeof (instable_t); 4020 dp = (instable_t *)&dis_opSIMD7123[off]; 4021 opnd_size_prefix = 0; 4022 if (opnd_size == SIZE16) 4023 opnd_size = SIZE32; 4024 } 4025 break; 4026 case MRw: 4027 if (rep_prefix) { 4028 if (rep_prefix == 0xf3) { 4029 4030 /* 4031 * Calculate our offset in dis_op0F 4032 */ 4033 if ((uintptr_t)dp - (uintptr_t)dis_op0F > 4034 sizeof (dis_op0F)) 4035 goto error; 4036 4037 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4038 sizeof (instable_t); 4039 4040 dp = (instable_t *)&dis_opSIMDrepz[off]; 4041 rep_prefix = 0; 4042 } else { 4043 goto error; 4044 } 4045 } 4046 break; 4047 case FSGS: 4048 if (rep_prefix == 0xf3) { 4049 if ((uintptr_t)dp - (uintptr_t)dis_op0FAE > 4050 sizeof (dis_op0FAE)) 4051 goto error; 4052 4053 off = ((uintptr_t)dp - (uintptr_t)dis_op0FAE) / 4054 sizeof (instable_t); 4055 dp = (instable_t *)&dis_opF30FAE[off]; 4056 rep_prefix = 0; 4057 } else if (rep_prefix != 0x00) { 4058 goto error; 4059 } 4060 } 4061 4062 /* 4063 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 4064 */ 4065 if (cpu_mode == SIZE64) 4066 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 4067 opnd_size = SIZE64; 4068 4069 #ifdef DIS_TEXT 4070 /* 4071 * At this point most instructions can format the opcode mnemonic 4072 * including the prefixes. 4073 */ 4074 if (lock_prefix) 4075 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 4076 4077 if (rep_prefix == 0xf2) 4078 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 4079 else if (rep_prefix == 0xf3) 4080 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 4081 4082 if (cpu_mode == SIZE64 && addr_size_prefix) 4083 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 4084 4085 if (dp->it_adrmode != CBW && 4086 dp->it_adrmode != CWD && 4087 dp->it_adrmode != XMMSFNC) { 4088 if (strcmp(dp->it_name, "INVALID") == 0) 4089 goto error; 4090 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 4091 if (dp->it_avxsuf == AVS2 && dp->it_suffix) { 4092 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 4093 OPLEN); 4094 } else if (dp->it_vexopmask && dp->it_suffix) { 4095 /* opmask instructions */ 4096 4097 if (opcode1 == 4 && opcode2 == 0xb) { 4098 /* It's a kunpck. */ 4099 if (vex_prefix == VEX_2bytes) { 4100 (void) strlcat(x->d86_mnem, 4101 vex_p == 0 ? "wd" : "bw", OPLEN); 4102 } else { 4103 /* vex_prefix == VEX_3bytes */ 4104 (void) strlcat(x->d86_mnem, 4105 "dq", OPLEN); 4106 } 4107 } else if (opcode1 == 3) { 4108 /* It's a kshift[l|r]. */ 4109 if (vex_W == 0) { 4110 (void) strlcat(x->d86_mnem, 4111 opcode2 == 2 || 4112 opcode2 == 0 ? 4113 "b" : "d", OPLEN); 4114 } else { 4115 /* W == 1 */ 4116 (void) strlcat(x->d86_mnem, 4117 opcode2 == 3 || opcode2 == 1 ? 4118 "q" : "w", OPLEN); 4119 } 4120 } else { 4121 /* if (vex_prefix == VEX_2bytes) { */ 4122 if ((cpu_mode == SIZE64 && opnd_size == 2) || 4123 vex_prefix == VEX_2bytes) { 4124 (void) strlcat(x->d86_mnem, 4125 vex_p == 0 ? "w" : 4126 vex_p == 1 ? "b" : "d", 4127 OPLEN); 4128 } else { 4129 /* vex_prefix == VEX_3bytes */ 4130 (void) strlcat(x->d86_mnem, 4131 vex_p == 1 ? "d" : "q", OPLEN); 4132 } 4133 } 4134 } else if (dp->it_suffix) { 4135 char *types[] = {"", "w", "l", "q"}; 4136 if (opcode_bytes == 2 && opcode4 == 4) { 4137 /* It's a cmovx.yy. Replace the suffix x */ 4138 for (i = 5; i < OPLEN; i++) { 4139 if (x->d86_mnem[i] == '.') 4140 break; 4141 } 4142 x->d86_mnem[i - 1] = *types[opnd_size]; 4143 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 4144 ((opcode6 == 1 && opcode7 == 6) || 4145 (opcode6 == 2 && opcode7 == 2))) { 4146 /* 4147 * To handle PINSRD and PEXTRD 4148 */ 4149 (void) strlcat(x->d86_mnem, "d", OPLEN); 4150 } else if (dp != &dis_distable[0x6][0x2]) { 4151 /* bound instructions (0x62) have no suffix */ 4152 (void) strlcat(x->d86_mnem, types[opnd_size], 4153 OPLEN); 4154 } 4155 } 4156 } 4157 #endif 4158 4159 /* 4160 * Process operands based on the addressing modes. 4161 */ 4162 x->d86_mode = cpu_mode; 4163 /* 4164 * In vex mode the rex_prefix has no meaning 4165 */ 4166 if (!vex_prefix) 4167 x->d86_rex_prefix = rex_prefix; 4168 x->d86_opnd_size = opnd_size; 4169 x->d86_addr_size = addr_size; 4170 vbit = 0; /* initialize for mem/reg -> reg */ 4171 switch (dp->it_adrmode) { 4172 /* 4173 * amd64 instruction to sign extend 32 bit reg/mem operands 4174 * into 64 bit register values 4175 */ 4176 case MOVSXZ: 4177 #ifdef DIS_TEXT 4178 if (rex_prefix == 0) 4179 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 4180 #endif 4181 dtrace_get_modrm(x, &mode, ®, &r_m); 4182 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4183 x->d86_opnd_size = SIZE64; 4184 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4185 x->d86_opnd_size = opnd_size = SIZE32; 4186 wbit = LONG_OPND; 4187 dtrace_get_operand(x, mode, r_m, wbit, 0); 4188 break; 4189 4190 /* 4191 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 4192 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 4193 * wbit lives in 2nd byte, note that operands 4194 * are different sized 4195 */ 4196 case MOVZ: 4197 if (rex_prefix & REX_W) { 4198 /* target register size = 64 bit */ 4199 x->d86_mnem[5] = 'q'; 4200 } 4201 dtrace_get_modrm(x, &mode, ®, &r_m); 4202 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4203 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4204 x->d86_opnd_size = opnd_size = SIZE16; 4205 wbit = WBIT(opcode5); 4206 dtrace_get_operand(x, mode, r_m, wbit, 0); 4207 break; 4208 case CRC32: 4209 opnd_size = SIZE32; 4210 if (rex_prefix & REX_W) 4211 opnd_size = SIZE64; 4212 x->d86_opnd_size = opnd_size; 4213 4214 dtrace_get_modrm(x, &mode, ®, &r_m); 4215 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4216 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4217 wbit = WBIT(opcode7); 4218 if (opnd_size_prefix) 4219 x->d86_opnd_size = opnd_size = SIZE16; 4220 dtrace_get_operand(x, mode, r_m, wbit, 0); 4221 break; 4222 case MOVBE: 4223 opnd_size = SIZE32; 4224 if (rex_prefix & REX_W) 4225 opnd_size = SIZE64; 4226 x->d86_opnd_size = opnd_size; 4227 4228 dtrace_get_modrm(x, &mode, ®, &r_m); 4229 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4230 wbit = WBIT(opcode7); 4231 if (opnd_size_prefix) 4232 x->d86_opnd_size = opnd_size = SIZE16; 4233 if (wbit) { 4234 /* reg -> mem */ 4235 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4236 dtrace_get_operand(x, mode, r_m, wbit, 1); 4237 } else { 4238 /* mem -> reg */ 4239 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4240 dtrace_get_operand(x, mode, r_m, wbit, 0); 4241 } 4242 break; 4243 4244 /* 4245 * imul instruction, with either 8-bit or longer immediate 4246 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 4247 */ 4248 case IMUL: 4249 wbit = LONG_OPND; 4250 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 4251 OPSIZE(opnd_size, opcode2 == 0x9), 1); 4252 break; 4253 4254 /* memory or register operand to register, with 'w' bit */ 4255 case MRw: 4256 case ADX: 4257 wbit = WBIT(opcode2); 4258 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4259 break; 4260 4261 /* register to memory or register operand, with 'w' bit */ 4262 /* arpl happens to fit here also because it is odd */ 4263 case RMw: 4264 if (opcode_bytes == 2) 4265 wbit = WBIT(opcode5); 4266 else 4267 wbit = WBIT(opcode2); 4268 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4269 break; 4270 4271 /* xaddb instruction */ 4272 case XADDB: 4273 wbit = 0; 4274 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4275 break; 4276 4277 /* MMX register to memory or register operand */ 4278 case MMS: 4279 case MMOS: 4280 #ifdef DIS_TEXT 4281 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4282 #else 4283 wbit = LONG_OPND; 4284 #endif 4285 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4286 break; 4287 4288 /* MMX register to memory */ 4289 case MMOMS: 4290 dtrace_get_modrm(x, &mode, ®, &r_m); 4291 if (mode == REG_ONLY) 4292 goto error; 4293 wbit = MM_OPND; 4294 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4295 break; 4296 4297 /* Double shift. Has immediate operand specifying the shift. */ 4298 case DSHIFT: 4299 wbit = LONG_OPND; 4300 dtrace_get_modrm(x, &mode, ®, &r_m); 4301 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4302 dtrace_get_operand(x, mode, r_m, wbit, 2); 4303 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4304 dtrace_imm_opnd(x, wbit, 1, 0); 4305 break; 4306 4307 /* 4308 * Double shift. With no immediate operand, specifies using %cl. 4309 */ 4310 case DSHIFTcl: 4311 wbit = LONG_OPND; 4312 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4313 break; 4314 4315 /* immediate to memory or register operand */ 4316 case IMlw: 4317 wbit = WBIT(opcode2); 4318 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4319 dtrace_get_operand(x, mode, r_m, wbit, 1); 4320 /* 4321 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 4322 */ 4323 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 4324 break; 4325 4326 /* immediate to memory or register operand with the */ 4327 /* 'w' bit present */ 4328 case IMw: 4329 wbit = WBIT(opcode2); 4330 dtrace_get_modrm(x, &mode, ®, &r_m); 4331 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4332 dtrace_get_operand(x, mode, r_m, wbit, 1); 4333 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4334 break; 4335 4336 /* immediate to register with register in low 3 bits */ 4337 /* of op code */ 4338 case IR: 4339 /* w-bit here (with regs) is bit 3 */ 4340 wbit = opcode2 >>3 & 0x1; 4341 reg = REGNO(opcode2); 4342 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4343 mode = REG_ONLY; 4344 r_m = reg; 4345 dtrace_get_operand(x, mode, r_m, wbit, 1); 4346 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 4347 break; 4348 4349 /* MMX immediate shift of register */ 4350 case MMSH: 4351 case MMOSH: 4352 wbit = MM_OPND; 4353 goto mm_shift; /* in next case */ 4354 4355 /* SIMD immediate shift of register */ 4356 case XMMSH: 4357 wbit = XMM_OPND; 4358 mm_shift: 4359 reg = REGNO(opcode7); 4360 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4361 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4362 dtrace_imm_opnd(x, wbit, 1, 0); 4363 NOMEM; 4364 break; 4365 4366 /* accumulator to memory operand */ 4367 case AO: 4368 vbit = 1; 4369 /*FALLTHROUGH*/ 4370 4371 /* memory operand to accumulator */ 4372 case OA: 4373 wbit = WBIT(opcode2); 4374 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 4375 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 4376 #ifdef DIS_TEXT 4377 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 4378 #endif 4379 break; 4380 4381 4382 /* segment register to memory or register operand */ 4383 case SM: 4384 vbit = 1; 4385 /*FALLTHROUGH*/ 4386 4387 /* memory or register operand to segment register */ 4388 case MS: 4389 dtrace_get_modrm(x, &mode, ®, &r_m); 4390 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4391 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 4392 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 4393 break; 4394 4395 /* 4396 * rotate or shift instructions, which may shift by 1 or 4397 * consult the cl register, depending on the 'v' bit 4398 */ 4399 case Mv: 4400 vbit = VBIT(opcode2); 4401 wbit = WBIT(opcode2); 4402 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4403 dtrace_get_operand(x, mode, r_m, wbit, 1); 4404 #ifdef DIS_TEXT 4405 if (vbit) { 4406 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 4407 } else { 4408 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4409 x->d86_opnd[0].d86_value_size = 1; 4410 x->d86_opnd[0].d86_value = 1; 4411 } 4412 #endif 4413 break; 4414 /* 4415 * immediate rotate or shift instructions 4416 */ 4417 case MvI: 4418 wbit = WBIT(opcode2); 4419 normal_imm_mem: 4420 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4421 dtrace_get_operand(x, mode, r_m, wbit, 1); 4422 dtrace_imm_opnd(x, wbit, 1, 0); 4423 break; 4424 4425 /* bit test instructions */ 4426 case MIb: 4427 wbit = LONG_OPND; 4428 goto normal_imm_mem; 4429 4430 /* single memory or register operand with 'w' bit present */ 4431 case Mw: 4432 wbit = WBIT(opcode2); 4433 just_mem: 4434 dtrace_get_modrm(x, &mode, ®, &r_m); 4435 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4436 dtrace_get_operand(x, mode, r_m, wbit, 0); 4437 break; 4438 4439 case SWAPGS_RDTSCP: 4440 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 4441 #ifdef DIS_TEXT 4442 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 4443 #endif 4444 NOMEM; 4445 break; 4446 } else if (mode == 3 && r_m == 1) { 4447 #ifdef DIS_TEXT 4448 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 4449 #endif 4450 NOMEM; 4451 break; 4452 } else if (mode == 3 && r_m == 2) { 4453 #ifdef DIS_TEXT 4454 (void) strncpy(x->d86_mnem, "monitorx", OPLEN); 4455 #endif 4456 NOMEM; 4457 break; 4458 } else if (mode == 3 && r_m == 3) { 4459 #ifdef DIS_TEXT 4460 (void) strncpy(x->d86_mnem, "mwaitx", OPLEN); 4461 #endif 4462 NOMEM; 4463 break; 4464 } else if (mode == 3 && r_m == 4) { 4465 #ifdef DIS_TEXT 4466 (void) strncpy(x->d86_mnem, "clzero", OPLEN); 4467 #endif 4468 NOMEM; 4469 break; 4470 } 4471 4472 /*FALLTHROUGH*/ 4473 4474 /* prefetch instruction - memory operand, but no memory acess */ 4475 case PREF: 4476 NOMEM; 4477 /*FALLTHROUGH*/ 4478 4479 /* single memory or register operand */ 4480 case M: 4481 case MG9: 4482 wbit = LONG_OPND; 4483 goto just_mem; 4484 4485 /* single memory or register byte operand */ 4486 case Mb: 4487 wbit = BYTE_OPND; 4488 goto just_mem; 4489 4490 case VMx: 4491 if (mode == 3) { 4492 #ifdef DIS_TEXT 4493 char *vminstr; 4494 4495 switch (r_m) { 4496 case 1: 4497 vminstr = "vmcall"; 4498 break; 4499 case 2: 4500 vminstr = "vmlaunch"; 4501 break; 4502 case 3: 4503 vminstr = "vmresume"; 4504 break; 4505 case 4: 4506 vminstr = "vmxoff"; 4507 break; 4508 default: 4509 goto error; 4510 } 4511 4512 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 4513 #else 4514 if (r_m < 1 || r_m > 4) 4515 goto error; 4516 #endif 4517 4518 NOMEM; 4519 break; 4520 } 4521 /*FALLTHROUGH*/ 4522 case SVM: 4523 if (mode == 3) { 4524 #if DIS_TEXT 4525 char *vinstr; 4526 4527 switch (r_m) { 4528 case 0: 4529 vinstr = "vmrun"; 4530 break; 4531 case 1: 4532 vinstr = "vmmcall"; 4533 break; 4534 case 2: 4535 vinstr = "vmload"; 4536 break; 4537 case 3: 4538 vinstr = "vmsave"; 4539 break; 4540 case 4: 4541 vinstr = "stgi"; 4542 break; 4543 case 5: 4544 vinstr = "clgi"; 4545 break; 4546 case 6: 4547 vinstr = "skinit"; 4548 break; 4549 case 7: 4550 vinstr = "invlpga"; 4551 break; 4552 } 4553 4554 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 4555 #endif 4556 NOMEM; 4557 break; 4558 } 4559 /*FALLTHROUGH*/ 4560 case MONITOR_MWAIT: 4561 if (mode == 3) { 4562 if (r_m == 0) { 4563 #ifdef DIS_TEXT 4564 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 4565 #endif 4566 NOMEM; 4567 break; 4568 } else if (r_m == 1) { 4569 #ifdef DIS_TEXT 4570 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 4571 #endif 4572 NOMEM; 4573 break; 4574 } else if (r_m == 2) { 4575 #ifdef DIS_TEXT 4576 (void) strncpy(x->d86_mnem, "clac", OPLEN); 4577 #endif 4578 NOMEM; 4579 break; 4580 } else if (r_m == 3) { 4581 #ifdef DIS_TEXT 4582 (void) strncpy(x->d86_mnem, "stac", OPLEN); 4583 #endif 4584 NOMEM; 4585 break; 4586 } else { 4587 goto error; 4588 } 4589 } 4590 /*FALLTHROUGH*/ 4591 case XGETBV_XSETBV: 4592 if (mode == 3) { 4593 if (r_m == 0) { 4594 #ifdef DIS_TEXT 4595 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 4596 #endif 4597 NOMEM; 4598 break; 4599 } else if (r_m == 1) { 4600 #ifdef DIS_TEXT 4601 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 4602 #endif 4603 NOMEM; 4604 break; 4605 } else { 4606 goto error; 4607 } 4608 4609 } 4610 /*FALLTHROUGH*/ 4611 case MO: 4612 /* Similar to M, but only memory (no direct registers) */ 4613 wbit = LONG_OPND; 4614 dtrace_get_modrm(x, &mode, ®, &r_m); 4615 if (mode == 3) 4616 goto error; 4617 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4618 dtrace_get_operand(x, mode, r_m, wbit, 0); 4619 break; 4620 4621 /* move special register to register or reverse if vbit */ 4622 case SREG: 4623 switch (opcode5) { 4624 4625 case 2: 4626 vbit = 1; 4627 /*FALLTHROUGH*/ 4628 case 0: 4629 wbit = CONTROL_OPND; 4630 break; 4631 4632 case 3: 4633 vbit = 1; 4634 /*FALLTHROUGH*/ 4635 case 1: 4636 wbit = DEBUG_OPND; 4637 break; 4638 4639 case 6: 4640 vbit = 1; 4641 /*FALLTHROUGH*/ 4642 case 4: 4643 wbit = TEST_OPND; 4644 break; 4645 4646 } 4647 dtrace_get_modrm(x, &mode, ®, &r_m); 4648 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4649 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 4650 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 4651 NOMEM; 4652 break; 4653 4654 /* 4655 * single register operand with register in the low 3 4656 * bits of op code 4657 */ 4658 case R: 4659 if (opcode_bytes == 2) 4660 reg = REGNO(opcode5); 4661 else 4662 reg = REGNO(opcode2); 4663 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4664 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4665 NOMEM; 4666 break; 4667 4668 /* 4669 * register to accumulator with register in the low 3 4670 * bits of op code, xchg instructions 4671 */ 4672 case RA: 4673 NOMEM; 4674 reg = REGNO(opcode2); 4675 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4676 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4677 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 4678 break; 4679 4680 /* 4681 * single segment register operand, with register in 4682 * bits 3-4 of op code byte 4683 */ 4684 case SEG: 4685 NOMEM; 4686 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 4687 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4688 break; 4689 4690 /* 4691 * single segment register operand, with register in 4692 * bits 3-5 of op code 4693 */ 4694 case LSEG: 4695 NOMEM; 4696 /* long seg reg from opcode */ 4697 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 4698 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 4699 break; 4700 4701 /* memory or register operand to register */ 4702 case MR: 4703 if (vex_prefetch) 4704 x->d86_got_modrm = 1; 4705 wbit = LONG_OPND; 4706 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4707 break; 4708 4709 case RM: 4710 case RM_66r: 4711 if (vex_prefetch) 4712 x->d86_got_modrm = 1; 4713 wbit = LONG_OPND; 4714 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4715 break; 4716 4717 /* MMX/SIMD-Int memory or mm reg to mm reg */ 4718 case MM: 4719 case MMO: 4720 #ifdef DIS_TEXT 4721 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4722 #else 4723 wbit = LONG_OPND; 4724 #endif 4725 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4726 break; 4727 4728 case MMOIMPL: 4729 #ifdef DIS_TEXT 4730 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4731 #else 4732 wbit = LONG_OPND; 4733 #endif 4734 dtrace_get_modrm(x, &mode, ®, &r_m); 4735 if (mode != REG_ONLY) 4736 goto error; 4737 4738 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4739 dtrace_get_operand(x, mode, r_m, wbit, 0); 4740 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 4741 mode = 0; /* change for memory access size... */ 4742 break; 4743 4744 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 4745 case MMO3P: 4746 wbit = MM_OPND; 4747 goto xmm3p; 4748 case XMM3P: 4749 wbit = XMM_OPND; 4750 xmm3p: 4751 dtrace_get_modrm(x, &mode, ®, &r_m); 4752 if (mode != REG_ONLY) 4753 goto error; 4754 4755 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 4756 1); 4757 NOMEM; 4758 break; 4759 4760 case XMM3PM_66r: 4761 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 4762 1, 0); 4763 break; 4764 4765 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 4766 case MMOPRM: 4767 wbit = LONG_OPND; 4768 w2 = MM_OPND; 4769 goto xmmprm; 4770 case XMMPRM: 4771 case XMMPRM_66r: 4772 wbit = LONG_OPND; 4773 w2 = XMM_OPND; 4774 xmmprm: 4775 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 4776 break; 4777 4778 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 4779 case MMOPM: 4780 case MMOPM_66o: 4781 wbit = w2 = MM_OPND; 4782 goto xmmprm; 4783 4784 /* MMX/SIMD-Int mm reg to r32 */ 4785 case MMOM3: 4786 NOMEM; 4787 dtrace_get_modrm(x, &mode, ®, &r_m); 4788 if (mode != REG_ONLY) 4789 goto error; 4790 wbit = MM_OPND; 4791 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4792 break; 4793 4794 /* SIMD memory or xmm reg operand to xmm reg */ 4795 case XMM: 4796 case XMM_66o: 4797 case XMM_66r: 4798 case XMMO: 4799 case XMMXIMPL: 4800 wbit = XMM_OPND; 4801 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4802 4803 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 4804 goto error; 4805 4806 #ifdef DIS_TEXT 4807 /* 4808 * movlps and movhlps share opcodes. They differ in the 4809 * addressing modes allowed for their operands. 4810 * movhps and movlhps behave similarly. 4811 */ 4812 if (mode == REG_ONLY) { 4813 if (strcmp(dp->it_name, "movlps") == 0) 4814 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 4815 else if (strcmp(dp->it_name, "movhps") == 0) 4816 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4817 } 4818 #endif 4819 if (dp->it_adrmode == XMMXIMPL) 4820 mode = 0; /* change for memory access size... */ 4821 break; 4822 4823 /* SIMD xmm reg to memory or xmm reg */ 4824 case XMMS: 4825 case XMMOS: 4826 case XMMMS: 4827 case XMMOMS: 4828 dtrace_get_modrm(x, &mode, ®, &r_m); 4829 #ifdef DIS_TEXT 4830 if ((strcmp(dp->it_name, "movlps") == 0 || 4831 strcmp(dp->it_name, "movhps") == 0 || 4832 strcmp(dp->it_name, "movntps") == 0) && 4833 mode == REG_ONLY) 4834 goto error; 4835 #endif 4836 wbit = XMM_OPND; 4837 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4838 break; 4839 4840 /* SIMD memory to xmm reg */ 4841 case XMMM: 4842 case XMMM_66r: 4843 case XMMOM: 4844 wbit = XMM_OPND; 4845 dtrace_get_modrm(x, &mode, ®, &r_m); 4846 #ifdef DIS_TEXT 4847 if (mode == REG_ONLY) { 4848 if (strcmp(dp->it_name, "movhps") == 0) 4849 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 4850 else 4851 goto error; 4852 } 4853 #endif 4854 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4855 break; 4856 4857 /* SIMD memory or r32 to xmm reg */ 4858 case XMM3MX: 4859 wbit = LONG_OPND; 4860 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4861 break; 4862 4863 case XMM3MXS: 4864 wbit = LONG_OPND; 4865 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 4866 break; 4867 4868 /* SIMD memory or mm reg to xmm reg */ 4869 case XMMOMX: 4870 /* SIMD mm to xmm */ 4871 case XMMMX: 4872 wbit = MM_OPND; 4873 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 4874 break; 4875 4876 /* SIMD memory or xmm reg to mm reg */ 4877 case XMMXMM: 4878 case XMMOXMM: 4879 case XMMXM: 4880 wbit = XMM_OPND; 4881 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 4882 break; 4883 4884 4885 /* SIMD memory or xmm reg to r32 */ 4886 case XMMXM3: 4887 wbit = XMM_OPND; 4888 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 4889 break; 4890 4891 /* SIMD xmm to r32 */ 4892 case XMMX3: 4893 case XMMOX3: 4894 dtrace_get_modrm(x, &mode, ®, &r_m); 4895 if (mode != REG_ONLY) 4896 goto error; 4897 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4898 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 4899 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4900 NOMEM; 4901 break; 4902 4903 /* SIMD predicated memory or xmm reg with/to xmm reg */ 4904 case XMMP: 4905 case XMMP_66r: 4906 case XMMP_66o: 4907 case XMMOPM: 4908 wbit = XMM_OPND; 4909 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 4910 1); 4911 4912 #ifdef DIS_TEXT 4913 /* 4914 * cmpps and cmpss vary their instruction name based 4915 * on the value of imm8. Other XMMP instructions, 4916 * such as shufps, require explicit specification of 4917 * the predicate. 4918 */ 4919 if (dp->it_name[0] == 'c' && 4920 dp->it_name[1] == 'm' && 4921 dp->it_name[2] == 'p' && 4922 strlen(dp->it_name) == 5) { 4923 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 4924 4925 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 4926 goto error; 4927 4928 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 4929 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 4930 OPLEN); 4931 (void) strlcat(x->d86_mnem, 4932 dp->it_name + strlen(dp->it_name) - 2, 4933 OPLEN); 4934 x->d86_opnd[0] = x->d86_opnd[1]; 4935 x->d86_opnd[1] = x->d86_opnd[2]; 4936 x->d86_numopnds = 2; 4937 } 4938 4939 /* 4940 * The pclmulqdq instruction has a series of alternate names for 4941 * various encodings of the immediate byte. As such, if we 4942 * happen to find it and the immediate value matches, we'll 4943 * rewrite the mnemonic. 4944 */ 4945 if (strcmp(dp->it_name, "pclmulqdq") == 0) { 4946 boolean_t changed = B_TRUE; 4947 switch (x->d86_opnd[0].d86_value) { 4948 case 0x00: 4949 (void) strncpy(x->d86_mnem, "pclmullqlqdq", 4950 OPLEN); 4951 break; 4952 case 0x01: 4953 (void) strncpy(x->d86_mnem, "pclmulhqlqdq", 4954 OPLEN); 4955 break; 4956 case 0x10: 4957 (void) strncpy(x->d86_mnem, "pclmullqhqdq", 4958 OPLEN); 4959 break; 4960 case 0x11: 4961 (void) strncpy(x->d86_mnem, "pclmulhqhqdq", 4962 OPLEN); 4963 break; 4964 default: 4965 changed = B_FALSE; 4966 break; 4967 } 4968 4969 if (changed == B_TRUE) { 4970 x->d86_opnd[0].d86_value_size = 0; 4971 x->d86_opnd[0] = x->d86_opnd[1]; 4972 x->d86_opnd[1] = x->d86_opnd[2]; 4973 x->d86_numopnds = 2; 4974 } 4975 } 4976 #endif 4977 break; 4978 4979 case XMMX2I: 4980 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 4981 1); 4982 NOMEM; 4983 break; 4984 4985 case XMM2I: 4986 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 4987 NOMEM; 4988 break; 4989 4990 /* immediate operand to accumulator */ 4991 case IA: 4992 wbit = WBIT(opcode2); 4993 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 4994 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4995 NOMEM; 4996 break; 4997 4998 /* memory or register operand to accumulator */ 4999 case MA: 5000 wbit = WBIT(opcode2); 5001 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5002 dtrace_get_operand(x, mode, r_m, wbit, 0); 5003 break; 5004 5005 /* si register to di register used to reference memory */ 5006 case SD: 5007 #ifdef DIS_TEXT 5008 dtrace_check_override(x, 0); 5009 x->d86_numopnds = 2; 5010 if (addr_size == SIZE64) { 5011 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5012 OPLEN); 5013 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5014 OPLEN); 5015 } else if (addr_size == SIZE32) { 5016 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5017 OPLEN); 5018 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5019 OPLEN); 5020 } else { 5021 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5022 OPLEN); 5023 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5024 OPLEN); 5025 } 5026 #endif 5027 wbit = LONG_OPND; 5028 break; 5029 5030 /* accumulator to di register */ 5031 case AD: 5032 wbit = WBIT(opcode2); 5033 #ifdef DIS_TEXT 5034 dtrace_check_override(x, 1); 5035 x->d86_numopnds = 2; 5036 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 5037 if (addr_size == SIZE64) 5038 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5039 OPLEN); 5040 else if (addr_size == SIZE32) 5041 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5042 OPLEN); 5043 else 5044 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5045 OPLEN); 5046 #endif 5047 break; 5048 5049 /* si register to accumulator */ 5050 case SA: 5051 wbit = WBIT(opcode2); 5052 #ifdef DIS_TEXT 5053 dtrace_check_override(x, 0); 5054 x->d86_numopnds = 2; 5055 if (addr_size == SIZE64) 5056 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5057 OPLEN); 5058 else if (addr_size == SIZE32) 5059 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5060 OPLEN); 5061 else 5062 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5063 OPLEN); 5064 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5065 #endif 5066 break; 5067 5068 /* 5069 * single operand, a 16/32 bit displacement 5070 */ 5071 case D: 5072 wbit = LONG_OPND; 5073 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5074 NOMEM; 5075 break; 5076 5077 /* jmp/call indirect to memory or register operand */ 5078 case INM: 5079 #ifdef DIS_TEXT 5080 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 5081 #endif 5082 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5083 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5084 wbit = LONG_OPND; 5085 break; 5086 5087 /* 5088 * for long jumps and long calls -- a new code segment 5089 * register and an offset in IP -- stored in object 5090 * code in reverse order. Note - not valid in amd64 5091 */ 5092 case SO: 5093 dtrace_check_override(x, 1); 5094 wbit = LONG_OPND; 5095 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 5096 #ifdef DIS_TEXT 5097 x->d86_opnd[1].d86_mode = MODE_SIGNED; 5098 #endif 5099 /* will now get segment operand */ 5100 dtrace_imm_opnd(x, wbit, 2, 0); 5101 break; 5102 5103 /* 5104 * jmp/call. single operand, 8 bit displacement. 5105 * added to current EIP in 'compofff' 5106 */ 5107 case BD: 5108 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 5109 NOMEM; 5110 break; 5111 5112 /* single 32/16 bit immediate operand */ 5113 case I: 5114 wbit = LONG_OPND; 5115 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5116 break; 5117 5118 /* single 8 bit immediate operand */ 5119 case Ib: 5120 wbit = LONG_OPND; 5121 dtrace_imm_opnd(x, wbit, 1, 0); 5122 break; 5123 5124 case ENTER: 5125 wbit = LONG_OPND; 5126 dtrace_imm_opnd(x, wbit, 2, 0); 5127 dtrace_imm_opnd(x, wbit, 1, 1); 5128 switch (opnd_size) { 5129 case SIZE64: 5130 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 5131 break; 5132 case SIZE32: 5133 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 5134 break; 5135 case SIZE16: 5136 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 5137 break; 5138 } 5139 5140 break; 5141 5142 /* 16-bit immediate operand */ 5143 case RET: 5144 wbit = LONG_OPND; 5145 dtrace_imm_opnd(x, wbit, 2, 0); 5146 break; 5147 5148 /* single 8 bit port operand */ 5149 case P: 5150 dtrace_check_override(x, 0); 5151 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5152 NOMEM; 5153 break; 5154 5155 /* single operand, dx register (variable port instruction) */ 5156 case V: 5157 x->d86_numopnds = 1; 5158 dtrace_check_override(x, 0); 5159 #ifdef DIS_TEXT 5160 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 5161 #endif 5162 NOMEM; 5163 break; 5164 5165 /* 5166 * The int instruction, which has two forms: 5167 * int 3 (breakpoint) or 5168 * int n, where n is indicated in the subsequent 5169 * byte (format Ib). The int 3 instruction (opcode 0xCC), 5170 * where, although the 3 looks like an operand, 5171 * it is implied by the opcode. It must be converted 5172 * to the correct base and output. 5173 */ 5174 case INT3: 5175 #ifdef DIS_TEXT 5176 x->d86_numopnds = 1; 5177 x->d86_opnd[0].d86_mode = MODE_SIGNED; 5178 x->d86_opnd[0].d86_value_size = 1; 5179 x->d86_opnd[0].d86_value = 3; 5180 #endif 5181 NOMEM; 5182 break; 5183 5184 /* single 8 bit immediate operand */ 5185 case INTx: 5186 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5187 NOMEM; 5188 break; 5189 5190 /* an unused byte must be discarded */ 5191 case U: 5192 if (x->d86_get_byte(x->d86_data) < 0) 5193 goto error; 5194 x->d86_len++; 5195 NOMEM; 5196 break; 5197 5198 case CBW: 5199 #ifdef DIS_TEXT 5200 if (opnd_size == SIZE16) 5201 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 5202 else if (opnd_size == SIZE32) 5203 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 5204 else 5205 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 5206 #endif 5207 wbit = LONG_OPND; 5208 NOMEM; 5209 break; 5210 5211 case CWD: 5212 #ifdef DIS_TEXT 5213 if (opnd_size == SIZE16) 5214 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 5215 else if (opnd_size == SIZE32) 5216 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 5217 else 5218 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 5219 #endif 5220 wbit = LONG_OPND; 5221 NOMEM; 5222 break; 5223 5224 case XMMSFNC: 5225 /* 5226 * sfence is sfence if mode is REG_ONLY. If mode isn't 5227 * REG_ONLY, mnemonic should be 'clflush'. 5228 */ 5229 dtrace_get_modrm(x, &mode, ®, &r_m); 5230 5231 /* sfence doesn't take operands */ 5232 if (mode != REG_ONLY) { 5233 if (opnd_size_prefix == 0x66) { 5234 #ifdef DIS_TEXT 5235 (void) strlcat(x->d86_mnem, "clflushopt", 5236 OPLEN); 5237 #endif 5238 } else if (opnd_size_prefix == 0) { 5239 #ifdef DIS_TEXT 5240 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 5241 #endif 5242 } else { 5243 /* Unknown instruction */ 5244 goto error; 5245 } 5246 5247 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5248 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5249 NOMEM; 5250 #ifdef DIS_TEXT 5251 } else { 5252 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 5253 #endif 5254 } 5255 break; 5256 5257 case FSGS: 5258 /* 5259 * The FSGSBASE instructions are taken only when the mode is set 5260 * to registers. They share opcodes with instructions like 5261 * fxrstor, stmxcsr, etc. We handle the repz prefix earlier. 5262 */ 5263 wbit = WBIT(opcode2); 5264 dtrace_get_modrm(x, &mode, ®, &r_m); 5265 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5266 dtrace_get_operand(x, mode, r_m, wbit, 0); 5267 if (mode == REG_ONLY) { 5268 NOMEM; 5269 } 5270 break; 5271 5272 /* 5273 * no disassembly, the mnemonic was all there was so go on 5274 */ 5275 case NORM: 5276 if (dp->it_invalid32 && cpu_mode != SIZE64) 5277 goto error; 5278 NOMEM; 5279 /*FALLTHROUGH*/ 5280 case IMPLMEM: 5281 break; 5282 5283 case XMMFENCE: 5284 /* 5285 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but 5286 * differ in mode and reg. 5287 */ 5288 dtrace_get_modrm(x, &mode, ®, &r_m); 5289 5290 if (mode == REG_ONLY) { 5291 /* 5292 * Only the following exact byte sequences are allowed: 5293 * 5294 * 0f ae e8 lfence 5295 * 0f ae f0 mfence 5296 */ 5297 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 5298 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 5299 goto error; 5300 } else { 5301 #ifdef DIS_TEXT 5302 if (reg == 5) { 5303 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 5304 } else if (reg == 6) { 5305 if (opnd_size_prefix == 0x66) { 5306 (void) strncpy(x->d86_mnem, "clwb", 5307 OPLEN); 5308 } else if (opnd_size_prefix == 0x00) { 5309 (void) strncpy(x->d86_mnem, "xsaveopt", 5310 OPLEN); 5311 } else { 5312 goto error; 5313 } 5314 } else { 5315 goto error; 5316 } 5317 #endif 5318 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5319 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5320 } 5321 break; 5322 5323 /* float reg */ 5324 case F: 5325 #ifdef DIS_TEXT 5326 x->d86_numopnds = 1; 5327 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 5328 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 5329 #endif 5330 NOMEM; 5331 break; 5332 5333 /* float reg to float reg, with ret bit present */ 5334 case FF: 5335 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 5336 /*FALLTHROUGH*/ 5337 case FFC: /* case for vbit always = 0 */ 5338 #ifdef DIS_TEXT 5339 x->d86_numopnds = 2; 5340 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 5341 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 5342 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 5343 #endif 5344 NOMEM; 5345 break; 5346 5347 /* AVX instructions */ 5348 case VEX_MO: 5349 /* op(ModR/M.r/m) */ 5350 x->d86_numopnds = 1; 5351 dtrace_get_modrm(x, &mode, ®, &r_m); 5352 #ifdef DIS_TEXT 5353 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 5354 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 5355 #endif 5356 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5357 dtrace_get_operand(x, mode, r_m, wbit, 0); 5358 break; 5359 case VEX_RMrX: 5360 case FMA: 5361 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 5362 x->d86_numopnds = 3; 5363 dtrace_get_modrm(x, &mode, ®, &r_m); 5364 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5365 5366 /* 5367 * In classic Intel fashion, the opcodes for all of the FMA 5368 * instructions all have two possible mnemonics which vary by 5369 * one letter, which is selected based on the value of the wbit. 5370 * When wbit is one, they have the 'd' suffix and when 'wbit' is 5371 * 0, they have the 's' suffix. Otherwise, the FMA instructions 5372 * are all a standard VEX_RMrX. 5373 */ 5374 #ifdef DIS_TEXT 5375 if (dp->it_adrmode == FMA) { 5376 size_t len = strlen(dp->it_name); 5377 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5378 if (len + 1 < OPLEN) { 5379 (void) strncpy(x->d86_mnem + len, 5380 vex_W != 0 ? "d" : "s", OPLEN - len); 5381 } 5382 } 5383 #endif 5384 5385 if (mode != REG_ONLY) { 5386 if ((dp == &dis_opAVXF20F[0x10]) || 5387 (dp == &dis_opAVXF30F[0x10])) { 5388 /* vmovsd <m64>, <xmm> */ 5389 /* or vmovss <m64>, <xmm> */ 5390 x->d86_numopnds = 2; 5391 goto L_VEX_MX; 5392 } 5393 } 5394 5395 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5396 /* 5397 * VEX prefix uses the 1's complement form to encode the 5398 * XMM/YMM regs 5399 */ 5400 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5401 5402 if ((dp == &dis_opAVXF20F[0x2A]) || 5403 (dp == &dis_opAVXF30F[0x2A])) { 5404 /* 5405 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 5406 * <xmm>, <xmm> 5407 */ 5408 wbit = LONG_OPND; 5409 } 5410 #ifdef DIS_TEXT 5411 else if ((mode == REG_ONLY) && 5412 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 5413 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 5414 } else if ((mode == REG_ONLY) && 5415 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 5416 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 5417 } 5418 #endif 5419 dtrace_get_operand(x, mode, r_m, wbit, 0); 5420 5421 break; 5422 5423 case VEX_VRMrX: 5424 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */ 5425 x->d86_numopnds = 3; 5426 dtrace_get_modrm(x, &mode, ®, &r_m); 5427 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5428 5429 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5430 /* 5431 * VEX prefix uses the 1's complement form to encode the 5432 * XMM/YMM regs 5433 */ 5434 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0); 5435 5436 dtrace_get_operand(x, mode, r_m, wbit, 1); 5437 break; 5438 5439 case VEX_SbVM: 5440 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */ 5441 x->d86_numopnds = 3; 5442 x->d86_vsib = 1; 5443 5444 /* 5445 * All instructions that use VSIB are currently a mess. See the 5446 * comment around the dis_gather_regs_t structure definition. 5447 */ 5448 5449 vreg = &dis_vgather[opcode2][vex_W][vex_L]; 5450 5451 #ifdef DIS_TEXT 5452 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5453 (void) strlcat(x->d86_mnem + strlen(dp->it_name), 5454 vreg->dgr_suffix, OPLEN - strlen(dp->it_name)); 5455 #endif 5456 5457 dtrace_get_modrm(x, &mode, ®, &r_m); 5458 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5459 5460 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2); 5461 /* 5462 * VEX prefix uses the 1's complement form to encode the 5463 * XMM/YMM regs 5464 */ 5465 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0, 5466 0); 5467 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1); 5468 break; 5469 5470 case VEX_RRX: 5471 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5472 x->d86_numopnds = 3; 5473 5474 dtrace_get_modrm(x, &mode, ®, &r_m); 5475 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5476 5477 if (mode != REG_ONLY) { 5478 if ((dp == &dis_opAVXF20F[0x11]) || 5479 (dp == &dis_opAVXF30F[0x11])) { 5480 /* vmovsd <xmm>, <m64> */ 5481 /* or vmovss <xmm>, <m64> */ 5482 x->d86_numopnds = 2; 5483 goto L_VEX_RM; 5484 } 5485 } 5486 5487 dtrace_get_operand(x, mode, r_m, wbit, 2); 5488 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5489 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5490 break; 5491 5492 case VEX_RMRX: 5493 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 5494 x->d86_numopnds = 4; 5495 5496 dtrace_get_modrm(x, &mode, ®, &r_m); 5497 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5498 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 5499 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5500 if (dp == &dis_opAVX660F3A[0x18]) { 5501 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 5502 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 5503 } else if ((dp == &dis_opAVX660F3A[0x20]) || 5504 (dp == & dis_opAVX660F[0xC4])) { 5505 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 5506 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 5507 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5508 } else if (dp == &dis_opAVX660F3A[0x22]) { 5509 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 5510 #ifdef DIS_TEXT 5511 if (vex_W) 5512 x->d86_mnem[6] = 'q'; 5513 #endif 5514 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5515 } else { 5516 dtrace_get_operand(x, mode, r_m, wbit, 1); 5517 } 5518 5519 /* one byte immediate number */ 5520 dtrace_imm_opnd(x, wbit, 1, 0); 5521 5522 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 5523 if ((dp == &dis_opAVX660F3A[0x4A]) || 5524 (dp == &dis_opAVX660F3A[0x4B]) || 5525 (dp == &dis_opAVX660F3A[0x4C])) { 5526 #ifdef DIS_TEXT 5527 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 5528 #endif 5529 x->d86_opnd[0].d86_mode = MODE_NONE; 5530 #ifdef DIS_TEXT 5531 if (vex_L) 5532 (void) strncpy(x->d86_opnd[0].d86_opnd, 5533 dis_YMMREG[regnum], OPLEN); 5534 else 5535 (void) strncpy(x->d86_opnd[0].d86_opnd, 5536 dis_XMMREG[regnum], OPLEN); 5537 #endif 5538 } 5539 break; 5540 5541 case VEX_MX: 5542 /* ModR/M.reg := op(ModR/M.rm) */ 5543 x->d86_numopnds = 2; 5544 5545 dtrace_get_modrm(x, &mode, ®, &r_m); 5546 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5547 L_VEX_MX: 5548 5549 if ((dp == &dis_opAVXF20F[0xE6]) || 5550 (dp == &dis_opAVX660F[0x5A]) || 5551 (dp == &dis_opAVX660F[0xE6])) { 5552 /* vcvtpd2dq <ymm>, <xmm> */ 5553 /* or vcvtpd2ps <ymm>, <xmm> */ 5554 /* or vcvttpd2dq <ymm>, <xmm> */ 5555 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 5556 dtrace_get_operand(x, mode, r_m, wbit, 0); 5557 } else if ((dp == &dis_opAVXF30F[0xE6]) || 5558 (dp == &dis_opAVX0F[0x5][0xA]) || 5559 (dp == &dis_opAVX660F38[0x13]) || 5560 (dp == &dis_opAVX660F38[0x18]) || 5561 (dp == &dis_opAVX660F38[0x19]) || 5562 (dp == &dis_opAVX660F38[0x58]) || 5563 (dp == &dis_opAVX660F38[0x78]) || 5564 (dp == &dis_opAVX660F38[0x79]) || 5565 (dp == &dis_opAVX660F38[0x59])) { 5566 /* vcvtdq2pd <xmm>, <ymm> */ 5567 /* or vcvtps2pd <xmm>, <ymm> */ 5568 /* or vcvtph2ps <xmm>, <ymm> */ 5569 /* or vbroadcasts* <xmm>, <ymm> */ 5570 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5571 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 5572 } else if (dp == &dis_opAVX660F[0x6E]) { 5573 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5574 #ifdef DIS_TEXT 5575 if (vex_W) 5576 x->d86_mnem[4] = 'q'; 5577 #endif 5578 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5579 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5580 } else { 5581 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5582 dtrace_get_operand(x, mode, r_m, wbit, 0); 5583 } 5584 5585 break; 5586 5587 case VEX_MXI: 5588 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 5589 x->d86_numopnds = 3; 5590 5591 dtrace_get_modrm(x, &mode, ®, &r_m); 5592 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5593 5594 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5595 dtrace_get_operand(x, mode, r_m, wbit, 1); 5596 5597 /* one byte immediate number */ 5598 dtrace_imm_opnd(x, wbit, 1, 0); 5599 break; 5600 5601 case VEX_XXI: 5602 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 5603 x->d86_numopnds = 3; 5604 5605 dtrace_get_modrm(x, &mode, ®, &r_m); 5606 #ifdef DIS_TEXT 5607 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 5608 OPLEN); 5609 #endif 5610 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5611 5612 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 5613 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 5614 5615 /* one byte immediate number */ 5616 dtrace_imm_opnd(x, wbit, 1, 0); 5617 break; 5618 5619 case VEX_MR: 5620 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 5621 if (dp == &dis_opAVX660F[0xC5]) { 5622 /* vpextrw <imm8>, <xmm>, <reg> */ 5623 x->d86_numopnds = 2; 5624 vbit = 2; 5625 } else { 5626 x->d86_numopnds = 2; 5627 vbit = 1; 5628 } 5629 5630 dtrace_get_modrm(x, &mode, ®, &r_m); 5631 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5632 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 5633 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 5634 5635 if (vbit == 2) 5636 dtrace_imm_opnd(x, wbit, 1, 0); 5637 5638 break; 5639 5640 case VEX_KMR: 5641 /* opmask: mod_rm := %k */ 5642 x->d86_numopnds = 2; 5643 dtrace_get_modrm(x, &mode, ®, &r_m); 5644 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5645 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5646 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5647 break; 5648 5649 case VEX_KRM: 5650 /* opmask: mod_reg := mod_rm */ 5651 x->d86_numopnds = 2; 5652 dtrace_get_modrm(x, &mode, ®, &r_m); 5653 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5654 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5655 if (mode == REG_ONLY) { 5656 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0); 5657 } else { 5658 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5659 } 5660 break; 5661 5662 case VEX_KRR: 5663 /* opmask: mod_reg := mod_rm */ 5664 x->d86_numopnds = 2; 5665 dtrace_get_modrm(x, &mode, ®, &r_m); 5666 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5667 dtrace_get_operand(x, mode, reg, wbit, 1); 5668 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0); 5669 break; 5670 5671 case VEX_RRI: 5672 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 5673 x->d86_numopnds = 2; 5674 5675 dtrace_get_modrm(x, &mode, ®, &r_m); 5676 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5677 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5678 dtrace_get_operand(x, mode, r_m, wbit, 0); 5679 break; 5680 5681 case VEX_RX: 5682 /* ModR/M.rm := op(ModR/M.reg) */ 5683 /* vextractf128 || vcvtps2ph */ 5684 if (dp == &dis_opAVX660F3A[0x19] || 5685 dp == &dis_opAVX660F3A[0x1d]) { 5686 x->d86_numopnds = 3; 5687 5688 dtrace_get_modrm(x, &mode, ®, &r_m); 5689 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5690 5691 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5692 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5693 5694 /* one byte immediate number */ 5695 dtrace_imm_opnd(x, wbit, 1, 0); 5696 break; 5697 } 5698 5699 x->d86_numopnds = 2; 5700 5701 dtrace_get_modrm(x, &mode, ®, &r_m); 5702 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5703 dtrace_get_operand(x, mode, r_m, wbit, 1); 5704 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5705 break; 5706 5707 case VEX_RR: 5708 /* ModR/M.rm := op(ModR/M.reg) */ 5709 x->d86_numopnds = 2; 5710 5711 dtrace_get_modrm(x, &mode, ®, &r_m); 5712 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5713 5714 if (dp == &dis_opAVX660F[0x7E]) { 5715 /* vmovd/q <reg/mem 32/64>, <xmm> */ 5716 #ifdef DIS_TEXT 5717 if (vex_W) 5718 x->d86_mnem[4] = 'q'; 5719 #endif 5720 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 5721 } else 5722 dtrace_get_operand(x, mode, r_m, wbit, 1); 5723 5724 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5725 break; 5726 5727 case VEX_RRi: 5728 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5729 x->d86_numopnds = 3; 5730 5731 dtrace_get_modrm(x, &mode, ®, &r_m); 5732 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5733 5734 #ifdef DIS_TEXT 5735 if (dp == &dis_opAVX660F3A[0x16]) { 5736 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 5737 if (vex_W) 5738 x->d86_mnem[6] = 'q'; 5739 } 5740 #endif 5741 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5742 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5743 5744 /* one byte immediate number */ 5745 dtrace_imm_opnd(x, wbit, 1, 0); 5746 break; 5747 case VEX_RIM: 5748 /* ModR/M.rm := op(ModR/M.reg, imm) */ 5749 x->d86_numopnds = 3; 5750 5751 dtrace_get_modrm(x, &mode, ®, &r_m); 5752 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5753 5754 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 5755 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5756 /* one byte immediate number */ 5757 dtrace_imm_opnd(x, wbit, 1, 0); 5758 break; 5759 5760 case VEX_RM: 5761 /* ModR/M.rm := op(ModR/M.reg) */ 5762 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 5763 x->d86_numopnds = 3; 5764 5765 dtrace_get_modrm(x, &mode, ®, &r_m); 5766 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5767 5768 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 5769 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5770 /* one byte immediate number */ 5771 dtrace_imm_opnd(x, wbit, 1, 0); 5772 break; 5773 } 5774 x->d86_numopnds = 2; 5775 5776 dtrace_get_modrm(x, &mode, ®, &r_m); 5777 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5778 L_VEX_RM: 5779 vbit = 1; 5780 dtrace_get_operand(x, mode, r_m, wbit, vbit); 5781 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 5782 5783 break; 5784 5785 case VEX_RRM: 5786 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5787 x->d86_numopnds = 3; 5788 5789 dtrace_get_modrm(x, &mode, ®, &r_m); 5790 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5791 dtrace_get_operand(x, mode, r_m, wbit, 2); 5792 /* VEX use the 1's complement form encode the XMM/YMM regs */ 5793 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5794 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5795 break; 5796 5797 case VEX_RMX: 5798 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 5799 x->d86_numopnds = 3; 5800 5801 dtrace_get_modrm(x, &mode, ®, &r_m); 5802 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5803 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5804 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5805 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 5806 break; 5807 5808 case VEX_NONE: 5809 #ifdef DIS_TEXT 5810 if (vex_L) 5811 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 5812 #endif 5813 break; 5814 case BLS: { 5815 5816 /* 5817 * The BLS instructions are VEX instructions that are based on 5818 * VEX.0F38.F3; however, they are considered special group 17 5819 * and like everything else, they use the bits in 3-5 of the 5820 * MOD R/M to determine the sub instruction. Unlike many others 5821 * like the VMX instructions, these are valid both for memory 5822 * and register forms. 5823 */ 5824 5825 dtrace_get_modrm(x, &mode, ®, &r_m); 5826 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5827 5828 switch (reg) { 5829 case 1: 5830 #ifdef DIS_TEXT 5831 blsinstr = "blsr"; 5832 #endif 5833 break; 5834 case 2: 5835 #ifdef DIS_TEXT 5836 blsinstr = "blsmsk"; 5837 #endif 5838 break; 5839 case 3: 5840 #ifdef DIS_TEXT 5841 blsinstr = "blsi"; 5842 #endif 5843 break; 5844 default: 5845 goto error; 5846 } 5847 5848 x->d86_numopnds = 2; 5849 #ifdef DIS_TEXT 5850 (void) strncpy(x->d86_mnem, blsinstr, OPLEN); 5851 #endif 5852 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5853 dtrace_get_operand(x, mode, r_m, wbit, 0); 5854 break; 5855 } 5856 case EVEX_MX: 5857 /* ModR/M.reg := op(ModR/M.rm) */ 5858 x->d86_numopnds = 2; 5859 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5860 dtrace_get_modrm(x, &mode, ®, &r_m); 5861 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5862 dtrace_evex_adjust_reg(evex_byte1, ®); 5863 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5864 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5865 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5866 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 5867 dtrace_get_operand(x, mode, r_m, wbit, 0); 5868 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 5869 break; 5870 case EVEX_RX: 5871 /* ModR/M.rm := op(ModR/M.reg) */ 5872 x->d86_numopnds = 2; 5873 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5874 dtrace_get_modrm(x, &mode, ®, &r_m); 5875 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5876 dtrace_evex_adjust_reg(evex_byte1, ®); 5877 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5878 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5879 dtrace_get_operand(x, mode, r_m, wbit, 1); 5880 dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); 5881 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 5882 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 5883 break; 5884 case EVEX_RMrX: 5885 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */ 5886 x->d86_numopnds = 3; 5887 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 5888 dtrace_get_modrm(x, &mode, ®, &r_m); 5889 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 5890 dtrace_evex_adjust_reg(evex_byte1, ®); 5891 dtrace_evex_adjust_rm(evex_byte1, &r_m); 5892 dtrace_evex_adjust_reg_name(evex_L, &wbit); 5893 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5894 /* 5895 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 5896 * register specifier). The EVEX prefix handling uses the vex_v 5897 * variable for these bits. 5898 */ 5899 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5900 dtrace_get_operand(x, mode, r_m, wbit, 0); 5901 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 5902 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); 5903 break; 5904 /* an invalid op code */ 5905 case AM: 5906 case DM: 5907 case OVERRIDE: 5908 case PREFIX: 5909 case UNKNOWN: 5910 NOMEM; 5911 default: 5912 goto error; 5913 } /* end switch */ 5914 if (x->d86_error) 5915 goto error; 5916 5917 done: 5918 #ifdef DIS_MEM 5919 /* 5920 * compute the size of any memory accessed by the instruction 5921 */ 5922 if (x->d86_memsize != 0) { 5923 return (0); 5924 } else if (dp->it_stackop) { 5925 switch (opnd_size) { 5926 case SIZE16: 5927 x->d86_memsize = 2; 5928 break; 5929 case SIZE32: 5930 x->d86_memsize = 4; 5931 break; 5932 case SIZE64: 5933 x->d86_memsize = 8; 5934 break; 5935 } 5936 } else if (nomem || mode == REG_ONLY) { 5937 x->d86_memsize = 0; 5938 5939 } else if (dp->it_size != 0) { 5940 /* 5941 * In 64 bit mode descriptor table entries 5942 * go up to 10 bytes and popf/pushf are always 8 bytes 5943 */ 5944 if (x->d86_mode == SIZE64 && dp->it_size == 6) 5945 x->d86_memsize = 10; 5946 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 5947 (opcode2 == 0xc || opcode2 == 0xd)) 5948 x->d86_memsize = 8; 5949 else 5950 x->d86_memsize = dp->it_size; 5951 5952 } else if (wbit == 0) { 5953 x->d86_memsize = 1; 5954 5955 } else if (wbit == LONG_OPND) { 5956 if (opnd_size == SIZE64) 5957 x->d86_memsize = 8; 5958 else if (opnd_size == SIZE32) 5959 x->d86_memsize = 4; 5960 else 5961 x->d86_memsize = 2; 5962 5963 } else if (wbit == SEG_OPND) { 5964 x->d86_memsize = 4; 5965 5966 } else { 5967 x->d86_memsize = 8; 5968 } 5969 #endif 5970 return (0); 5971 5972 error: 5973 #ifdef DIS_TEXT 5974 (void) strlcat(x->d86_mnem, "undef", OPLEN); 5975 #endif 5976 return (1); 5977 } 5978 5979 #ifdef DIS_TEXT 5980 5981 /* 5982 * Some instructions should have immediate operands printed 5983 * as unsigned integers. We compare against this table. 5984 */ 5985 static char *unsigned_ops[] = { 5986 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 5987 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 5988 0 5989 }; 5990 5991 5992 static int 5993 isunsigned_op(char *opcode) 5994 { 5995 char *where; 5996 int i; 5997 int is_unsigned = 0; 5998 5999 /* 6000 * Work back to start of last mnemonic, since we may have 6001 * prefixes on some opcodes. 6002 */ 6003 where = opcode + strlen(opcode) - 1; 6004 while (where > opcode && *where != ' ') 6005 --where; 6006 if (*where == ' ') 6007 ++where; 6008 6009 for (i = 0; unsigned_ops[i]; ++i) { 6010 if (strncmp(where, unsigned_ops[i], 6011 strlen(unsigned_ops[i]))) 6012 continue; 6013 is_unsigned = 1; 6014 break; 6015 } 6016 return (is_unsigned); 6017 } 6018 6019 /* 6020 * Print a numeric immediate into end of buf, maximum length buflen. 6021 * The immediate may be an address or a displacement. Mask is set 6022 * for address size. If the immediate is a "small negative", or 6023 * if it's a negative displacement of any magnitude, print as -<absval>. 6024 * Respect the "octal" flag. "Small negative" is defined as "in the 6025 * interval [NEG_LIMIT, 0)". 6026 * 6027 * Also, "isunsigned_op()" instructions never print negatives. 6028 * 6029 * Return whether we decided to print a negative value or not. 6030 */ 6031 6032 #define NEG_LIMIT -255 6033 enum {IMM, DISP}; 6034 enum {POS, TRY_NEG}; 6035 6036 static int 6037 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 6038 size_t buflen, int disp, int try_neg) 6039 { 6040 int curlen; 6041 int64_t sv = (int64_t)usv; 6042 int octal = dis->d86_flags & DIS_F_OCTAL; 6043 6044 curlen = strlen(buf); 6045 6046 if (try_neg == TRY_NEG && sv < 0 && 6047 (disp || sv >= NEG_LIMIT) && 6048 !isunsigned_op(dis->d86_mnem)) { 6049 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6050 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 6051 return (1); 6052 } else { 6053 if (disp == DISP) 6054 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6055 octal ? "+0%llo" : "+0x%llx", usv & mask); 6056 else 6057 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6058 octal ? "0%llo" : "0x%llx", usv & mask); 6059 return (0); 6060 6061 } 6062 } 6063 6064 6065 static int 6066 log2(int size) 6067 { 6068 switch (size) { 6069 case 1: return (0); 6070 case 2: return (1); 6071 case 4: return (2); 6072 case 8: return (3); 6073 } 6074 return (0); 6075 } 6076 6077 /* ARGSUSED */ 6078 void 6079 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 6080 size_t buflen) 6081 { 6082 uint64_t reltgt = 0; 6083 uint64_t tgt = 0; 6084 int curlen; 6085 int (*lookup)(void *, uint64_t, char *, size_t); 6086 int i; 6087 int64_t sv; 6088 uint64_t usv, mask, save_mask, save_usv; 6089 static uint64_t masks[] = 6090 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 6091 save_usv = 0; 6092 6093 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 6094 6095 /* 6096 * For PC-relative jumps, the pc is really the next pc after executing 6097 * this instruction, so increment it appropriately. 6098 */ 6099 pc += dis->d86_len; 6100 6101 for (i = 0; i < dis->d86_numopnds; i++) { 6102 d86opnd_t *op = &dis->d86_opnd[i]; 6103 6104 if (i != 0) 6105 (void) strlcat(buf, ",", buflen); 6106 6107 (void) strlcat(buf, op->d86_prefix, buflen); 6108 6109 /* 6110 * sv is for the signed, possibly-truncated immediate or 6111 * displacement; usv retains the original size and 6112 * unsignedness for symbol lookup. 6113 */ 6114 6115 sv = usv = op->d86_value; 6116 6117 /* 6118 * About masks: for immediates that represent 6119 * addresses, the appropriate display size is 6120 * the effective address size of the instruction. 6121 * This includes MODE_OFFSET, MODE_IPREL, and 6122 * MODE_RIPREL. Immediates that are simply 6123 * immediate values should display in the operand's 6124 * size, however, since they don't represent addresses. 6125 */ 6126 6127 /* d86_addr_size is SIZEnn, which is log2(real size) */ 6128 mask = masks[dis->d86_addr_size]; 6129 6130 /* d86_value_size and d86_imm_bytes are in bytes */ 6131 if (op->d86_mode == MODE_SIGNED || 6132 op->d86_mode == MODE_IMPLIED) 6133 mask = masks[log2(op->d86_value_size)]; 6134 6135 switch (op->d86_mode) { 6136 6137 case MODE_NONE: 6138 6139 (void) strlcat(buf, op->d86_opnd, buflen); 6140 break; 6141 6142 case MODE_SIGNED: 6143 case MODE_IMPLIED: 6144 case MODE_OFFSET: 6145 6146 tgt = usv; 6147 6148 if (dis->d86_seg_prefix) 6149 (void) strlcat(buf, dis->d86_seg_prefix, 6150 buflen); 6151 6152 if (op->d86_mode == MODE_SIGNED || 6153 op->d86_mode == MODE_IMPLIED) { 6154 (void) strlcat(buf, "$", buflen); 6155 } 6156 6157 if (print_imm(dis, usv, mask, buf, buflen, 6158 IMM, TRY_NEG) && 6159 (op->d86_mode == MODE_SIGNED || 6160 op->d86_mode == MODE_IMPLIED)) { 6161 6162 /* 6163 * We printed a negative value for an 6164 * immediate that wasn't a 6165 * displacement. Note that fact so we can 6166 * print the positive value as an 6167 * annotation. 6168 */ 6169 6170 save_usv = usv; 6171 save_mask = mask; 6172 } 6173 (void) strlcat(buf, op->d86_opnd, buflen); 6174 6175 break; 6176 6177 case MODE_IPREL: 6178 case MODE_RIPREL: 6179 6180 reltgt = pc + sv; 6181 6182 switch (mode) { 6183 case SIZE16: 6184 reltgt = (uint16_t)reltgt; 6185 break; 6186 case SIZE32: 6187 reltgt = (uint32_t)reltgt; 6188 break; 6189 } 6190 6191 (void) print_imm(dis, usv, mask, buf, buflen, 6192 DISP, TRY_NEG); 6193 6194 if (op->d86_mode == MODE_RIPREL) 6195 (void) strlcat(buf, "(%rip)", buflen); 6196 break; 6197 } 6198 } 6199 6200 /* 6201 * The symbol lookups may result in false positives, 6202 * particularly on object files, where small numbers may match 6203 * the 0-relative non-relocated addresses of symbols. 6204 */ 6205 6206 lookup = dis->d86_sym_lookup; 6207 if (tgt != 0) { 6208 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 6209 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 6210 (void) strlcat(buf, "\t<", buflen); 6211 curlen = strlen(buf); 6212 lookup(dis->d86_data, tgt, buf + curlen, 6213 buflen - curlen); 6214 (void) strlcat(buf, ">", buflen); 6215 } 6216 6217 /* 6218 * If we printed a negative immediate above, print the 6219 * positive in case our heuristic was unhelpful 6220 */ 6221 if (save_usv) { 6222 (void) strlcat(buf, "\t<", buflen); 6223 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 6224 IMM, POS); 6225 (void) strlcat(buf, ">", buflen); 6226 } 6227 } 6228 6229 if (reltgt != 0) { 6230 /* Print symbol or effective address for reltgt */ 6231 6232 (void) strlcat(buf, "\t<", buflen); 6233 curlen = strlen(buf); 6234 lookup(dis->d86_data, reltgt, buf + curlen, 6235 buflen - curlen); 6236 (void) strlcat(buf, ">", buflen); 6237 } 6238 } 6239 6240 #endif /* DIS_TEXT */ 6241