1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2019 Joyent, Inc. 25 * Copyright 2024 Oxide Computer Company 26 */ 27 28 /* 29 * Copyright (c) 2010, Intel Corporation. 30 * All rights reserved. 31 */ 32 33 /* Copyright (c) 1988 AT&T */ 34 /* All Rights Reserved */ 35 36 #include "dis_tables.h" 37 38 /* BEGIN CSTYLED */ 39 40 /* 41 * Disassembly begins in dis_distable, which is equivalent to the One-byte 42 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 43 * decoding loops then traverse out through the other tables as necessary to 44 * decode a given instruction. 45 * 46 * The behavior of this file can be controlled by one of the following flags: 47 * 48 * DIS_TEXT Include text for disassembly 49 * DIS_MEM Include memory-size calculations 50 * 51 * Either or both of these can be defined. 52 * 53 * This file is not, and will never be, cstyled. If anything, the tables should 54 * be taken out another tab stop or two so nothing overlaps. 55 */ 56 57 /* 58 * These functions must be provided for the consumer to do disassembly. 59 */ 60 #ifdef DIS_TEXT 61 extern char *strncpy(char *, const char *, size_t); 62 extern size_t strlen(const char *); 63 extern int strcmp(const char *, const char *); 64 extern int strncmp(const char *, const char *, size_t); 65 extern size_t strlcat(char *, const char *, size_t); 66 #endif 67 68 69 #define TERM 0 /* used to indicate that the 'indirect' */ 70 /* field terminates - no pointer. */ 71 72 /* Used to decode instructions. */ 73 typedef struct instable { 74 struct instable *it_indirect; /* for decode op codes */ 75 uchar_t it_adrmode; 76 #ifdef DIS_TEXT 77 char it_name[NCPS]; 78 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 79 #endif 80 #ifdef DIS_MEM 81 uint_t it_size:16; 82 #endif 83 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 84 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 85 uint_t it_invalid32:1; /* invalid in IA32 */ 86 uint_t it_stackop:1; /* push/pop stack operation */ 87 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ 88 uint_t it_avxsuf:3; /* AVX2/AVX512 suffix rqd. */ 89 uint_t it_vexopmask:1; /* VEX inst. that use opmask */ 90 } instable_t; 91 92 /* 93 * Instruction formats. 94 */ 95 enum { 96 UNKNOWN, 97 MRw, 98 IMlw, 99 IMw, 100 IR, 101 OA, 102 AO, 103 MS, 104 SM, 105 Mv, 106 Mw, 107 M, /* register or memory */ 108 MG9, /* register or memory in group 9 (prefix optional) */ 109 Mb, /* register or memory, always byte sized */ 110 MO, /* memory only (no registers) */ 111 PREF, 112 SWAPGS_RDTSCP, 113 MONITOR_MWAIT, 114 R, 115 RA, 116 SEG, 117 MR, 118 RM, 119 RM_66r, /* RM, but with a required 0x66 prefix */ 120 IA, 121 MA, 122 SD, 123 AD, 124 SA, 125 D, 126 INM, 127 SO, 128 BD, 129 I, 130 P, 131 V, 132 DSHIFT, /* for double shift that has an 8-bit immediate */ 133 U, 134 OVERRIDE, 135 NORM, /* instructions w/o ModR/M byte, no memory access */ 136 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 137 O, /* for call */ 138 JTAB, /* jump table */ 139 IMUL, /* for 186 iimul instr */ 140 CBW, /* so data16 can be evaluated for cbw and variants */ 141 MvI, /* for 186 logicals */ 142 ENTER, /* for 186 enter instr */ 143 RMw, /* for 286 arpl instr */ 144 Ib, /* for push immediate byte */ 145 F, /* for 287 instructions */ 146 FF, /* for 287 instructions */ 147 FFC, /* for 287 instructions */ 148 DM, /* 16-bit data */ 149 AM, /* 16-bit addr */ 150 LSEG, /* for 3-bit seg reg encoding */ 151 MIb, /* for 386 logicals */ 152 SREG, /* for 386 special registers */ 153 PREFIX, /* a REP instruction prefix */ 154 LOCK, /* a LOCK instruction prefix */ 155 INT3, /* The int 3 instruction, which has a fake operand */ 156 INTx, /* The normal int instruction, with explicit int num */ 157 DSHIFTcl, /* for double shift that implicitly uses %cl */ 158 CWD, /* so data16 can be evaluated for cwd and variants */ 159 RET, /* single immediate 16-bit operand */ 160 MOVZ, /* for movs and movz, with different size operands */ 161 CRC32, /* for crc32, with different size operands */ 162 XADDB, /* for xaddb */ 163 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 164 MOVBE, /* movbe instruction */ 165 MOVDIR, /* movdir64b register semantics m512 -> r16/32/64 */ 166 RMATCH, /* register, but type matches CPU, not prefixes */ 167 168 /* 169 * MMX/SIMD addressing modes. 170 */ 171 172 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 173 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 174 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 175 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 176 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 177 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 178 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 179 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 180 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 181 MMOSH, /* Prefixable MMX mm,imm8 */ 182 MM, /* MMX/SIMD-Int mm/mem -> mm */ 183 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 184 MMSH, /* MMX mm,imm8 */ 185 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 186 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 187 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 188 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 189 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 190 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 191 XMMOM, /* Prefixable SIMD xmm -> mem */ 192 XMMOMS, /* Prefixable SIMD mem -> xmm */ 193 XMM, /* SIMD xmm/mem -> xmm */ 194 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 195 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 196 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 197 XMM3P, /* SIMD xmm -> r32,imm8 */ 198 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 199 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 200 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 201 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 202 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 203 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 204 XMMS, /* SIMD xmm -> xmm/mem */ 205 XMMM, /* SIMD mem -> xmm */ 206 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 207 XMMMS, /* SIMD xmm -> mem */ 208 XMM3MX, /* SIMD r32/mem -> xmm */ 209 XMM3MXS, /* SIMD xmm -> r32/mem */ 210 XMMSH, /* SIMD xmm,imm8 */ 211 XMMXM3, /* SIMD xmm/mem -> r32 */ 212 XMMX3, /* SIMD xmm -> r32 */ 213 XMMXMM, /* SIMD xmm/mem -> mm */ 214 XMMMX, /* SIMD mm -> xmm */ 215 XMMXM, /* SIMD xmm -> mm */ 216 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 217 XMM2I, /* SIMD xmm, imm, imm */ 218 XMMFENCE, /* SIMD lfence or mfence */ 219 XMMSFNC, /* SIMD sfence (none or mem) */ 220 FSGS, /* FSGSBASE if reg */ 221 XGETBV_XSETBV, 222 VEX_NONE, /* VEX no operand */ 223 VEX_MO, /* VEX mod_rm -> implicit reg */ 224 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 225 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */ 226 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 227 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 228 VEX_MX, /* VEX mod_rm -> mod_reg */ 229 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 230 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 231 VEX_MR, /* VEX mod_rm -> mod_reg */ 232 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 233 VEX_RX, /* VEX mod_reg -> mod_rm */ 234 VEX_KRR, /* VEX mod_rm -> mod_reg */ 235 VEX_KMR, /* VEX mod_reg -> mod_rm */ 236 VEX_KRM, /* VEX mod_rm -> mod_reg */ 237 VEX_RR, /* VEX mod_rm -> mod_reg */ 238 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 239 VEX_RM, /* VEX mod_reg -> mod_rm */ 240 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */ 241 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 242 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 243 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */ 244 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 245 VMxo, /* VMx instruction with optional prefix */ 246 SVM, /* AMD SVM instructions */ 247 BLS, /* BLSR, BLSMSK, BLSI */ 248 FMA, /* FMA instructions, all VEX_RMrX */ 249 ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */ 250 EVEX_RX, /* EVEX mod_reg -> mod_rm */ 251 EVEX_MX, /* EVEX mod_rm -> mod_reg */ 252 EVEX_MBX, /* EVEX mod_rm/bcast -> mod_reg */ 253 EVEX_RMrX, /* EVEX EVEX.vvvv, mod_rm -> mod_reg */ 254 EVEX_RMBrX, /* EVEX EVEX.vvvv, mod_rm/bcast -> mod_reg */ 255 EVEX_RMRX, /* EVEX EVEX.vvvv, mod_rm, imm8 -> mod_reg */ 256 EVEX_RMrK, /* EVEX EVEX.vvvv, mod_rm -> opmask */ 257 }; 258 259 /* 260 * VEX prefixes 261 */ 262 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 263 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 264 265 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 266 267 /* 268 ** Register numbers for the i386 269 */ 270 #define EAX_REGNO 0 271 #define ECX_REGNO 1 272 #define EDX_REGNO 2 273 #define EBX_REGNO 3 274 #define ESP_REGNO 4 275 #define EBP_REGNO 5 276 #define ESI_REGNO 6 277 #define EDI_REGNO 7 278 279 /* 280 * modes for immediate values 281 */ 282 #define MODE_NONE 0 283 #define MODE_IPREL 1 /* signed IP relative value */ 284 #define MODE_SIGNED 2 /* sign extended immediate */ 285 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 286 #define MODE_OFFSET 4 /* offset part of an address */ 287 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 288 289 /* 290 * The letters used in these macros are: 291 * IND - indirect to another to another table 292 * "T" - means to Terminate indirections (this is the final opcode) 293 * "S" - means "operand length suffix required" 294 * "Sa" - means AVX2 suffix (q/d) required 295 * "Sq" - means AVX512 suffix (q/d) required 296 * "Sd" - means AVX512 suffix (d/s) required 297 * "Sb" - means AVX512 suffix (b/w) required 298 * "NS" - means "no suffix" which is the operand length suffix of the opcode 299 * "Z" - means instruction size arg required 300 * "u" - means the opcode is invalid in IA32 but valid in amd64 301 * "x" - means the opcode is invalid in amd64, but not IA32 302 * "y" - means the operand size is always 64 bits in 64 bit mode 303 * "p" - means push/pop stack operation 304 * "vr" - means VEX instruction that operates on normal registers, not fpu 305 * "vo" - means VEX instruction that operates on opmask registers, not fpu 306 */ 307 308 #define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling */ 309 #define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix handling */ 310 #define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix handling */ 311 #define AVS5B (uint_t)4 /* it_avxsuf: AVX512 b/w suffix handling */ 312 313 #if defined(DIS_TEXT) && defined(DIS_MEM) 314 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 315 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 316 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 317 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 318 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 319 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 320 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 321 #define TNSSb(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5B } 322 #define TNSSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q } 323 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 324 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 325 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} 326 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} 327 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 328 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 329 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 330 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 331 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 332 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2} 333 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q} 334 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D} 335 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 336 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 337 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 338 #elif defined(DIS_TEXT) 339 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 340 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 341 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 342 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 343 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 344 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 345 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 346 #define TNSSb(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5B } 347 #define TNSSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q } 348 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 349 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 350 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1} 351 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1} 352 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 353 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 354 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 355 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 356 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 357 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2} 358 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q} 359 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 360 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 361 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 362 #elif defined(DIS_MEM) 363 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 364 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 365 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 366 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 367 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 368 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 369 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 370 #define TNSSb(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5B } 371 #define TNSSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q } 372 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 373 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 374 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1} 375 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1} 376 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 377 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 378 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 379 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 380 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 381 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2} 382 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q} 383 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 384 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 385 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 386 #else 387 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 388 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 389 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 390 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 391 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 392 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 393 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 394 #define TNSSb(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5B } 395 #define TNSSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q } 396 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 397 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 398 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1} 399 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1} 400 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 401 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 402 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 403 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 404 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 405 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2} 406 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q} 407 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D} 408 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 409 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 410 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 411 #endif 412 413 #ifdef DIS_TEXT 414 /* 415 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 416 */ 417 const char *const dis_addr16[3][8] = { 418 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 419 "(%bx)", 420 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 421 "(%bx)", 422 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 423 "(%bx)", 424 }; 425 426 427 /* 428 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 429 */ 430 const char *const dis_addr32_mode0[16] = { 431 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 432 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 433 }; 434 435 const char *const dis_addr32_mode12[16] = { 436 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 437 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 438 }; 439 440 /* 441 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 442 */ 443 const char *const dis_addr64_mode0[16] = { 444 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 445 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 446 }; 447 const char *const dis_addr64_mode12[16] = { 448 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 449 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 450 }; 451 452 /* 453 * decode for scale from SIB byte 454 */ 455 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 456 457 /* 458 * decode for scale from VSIB byte, note that we always include the scale factor 459 * to match gas. 460 */ 461 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" }; 462 463 /* 464 * register decoding for normal references to registers (ie. not addressing) 465 */ 466 const char *const dis_REG8[16] = { 467 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 468 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 469 }; 470 471 const char *const dis_REG8_REX[16] = { 472 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 473 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 474 }; 475 476 const char *const dis_REG16[16] = { 477 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 478 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 479 }; 480 481 const char *const dis_REG32[16] = { 482 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 483 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 484 }; 485 486 const char *const dis_REG64[16] = { 487 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 488 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 489 }; 490 491 const char *const dis_DEBUGREG[16] = { 492 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 493 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 494 }; 495 496 const char *const dis_CONTROLREG[16] = { 497 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 498 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 499 }; 500 501 const char *const dis_TESTREG[16] = { 502 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 503 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 504 }; 505 506 const char *const dis_MMREG[16] = { 507 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 508 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 509 }; 510 511 const char *const dis_XMMREG[32] = { 512 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 513 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 514 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 515 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 516 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 517 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 518 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 519 "%xmm28", "%xmm29", "%xmm30", "%xmm31", 520 }; 521 522 const char *const dis_YMMREG[32] = { 523 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 524 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 525 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 526 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 527 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 528 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 529 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 530 "%ymm28", "%ymm29", "%ymm30", "%ymm31", 531 }; 532 533 const char *const dis_ZMMREG[32] = { 534 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 535 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 536 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 537 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 538 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 539 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 540 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 541 "%zmm28", "%zmm29", "%zmm30", "%zmm31", 542 }; 543 544 const char *const dis_KOPMASKREG[8] = { 545 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 546 }; 547 548 const char *const dis_SEGREG[16] = { 549 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 550 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 551 }; 552 553 /* 554 * SIMD predicate suffixes 555 */ 556 const char *const dis_PREDSUFFIX[8] = { 557 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 558 }; 559 560 const char *const dis_AVXvgrp7[3][8] = { 561 /*0 1 2 3 4 5 6 7*/ 562 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 563 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 564 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 565 }; 566 567 #endif /* DIS_TEXT */ 568 569 /* 570 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 571 */ 572 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 573 574 /* 575 * "decode table" for pause and clflush instructions 576 */ 577 const instable_t dis_opPause = TNS("pause", NORM); 578 579 /* 580 * "decode table" for wbnoinvd instruction 581 */ 582 const instable_t dis_opWbnoinvd = TNS("wbnoinvd", NORM); 583 584 /* 585 * Decode table for 0x0F00 opcodes 586 */ 587 const instable_t dis_op0F00[8] = { 588 589 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 590 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 591 }; 592 593 594 /* 595 * Decode table for 0x0F01 opcodes 596 */ 597 const instable_t dis_op0F01[8] = { 598 599 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 600 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 601 }; 602 603 /* 604 * Decode table for 0x0F18 opcodes -- SIMD prefetch 605 */ 606 const instable_t dis_op0F18[8] = { 607 608 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 609 /* [4] */ INVALID, INVALID, TNSu("prefetchit1",PREF),TNSu("prefetchit0",PREF), 610 }; 611 612 /* 613 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 614 */ 615 const instable_t dis_op0FAE[8] = { 616 /* [0] */ TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS), TNS("stmxcsr",FSGS), 617 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 618 }; 619 620 /* 621 * Decode table for 0xF30FAE opcodes -- FSGSBASE 622 */ 623 const instable_t dis_opF30FAE[8] = { 624 /* [0] */ TNSx("rdfsbase",FSGS), TNSx("rdgsbase",FSGS), TNSx("wrfsbase",FSGS), TNSx("wrgsbase",FSGS), 625 /* [4] */ INVALID, INVALID, INVALID, INVALID, 626 }; 627 628 /* 629 * Decode table for 0x0FBA opcodes 630 */ 631 632 const instable_t dis_op0FBA[8] = { 633 634 /* [0] */ INVALID, INVALID, INVALID, INVALID, 635 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 636 }; 637 638 /* 639 * Decode table for 0x0FC7 opcode (group 9) 640 */ 641 642 const instable_t dis_op0FC7[8] = { 643 644 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9), 645 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9), 646 }; 647 648 /* 649 * Decode table for 0x0FC7 opcode (group 9) mode 3 650 */ 651 652 const instable_t dis_op0FC7m3[8] = { 653 654 /* [0] */ INVALID, INVALID, INVALID, INVALID, 655 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9), 656 }; 657 658 /* 659 * Decode table for 0x0FC7 opcode with 0x66 prefix 660 */ 661 662 const instable_t dis_op660FC7[8] = { 663 664 /* [0] */ INVALID, INVALID, INVALID, INVALID, 665 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 666 }; 667 668 /* 669 * Decode table for 0x0FC7 opcode with 0xF3 prefix -- memory instructions 670 */ 671 672 const instable_t dis_opF30FC7[8] = { 673 674 /* [0] */ INVALID, INVALID, INVALID, INVALID, 675 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 676 }; 677 678 /* 679 * Decode table for 0x0FC7 opcode with 0xF3 prefix -- register instructions 680 */ 681 682 const instable_t dis_opF30FC7m3[8] = { 683 684 /* [0] */ INVALID, INVALID, INVALID, INVALID, 685 /* [4] */ INVALID, INVALID, INVALID, TNS("rdpid",RMATCH) 686 }; 687 688 /* 689 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 690 * 691 *bit pattern: 0000 1111 1100 1reg 692 */ 693 const instable_t dis_op0FC8[4] = { 694 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 695 }; 696 697 /* 698 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 699 */ 700 const instable_t dis_op0F7123[4][8] = { 701 { 702 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 703 /* .4 */ INVALID, INVALID, INVALID, INVALID, 704 }, { 705 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 706 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 707 }, { 708 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 709 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 710 }, { 711 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 712 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 713 } }; 714 715 /* 716 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 717 */ 718 const instable_t dis_opSIMD7123[32] = { 719 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 720 /* .4 */ INVALID, INVALID, INVALID, INVALID, 721 722 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 723 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 724 725 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 726 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 727 728 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 729 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 730 }; 731 732 /* 733 * SIMD instructions have been wedged into the existing IA32 instruction 734 * set through the use of prefixes. That is, while 0xf0 0x58 may be 735 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 736 * instruction - addss. At present, three prefixes have been coopted in 737 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 738 * following tables are used to provide the prefixed instruction names. 739 * The arrays are sparse, but they're fast. 740 */ 741 742 /* 743 * Decode table for SIMD instructions with the address size (0x66) prefix. 744 */ 745 const instable_t dis_opSIMDdata16[256] = { 746 /* [00] */ INVALID, INVALID, INVALID, INVALID, 747 /* [04] */ INVALID, INVALID, INVALID, INVALID, 748 /* [08] */ INVALID, INVALID, INVALID, INVALID, 749 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 750 751 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 752 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 753 /* [18] */ INVALID, INVALID, INVALID, INVALID, 754 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 755 756 /* [20] */ INVALID, INVALID, INVALID, INVALID, 757 /* [24] */ INVALID, INVALID, INVALID, INVALID, 758 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 759 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 760 761 /* [30] */ INVALID, INVALID, INVALID, INVALID, 762 /* [34] */ INVALID, INVALID, INVALID, INVALID, 763 /* [38] */ INVALID, INVALID, INVALID, INVALID, 764 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 765 766 /* [40] */ INVALID, INVALID, INVALID, INVALID, 767 /* [44] */ INVALID, INVALID, INVALID, INVALID, 768 /* [48] */ INVALID, INVALID, INVALID, INVALID, 769 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 770 771 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 772 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 773 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 774 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 775 776 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 777 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 778 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 779 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 780 781 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 782 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 783 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 784 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 785 786 /* [80] */ INVALID, INVALID, INVALID, INVALID, 787 /* [84] */ INVALID, INVALID, INVALID, INVALID, 788 /* [88] */ INVALID, INVALID, INVALID, INVALID, 789 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 790 791 /* [90] */ INVALID, INVALID, INVALID, INVALID, 792 /* [94] */ INVALID, INVALID, INVALID, INVALID, 793 /* [98] */ INVALID, INVALID, INVALID, INVALID, 794 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 795 796 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 797 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 798 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 799 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 800 801 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 802 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 803 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 804 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 805 806 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 807 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 808 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 809 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 810 811 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 812 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 813 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 814 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 815 816 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 817 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 818 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 819 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 820 821 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 822 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 823 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 824 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 825 }; 826 827 const instable_t dis_opAVX660F[256] = { 828 /* [00] */ INVALID, INVALID, INVALID, INVALID, 829 /* [04] */ INVALID, INVALID, INVALID, INVALID, 830 /* [08] */ INVALID, INVALID, INVALID, INVALID, 831 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 832 833 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 834 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 835 /* [18] */ INVALID, INVALID, INVALID, INVALID, 836 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 837 838 /* [20] */ INVALID, INVALID, INVALID, INVALID, 839 /* [24] */ INVALID, INVALID, INVALID, INVALID, 840 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 841 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 842 843 /* [30] */ INVALID, INVALID, INVALID, INVALID, 844 /* [34] */ INVALID, INVALID, INVALID, INVALID, 845 /* [38] */ INVALID, INVALID, INVALID, INVALID, 846 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 847 848 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 849 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 850 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 851 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 852 853 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 854 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 855 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 856 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 857 858 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 859 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 860 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 861 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 862 863 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 864 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 865 /* [78] */ INVALID, INVALID, INVALID, INVALID, 866 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 867 868 /* [80] */ INVALID, INVALID, INVALID, INVALID, 869 /* [84] */ INVALID, INVALID, INVALID, INVALID, 870 /* [88] */ INVALID, INVALID, INVALID, INVALID, 871 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 872 873 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 874 /* [94] */ INVALID, INVALID, INVALID, INVALID, 875 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 876 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 877 878 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 879 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 880 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 881 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 882 883 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 884 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 885 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 886 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 887 888 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 889 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 890 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 891 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 892 893 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 894 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 895 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 896 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 897 898 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 899 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 900 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 901 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 902 903 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 904 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 905 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 906 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 907 }; 908 909 /* 910 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 911 */ 912 const instable_t dis_opSIMDrepnz[256] = { 913 /* [00] */ INVALID, INVALID, INVALID, INVALID, 914 /* [04] */ INVALID, INVALID, INVALID, INVALID, 915 /* [08] */ INVALID, INVALID, INVALID, INVALID, 916 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 917 918 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID, 919 /* [14] */ INVALID, INVALID, INVALID, INVALID, 920 /* [18] */ INVALID, INVALID, INVALID, INVALID, 921 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 922 923 /* [20] */ INVALID, INVALID, INVALID, INVALID, 924 /* [24] */ INVALID, INVALID, INVALID, INVALID, 925 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 926 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 927 928 /* [30] */ INVALID, INVALID, INVALID, INVALID, 929 /* [34] */ INVALID, INVALID, INVALID, INVALID, 930 /* [38] */ INVALID, INVALID, INVALID, INVALID, 931 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 932 933 /* [40] */ INVALID, INVALID, INVALID, INVALID, 934 /* [44] */ INVALID, INVALID, INVALID, INVALID, 935 /* [48] */ INVALID, INVALID, INVALID, INVALID, 936 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 937 938 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 939 /* [54] */ INVALID, INVALID, INVALID, INVALID, 940 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 941 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 942 943 /* [60] */ INVALID, INVALID, INVALID, INVALID, 944 /* [64] */ INVALID, INVALID, INVALID, INVALID, 945 /* [68] */ INVALID, INVALID, INVALID, INVALID, 946 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 947 948 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 949 /* [74] */ INVALID, INVALID, INVALID, INVALID, 950 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 951 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID, 952 953 /* [80] */ INVALID, INVALID, INVALID, INVALID, 954 /* [84] */ INVALID, INVALID, INVALID, INVALID, 955 /* [88] */ INVALID, INVALID, INVALID, INVALID, 956 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 957 958 /* [90] */ INVALID, INVALID, INVALID, INVALID, 959 /* [94] */ INVALID, INVALID, INVALID, INVALID, 960 /* [98] */ INVALID, INVALID, INVALID, INVALID, 961 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 962 963 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 964 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 965 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 966 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 967 968 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 969 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 970 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 971 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 972 973 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 974 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 975 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 976 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 977 978 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID, 979 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 980 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 981 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 982 983 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 984 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 985 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 986 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 987 988 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID, 989 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 990 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 991 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 992 }; 993 994 const instable_t dis_opAVXF20F[256] = { 995 /* [00] */ INVALID, INVALID, INVALID, INVALID, 996 /* [04] */ INVALID, INVALID, INVALID, INVALID, 997 /* [08] */ INVALID, INVALID, INVALID, INVALID, 998 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 999 1000 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 1001 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1002 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1003 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1004 1005 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1006 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1007 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 1008 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 1009 1010 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1011 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1012 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1013 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1014 1015 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1016 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1017 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1018 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1019 1020 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 1021 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1022 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 1023 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 1024 1025 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1026 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1027 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1028 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1029 1030 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 1031 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1032 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1033 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 1034 1035 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1036 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1037 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1038 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1039 1040 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 1041 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1042 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1043 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1044 1045 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1046 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1047 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1048 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1049 1050 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1051 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1052 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1053 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1054 1055 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 1056 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1057 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1058 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1059 1060 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 1061 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1062 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1063 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1064 1065 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1066 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 1067 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1068 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1069 1070 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 1071 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1072 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1073 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1074 }; 1075 1076 const instable_t dis_opAVXF20F3A[256] = { 1077 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1078 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1079 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1080 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1081 1082 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1083 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1084 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1085 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1086 1087 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1088 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1089 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1090 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1091 1092 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1093 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1094 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1095 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1096 1097 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1098 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1099 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1100 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1101 1102 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1103 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1104 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1105 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1106 1107 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1108 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1109 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1110 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1111 1112 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1113 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1114 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1115 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1116 1117 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1118 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1119 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1120 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1121 1122 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1123 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1124 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1125 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1126 1127 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1128 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1129 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1130 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1131 1132 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1133 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1134 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1135 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1136 1137 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1138 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1139 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1140 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1141 1142 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1143 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1144 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1145 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1146 1147 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1148 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1149 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1150 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1151 1152 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID, 1153 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1154 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1155 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1156 }; 1157 1158 const instable_t dis_opAVXF20F38[256] = { 1159 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1160 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1161 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1162 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1163 1164 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1165 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1166 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1167 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1168 1169 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1170 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1171 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1172 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1173 1174 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1175 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1176 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1177 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1178 1179 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1180 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1181 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1182 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1183 1184 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1185 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1186 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1187 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1188 1189 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1190 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1191 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1192 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1193 1194 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1195 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1196 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1197 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1198 1199 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1200 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1201 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1202 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1203 1204 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1205 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1206 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1207 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1208 1209 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1210 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1211 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1212 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1213 1214 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1215 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1216 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1217 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1218 1219 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1220 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1221 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1222 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1223 1224 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1225 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1226 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1227 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1228 1229 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1230 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1231 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1232 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1233 1234 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1235 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5), 1236 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1237 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1238 }; 1239 1240 const instable_t dis_opAVXF30F38[256] = { 1241 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1242 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1243 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1244 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1245 1246 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1247 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1248 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1250 1251 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1252 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1253 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1254 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1255 1256 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1257 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1258 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1260 1261 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1262 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1263 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1265 1266 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1267 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1268 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1270 1271 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1272 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1273 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1275 1276 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1277 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1278 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1279 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1280 1281 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1282 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1283 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1285 1286 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1287 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1288 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1290 1291 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1292 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1293 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1294 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1295 1296 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1297 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1298 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1299 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1300 1301 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1302 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1303 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1304 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1305 1306 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1307 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1308 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1309 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1310 1311 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1312 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1313 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1314 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1315 1316 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1317 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5), 1318 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1319 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1320 }; 1321 /* 1322 * Decode table for SIMD instructions with the repz (0xf3) prefix. 1323 */ 1324 const instable_t dis_opSIMDrepz[256] = { 1325 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1326 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1327 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1328 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1329 1330 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID, 1331 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID, 1332 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1333 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1334 1335 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1336 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1337 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 1338 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 1339 1340 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1341 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1342 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1343 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1344 1345 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1346 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1347 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1348 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1349 1350 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 1351 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1352 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 1353 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 1354 1355 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1356 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1357 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1358 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 1359 1360 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1361 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1362 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1363 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1364 1365 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1366 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1367 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1368 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1369 1370 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1371 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1372 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1373 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1374 1375 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1376 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1377 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1378 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1379 1380 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1381 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1382 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1383 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID, 1384 1385 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1386 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1387 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1388 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1389 1390 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1391 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1392 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1393 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1394 1395 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1396 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1397 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1398 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1399 1400 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1401 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1402 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1403 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1404 }; 1405 1406 const instable_t dis_opAVXF30F[256] = { 1407 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1408 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1409 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1410 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1411 1412 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1413 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1414 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1415 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1416 1417 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1418 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1419 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1420 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1421 1422 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1423 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1424 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1425 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1426 1427 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1428 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1429 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1430 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1431 1432 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1433 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1434 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1435 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1436 1437 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1438 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1439 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1440 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1441 1442 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1443 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1444 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1445 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1446 1447 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1448 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1449 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1450 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1451 1452 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1453 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1454 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1455 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1456 1457 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1458 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1459 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1460 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1461 1462 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1463 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1464 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1465 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1466 1467 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1468 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1469 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1470 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1471 1472 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1473 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1474 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1475 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1476 1477 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1478 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1479 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1480 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1481 1482 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1483 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1484 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1485 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1486 }; 1487 1488 /* 1489 * Table for instructions with an EVEX prefix followed by 0F. 1490 */ 1491 const instable_t dis_opEVEX0F[256] = { 1492 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1493 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1494 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1495 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1496 1497 /* [10] */ TNS("vmovups",EVEX_MX), TNS("vmovups",EVEX_RX), INVALID, INVALID, 1498 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1499 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1500 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1501 1502 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1503 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1504 /* [28] */ TNS("vmovaps",EVEX_MX), TNS("vmovaps",EVEX_RX), INVALID, INVALID, 1505 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1506 1507 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1508 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1509 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1510 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1511 1512 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1513 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1514 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1515 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1516 1517 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1518 /* [54] */ TNS("vandps",EVEX_RMrX),TNS("vandnps",EVEX_RMrX),TNS("vorps",EVEX_RMrX),TNS("vxorps",EVEX_RMrX), 1519 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1520 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1521 1522 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1523 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1524 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1525 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1526 1527 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1528 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1529 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1530 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1531 1532 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1533 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1534 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1535 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1536 1537 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1538 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1539 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1540 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1541 1542 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1543 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1544 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1545 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1546 1547 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1548 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1549 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1550 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1551 1552 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1553 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1554 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1555 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1556 1557 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1558 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1559 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1560 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1561 1562 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1563 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1564 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1565 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1566 1567 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1568 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1569 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1570 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1571 }; 1572 1573 /* 1574 * Decode tables for EVEX 66 0F 1575 */ 1576 const instable_t dis_opEVEX660F[256] = { 1577 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1578 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1579 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1580 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1581 1582 /* [10] */ TNS("vmovupd",EVEX_MX), TNS("vmovupd",EVEX_RX), INVALID, INVALID, 1583 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1584 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1585 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1586 1587 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1588 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1589 /* [28] */ TNS("vmovapd",EVEX_MX), TNS("vmovapd",EVEX_RX), INVALID, INVALID, 1590 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1591 1592 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1593 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1594 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1595 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1596 1597 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1598 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1599 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1600 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1601 1602 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1603 /* [54] */ TNS("vandpd",EVEX_RMrX),TNS("vandnpd",EVEX_RMrX),TNS("vorpd",EVEX_RMrX),TNS("vxorpd",EVEX_RMrX), 1604 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1605 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1606 1607 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1608 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1609 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1610 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqa",EVEX_MX), 1611 1612 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1613 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1614 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1615 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqa",EVEX_RX), 1616 1617 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1618 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1619 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1620 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1621 1622 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1623 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1624 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1625 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1626 1627 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1628 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1629 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1630 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1631 1632 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1633 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1634 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1635 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1636 1637 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1638 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1639 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1640 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1641 1642 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1643 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1644 /* [D8] */ INVALID, INVALID, INVALID, TSq("vpand",EVEX_RMrX), 1645 /* [DC] */ INVALID, INVALID, INVALID, TSq("vpandn",EVEX_RMrX), 1646 1647 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1648 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1649 /* [E8] */ INVALID, INVALID, INVALID, TSq("vpor",EVEX_RMrX), 1650 /* [EC] */ INVALID, INVALID, INVALID, TSq("vpxor",EVEX_RMrX), 1651 1652 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1653 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1654 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1655 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1656 }; 1657 1658 const instable_t dis_opEVEX660F38[256] = { 1659 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1660 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1661 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1662 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1663 1664 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1665 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1666 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1667 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1668 1669 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1670 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1671 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1672 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1673 1674 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1675 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1676 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1677 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1678 1679 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1680 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1681 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1682 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1683 1684 /* [50] */ TNSZ("vpdpbusd",EVEX_RMBrX,16),TNSZ("vpdpbusds",EVEX_RMBrX,16),TNSZ("vpdpwssd",EVEX_RMBrX,16),TNSZ("vpdpwssds",EVEX_RMBrX,16), 1685 /* [54] */ TNSSb("vpopcnt",EVEX_MX),TNSSq("vpopcnt",EVEX_MBX),INVALID, INVALID, 1686 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1687 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1688 1689 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1690 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1691 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1692 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1693 1694 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1695 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1696 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1697 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1698 1699 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1700 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1701 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1702 /* [8C] */ INVALID, INVALID, INVALID, TNS("vpshufbitqmb",EVEX_RMrK), 1703 1704 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1705 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1706 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1707 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1708 1709 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1710 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1711 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1712 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1713 1714 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1715 /* [B4] */ TNS("vpmadd52luq",EVEX_RMBrX),TNS("vpmadd52huq",EVEX_RMBrX),INVALID, INVALID, 1716 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1717 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1718 1719 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1720 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1721 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1722 /* [CC] */ INVALID, INVALID, INVALID, TNS("vgf2p8mulb",EVEX_RMrX), 1723 1724 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1725 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1726 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1727 /* [DC] */ TNSZ("vaesenc",EVEX_RMrX,16),TNSZ("vaesenclast",EVEX_RMrX,16),TNSZ("vaesdec",EVEX_RMrX,16),TNSZ("vaesdeclast",EVEX_RMrX,16), 1728 1729 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1730 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1731 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1732 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1733 1734 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1735 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1736 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1737 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1738 }; 1739 1740 const instable_t dis_opEVEX660F3A[256] = { 1741 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1742 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1743 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1744 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1745 1746 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1747 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1748 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1749 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1750 1751 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1752 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1753 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1754 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1755 1756 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1757 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1758 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1759 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1760 1761 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1762 /* [44] */ TNSZ("vpclmulqdq",EVEX_RMRX,16),INVALID, INVALID, INVALID, 1763 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1764 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1765 1766 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1767 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1768 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1769 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1770 1771 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1772 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1773 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1774 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1775 1776 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1777 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1778 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1779 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1780 1781 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1782 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1783 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1784 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1785 1786 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1787 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1788 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1789 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1790 1791 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1792 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1793 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1794 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1795 1796 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1797 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1798 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1799 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1800 1801 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1802 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1803 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1804 /* [CC] */ INVALID, INVALID, TNS("vgf2p8affineqb",EVEX_RMRX),TNS("vgf2p8affineinvqb",EVEX_RMRX), 1805 1806 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1807 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1808 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1809 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1810 1811 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1812 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1813 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1814 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1815 1816 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1817 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1818 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1819 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1820 }; 1821 1822 1823 const instable_t dis_opEVEXF20F[256] = { 1824 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1825 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1826 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1827 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1828 1829 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1830 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1831 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1832 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1833 1834 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1835 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1836 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1837 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1838 1839 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1840 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1841 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1842 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1843 1844 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1845 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1846 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1847 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1848 1849 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1850 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1851 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1852 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1853 1854 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1855 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1856 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1857 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_MX), 1858 1859 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1860 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1861 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1862 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_RX), 1863 1864 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1865 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1866 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1867 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1868 1869 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1870 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1871 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1872 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1873 1874 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1875 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1876 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1877 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1878 1879 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1880 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1881 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1882 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1883 1884 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1885 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1886 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1887 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1888 1889 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1890 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1891 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1892 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1893 1894 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1895 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1896 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1897 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1898 1899 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1900 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1901 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1902 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1903 }; 1904 1905 const instable_t dis_opEVEXF20F38[256] = { 1906 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1907 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1908 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1909 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1910 1911 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1912 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1913 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1914 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1915 1916 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1917 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1918 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1919 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1920 1921 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1922 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1923 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1924 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1925 1926 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1927 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1928 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1929 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1930 1931 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1932 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1933 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1934 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1935 1936 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1937 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1938 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1939 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1940 1941 /* [70] */ INVALID, INVALID, TNS("vcvtneps2bf16",EVEX_RMBrX),INVALID, 1942 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1943 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1944 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1945 1946 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1947 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1948 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1949 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1950 1951 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1952 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1953 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1954 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1955 1956 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1957 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1958 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1959 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1960 1961 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1962 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1963 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1964 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1965 1966 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1967 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1968 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1969 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1970 1971 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1972 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1973 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1974 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1975 1976 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1977 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1978 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1979 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1980 1981 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1982 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1983 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1984 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1985 }; 1986 1987 const instable_t dis_opEVEXF30F[256] = { 1988 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1989 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1990 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1991 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1992 1993 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1994 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1995 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1996 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1997 1998 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1999 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2000 /* [28] */ INVALID, INVALID, INVALID, INVALID, 2001 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2002 2003 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2004 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2005 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2006 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2007 2008 /* [40] */ INVALID, INVALID, INVALID, INVALID, 2009 /* [44] */ INVALID, INVALID, INVALID, INVALID, 2010 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2011 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2012 2013 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2014 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2015 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2016 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2017 2018 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2019 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2020 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2021 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_MX), 2022 2023 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2024 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2025 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2026 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_RX), 2027 2028 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2029 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2030 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2031 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 2032 2033 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2034 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2035 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2036 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2037 2038 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2039 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2040 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2041 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2042 2043 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2044 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2045 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2046 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2047 2048 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2049 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2050 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2051 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2052 2053 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2054 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2055 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2056 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2057 2058 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2059 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2060 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2061 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2062 2063 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 2064 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 2065 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2066 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2067 }; 2068 2069 const instable_t dis_opEVEXF30F38[256] = { 2070 /* [00] */ INVALID, INVALID, INVALID, INVALID, 2071 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2072 /* [08] */ INVALID, INVALID, INVALID, INVALID, 2073 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 2074 2075 /* [10] */ INVALID, INVALID, INVALID, INVALID, 2076 /* [14] */ INVALID, INVALID, INVALID, INVALID, 2077 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2078 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 2079 2080 /* [20] */ INVALID, INVALID, INVALID, INVALID, 2081 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2082 /* [28] */ INVALID, INVALID, INVALID, INVALID, 2083 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2084 2085 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2086 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2087 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2088 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2089 2090 /* [40] */ INVALID, INVALID, INVALID, INVALID, 2091 /* [44] */ INVALID, INVALID, INVALID, INVALID, 2092 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2093 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2094 2095 /* [50] */ INVALID, INVALID, TNS("vdpbf16ps",EVEX_RMBrX),INVALID, 2096 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2097 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2098 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2099 2100 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2101 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2102 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2103 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2104 2105 /* [70] */ INVALID, INVALID, TNS("vcvtneps2bf16",EVEX_MBX),INVALID, 2106 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2107 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2108 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2109 2110 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2111 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2112 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2113 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 2114 2115 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2116 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2117 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2118 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2119 2120 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2121 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2122 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2123 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2124 2125 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2126 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2127 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2128 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2129 2130 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2131 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2132 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2133 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2134 2135 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2136 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2137 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2138 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2139 2140 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2141 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2142 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2143 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2144 2145 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 2146 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 2147 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2148 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2149 }; 2150 2151 2152 /* 2153 * The following two tables are used to encode crc32 and movbe 2154 * since they share the same opcodes. 2155 */ 2156 const instable_t dis_op0F38F0[2] = { 2157 /* [00] */ TNS("crc32b",CRC32), 2158 TS("movbe",MOVBE), 2159 }; 2160 2161 const instable_t dis_op0F38F1[2] = { 2162 /* [00] */ TS("crc32",CRC32), 2163 TS("movbe",MOVBE), 2164 }; 2165 2166 /* 2167 * The following table is used to distinguish between adox and adcx which share 2168 * the same opcodes. 2169 */ 2170 const instable_t dis_op0F38F6[2] = { 2171 /* [00] */ TNS("adcx",ADX), 2172 TNS("adox",ADX), 2173 }; 2174 2175 const instable_t dis_op0F38[256] = { 2176 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 2177 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 2178 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 2179 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 2180 2181 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 2182 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 2183 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2184 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 2185 2186 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 2187 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 2188 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 2189 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2190 2191 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 2192 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 2193 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 2194 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 2195 2196 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 2197 /* [44] */ INVALID, INVALID, INVALID, INVALID, 2198 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2199 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2200 2201 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2202 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2203 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2204 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2205 2206 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2207 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2208 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2209 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2210 2211 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2212 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2213 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2214 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2215 2216 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID, 2217 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2218 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2219 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2220 2221 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2222 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2223 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2224 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2225 2226 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2227 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2228 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2229 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2230 2231 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2232 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2233 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2234 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2235 2236 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2237 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2238 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16), 2239 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, TNS("gf2p8mulb",XMM_66r), 2240 2241 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2242 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2243 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 2244 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 2245 2246 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2247 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2248 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2249 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2250 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 2251 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID, 2252 /* [F8] */ TNS("movdir64b",MOVDIR),TNS("movdiri",RM), INVALID, INVALID, 2253 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2254 }; 2255 2256 const instable_t dis_opAVX660F38[256] = { 2257 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 2258 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 2259 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 2260 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 2261 2262 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 2263 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16), 2264 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 2265 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 2266 2267 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 2268 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 2269 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 2270 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 2271 2272 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 2273 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16), 2274 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 2275 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 2276 2277 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 2278 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16), 2279 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2280 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2281 2282 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2283 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2284 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID, 2285 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2286 2287 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2288 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2289 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2290 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2291 2292 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2293 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2294 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID, 2295 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2296 2297 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2298 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2299 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2300 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID, 2301 2302 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16), 2303 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 2304 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 2305 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16), 2306 2307 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2308 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16), 2309 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16), 2310 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16), 2311 2312 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2313 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16), 2314 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16), 2315 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16), 2316 2317 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2318 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2319 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2320 /* [CC] */ INVALID, INVALID, INVALID, TNS("vgf2p8mulb",VEX_RMrX), 2321 2322 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2323 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2324 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 2325 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 2326 2327 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2328 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2329 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2330 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2331 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 2332 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5), 2333 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2334 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2335 }; 2336 2337 const instable_t dis_op0F3A[256] = { 2338 /* [00] */ INVALID, INVALID, INVALID, INVALID, 2339 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2340 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 2341 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 2342 2343 /* [10] */ INVALID, INVALID, INVALID, INVALID, 2344 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 2345 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2346 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 2347 2348 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 2349 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2350 /* [28] */ INVALID, INVALID, INVALID, INVALID, 2351 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2352 2353 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2354 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2355 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2356 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2357 2358 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 2359 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 2360 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2361 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2362 2363 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2364 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2365 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2366 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2367 2368 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 2369 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2370 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2371 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2372 2373 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2374 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2375 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2376 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2377 2378 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2379 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2380 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2381 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2382 2383 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2384 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2385 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2386 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2387 2388 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2389 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2390 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2391 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2392 2393 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2394 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2395 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2396 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2397 2398 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2399 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2400 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2401 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, TNS("gf2p8affineqb",XMMP_66r),TNS("gf2p8affineinvqb",XMMP_66r), 2402 2403 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2404 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2405 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2406 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 2407 2408 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2409 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2410 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2411 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2412 2413 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 2414 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 2415 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2416 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2417 }; 2418 2419 const instable_t dis_opAVX660F3A[256] = { 2420 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID, 2421 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 2422 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 2423 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 2424 2425 /* [10] */ INVALID, INVALID, INVALID, INVALID, 2426 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 2427 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 2428 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 2429 2430 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 2431 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2432 /* [28] */ INVALID, INVALID, INVALID, INVALID, 2433 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2434 2435 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI), 2436 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2437 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID, 2438 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2439 2440 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 2441 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID, 2442 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 2443 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 2444 2445 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2446 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2447 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2448 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2449 2450 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 2451 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2452 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2453 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2454 2455 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2456 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2457 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2458 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2459 2460 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2461 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2462 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2463 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2464 2465 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2466 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2467 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2468 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2469 2470 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2471 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2472 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2473 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2474 2475 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2476 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2477 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2478 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2479 2480 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2481 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2482 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2483 /* [CC] */ INVALID, INVALID, TNS("vgf2p8affineqb",VEX_RMRX),TNS("vgf2p8affineinvqb",VEX_RMRX), 2484 2485 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2486 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2487 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2488 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 2489 2490 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2491 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2492 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2493 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2494 2495 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 2496 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 2497 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2498 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2499 }; 2500 2501 /* 2502 * Decode table for 0x0F0D which uses the first byte of the mod_rm to 2503 * indicate a sub-code. 2504 */ 2505 const instable_t dis_op0F0D[8] = { 2506 /* [00] */ TNS("prefetch",PREF), TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID, 2507 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2508 }; 2509 2510 /* 2511 * Decode table for 0x0F opcodes 2512 */ 2513 2514 const instable_t dis_op0F[16][16] = { 2515 { 2516 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 2517 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 2518 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 2519 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID, 2520 }, { 2521 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 2522 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 2523 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 2524 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 2525 }, { 2526 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 2527 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 2528 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 2529 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 2530 }, { 2531 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 2532 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID, 2533 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2534 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2535 }, { 2536 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 2537 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 2538 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 2539 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 2540 }, { 2541 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 2542 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 2543 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 2544 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 2545 }, { 2546 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 2547 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 2548 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 2549 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 2550 }, { 2551 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 2552 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 2553 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 2554 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 2555 }, { 2556 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 2557 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 2558 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 2559 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 2560 }, { 2561 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 2562 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 2563 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 2564 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 2565 }, { 2566 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 2567 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 2568 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 2569 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 2570 }, { 2571 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 2572 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 2573 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 2574 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 2575 }, { 2576 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 2577 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 2578 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2579 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2580 }, { 2581 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 2582 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 2583 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 2584 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 2585 }, { 2586 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 2587 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 2588 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 2589 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 2590 }, { 2591 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 2592 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 2593 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 2594 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 2595 } }; 2596 2597 const instable_t dis_opAVX0F[16][16] = { 2598 { 2599 /* [00] */ INVALID, INVALID, INVALID, INVALID, 2600 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2601 /* [08] */ INVALID, INVALID, INVALID, INVALID, 2602 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 2603 }, { 2604 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 2605 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 2606 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2607 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 2608 }, { 2609 /* [20] */ INVALID, INVALID, INVALID, INVALID, 2610 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2611 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 2612 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 2613 }, { 2614 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2615 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2616 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2617 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2618 }, { 2619 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 2620 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 2621 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 2622 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2623 }, { 2624 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 2625 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 2626 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 2627 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 2628 }, { 2629 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2630 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2631 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2632 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2633 }, { 2634 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2635 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 2636 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2637 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2638 }, { 2639 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2640 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2641 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2642 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2643 }, { 2644 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 2645 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2646 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 2647 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2648 }, { 2649 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2650 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2651 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2652 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 2653 }, { 2654 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2655 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2656 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2657 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2658 }, { 2659 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 2660 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 2661 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2662 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2663 }, { 2664 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2665 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2666 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2667 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2668 }, { 2669 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2670 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2671 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2672 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2673 }, { 2674 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5), 2675 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5), 2676 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2677 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2678 } }; 2679 2680 /* 2681 * Decode table for 0x80 opcodes 2682 */ 2683 2684 const instable_t dis_op80[8] = { 2685 2686 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 2687 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 2688 }; 2689 2690 2691 /* 2692 * Decode table for 0x81 opcodes. 2693 */ 2694 2695 const instable_t dis_op81[8] = { 2696 2697 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 2698 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 2699 }; 2700 2701 2702 /* 2703 * Decode table for 0x82 opcodes. 2704 */ 2705 2706 const instable_t dis_op82[8] = { 2707 2708 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 2709 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 2710 }; 2711 /* 2712 * Decode table for 0x83 opcodes. 2713 */ 2714 2715 const instable_t dis_op83[8] = { 2716 2717 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 2718 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 2719 }; 2720 2721 /* 2722 * Decode table for 0xC0 opcodes. 2723 */ 2724 2725 const instable_t dis_opC0[8] = { 2726 2727 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 2728 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 2729 }; 2730 2731 /* 2732 * Decode table for 0xD0 opcodes. 2733 */ 2734 2735 const instable_t dis_opD0[8] = { 2736 2737 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2738 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2739 }; 2740 2741 /* 2742 * Decode table for 0xC1 opcodes. 2743 * 186 instruction set 2744 */ 2745 2746 const instable_t dis_opC1[8] = { 2747 2748 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 2749 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 2750 }; 2751 2752 /* 2753 * Decode table for 0xD1 opcodes. 2754 */ 2755 2756 const instable_t dis_opD1[8] = { 2757 2758 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2759 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 2760 }; 2761 2762 2763 /* 2764 * Decode table for 0xD2 opcodes. 2765 */ 2766 2767 const instable_t dis_opD2[8] = { 2768 2769 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2770 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2771 }; 2772 /* 2773 * Decode table for 0xD3 opcodes. 2774 */ 2775 2776 const instable_t dis_opD3[8] = { 2777 2778 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2779 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 2780 }; 2781 2782 2783 /* 2784 * Decode table for 0xF6 opcodes. 2785 */ 2786 2787 const instable_t dis_opF6[8] = { 2788 2789 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 2790 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 2791 }; 2792 2793 2794 /* 2795 * Decode table for 0xF7 opcodes. 2796 */ 2797 2798 const instable_t dis_opF7[8] = { 2799 2800 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 2801 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 2802 }; 2803 2804 2805 /* 2806 * Decode table for 0xFE opcodes. 2807 */ 2808 2809 const instable_t dis_opFE[8] = { 2810 2811 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 2812 /* [4] */ INVALID, INVALID, INVALID, INVALID, 2813 }; 2814 /* 2815 * Decode table for 0xFF opcodes. 2816 */ 2817 2818 const instable_t dis_opFF[8] = { 2819 2820 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 2821 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 2822 }; 2823 2824 /* for 287 instructions, which are a mess to decode */ 2825 2826 const instable_t dis_opFP1n2[8][8] = { 2827 { 2828 /* bit pattern: 1101 1xxx MODxx xR/M */ 2829 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 2830 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 2831 }, { 2832 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 2833 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 2834 }, { 2835 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 2836 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 2837 }, { 2838 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M), 2839 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 2840 }, { 2841 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 2842 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 2843 }, { 2844 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 2845 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 2846 }, { 2847 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 2848 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 2849 }, { 2850 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2), 2851 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 2852 } }; 2853 2854 const instable_t dis_opFP3[8][8] = { 2855 { 2856 /* bit pattern: 1101 1xxx 11xx xREG */ 2857 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2858 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2859 }, { 2860 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 2861 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 2862 }, { 2863 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 2864 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 2865 }, { 2866 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 2867 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 2868 }, { 2869 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2870 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2871 }, { 2872 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 2873 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 2874 }, { 2875 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 2876 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 2877 }, { 2878 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 2879 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 2880 } }; 2881 2882 const instable_t dis_opFP4[4][8] = { 2883 { 2884 /* bit pattern: 1101 1001 111x xxxx */ 2885 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 2886 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 2887 }, { 2888 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 2889 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 2890 }, { 2891 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 2892 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 2893 }, { 2894 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 2895 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 2896 } }; 2897 2898 const instable_t dis_opFP5[8] = { 2899 /* bit pattern: 1101 1011 111x xxxx */ 2900 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 2901 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 2902 }; 2903 2904 const instable_t dis_opFP6[8] = { 2905 /* bit pattern: 1101 1011 11yy yxxx */ 2906 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 2907 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 2908 }; 2909 2910 const instable_t dis_opFP7[8] = { 2911 /* bit pattern: 1101 1010 11yy yxxx */ 2912 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 2913 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2914 }; 2915 2916 /* 2917 * Main decode table for the op codes. The first two nibbles 2918 * will be used as an index into the table. If there is a 2919 * a need to further decode an instruction, the array to be 2920 * referenced is indicated with the other two entries being 2921 * empty. 2922 */ 2923 2924 const instable_t dis_distable[16][16] = { 2925 { 2926 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 2927 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 2928 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 2929 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 2930 }, { 2931 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 2932 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 2933 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 2934 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 2935 }, { 2936 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 2937 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 2938 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 2939 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 2940 }, { 2941 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 2942 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 2943 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 2944 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 2945 }, { 2946 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2947 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2948 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2949 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2950 }, { 2951 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2952 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2953 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2954 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2955 }, { 2956 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw), 2957 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 2958 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 2959 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 2960 }, { 2961 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 2962 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 2963 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 2964 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 2965 }, { 2966 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 2967 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 2968 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 2969 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 2970 }, { 2971 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2972 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2973 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 2974 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM), 2975 }, { 2976 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 2977 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 2978 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 2979 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 2980 }, { 2981 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2982 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2983 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2984 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2985 }, { 2986 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 2987 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 2988 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 2989 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 2990 }, { 2991 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 2992 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 2993 2994 /* 287 instructions. Note that although the indirect field */ 2995 /* indicates opFP1n2 for further decoding, this is not necessarily */ 2996 /* the case since the opFP arrays are not partitioned according to key1 */ 2997 /* and key2. opFP1n2 is given only to indicate that we haven't */ 2998 /* finished decoding the instruction. */ 2999 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 3000 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 3001 }, { 3002 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 3003 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 3004 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 3005 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 3006 }, { 3007 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 3008 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 3009 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 3010 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 3011 } }; 3012 3013 /* END CSTYLED */ 3014 3015 /* 3016 * common functions to decode and disassemble an x86 or amd64 instruction 3017 */ 3018 3019 /* 3020 * These are the individual fields of a REX prefix. Note that a REX 3021 * prefix with none of these set is still needed to: 3022 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 3023 * - access the %sil, %dil, %bpl, %spl registers 3024 */ 3025 #define REX_W 0x08 /* 64 bit operand size when set */ 3026 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 3027 #define REX_X 0x02 /* high order bit extension of SIB index field */ 3028 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 3029 3030 /* 3031 * These are the individual fields of a VEX/EVEX prefix. 3032 */ 3033 #define VEX_R 0x08 /* REX.R in 1's complement form */ 3034 #define VEX_X 0x04 /* REX.X in 1's complement form */ 3035 #define VEX_B 0x02 /* REX.B in 1's complement form */ 3036 3037 /* Additional EVEX prefix definitions */ 3038 #define EVEX_R 0x01 /* REX.R' in 1's complement form */ 3039 #define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */ 3040 #define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */ 3041 3042 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 3043 #define VEX_L 0x04 3044 #define EVEX_B 0x01 /* Embedded Broadcast, RC, SAE context */ 3045 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */ 3046 #define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */ 3047 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 3048 #define VEX_m 0x1F /* VEX m-mmmm field */ 3049 #define EVEX_m 0x3 /* EVEX mm field */ 3050 #define VEX_v 0x78 /* VEX/EVEX register specifier */ 3051 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 3052 #define EVEX_V 0x8 /* EVEX.V' field, register extension */ 3053 3054 /* VEX m-mmmm field, only used by three bytes prefix */ 3055 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 3056 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 3057 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 3058 3059 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 3060 #define VEX_p_66 0x01 3061 #define VEX_p_F3 0x02 3062 #define VEX_p_F2 0x03 3063 3064 /* 3065 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 3066 */ 3067 static int isize[] = {1, 2, 4, 4}; 3068 static int isize64[] = {1, 2, 4, 8}; 3069 3070 /* 3071 * Just a bunch of useful macros. 3072 */ 3073 #define WBIT(x) (x & 0x1) /* to get w bit */ 3074 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 3075 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 3076 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 3077 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 3078 3079 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 3080 3081 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 3082 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 3083 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 3084 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 3085 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 3086 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 3087 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 3088 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 3089 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 3090 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 3091 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ 3092 #define ZMM_OPND 11 /* "value" used to indicate a zmm reg */ 3093 3094 /* 3095 * The AVX2 gather instructions are a bit of a mess. While there's a pattern, 3096 * there's not really a consistent scheme that we can use to know what the mode 3097 * is supposed to be for a given type. Various instructions, like VPGATHERDD, 3098 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have 3099 * some registers match VEX_L, but the VSIB is always XMM. 3100 * 3101 * The simplest way to deal with this is to just define a table based on the 3102 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into 3103 * them. 3104 * 3105 * We further have to subdivide this based on the value of VEX_W and the value 3106 * of VEX_L. The array is constructed to be indexed as: 3107 * [opcode - 0x90][VEX_W][VEX_L]. 3108 */ 3109 /* w = 0, 0x90 */ 3110 typedef struct dis_gather_regs { 3111 uint_t dgr_arg0; /* src reg */ 3112 uint_t dgr_arg1; /* vsib reg */ 3113 uint_t dgr_arg2; /* dst reg */ 3114 char *dgr_suffix; /* suffix to append */ 3115 } dis_gather_regs_t; 3116 3117 static dis_gather_regs_t dis_vgather[4][2][2] = { 3118 { 3119 /* op 0x90, W.0 */ 3120 { 3121 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 3122 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 3123 }, 3124 /* op 0x90, W.1 */ 3125 { 3126 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 3127 { YMM_OPND, XMM_OPND, YMM_OPND, "q" } 3128 } 3129 }, 3130 { 3131 /* op 0x91, W.0 */ 3132 { 3133 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 3134 { XMM_OPND, YMM_OPND, XMM_OPND, "d" }, 3135 }, 3136 /* op 0x91, W.1 */ 3137 { 3138 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 3139 { YMM_OPND, YMM_OPND, YMM_OPND, "q" }, 3140 } 3141 }, 3142 { 3143 /* op 0x92, W.0 */ 3144 { 3145 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 3146 { YMM_OPND, YMM_OPND, YMM_OPND, "s" } 3147 }, 3148 /* op 0x92, W.1 */ 3149 { 3150 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 3151 { YMM_OPND, XMM_OPND, YMM_OPND, "d" } 3152 } 3153 }, 3154 { 3155 /* op 0x93, W.0 */ 3156 { 3157 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 3158 { XMM_OPND, YMM_OPND, XMM_OPND, "s" } 3159 }, 3160 /* op 0x93, W.1 */ 3161 { 3162 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 3163 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 3164 } 3165 } 3166 }; 3167 3168 /* 3169 * Get the next byte and separate the op code into the high and low nibbles. 3170 */ 3171 static int 3172 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 3173 { 3174 int byte; 3175 3176 /* 3177 * x86 instructions have a maximum length of 15 bytes. Bail out if 3178 * we try to read more. 3179 */ 3180 if (x->d86_len >= 15) 3181 return (x->d86_error = 1); 3182 3183 if (x->d86_error) 3184 return (1); 3185 byte = x->d86_get_byte(x->d86_data); 3186 if (byte < 0) 3187 return (x->d86_error = 1); 3188 x->d86_bytes[x->d86_len++] = byte; 3189 *low = byte & 0xf; /* ----xxxx low 4 bits */ 3190 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 3191 return (0); 3192 } 3193 3194 /* 3195 * Get and decode an SIB (scaled index base) byte 3196 */ 3197 static void 3198 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 3199 { 3200 int byte; 3201 3202 if (x->d86_error) 3203 return; 3204 3205 byte = x->d86_get_byte(x->d86_data); 3206 if (byte < 0) { 3207 x->d86_error = 1; 3208 return; 3209 } 3210 x->d86_bytes[x->d86_len++] = byte; 3211 3212 *base = byte & 0x7; 3213 *index = (byte >> 3) & 0x7; 3214 *ss = (byte >> 6) & 0x3; 3215 } 3216 3217 /* 3218 * Get the byte following the op code and separate it into the 3219 * mode, register, and r/m fields. 3220 */ 3221 static void 3222 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 3223 { 3224 if (x->d86_got_modrm == 0) { 3225 if (x->d86_rmindex == -1) 3226 x->d86_rmindex = x->d86_len; 3227 dtrace_get_SIB(x, mode, reg, r_m); 3228 x->d86_got_modrm = 1; 3229 } 3230 } 3231 3232 /* 3233 * Adjust register selection based on any REX prefix bits present. 3234 */ 3235 /*ARGSUSED*/ 3236 static void 3237 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 3238 { 3239 if (reg != NULL && r_m == NULL) { 3240 if (rex_prefix & REX_B) 3241 *reg += 8; 3242 } else { 3243 if (reg != NULL && (REX_R & rex_prefix) != 0) 3244 *reg += 8; 3245 if (r_m != NULL && (REX_B & rex_prefix) != 0) 3246 *r_m += 8; 3247 } 3248 } 3249 3250 /* 3251 * Adjust register selection based on any VEX prefix bits present. 3252 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 3253 */ 3254 /*ARGSUSED*/ 3255 static void 3256 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 3257 { 3258 if (reg != NULL && r_m == NULL) { 3259 if (!(vex_byte1 & VEX_B)) 3260 *reg += 8; 3261 } else { 3262 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 3263 *reg += 8; 3264 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 3265 *r_m += 8; 3266 } 3267 } 3268 3269 /* 3270 * Adjust the instruction mnemonic with the appropriate suffix. 3271 */ 3272 /* ARGSUSED */ 3273 static void 3274 dtrace_evex_mnem_adjust(dis86_t *x, const instable_t *dp, uint_t vex_W, 3275 uint_t evex_byte2) 3276 { 3277 #ifdef DIS_TEXT 3278 if (dp == &dis_opEVEX660F[0x7f] || /* vmovdqa */ 3279 dp == &dis_opEVEX660F[0x6f]) { 3280 (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32", 3281 OPLEN); 3282 } 3283 3284 if (dp == &dis_opEVEXF20F[0x7f] || /* vmovdqu */ 3285 dp == &dis_opEVEXF20F[0x6f] || 3286 dp == &dis_opEVEXF30F[0x7f] || 3287 dp == &dis_opEVEXF30F[0x6f]) { 3288 switch (evex_byte2 & 0x81) { 3289 case 0x0: 3290 (void) strlcat(x->d86_mnem, "32", OPLEN); 3291 break; 3292 case 0x1: 3293 (void) strlcat(x->d86_mnem, "8", OPLEN); 3294 break; 3295 case 0x80: 3296 (void) strlcat(x->d86_mnem, "64", OPLEN); 3297 break; 3298 case 0x81: 3299 (void) strlcat(x->d86_mnem, "16", OPLEN); 3300 break; 3301 } 3302 } 3303 3304 if (dp->it_avxsuf == AVS5Q) { 3305 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 3306 OPLEN); 3307 } else if (dp->it_avxsuf == AVS5B) { 3308 (void) strlcat(x->d86_mnem, vex_W != 0 ? "w" : "b", 3309 OPLEN); 3310 } 3311 #endif 3312 } 3313 3314 /* 3315 * The following three functions adjust the register selection based on any 3316 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software 3317 * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and 3318 * section 2.6.2 Table 2-31. 3319 */ 3320 static void 3321 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg) 3322 { 3323 if (reg != NULL) { 3324 if ((VEX_R & evex_byte1) == 0) { 3325 *reg += 8; 3326 } 3327 if ((EVEX_R & evex_byte1) == 0) { 3328 *reg += 16; 3329 } 3330 } 3331 } 3332 3333 static void 3334 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m) 3335 { 3336 if (r_m != NULL) { 3337 if ((VEX_B & evex_byte1) == 0) { 3338 *r_m += 8; 3339 } 3340 if ((VEX_X & evex_byte1) == 0) { 3341 *r_m += 16; 3342 } 3343 } 3344 } 3345 3346 /* 3347 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36. 3348 */ 3349 static void 3350 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp) 3351 { 3352 switch (evex_L) { 3353 case 0x0: 3354 *wbitp = XMM_OPND; 3355 break; 3356 case 0x1: 3357 *wbitp = YMM_OPND; 3358 break; 3359 case 0x2: 3360 *wbitp = ZMM_OPND; 3361 break; 3362 } 3363 } 3364 3365 /* 3366 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5. 3367 * This currently only handles a subset of the possibilities. 3368 */ 3369 static void 3370 dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) 3371 { 3372 d86opnd_t *opnd = &x->d86_opnd[opindex]; 3373 3374 if (x->d86_error) 3375 return; 3376 3377 /* Check disp8 bit in the ModR/M byte */ 3378 if ((modrm & 0x80) == 0x80) 3379 return; 3380 3381 /* use evex_L to adjust the value */ 3382 switch (L) { 3383 case 0x0: 3384 opnd->d86_value *= 16; 3385 break; 3386 case 0x1: 3387 opnd->d86_value *= 32; 3388 break; 3389 case 0x2: 3390 opnd->d86_value *= 64; 3391 break; 3392 } 3393 } 3394 3395 /* 3396 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30. 3397 */ 3398 static void 3399 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3) 3400 { 3401 #ifdef DIS_TEXT 3402 char *opnd = x->d86_opnd[tgtop].d86_opnd; 3403 int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; 3404 #endif 3405 if (x->d86_error) 3406 return; 3407 3408 #ifdef DIS_TEXT 3409 if (opmask_reg != 0) { 3410 /* Append the opmask register to operand 1 */ 3411 (void) strlcat(opnd, "{", OPLEN); 3412 (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN); 3413 (void) strlcat(opnd, "}", OPLEN); 3414 } 3415 if ((evex_byte3 & EVEX_ZERO_MASK) != 0) { 3416 /* Append the 'zeroing' modifier to operand 1 */ 3417 (void) strlcat(opnd, "{z}", OPLEN); 3418 } 3419 #endif /* DIS_TEXT */ 3420 } 3421 3422 /* 3423 * Adjust the target for broadcast mode. This uses the GNU syntax for 3424 * broadcasting of {1toX}. The EVEX W bit determines whether we have a 32-bit or 3425 * 64-bit target that we're broadcasting to. Once we know that, then the 3426 * register length determines the ratio. 3427 */ 3428 static void 3429 dtrace_evex_adjust_bcast(dis86_t *x, uint_t tgtop, uint_t vex_W, uint_t wbit, 3430 uint_t evex_b) 3431 { 3432 #ifdef DIS_TEXT 3433 char *opnd = x->d86_opnd[tgtop].d86_opnd; 3434 const char *bcast; 3435 #endif 3436 if (x->d86_error || evex_b == 0) 3437 return; 3438 3439 /* 3440 * vex_W tells us whether this is a 32-bit or 64-bit broadcast. The 3441 * ratio then assumes a full tuple right now and therefore this is just 3442 * vector / size. 3443 */ 3444 switch (wbit) { 3445 case XMM_OPND: 3446 #ifdef DIS_TEXT 3447 bcast = vex_W == 0 ? "4" : "2"; 3448 #endif 3449 break; 3450 case YMM_OPND: 3451 #ifdef DIS_TEXT 3452 bcast = vex_W == 0 ? "8" : "4"; 3453 #endif 3454 break; 3455 case ZMM_OPND: 3456 #ifdef DIS_TEXT 3457 bcast = vex_W == 0 ? "16" : "8"; 3458 #endif 3459 break; 3460 default: 3461 x->d86_error = 1; 3462 return; 3463 } 3464 3465 #ifdef DIS_TEXT 3466 (void) strlcat(opnd, "{1to", OPLEN); 3467 (void) strlcat(opnd, bcast, OPLEN); 3468 (void) strlcat(opnd, "}", OPLEN); 3469 #endif /* DIS_TEXT */ 3470 } 3471 3472 /* 3473 * Get an immediate operand of the given size, with sign extension. 3474 */ 3475 static void 3476 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 3477 { 3478 int i; 3479 int byte; 3480 int valsize; 3481 3482 if (x->d86_numopnds < opindex + 1) 3483 x->d86_numopnds = opindex + 1; 3484 3485 switch (wbit) { 3486 case BYTE_OPND: 3487 valsize = 1; 3488 break; 3489 case LONG_OPND: 3490 if (x->d86_opnd_size == SIZE16) 3491 valsize = 2; 3492 else if (x->d86_opnd_size == SIZE32) 3493 valsize = 4; 3494 else 3495 valsize = 8; 3496 break; 3497 case MM_OPND: 3498 case XMM_OPND: 3499 case YMM_OPND: 3500 case ZMM_OPND: 3501 case SEG_OPND: 3502 case CONTROL_OPND: 3503 case DEBUG_OPND: 3504 case TEST_OPND: 3505 valsize = size; 3506 break; 3507 case WORD_OPND: 3508 valsize = 2; 3509 break; 3510 } 3511 if (valsize < size) 3512 valsize = size; 3513 3514 if (x->d86_error) 3515 return; 3516 x->d86_opnd[opindex].d86_value = 0; 3517 for (i = 0; i < size; ++i) { 3518 byte = x->d86_get_byte(x->d86_data); 3519 if (byte < 0) { 3520 x->d86_error = 1; 3521 return; 3522 } 3523 x->d86_bytes[x->d86_len++] = byte; 3524 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 3525 } 3526 /* Do sign extension */ 3527 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 3528 for (; i < sizeof (uint64_t); i++) 3529 x->d86_opnd[opindex].d86_value |= 3530 (uint64_t)0xff << (i * 8); 3531 } 3532 #ifdef DIS_TEXT 3533 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3534 x->d86_opnd[opindex].d86_value_size = valsize; 3535 x->d86_imm_bytes += size; 3536 #endif 3537 } 3538 3539 /* 3540 * Get an ip relative operand of the given size, with sign extension. 3541 */ 3542 static void 3543 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 3544 { 3545 dtrace_imm_opnd(x, wbit, size, opindex); 3546 #ifdef DIS_TEXT 3547 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 3548 #endif 3549 } 3550 3551 /* 3552 * Check to see if there is a segment override prefix pending. 3553 * If so, print it in the current 'operand' location and set 3554 * the override flag back to false. 3555 */ 3556 /*ARGSUSED*/ 3557 static void 3558 dtrace_check_override(dis86_t *x, int opindex) 3559 { 3560 #ifdef DIS_TEXT 3561 if (x->d86_seg_prefix) { 3562 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 3563 x->d86_seg_prefix, PFIXLEN); 3564 } 3565 #endif 3566 x->d86_seg_prefix = NULL; 3567 } 3568 3569 3570 /* 3571 * Process a single instruction Register or Memory operand. 3572 * 3573 * mode = addressing mode from ModRM byte 3574 * r_m = r_m (or reg if mode == 3) field from ModRM byte 3575 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 3576 * o = index of operand that we are processing (0, 1 or 2) 3577 * 3578 * the value of reg or r_m must have already been adjusted for any REX prefix. 3579 */ 3580 /*ARGSUSED*/ 3581 static void 3582 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 3583 { 3584 int have_SIB = 0; /* flag presence of scale-index-byte */ 3585 uint_t ss; /* scale-factor from opcode */ 3586 uint_t index; /* index register number */ 3587 uint_t base; /* base register number */ 3588 int dispsize; /* size of displacement in bytes */ 3589 #ifdef DIS_TEXT 3590 char *opnd = x->d86_opnd[opindex].d86_opnd; 3591 #endif 3592 3593 if (x->d86_numopnds < opindex + 1) 3594 x->d86_numopnds = opindex + 1; 3595 3596 if (x->d86_error) 3597 return; 3598 3599 /* 3600 * first handle a simple register 3601 */ 3602 if (mode == REG_ONLY) { 3603 #ifdef DIS_TEXT 3604 switch (wbit) { 3605 case MM_OPND: 3606 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 3607 break; 3608 case XMM_OPND: 3609 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 3610 break; 3611 case YMM_OPND: 3612 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 3613 break; 3614 case ZMM_OPND: 3615 (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN); 3616 break; 3617 case KOPMASK_OPND: 3618 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); 3619 break; 3620 case SEG_OPND: 3621 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 3622 break; 3623 case CONTROL_OPND: 3624 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 3625 break; 3626 case DEBUG_OPND: 3627 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 3628 break; 3629 case TEST_OPND: 3630 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 3631 break; 3632 case BYTE_OPND: 3633 if (x->d86_rex_prefix == 0) 3634 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 3635 else 3636 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 3637 break; 3638 case WORD_OPND: 3639 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 3640 break; 3641 case LONG_OPND: 3642 if (x->d86_opnd_size == SIZE16) 3643 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 3644 else if (x->d86_opnd_size == SIZE32) 3645 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 3646 else 3647 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 3648 break; 3649 } 3650 #endif /* DIS_TEXT */ 3651 return; 3652 } 3653 3654 /* 3655 * if symbolic representation, skip override prefix, if any 3656 */ 3657 dtrace_check_override(x, opindex); 3658 3659 /* 3660 * Handle 16 bit memory references first, since they decode 3661 * the mode values more simply. 3662 * mode 1 is r_m + 8 bit displacement 3663 * mode 2 is r_m + 16 bit displacement 3664 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 3665 */ 3666 if (x->d86_addr_size == SIZE16) { 3667 if ((mode == 0 && r_m == 6) || mode == 2) 3668 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 3669 else if (mode == 1) 3670 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 3671 #ifdef DIS_TEXT 3672 if (mode == 0 && r_m == 6) 3673 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3674 else if (mode == 0) 3675 x->d86_opnd[opindex].d86_mode = MODE_NONE; 3676 else 3677 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3678 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 3679 #endif 3680 return; 3681 } 3682 3683 /* 3684 * 32 and 64 bit addressing modes are more complex since they can 3685 * involve an SIB (scaled index and base) byte to decode. When using VEX 3686 * and EVEX encodings, the r_m indicator for a SIB may be offset by 8 3687 * and 24 (8 + 16) respectively. 3688 */ 3689 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8 || r_m == ESP_REGNO + 24) { 3690 have_SIB = 1; 3691 dtrace_get_SIB(x, &ss, &index, &base); 3692 if (x->d86_error) 3693 return; 3694 if (base != 5 || mode != 0) 3695 if (x->d86_rex_prefix & REX_B) 3696 base += 8; 3697 if (x->d86_rex_prefix & REX_X) 3698 index += 8; 3699 } else { 3700 base = r_m; 3701 } 3702 3703 /* 3704 * Compute the displacement size and get its bytes 3705 */ 3706 dispsize = 0; 3707 3708 if (mode == 1) 3709 dispsize = 1; 3710 else if (mode == 2) 3711 dispsize = 4; 3712 else if ((r_m & 7) == EBP_REGNO || 3713 (have_SIB && (base & 7) == EBP_REGNO)) 3714 dispsize = 4; 3715 3716 if (dispsize > 0) { 3717 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 3718 dispsize, opindex); 3719 if (x->d86_error) 3720 return; 3721 } 3722 3723 #ifdef DIS_TEXT 3724 if (dispsize > 0) 3725 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3726 3727 if (have_SIB == 0) { 3728 if (x->d86_mode == SIZE32) { 3729 if (mode == 0) 3730 (void) strlcat(opnd, dis_addr32_mode0[r_m], 3731 OPLEN); 3732 else 3733 (void) strlcat(opnd, dis_addr32_mode12[r_m], 3734 OPLEN); 3735 } else { 3736 if (mode == 0) { 3737 (void) strlcat(opnd, dis_addr64_mode0[r_m], 3738 OPLEN); 3739 if (r_m == 5) { 3740 x->d86_opnd[opindex].d86_mode = 3741 MODE_RIPREL; 3742 } 3743 } else { 3744 (void) strlcat(opnd, dis_addr64_mode12[r_m], 3745 OPLEN); 3746 } 3747 } 3748 } else { 3749 uint_t need_paren = 0; 3750 char **regs; 3751 char **bregs; 3752 const char *const *sf; 3753 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 3754 regs = (char **)dis_REG32; 3755 else 3756 regs = (char **)dis_REG64; 3757 3758 if (x->d86_vsib != 0) { 3759 if (wbit == YMM_OPND) { /* NOTE this is not addr_size */ 3760 bregs = (char **)dis_YMMREG; 3761 } else if (wbit == XMM_OPND) { 3762 bregs = (char **)dis_XMMREG; 3763 } else { 3764 bregs = (char **)dis_ZMMREG; 3765 } 3766 sf = dis_vscale_factor; 3767 } else { 3768 bregs = regs; 3769 sf = dis_scale_factor; 3770 } 3771 3772 /* 3773 * print the base (if any) 3774 */ 3775 if (base == EBP_REGNO && mode == 0) { 3776 if (index != ESP_REGNO || x->d86_vsib != 0) { 3777 (void) strlcat(opnd, "(", OPLEN); 3778 need_paren = 1; 3779 } 3780 } else { 3781 (void) strlcat(opnd, "(", OPLEN); 3782 (void) strlcat(opnd, regs[base], OPLEN); 3783 need_paren = 1; 3784 } 3785 3786 /* 3787 * print the index (if any) 3788 */ 3789 if (index != ESP_REGNO || x->d86_vsib) { 3790 (void) strlcat(opnd, ",", OPLEN); 3791 (void) strlcat(opnd, bregs[index], OPLEN); 3792 (void) strlcat(opnd, sf[ss], OPLEN); 3793 } else 3794 if (need_paren) 3795 (void) strlcat(opnd, ")", OPLEN); 3796 } 3797 #endif 3798 } 3799 3800 /* 3801 * Operand sequence for standard instruction involving one register 3802 * and one register/memory operand. 3803 * wbit indicates a byte(0) or opnd_size(1) operation 3804 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 3805 */ 3806 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 3807 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3808 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3809 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3810 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 3811 } 3812 3813 /* 3814 * Similar to above, but allows for the two operands to be of different 3815 * classes (ie. wbit). 3816 * wbit is for the r_m operand 3817 * w2 is for the reg operand 3818 */ 3819 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 3820 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3821 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3822 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3823 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 3824 } 3825 3826 /* 3827 * Similar, but for 2 operands plus an immediate. 3828 * vbit indicates direction 3829 * 0 for "opcode imm, r, r_m" or 3830 * 1 for "opcode imm, r_m, r" 3831 */ 3832 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 3833 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3834 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3835 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 3836 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 3837 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3838 } 3839 3840 /* 3841 * Similar, but for 2 operands plus two immediates. 3842 */ 3843 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 3844 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3845 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3846 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3847 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 3848 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3849 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3850 } 3851 3852 /* 3853 * 1 operands plus two immediates. 3854 */ 3855 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 3856 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3857 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3858 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3859 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3860 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3861 } 3862 3863 /* 3864 * Dissassemble a single x86 or amd64 instruction. 3865 * 3866 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 3867 * for interpreting instructions. 3868 * 3869 * returns non-zero for bad opcode 3870 */ 3871 int 3872 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 3873 { 3874 const instable_t *dp = NULL; /* decode table being used */ 3875 #ifdef DIS_TEXT 3876 uint_t i; 3877 #endif 3878 #ifdef DIS_MEM 3879 uint_t nomem = 0; 3880 #define NOMEM (nomem = 1) 3881 #else 3882 #define NOMEM /* nothing */ 3883 #endif 3884 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 3885 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 3886 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 3887 uint_t w2; /* wbit value for second operand */ 3888 uint_t vbit; 3889 uint_t mode = 0; /* mode value from ModRM byte */ 3890 uint_t reg; /* reg value from ModRM byte */ 3891 uint_t r_m; /* r_m value from ModRM byte */ 3892 3893 uint_t opcode1; /* high nibble of 1st byte */ 3894 uint_t opcode2; /* low nibble of 1st byte */ 3895 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 3896 uint_t opcode4; /* high nibble of 2nd byte */ 3897 uint_t opcode5; /* low nibble of 2nd byte */ 3898 uint_t opcode6; /* high nibble of 3rd byte */ 3899 uint_t opcode7; /* low nibble of 3rd byte */ 3900 uint_t opcode8; /* high nibble of 4th byte */ 3901 uint_t opcode9; /* low nibble of 4th byte */ 3902 uint_t opcode_bytes = 1; 3903 3904 /* 3905 * legacy prefixes come in 5 flavors, you should have only one of each 3906 */ 3907 uint_t opnd_size_prefix = 0; 3908 uint_t addr_size_prefix = 0; 3909 uint_t segment_prefix = 0; 3910 uint_t lock_prefix = 0; 3911 uint_t rep_prefix = 0; 3912 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 3913 3914 /* 3915 * Intel VEX instruction encoding prefix and fields 3916 */ 3917 3918 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 3919 uint_t vex_prefix = 0; 3920 3921 /* 3922 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 3923 * (for 3 bytes prefix) 3924 */ 3925 uint_t vex_byte1 = 0; 3926 3927 /* 3928 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r. 3929 */ 3930 uint_t evex_byte1 = 0; 3931 uint_t evex_byte2 = 0; 3932 uint_t evex_byte3 = 0; 3933 3934 /* 3935 * For 32-bit mode, it should prefetch the next byte to 3936 * distinguish between AVX and les/lds 3937 */ 3938 uint_t vex_prefetch = 0; 3939 3940 uint_t vex_m = 0; 3941 uint_t vex_v = 0; 3942 uint_t vex_p = 0; 3943 uint_t vex_R = 1; 3944 uint_t vex_X = 1; 3945 uint_t vex_B = 1; 3946 uint_t vex_W = 0; 3947 uint_t vex_L = 0; 3948 uint_t evex_L = 0; 3949 uint_t evex_b = 0; 3950 uint_t evex_modrm = 0; 3951 uint_t evex_prefix = 0; 3952 dis_gather_regs_t *vreg; 3953 3954 #ifdef DIS_TEXT 3955 /* Instruction name for BLS* family of instructions */ 3956 char *blsinstr; 3957 #endif 3958 3959 size_t off; 3960 3961 instable_t dp_mmx; 3962 3963 x->d86_len = 0; 3964 x->d86_rmindex = -1; 3965 x->d86_error = 0; 3966 #ifdef DIS_TEXT 3967 x->d86_numopnds = 0; 3968 x->d86_seg_prefix = NULL; 3969 x->d86_mnem[0] = 0; 3970 for (i = 0; i < 4; ++i) { 3971 x->d86_opnd[i].d86_opnd[0] = 0; 3972 x->d86_opnd[i].d86_prefix[0] = 0; 3973 x->d86_opnd[i].d86_value_size = 0; 3974 x->d86_opnd[i].d86_value = 0; 3975 x->d86_opnd[i].d86_mode = MODE_NONE; 3976 } 3977 #endif 3978 x->d86_rex_prefix = 0; 3979 x->d86_got_modrm = 0; 3980 x->d86_memsize = 0; 3981 x->d86_vsib = 0; 3982 3983 if (cpu_mode == SIZE16) { 3984 opnd_size = SIZE16; 3985 addr_size = SIZE16; 3986 } else if (cpu_mode == SIZE32) { 3987 opnd_size = SIZE32; 3988 addr_size = SIZE32; 3989 } else { 3990 opnd_size = SIZE32; 3991 addr_size = SIZE64; 3992 } 3993 3994 /* 3995 * Get one opcode byte and check for zero padding that follows 3996 * jump tables. 3997 */ 3998 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3999 goto error; 4000 4001 if (opcode1 == 0 && opcode2 == 0 && 4002 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 4003 #ifdef DIS_TEXT 4004 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 4005 #endif 4006 goto done; 4007 } 4008 4009 /* 4010 * Gather up legacy x86 prefix bytes. 4011 */ 4012 for (;;) { 4013 uint_t *which_prefix = NULL; 4014 4015 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 4016 4017 switch (dp->it_adrmode) { 4018 case PREFIX: 4019 which_prefix = &rep_prefix; 4020 break; 4021 case LOCK: 4022 which_prefix = &lock_prefix; 4023 break; 4024 case OVERRIDE: 4025 which_prefix = &segment_prefix; 4026 #ifdef DIS_TEXT 4027 x->d86_seg_prefix = (char *)dp->it_name; 4028 #endif 4029 if (dp->it_invalid64 && cpu_mode == SIZE64) 4030 goto error; 4031 break; 4032 case AM: 4033 which_prefix = &addr_size_prefix; 4034 break; 4035 case DM: 4036 which_prefix = &opnd_size_prefix; 4037 break; 4038 } 4039 if (which_prefix == NULL) 4040 break; 4041 *which_prefix = (opcode1 << 4) | opcode2; 4042 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 4043 goto error; 4044 } 4045 4046 /* 4047 * Handle amd64 mode PREFIX values. 4048 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 4049 * We might have a REX prefix (opcodes 0x40-0x4f) 4050 */ 4051 if (cpu_mode == SIZE64) { 4052 if (segment_prefix != 0x64 && segment_prefix != 0x65) 4053 segment_prefix = 0; 4054 4055 if (opcode1 == 0x4) { 4056 rex_prefix = (opcode1 << 4) | opcode2; 4057 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 4058 goto error; 4059 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 4060 } else if (opcode1 == 0xC && 4061 (opcode2 == 0x4 || opcode2 == 0x5)) { 4062 /* AVX instructions */ 4063 vex_prefix = (opcode1 << 4) | opcode2; 4064 x->d86_rex_prefix = 0x40; 4065 } 4066 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 4067 /* LDS, LES or AVX */ 4068 dtrace_get_modrm(x, &mode, ®, &r_m); 4069 vex_prefetch = 1; 4070 4071 if (mode == REG_ONLY) { 4072 /* AVX */ 4073 vex_prefix = (opcode1 << 4) | opcode2; 4074 x->d86_rex_prefix = 0x40; 4075 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 4076 opcode4 = ((reg << 3) | r_m) & 0x0F; 4077 } 4078 } 4079 4080 /* 4081 * The EVEX prefix and "bound" instruction share the same first byte. 4082 * "bound" is only valid for 32-bit. For 64-bit this byte begins the 4083 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0. 4084 */ 4085 if (opcode1 == 0x6 && opcode2 == 0x2) { 4086 evex_prefix = 0x62; 4087 4088 /* 4089 * An EVEX prefix is 4 bytes long, get the next 3 bytes. 4090 */ 4091 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 4092 goto error; 4093 4094 if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) { 4095 /* 4096 * Upper bits in 2nd byte == 0 is 'bound' instn. 4097 * 4098 * We've already read the byte so perform the 4099 * equivalent of dtrace_get_modrm on the byte and set 4100 * the flag to indicate we've already read it. 4101 */ 4102 char b = (opcode4 << 4) | opcode5; 4103 4104 r_m = b & 0x7; 4105 reg = (b >> 3) & 0x7; 4106 mode = (b >> 6) & 0x3; 4107 vex_prefetch = 1; 4108 goto not_avx512; 4109 } 4110 4111 /* check for correct bits being 0 in 2nd byte */ 4112 if ((opcode5 & 0xc) != 0) 4113 goto error; 4114 4115 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4116 goto error; 4117 /* check for correct bit being 1 in 3rd byte */ 4118 if ((opcode7 & 0x4) == 0) 4119 goto error; 4120 4121 if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0) 4122 goto error; 4123 4124 /* Reuse opcode1 & opcode2 to get the real opcode now */ 4125 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 4126 goto error; 4127 4128 /* 4129 * We only use the high nibble from the 2nd byte of the prefix 4130 * and save it in the low bits of evex_byte1. This is because 4131 * two of the bits in opcode5 are constant 0 (checked above), 4132 * and the other two bits are captured in vex_m. Also, the VEX 4133 * constants we check in evex_byte1 are against the low bits. 4134 */ 4135 evex_byte1 = opcode4; 4136 evex_byte2 = (opcode6 << 4) | opcode7; 4137 evex_byte3 = (opcode8 << 4) | opcode9; 4138 4139 vex_m = opcode5 & EVEX_m; 4140 vex_W = (opcode6 & VEX_W) >> 3; 4141 vex_p = opcode7 & VEX_p; 4142 4143 /* 4144 * We store both EVEX.V' and EVEX.vvvv in here. 4145 */ 4146 vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3; 4147 vex_v |= (evex_byte3 & EVEX_V) << 1; 4148 4149 /* 4150 * Store the corresponding prefix information for later use when 4151 * calculating the SIB. 4152 */ 4153 if ((evex_byte1 & VEX_R) == 0) 4154 x->d86_rex_prefix |= REX_R; 4155 if ((evex_byte1 & VEX_X) == 0) 4156 x->d86_rex_prefix |= REX_X; 4157 if ((evex_byte1 & VEX_B) == 0) 4158 x->d86_rex_prefix |= REX_B; 4159 4160 /* Currently only 3 valid values for evex L'L: 00, 01, 10 */ 4161 evex_L = (opcode8 & EVEX_L) >> 1; 4162 evex_b = opcode8 & EVEX_B; 4163 4164 switch (vex_p) { 4165 case VEX_p_66: 4166 switch (vex_m) { 4167 case VEX_m_0F: 4168 dp = &dis_opEVEX660F[(opcode1 << 4) | opcode2]; 4169 break; 4170 case VEX_m_0F38: 4171 dp = &dis_opEVEX660F38[(opcode1 << 4) | 4172 opcode2]; 4173 break; 4174 case VEX_m_0F3A: 4175 dp = &dis_opEVEX660F3A[(opcode1 << 4) | 4176 opcode2]; 4177 break; 4178 default: 4179 goto error; 4180 } 4181 break; 4182 case VEX_p_F3: 4183 switch (vex_m) { 4184 case VEX_m_0F: 4185 dp = &dis_opEVEXF30F[(opcode1 << 4) | opcode2]; 4186 break; 4187 case VEX_m_0F38: 4188 dp = &dis_opEVEXF30F38[(opcode1 << 4) | 4189 opcode2]; 4190 break; 4191 default: 4192 goto error; 4193 } 4194 break; 4195 case VEX_p_F2: 4196 switch (vex_m) { 4197 case VEX_m_0F: 4198 dp = &dis_opEVEXF20F[(opcode1 << 4) | opcode2]; 4199 break; 4200 case VEX_m_0F38: 4201 dp = &dis_opEVEXF20F38[(opcode1 << 4) | 4202 opcode2]; 4203 break; 4204 default: 4205 goto error; 4206 } 4207 break; 4208 default: 4209 dp = &dis_opEVEX0F[(opcode1 << 4) | opcode2]; 4210 break; 4211 } 4212 } 4213 not_avx512: 4214 4215 if (vex_prefix == VEX_2bytes) { 4216 if (!vex_prefetch) { 4217 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 4218 goto error; 4219 } 4220 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 4221 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 4222 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 4223 vex_p = opcode4 & VEX_p; 4224 /* 4225 * The vex.x and vex.b bits are not defined in two bytes 4226 * mode vex prefix, their default values are 1 4227 */ 4228 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 4229 4230 if (vex_R == 0) 4231 x->d86_rex_prefix |= REX_R; 4232 4233 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 4234 goto error; 4235 4236 switch (vex_p) { 4237 case VEX_p_66: 4238 dp = (instable_t *) 4239 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 4240 break; 4241 case VEX_p_F3: 4242 dp = (instable_t *) 4243 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 4244 break; 4245 case VEX_p_F2: 4246 dp = (instable_t *) 4247 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 4248 break; 4249 default: 4250 dp = (instable_t *) 4251 &dis_opAVX0F[opcode1][opcode2]; 4252 4253 } 4254 4255 } else if (vex_prefix == VEX_3bytes) { 4256 if (!vex_prefetch) { 4257 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 4258 goto error; 4259 } 4260 vex_R = (opcode3 & VEX_R) >> 3; 4261 vex_X = (opcode3 & VEX_X) >> 2; 4262 vex_B = (opcode3 & VEX_B) >> 1; 4263 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 4264 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 4265 4266 if (vex_R == 0) 4267 x->d86_rex_prefix |= REX_R; 4268 if (vex_X == 0) 4269 x->d86_rex_prefix |= REX_X; 4270 if (vex_B == 0) 4271 x->d86_rex_prefix |= REX_B; 4272 4273 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 4274 goto error; 4275 vex_W = (opcode5 & VEX_W) >> 3; 4276 vex_L = (opcode6 & VEX_L) >> 2; 4277 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 4278 vex_p = opcode6 & VEX_p; 4279 4280 if (vex_W) 4281 x->d86_rex_prefix |= REX_W; 4282 4283 /* Only these three vex_m values valid; others are reserved */ 4284 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 4285 (vex_m != VEX_m_0F3A)) 4286 goto error; 4287 4288 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 4289 goto error; 4290 4291 switch (vex_p) { 4292 case VEX_p_66: 4293 if (vex_m == VEX_m_0F) { 4294 dp = (instable_t *) 4295 &dis_opAVX660F 4296 [(opcode1 << 4) | opcode2]; 4297 } else if (vex_m == VEX_m_0F38) { 4298 dp = (instable_t *) 4299 &dis_opAVX660F38 4300 [(opcode1 << 4) | opcode2]; 4301 } else if (vex_m == VEX_m_0F3A) { 4302 dp = (instable_t *) 4303 &dis_opAVX660F3A 4304 [(opcode1 << 4) | opcode2]; 4305 } else { 4306 goto error; 4307 } 4308 break; 4309 case VEX_p_F3: 4310 if (vex_m == VEX_m_0F) { 4311 dp = (instable_t *) 4312 &dis_opAVXF30F 4313 [(opcode1 << 4) | opcode2]; 4314 } else if (vex_m == VEX_m_0F38) { 4315 dp = (instable_t *) 4316 &dis_opAVXF30F38 4317 [(opcode1 << 4) | opcode2]; 4318 } else { 4319 goto error; 4320 } 4321 break; 4322 case VEX_p_F2: 4323 if (vex_m == VEX_m_0F) { 4324 dp = (instable_t *) 4325 &dis_opAVXF20F 4326 [(opcode1 << 4) | opcode2]; 4327 } else if (vex_m == VEX_m_0F3A) { 4328 dp = (instable_t *) 4329 &dis_opAVXF20F3A 4330 [(opcode1 << 4) | opcode2]; 4331 } else if (vex_m == VEX_m_0F38) { 4332 dp = (instable_t *) 4333 &dis_opAVXF20F38 4334 [(opcode1 << 4) | opcode2]; 4335 } else { 4336 goto error; 4337 } 4338 break; 4339 default: 4340 dp = (instable_t *) 4341 &dis_opAVX0F[opcode1][opcode2]; 4342 4343 } 4344 } 4345 if (vex_prefix) { 4346 if (dp->it_vexwoxmm) { 4347 wbit = LONG_OPND; 4348 } else if (dp->it_vexopmask) { 4349 wbit = KOPMASK_OPND; 4350 } else { 4351 if (vex_L) { 4352 wbit = YMM_OPND; 4353 } else { 4354 wbit = XMM_OPND; 4355 } 4356 } 4357 } 4358 4359 /* 4360 * Deal with selection of operand and address size now. 4361 * Note that the REX.W bit being set causes opnd_size_prefix to be 4362 * ignored. 4363 */ 4364 if (cpu_mode == SIZE64) { 4365 if ((rex_prefix & REX_W) || vex_W) 4366 opnd_size = SIZE64; 4367 else if (opnd_size_prefix) 4368 opnd_size = SIZE16; 4369 4370 if (addr_size_prefix) 4371 addr_size = SIZE32; 4372 } else if (cpu_mode == SIZE32) { 4373 if (opnd_size_prefix) 4374 opnd_size = SIZE16; 4375 if (addr_size_prefix) 4376 addr_size = SIZE16; 4377 } else { 4378 if (opnd_size_prefix) 4379 opnd_size = SIZE32; 4380 if (addr_size_prefix) 4381 addr_size = SIZE32; 4382 } 4383 /* 4384 * The pause instruction - a repz'd nop. This doesn't fit 4385 * with any of the other prefix goop added for SSE, so we'll 4386 * special-case it here. 4387 */ 4388 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 4389 rep_prefix = 0; 4390 dp = (instable_t *)&dis_opPause; 4391 } 4392 4393 /* 4394 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 4395 * byte so we may need to perform a table indirection. 4396 */ 4397 if (dp->it_indirect == (instable_t *)dis_op0F) { 4398 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 4399 goto error; 4400 opcode_bytes = 2; 4401 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 4402 uint_t subcode; 4403 4404 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4405 goto error; 4406 opcode_bytes = 3; 4407 subcode = ((opcode6 & 0x3) << 1) | 4408 ((opcode7 & 0x8) >> 3); 4409 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 4410 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 4411 dp = (instable_t *)&dis_op0FC8[0]; 4412 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 4413 opcode_bytes = 3; 4414 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4415 goto error; 4416 if (opnd_size == SIZE16) 4417 opnd_size = SIZE32; 4418 4419 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 4420 #ifdef DIS_TEXT 4421 if (strcmp(dp->it_name, "INVALID") == 0) 4422 goto error; 4423 #endif 4424 switch (dp->it_adrmode) { 4425 case XMMP: 4426 break; 4427 case XMMP_66r: 4428 case XMMPRM_66r: 4429 case XMM3PM_66r: 4430 if (opnd_size_prefix == 0) { 4431 goto error; 4432 } 4433 4434 break; 4435 case XMMP_66o: 4436 if (opnd_size_prefix == 0) { 4437 /* SSSE3 MMX instructions */ 4438 dp_mmx = *dp; 4439 dp_mmx.it_adrmode = MMOPM_66o; 4440 #ifdef DIS_MEM 4441 dp_mmx.it_size = 8; 4442 #endif 4443 dp = &dp_mmx; 4444 } 4445 break; 4446 default: 4447 goto error; 4448 } 4449 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 4450 opcode_bytes = 3; 4451 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4452 goto error; 4453 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 4454 4455 /* 4456 * Both crc32 and movbe have the same 3rd opcode 4457 * byte of either 0xF0 or 0xF1, so we use another 4458 * indirection to distinguish between the two. 4459 */ 4460 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 4461 dp->it_indirect == (instable_t *)dis_op0F38F1) { 4462 4463 dp = dp->it_indirect; 4464 if (rep_prefix != 0xF2) { 4465 /* It is movbe */ 4466 dp++; 4467 } 4468 } 4469 4470 /* 4471 * The adx family of instructions (adcx and adox) 4472 * continue the classic Intel tradition of abusing 4473 * arbitrary prefixes without actually meaning the 4474 * prefix bit. Therefore, if we find either the 4475 * opnd_size_prefix or rep_prefix we end up zeroing it 4476 * out after making our determination so as to ensure 4477 * that we don't get confused and accidentally print 4478 * repz prefixes and the like on these instructions. 4479 * 4480 * In addition, these instructions are actually much 4481 * closer to AVX instructions in semantics. Importantly, 4482 * they always default to having 32-bit operands. 4483 * However, if the CPU is in 64-bit mode, then and only 4484 * then, does it use REX.w promotes things to 64-bits 4485 * and REX.r allows 64-bit mode to use register r8-r15. 4486 */ 4487 if (dp->it_indirect == (instable_t *)dis_op0F38F6) { 4488 dp = dp->it_indirect; 4489 if (opnd_size_prefix == 0 && 4490 rep_prefix == 0xf3) { 4491 /* It is adox */ 4492 dp++; 4493 } else if (opnd_size_prefix != 0x66 && 4494 rep_prefix != 0) { 4495 /* It isn't adcx */ 4496 goto error; 4497 } 4498 opnd_size_prefix = 0; 4499 rep_prefix = 0; 4500 opnd_size = SIZE32; 4501 if (rex_prefix & REX_W) 4502 opnd_size = SIZE64; 4503 } 4504 4505 #ifdef DIS_TEXT 4506 if (strcmp(dp->it_name, "INVALID") == 0) 4507 goto error; 4508 #endif 4509 switch (dp->it_adrmode) { 4510 case ADX: 4511 case XMM: 4512 break; 4513 case RM_66r: 4514 case XMM_66r: 4515 case XMMM_66r: 4516 if (opnd_size_prefix == 0) { 4517 goto error; 4518 } 4519 break; 4520 case XMM_66o: 4521 if (opnd_size_prefix == 0) { 4522 /* SSSE3 MMX instructions */ 4523 dp_mmx = *dp; 4524 dp_mmx.it_adrmode = MM; 4525 #ifdef DIS_MEM 4526 dp_mmx.it_size = 8; 4527 #endif 4528 dp = &dp_mmx; 4529 } 4530 break; 4531 case CRC32: 4532 if (rep_prefix != 0xF2) { 4533 goto error; 4534 } 4535 rep_prefix = 0; 4536 break; 4537 case MOVBE: 4538 if (rep_prefix != 0x0) { 4539 goto error; 4540 } 4541 break; 4542 case RM: 4543 /* 4544 * Currently the MOVDIRI instruction is 4545 * the only known case here. It is not 4546 * allowed to have a prefix. 4547 */ 4548 if (rep_prefix != 0x0) { 4549 goto error; 4550 } 4551 break; 4552 case MOVDIR: 4553 /* 4554 * MOVDIR64B requires a opnd size prefix 4555 * of 0x66, but ignores it. This means 4556 * that we need to undo what we did 4557 * earlier and readjust the operator and 4558 * address size prefixes. 4559 */ 4560 if (opnd_size_prefix != 0x66) { 4561 goto error; 4562 } 4563 if (cpu_mode == SIZE64 || 4564 cpu_mode == SIZE16) { 4565 if (addr_size_prefix == 0x67) { 4566 opnd_size = SIZE32; 4567 } else { 4568 opnd_size = cpu_mode; 4569 } 4570 } else { 4571 if (addr_size_prefix == 0x67) { 4572 opnd_size = SIZE16; 4573 } else { 4574 opnd_size = SIZE32; 4575 } 4576 } 4577 addr_size = opnd_size; 4578 addr_size_prefix = 0; 4579 opnd_size_prefix = 0; 4580 break; 4581 default: 4582 goto error; 4583 } 4584 } else if (rep_prefix == 0xf3 && opcode4 == 0 && opcode5 == 9) { 4585 rep_prefix = 0; 4586 dp = (instable_t *)&dis_opWbnoinvd; 4587 } else { 4588 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 4589 } 4590 } 4591 4592 /* 4593 * If still not at a TERM decode entry, then a ModRM byte 4594 * exists and its fields further decode the instruction. 4595 */ 4596 x->d86_got_modrm = 0; 4597 if (dp->it_indirect != TERM) { 4598 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 4599 if (x->d86_error) 4600 goto error; 4601 reg = opcode3; 4602 4603 /* 4604 * decode 287 instructions (D8-DF) from opcodeN 4605 */ 4606 if (opcode1 == 0xD && opcode2 >= 0x8) { 4607 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 4608 dp = (instable_t *)&dis_opFP5[r_m]; 4609 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 4610 dp = (instable_t *)&dis_opFP7[opcode3]; 4611 else if (opcode2 == 0xB && mode == 0x3) 4612 dp = (instable_t *)&dis_opFP6[opcode3]; 4613 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 4614 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 4615 else if (mode == 0x3) 4616 dp = (instable_t *) 4617 &dis_opFP3[opcode2 - 8][opcode3]; 4618 else 4619 dp = (instable_t *) 4620 &dis_opFP1n2[opcode2 - 8][opcode3]; 4621 } else { 4622 dp = (instable_t *)dp->it_indirect + opcode3; 4623 } 4624 } 4625 4626 /* 4627 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 4628 * (sign extend 32bit to 64 bit) 4629 */ 4630 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 4631 opcode1 == 0x6 && opcode2 == 0x3) 4632 dp = (instable_t *)&dis_opMOVSLD; 4633 4634 /* 4635 * at this point we should have a correct (or invalid) opcode 4636 */ 4637 if ((cpu_mode == SIZE64 && dp->it_invalid64) || 4638 (cpu_mode != SIZE64 && dp->it_invalid32)) 4639 goto error; 4640 if (dp->it_indirect != TERM) 4641 goto error; 4642 4643 /* 4644 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do 4645 * need to include UNKNOWN below, as we may have instructions that 4646 * actually have a prefix, but don't exist in any other form. 4647 */ 4648 switch (dp->it_adrmode) { 4649 case UNKNOWN: 4650 case MMO: 4651 case MMOIMPL: 4652 case MMO3P: 4653 case MMOM3: 4654 case MMOMS: 4655 case MMOPM: 4656 case MMOPRM: 4657 case MMOS: 4658 case XMMO: 4659 case XMMOM: 4660 case XMMOMS: 4661 case XMMOPM: 4662 case XMMOS: 4663 case XMMOMX: 4664 case XMMOX3: 4665 case XMMOXMM: 4666 /* 4667 * This is horrible. Some SIMD instructions take the 4668 * form 0x0F 0x?? ..., which is easily decoded using the 4669 * existing tables. Other SIMD instructions use various 4670 * prefix bytes to overload existing instructions. For 4671 * Example, addps is F0, 58, whereas addss is F3 (repz), 4672 * F0, 58. Presumably someone got a raise for this. 4673 * 4674 * If we see one of the instructions which can be 4675 * modified in this way (if we've got one of the SIMDO* 4676 * address modes), we'll check to see if the last prefix 4677 * was a repz. If it was, we strip the prefix from the 4678 * mnemonic, and we indirect using the dis_opSIMDrepz 4679 * table. 4680 */ 4681 4682 /* 4683 * Calculate our offset in dis_op0F 4684 */ 4685 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 4686 goto error; 4687 4688 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4689 sizeof (instable_t); 4690 4691 /* 4692 * Rewrite if this instruction used one of the magic prefixes. 4693 */ 4694 if (rep_prefix) { 4695 if (rep_prefix == 0xf2) 4696 dp = (instable_t *)&dis_opSIMDrepnz[off]; 4697 else 4698 dp = (instable_t *)&dis_opSIMDrepz[off]; 4699 rep_prefix = 0; 4700 } else if (opnd_size_prefix) { 4701 dp = (instable_t *)&dis_opSIMDdata16[off]; 4702 opnd_size_prefix = 0; 4703 if (opnd_size == SIZE16) 4704 opnd_size = SIZE32; 4705 } 4706 break; 4707 4708 case MG9: 4709 /* 4710 * More horribleness: the group 9 (0xF0 0xC7) instructions are 4711 * allowed an optional prefix of 0x66 or 0xF3. This is similar 4712 * to the SIMD business described above, but with a different 4713 * addressing mode (and an indirect table), so we deal with it 4714 * separately (if similarly). 4715 * 4716 * Intel further complicated this with the release of Ivy Bridge 4717 * where they overloaded these instructions based on the ModR/M 4718 * bytes. The VMX instructions have a mode of 0 since they are 4719 * memory instructions but rdrand instructions have a mode of 4720 * 0b11 (REG_ONLY) because they only operate on registers. 4721 */ 4722 4723 /* 4724 * Calculate our offset in dis_op0FC7 (the group 9 table) 4725 */ 4726 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 4727 goto error; 4728 4729 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 4730 sizeof (instable_t); 4731 4732 /* 4733 * If we have a mode of 0b11 then we have to rewrite this. We 4734 * must check prefixes first. 4735 */ 4736 dtrace_get_modrm(x, &mode, ®, &r_m); 4737 4738 /* 4739 * Rewrite if this instruction used one of the magic prefixes. 4740 */ 4741 if (rep_prefix) { 4742 if (rep_prefix == 0xf3 && mode == REG_ONLY) 4743 dp = (instable_t *)&dis_opF30FC7m3[off]; 4744 else if (rep_prefix == 0xf3) 4745 dp = (instable_t *)&dis_opF30FC7[off]; 4746 else 4747 goto error; 4748 rep_prefix = 0; 4749 } else if (opnd_size_prefix) { 4750 if (mode == REG_ONLY) { 4751 dp = (instable_t *)&dis_op0FC7m3[reg]; 4752 } else { 4753 dp = (instable_t *)&dis_op660FC7[off]; 4754 opnd_size_prefix = 0; 4755 if (opnd_size == SIZE16) 4756 opnd_size = SIZE32; 4757 } 4758 } else if (mode == REG_ONLY) { 4759 dp = (instable_t *)&dis_op0FC7m3[off]; 4760 } else if (reg == 4 || reg == 5) { 4761 /* 4762 * We have xsavec (4) or xsaves (5), so rewrite. 4763 */ 4764 dp = (instable_t *)&dis_op0FC7[reg]; 4765 } 4766 break; 4767 4768 4769 case MMOSH: 4770 /* 4771 * As with the "normal" SIMD instructions, the MMX 4772 * shuffle instructions are overloaded. These 4773 * instructions, however, are special in that they use 4774 * an extra byte, and thus an extra table. As of this 4775 * writing, they only use the opnd_size prefix. 4776 */ 4777 4778 /* 4779 * Calculate our offset in dis_op0F7123 4780 */ 4781 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 4782 sizeof (dis_op0F7123)) 4783 goto error; 4784 4785 if (opnd_size_prefix) { 4786 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 4787 sizeof (instable_t); 4788 dp = (instable_t *)&dis_opSIMD7123[off]; 4789 opnd_size_prefix = 0; 4790 if (opnd_size == SIZE16) 4791 opnd_size = SIZE32; 4792 } 4793 break; 4794 case MRw: 4795 if (rep_prefix) { 4796 if (rep_prefix == 0xf3) { 4797 4798 /* 4799 * Calculate our offset in dis_op0F 4800 */ 4801 if ((uintptr_t)dp - (uintptr_t)dis_op0F > 4802 sizeof (dis_op0F)) 4803 goto error; 4804 4805 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4806 sizeof (instable_t); 4807 4808 dp = (instable_t *)&dis_opSIMDrepz[off]; 4809 rep_prefix = 0; 4810 } else { 4811 goto error; 4812 } 4813 } 4814 break; 4815 case FSGS: 4816 if (rep_prefix == 0xf3) { 4817 if ((uintptr_t)dp - (uintptr_t)dis_op0FAE > 4818 sizeof (dis_op0FAE)) 4819 goto error; 4820 4821 off = ((uintptr_t)dp - (uintptr_t)dis_op0FAE) / 4822 sizeof (instable_t); 4823 dp = (instable_t *)&dis_opF30FAE[off]; 4824 rep_prefix = 0; 4825 } else if (rep_prefix != 0x00) { 4826 goto error; 4827 } 4828 } 4829 4830 /* 4831 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 4832 */ 4833 if (cpu_mode == SIZE64) 4834 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 4835 opnd_size = SIZE64; 4836 4837 #ifdef DIS_TEXT 4838 /* 4839 * At this point most instructions can format the opcode mnemonic 4840 * including the prefixes. 4841 */ 4842 if (lock_prefix) 4843 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 4844 4845 if (rep_prefix == 0xf2) 4846 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 4847 else if (rep_prefix == 0xf3) 4848 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 4849 4850 if (cpu_mode == SIZE64 && addr_size_prefix) 4851 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 4852 4853 if (dp->it_adrmode != CBW && 4854 dp->it_adrmode != CWD && 4855 dp->it_adrmode != XMMSFNC) { 4856 if (strcmp(dp->it_name, "INVALID") == 0) 4857 goto error; 4858 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 4859 if (dp->it_avxsuf == AVS2 && dp->it_suffix) { 4860 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 4861 OPLEN); 4862 } else if (dp->it_vexopmask && dp->it_suffix) { 4863 /* opmask instructions */ 4864 4865 if (opcode1 == 4 && opcode2 == 0xb) { 4866 /* It's a kunpck. */ 4867 if (vex_prefix == VEX_2bytes) { 4868 (void) strlcat(x->d86_mnem, 4869 vex_p == 0 ? "wd" : "bw", OPLEN); 4870 } else { 4871 /* vex_prefix == VEX_3bytes */ 4872 (void) strlcat(x->d86_mnem, 4873 "dq", OPLEN); 4874 } 4875 } else if (opcode1 == 3) { 4876 /* It's a kshift[l|r]. */ 4877 if (vex_W == 0) { 4878 (void) strlcat(x->d86_mnem, 4879 opcode2 == 2 || 4880 opcode2 == 0 ? 4881 "b" : "d", OPLEN); 4882 } else { 4883 /* W == 1 */ 4884 (void) strlcat(x->d86_mnem, 4885 opcode2 == 3 || opcode2 == 1 ? 4886 "q" : "w", OPLEN); 4887 } 4888 } else { 4889 /* if (vex_prefix == VEX_2bytes) { */ 4890 if ((cpu_mode == SIZE64 && opnd_size == 2) || 4891 vex_prefix == VEX_2bytes) { 4892 (void) strlcat(x->d86_mnem, 4893 vex_p == 0 ? "w" : 4894 vex_p == 1 ? "b" : "d", 4895 OPLEN); 4896 } else { 4897 /* vex_prefix == VEX_3bytes */ 4898 (void) strlcat(x->d86_mnem, 4899 vex_p == 1 ? "d" : "q", OPLEN); 4900 } 4901 } 4902 } else if (dp->it_suffix) { 4903 char *types[] = {"", "w", "l", "q"}; 4904 if (opcode_bytes == 2 && opcode4 == 4) { 4905 /* It's a cmovx.yy. Replace the suffix x */ 4906 for (i = 5; i < OPLEN; i++) { 4907 if (x->d86_mnem[i] == '.') 4908 break; 4909 } 4910 x->d86_mnem[i - 1] = *types[opnd_size]; 4911 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 4912 ((opcode6 == 1 && opcode7 == 6) || 4913 (opcode6 == 2 && opcode7 == 2))) { 4914 /* 4915 * To handle PINSRD and PEXTRD 4916 */ 4917 (void) strlcat(x->d86_mnem, "d", OPLEN); 4918 } else if (dp != &dis_distable[0x6][0x2]) { 4919 /* bound instructions (0x62) have no suffix */ 4920 (void) strlcat(x->d86_mnem, types[opnd_size], 4921 OPLEN); 4922 } 4923 } 4924 } 4925 #endif 4926 4927 /* 4928 * Process operands based on the addressing modes. 4929 */ 4930 x->d86_mode = cpu_mode; 4931 /* 4932 * In vex mode the rex_prefix has no meaning 4933 */ 4934 if (!vex_prefix && evex_prefix == 0) 4935 x->d86_rex_prefix = rex_prefix; 4936 x->d86_opnd_size = opnd_size; 4937 x->d86_addr_size = addr_size; 4938 vbit = 0; /* initialize for mem/reg -> reg */ 4939 switch (dp->it_adrmode) { 4940 /* 4941 * amd64 instruction to sign extend 32 bit reg/mem operands 4942 * into 64 bit register values 4943 */ 4944 case MOVSXZ: 4945 #ifdef DIS_TEXT 4946 if (rex_prefix == 0) 4947 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 4948 #endif 4949 dtrace_get_modrm(x, &mode, ®, &r_m); 4950 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4951 x->d86_opnd_size = SIZE64; 4952 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4953 x->d86_opnd_size = opnd_size = SIZE32; 4954 wbit = LONG_OPND; 4955 dtrace_get_operand(x, mode, r_m, wbit, 0); 4956 break; 4957 4958 /* 4959 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 4960 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 4961 * wbit lives in 2nd byte, note that operands 4962 * are different sized 4963 */ 4964 case MOVZ: 4965 if (rex_prefix & REX_W) { 4966 /* target register size = 64 bit */ 4967 x->d86_mnem[5] = 'q'; 4968 } 4969 dtrace_get_modrm(x, &mode, ®, &r_m); 4970 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4971 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4972 x->d86_opnd_size = opnd_size = SIZE16; 4973 wbit = WBIT(opcode5); 4974 dtrace_get_operand(x, mode, r_m, wbit, 0); 4975 break; 4976 case CRC32: 4977 opnd_size = SIZE32; 4978 if (rex_prefix & REX_W) 4979 opnd_size = SIZE64; 4980 x->d86_opnd_size = opnd_size; 4981 4982 dtrace_get_modrm(x, &mode, ®, &r_m); 4983 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4984 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4985 wbit = WBIT(opcode7); 4986 if (opnd_size_prefix) 4987 x->d86_opnd_size = opnd_size = SIZE16; 4988 dtrace_get_operand(x, mode, r_m, wbit, 0); 4989 break; 4990 case MOVBE: 4991 opnd_size = SIZE32; 4992 if (rex_prefix & REX_W) 4993 opnd_size = SIZE64; 4994 x->d86_opnd_size = opnd_size; 4995 4996 dtrace_get_modrm(x, &mode, ®, &r_m); 4997 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4998 wbit = WBIT(opcode7); 4999 if (opnd_size_prefix) 5000 x->d86_opnd_size = opnd_size = SIZE16; 5001 if (wbit) { 5002 /* reg -> mem */ 5003 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 5004 dtrace_get_operand(x, mode, r_m, wbit, 1); 5005 } else { 5006 /* mem -> reg */ 5007 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 5008 dtrace_get_operand(x, mode, r_m, wbit, 0); 5009 } 5010 break; 5011 5012 /* 5013 * imul instruction, with either 8-bit or longer immediate 5014 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 5015 */ 5016 case IMUL: 5017 wbit = LONG_OPND; 5018 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 5019 OPSIZE(opnd_size, opcode2 == 0x9), 1); 5020 break; 5021 5022 /* memory or register operand to register, with 'w' bit */ 5023 case MRw: 5024 case ADX: 5025 wbit = WBIT(opcode2); 5026 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 5027 break; 5028 5029 /* register to memory or register operand, with 'w' bit */ 5030 /* arpl happens to fit here also because it is odd */ 5031 case RMw: 5032 if (opcode_bytes == 2) 5033 wbit = WBIT(opcode5); 5034 else 5035 wbit = WBIT(opcode2); 5036 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 5037 break; 5038 5039 /* xaddb instruction */ 5040 case XADDB: 5041 wbit = 0; 5042 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 5043 break; 5044 5045 /* MMX register to memory or register operand */ 5046 case MMS: 5047 case MMOS: 5048 #ifdef DIS_TEXT 5049 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 5050 #else 5051 wbit = LONG_OPND; 5052 #endif 5053 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 5054 break; 5055 5056 /* MMX register to memory */ 5057 case MMOMS: 5058 dtrace_get_modrm(x, &mode, ®, &r_m); 5059 if (mode == REG_ONLY) 5060 goto error; 5061 wbit = MM_OPND; 5062 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 5063 break; 5064 5065 /* Double shift. Has immediate operand specifying the shift. */ 5066 case DSHIFT: 5067 wbit = LONG_OPND; 5068 dtrace_get_modrm(x, &mode, ®, &r_m); 5069 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5070 dtrace_get_operand(x, mode, r_m, wbit, 2); 5071 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 5072 dtrace_imm_opnd(x, wbit, 1, 0); 5073 break; 5074 5075 /* 5076 * Double shift. With no immediate operand, specifies using %cl. 5077 */ 5078 case DSHIFTcl: 5079 wbit = LONG_OPND; 5080 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 5081 break; 5082 5083 /* immediate to memory or register operand */ 5084 case IMlw: 5085 wbit = WBIT(opcode2); 5086 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5087 dtrace_get_operand(x, mode, r_m, wbit, 1); 5088 /* 5089 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 5090 */ 5091 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 5092 break; 5093 5094 /* immediate to memory or register operand with the */ 5095 /* 'w' bit present */ 5096 case IMw: 5097 wbit = WBIT(opcode2); 5098 dtrace_get_modrm(x, &mode, ®, &r_m); 5099 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5100 dtrace_get_operand(x, mode, r_m, wbit, 1); 5101 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 5102 break; 5103 5104 /* immediate to register with register in low 3 bits */ 5105 /* of op code */ 5106 case IR: 5107 /* w-bit here (with regs) is bit 3 */ 5108 wbit = opcode2 >>3 & 0x1; 5109 reg = REGNO(opcode2); 5110 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 5111 mode = REG_ONLY; 5112 r_m = reg; 5113 dtrace_get_operand(x, mode, r_m, wbit, 1); 5114 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 5115 break; 5116 5117 /* MMX immediate shift of register */ 5118 case MMSH: 5119 case MMOSH: 5120 wbit = MM_OPND; 5121 goto mm_shift; /* in next case */ 5122 5123 /* SIMD immediate shift of register */ 5124 case XMMSH: 5125 wbit = XMM_OPND; 5126 mm_shift: 5127 reg = REGNO(opcode7); 5128 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 5129 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 5130 dtrace_imm_opnd(x, wbit, 1, 0); 5131 NOMEM; 5132 break; 5133 5134 /* accumulator to memory operand */ 5135 case AO: 5136 vbit = 1; 5137 /*FALLTHROUGH*/ 5138 5139 /* memory operand to accumulator */ 5140 case OA: 5141 wbit = WBIT(opcode2); 5142 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 5143 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 5144 #ifdef DIS_TEXT 5145 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 5146 #endif 5147 break; 5148 5149 5150 /* segment register to memory or register operand */ 5151 case SM: 5152 vbit = 1; 5153 /*FALLTHROUGH*/ 5154 5155 /* memory or register operand to segment register */ 5156 case MS: 5157 dtrace_get_modrm(x, &mode, ®, &r_m); 5158 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5159 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 5160 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 5161 break; 5162 5163 /* 5164 * rotate or shift instructions, which may shift by 1 or 5165 * consult the cl register, depending on the 'v' bit 5166 */ 5167 case Mv: 5168 vbit = VBIT(opcode2); 5169 wbit = WBIT(opcode2); 5170 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5171 dtrace_get_operand(x, mode, r_m, wbit, 1); 5172 #ifdef DIS_TEXT 5173 if (vbit) { 5174 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 5175 } else { 5176 x->d86_opnd[0].d86_mode = MODE_SIGNED; 5177 x->d86_opnd[0].d86_value_size = 1; 5178 x->d86_opnd[0].d86_value = 1; 5179 } 5180 #endif 5181 break; 5182 /* 5183 * immediate rotate or shift instructions 5184 */ 5185 case MvI: 5186 wbit = WBIT(opcode2); 5187 normal_imm_mem: 5188 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5189 dtrace_get_operand(x, mode, r_m, wbit, 1); 5190 dtrace_imm_opnd(x, wbit, 1, 0); 5191 break; 5192 5193 /* bit test instructions */ 5194 case MIb: 5195 wbit = LONG_OPND; 5196 goto normal_imm_mem; 5197 5198 /* single memory or register operand with 'w' bit present */ 5199 case Mw: 5200 wbit = WBIT(opcode2); 5201 just_mem: 5202 dtrace_get_modrm(x, &mode, ®, &r_m); 5203 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5204 dtrace_get_operand(x, mode, r_m, wbit, 0); 5205 break; 5206 5207 case SWAPGS_RDTSCP: 5208 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 5209 #ifdef DIS_TEXT 5210 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 5211 #endif 5212 NOMEM; 5213 break; 5214 } else if (mode == 3 && r_m == 1) { 5215 #ifdef DIS_TEXT 5216 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 5217 #endif 5218 NOMEM; 5219 break; 5220 } else if (mode == 3 && r_m == 2) { 5221 #ifdef DIS_TEXT 5222 (void) strncpy(x->d86_mnem, "monitorx", OPLEN); 5223 #endif 5224 NOMEM; 5225 break; 5226 } else if (mode == 3 && r_m == 3) { 5227 #ifdef DIS_TEXT 5228 (void) strncpy(x->d86_mnem, "mwaitx", OPLEN); 5229 #endif 5230 NOMEM; 5231 break; 5232 } else if (mode == 3 && r_m == 4) { 5233 #ifdef DIS_TEXT 5234 (void) strncpy(x->d86_mnem, "clzero", OPLEN); 5235 #endif 5236 NOMEM; 5237 break; 5238 } 5239 5240 /*FALLTHROUGH*/ 5241 5242 /* prefetch instruction - memory operand, but no memory acess */ 5243 case PREF: 5244 NOMEM; 5245 /*FALLTHROUGH*/ 5246 5247 /* single memory or register operand */ 5248 case M: 5249 case MG9: 5250 wbit = LONG_OPND; 5251 goto just_mem; 5252 5253 /* single memory or register byte operand */ 5254 case Mb: 5255 wbit = BYTE_OPND; 5256 goto just_mem; 5257 5258 case VMx: 5259 if (mode == 3) { 5260 #ifdef DIS_TEXT 5261 char *vminstr; 5262 5263 switch (r_m) { 5264 case 1: 5265 vminstr = "vmcall"; 5266 break; 5267 case 2: 5268 vminstr = "vmlaunch"; 5269 break; 5270 case 3: 5271 vminstr = "vmresume"; 5272 break; 5273 case 4: 5274 vminstr = "vmxoff"; 5275 break; 5276 default: 5277 goto error; 5278 } 5279 5280 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 5281 #else 5282 if (r_m < 1 || r_m > 4) 5283 goto error; 5284 #endif 5285 5286 NOMEM; 5287 break; 5288 } 5289 /*FALLTHROUGH*/ 5290 case SVM: 5291 if (mode == 3) { 5292 #if DIS_TEXT 5293 char *vinstr; 5294 5295 switch (r_m) { 5296 case 0: 5297 vinstr = "vmrun"; 5298 break; 5299 case 1: 5300 vinstr = "vmmcall"; 5301 break; 5302 case 2: 5303 vinstr = "vmload"; 5304 break; 5305 case 3: 5306 vinstr = "vmsave"; 5307 break; 5308 case 4: 5309 vinstr = "stgi"; 5310 break; 5311 case 5: 5312 vinstr = "clgi"; 5313 break; 5314 case 6: 5315 vinstr = "skinit"; 5316 break; 5317 case 7: 5318 vinstr = "invlpga"; 5319 break; 5320 } 5321 5322 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 5323 #endif 5324 NOMEM; 5325 break; 5326 } 5327 /*FALLTHROUGH*/ 5328 case MONITOR_MWAIT: 5329 if (mode == 3) { 5330 if (r_m == 0) { 5331 #ifdef DIS_TEXT 5332 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 5333 #endif 5334 NOMEM; 5335 break; 5336 } else if (r_m == 1) { 5337 #ifdef DIS_TEXT 5338 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 5339 #endif 5340 NOMEM; 5341 break; 5342 } else if (r_m == 2) { 5343 #ifdef DIS_TEXT 5344 (void) strncpy(x->d86_mnem, "clac", OPLEN); 5345 #endif 5346 NOMEM; 5347 break; 5348 } else if (r_m == 3) { 5349 #ifdef DIS_TEXT 5350 (void) strncpy(x->d86_mnem, "stac", OPLEN); 5351 #endif 5352 NOMEM; 5353 break; 5354 } else { 5355 goto error; 5356 } 5357 } 5358 /*FALLTHROUGH*/ 5359 case XGETBV_XSETBV: 5360 if (mode == 3) { 5361 if (r_m == 0) { 5362 #ifdef DIS_TEXT 5363 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 5364 #endif 5365 NOMEM; 5366 break; 5367 } else if (r_m == 1) { 5368 #ifdef DIS_TEXT 5369 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 5370 #endif 5371 NOMEM; 5372 break; 5373 } else { 5374 goto error; 5375 } 5376 5377 } 5378 /*FALLTHROUGH*/ 5379 case MO: 5380 /* Similar to M, but only memory (no direct registers) */ 5381 wbit = LONG_OPND; 5382 dtrace_get_modrm(x, &mode, ®, &r_m); 5383 if (mode == 3) 5384 goto error; 5385 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5386 dtrace_get_operand(x, mode, r_m, wbit, 0); 5387 break; 5388 5389 /* move special register to register or reverse if vbit */ 5390 case SREG: 5391 switch (opcode5) { 5392 5393 case 2: 5394 vbit = 1; 5395 /*FALLTHROUGH*/ 5396 case 0: 5397 wbit = CONTROL_OPND; 5398 break; 5399 5400 case 3: 5401 vbit = 1; 5402 /*FALLTHROUGH*/ 5403 case 1: 5404 wbit = DEBUG_OPND; 5405 break; 5406 5407 case 6: 5408 vbit = 1; 5409 /*FALLTHROUGH*/ 5410 case 4: 5411 wbit = TEST_OPND; 5412 break; 5413 5414 } 5415 dtrace_get_modrm(x, &mode, ®, &r_m); 5416 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5417 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 5418 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 5419 NOMEM; 5420 break; 5421 5422 /* 5423 * single register operand with register in the low 3 5424 * bits of op code 5425 */ 5426 case R: 5427 if (opcode_bytes == 2) 5428 reg = REGNO(opcode5); 5429 else 5430 reg = REGNO(opcode2); 5431 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 5432 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 5433 NOMEM; 5434 break; 5435 5436 /* 5437 * register to accumulator with register in the low 3 5438 * bits of op code, xchg instructions 5439 */ 5440 case RA: 5441 NOMEM; 5442 reg = REGNO(opcode2); 5443 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 5444 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 5445 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 5446 break; 5447 5448 case RMATCH: 5449 x->d86_opnd_size = x->d86_mode; 5450 dtrace_get_modrm(x, &mode, ®, &r_m); 5451 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5452 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5453 break; 5454 5455 /* 5456 * single segment register operand, with register in 5457 * bits 3-4 of op code byte 5458 */ 5459 case SEG: 5460 NOMEM; 5461 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 5462 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 5463 break; 5464 5465 /* 5466 * single segment register operand, with register in 5467 * bits 3-5 of op code 5468 */ 5469 case LSEG: 5470 NOMEM; 5471 /* long seg reg from opcode */ 5472 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 5473 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 5474 break; 5475 5476 /* memory or register operand to register */ 5477 case MR: 5478 if (vex_prefetch) 5479 x->d86_got_modrm = 1; 5480 wbit = LONG_OPND; 5481 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 5482 break; 5483 5484 case RM: 5485 case RM_66r: 5486 if (vex_prefetch) 5487 x->d86_got_modrm = 1; 5488 wbit = LONG_OPND; 5489 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 5490 break; 5491 5492 /* MMX/SIMD-Int memory or mm reg to mm reg */ 5493 case MM: 5494 case MMO: 5495 #ifdef DIS_TEXT 5496 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 5497 #else 5498 wbit = LONG_OPND; 5499 #endif 5500 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 5501 break; 5502 5503 case MMOIMPL: 5504 #ifdef DIS_TEXT 5505 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 5506 #else 5507 wbit = LONG_OPND; 5508 #endif 5509 dtrace_get_modrm(x, &mode, ®, &r_m); 5510 if (mode != REG_ONLY) 5511 goto error; 5512 5513 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5514 dtrace_get_operand(x, mode, r_m, wbit, 0); 5515 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 5516 mode = 0; /* change for memory access size... */ 5517 break; 5518 5519 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 5520 case MMO3P: 5521 wbit = MM_OPND; 5522 goto xmm3p; 5523 case XMM3P: 5524 wbit = XMM_OPND; 5525 xmm3p: 5526 dtrace_get_modrm(x, &mode, ®, &r_m); 5527 if (mode != REG_ONLY) 5528 goto error; 5529 5530 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 5531 1); 5532 NOMEM; 5533 break; 5534 5535 case XMM3PM_66r: 5536 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 5537 1, 0); 5538 break; 5539 5540 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 5541 case MMOPRM: 5542 wbit = LONG_OPND; 5543 w2 = MM_OPND; 5544 goto xmmprm; 5545 case XMMPRM: 5546 case XMMPRM_66r: 5547 wbit = LONG_OPND; 5548 w2 = XMM_OPND; 5549 xmmprm: 5550 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 5551 break; 5552 5553 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 5554 case MMOPM: 5555 case MMOPM_66o: 5556 wbit = w2 = MM_OPND; 5557 goto xmmprm; 5558 5559 /* MMX/SIMD-Int mm reg to r32 */ 5560 case MMOM3: 5561 NOMEM; 5562 dtrace_get_modrm(x, &mode, ®, &r_m); 5563 if (mode != REG_ONLY) 5564 goto error; 5565 wbit = MM_OPND; 5566 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 5567 break; 5568 5569 /* SIMD memory or xmm reg operand to xmm reg */ 5570 case XMM: 5571 case XMM_66o: 5572 case XMM_66r: 5573 case XMMO: 5574 case XMMXIMPL: 5575 wbit = XMM_OPND; 5576 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 5577 5578 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 5579 goto error; 5580 5581 #ifdef DIS_TEXT 5582 /* 5583 * movlps and movhlps share opcodes. They differ in the 5584 * addressing modes allowed for their operands. 5585 * movhps and movlhps behave similarly. 5586 */ 5587 if (mode == REG_ONLY) { 5588 if (strcmp(dp->it_name, "movlps") == 0) 5589 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 5590 else if (strcmp(dp->it_name, "movhps") == 0) 5591 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 5592 } 5593 #endif 5594 if (dp->it_adrmode == XMMXIMPL) 5595 mode = 0; /* change for memory access size... */ 5596 break; 5597 5598 /* SIMD xmm reg to memory or xmm reg */ 5599 case XMMS: 5600 case XMMOS: 5601 case XMMMS: 5602 case XMMOMS: 5603 dtrace_get_modrm(x, &mode, ®, &r_m); 5604 #ifdef DIS_TEXT 5605 if ((strcmp(dp->it_name, "movlps") == 0 || 5606 strcmp(dp->it_name, "movhps") == 0 || 5607 strcmp(dp->it_name, "movntps") == 0) && 5608 mode == REG_ONLY) 5609 goto error; 5610 #endif 5611 wbit = XMM_OPND; 5612 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 5613 break; 5614 5615 /* SIMD memory to xmm reg */ 5616 case XMMM: 5617 case XMMM_66r: 5618 case XMMOM: 5619 wbit = XMM_OPND; 5620 dtrace_get_modrm(x, &mode, ®, &r_m); 5621 #ifdef DIS_TEXT 5622 if (mode == REG_ONLY) { 5623 if (strcmp(dp->it_name, "movhps") == 0) 5624 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 5625 else 5626 goto error; 5627 } 5628 #endif 5629 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 5630 break; 5631 5632 /* SIMD memory or r32 to xmm reg */ 5633 case XMM3MX: 5634 wbit = LONG_OPND; 5635 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 5636 break; 5637 5638 case XMM3MXS: 5639 wbit = LONG_OPND; 5640 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 5641 break; 5642 5643 /* SIMD memory or mm reg to xmm reg */ 5644 case XMMOMX: 5645 /* SIMD mm to xmm */ 5646 case XMMMX: 5647 wbit = MM_OPND; 5648 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 5649 break; 5650 5651 /* SIMD memory or xmm reg to mm reg */ 5652 case XMMXMM: 5653 case XMMOXMM: 5654 case XMMXM: 5655 wbit = XMM_OPND; 5656 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 5657 break; 5658 5659 5660 /* SIMD memory or xmm reg to r32 */ 5661 case XMMXM3: 5662 wbit = XMM_OPND; 5663 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 5664 break; 5665 5666 /* SIMD xmm to r32 */ 5667 case XMMX3: 5668 case XMMOX3: 5669 dtrace_get_modrm(x, &mode, ®, &r_m); 5670 if (mode != REG_ONLY) 5671 goto error; 5672 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5673 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 5674 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 5675 NOMEM; 5676 break; 5677 5678 /* SIMD predicated memory or xmm reg with/to xmm reg */ 5679 case XMMP: 5680 case XMMP_66r: 5681 case XMMP_66o: 5682 case XMMOPM: 5683 wbit = XMM_OPND; 5684 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 5685 1); 5686 5687 #ifdef DIS_TEXT 5688 /* 5689 * cmpps and cmpss vary their instruction name based 5690 * on the value of imm8. Other XMMP instructions, 5691 * such as shufps, require explicit specification of 5692 * the predicate. 5693 */ 5694 if (dp->it_name[0] == 'c' && 5695 dp->it_name[1] == 'm' && 5696 dp->it_name[2] == 'p' && 5697 strlen(dp->it_name) == 5) { 5698 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 5699 5700 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 5701 goto error; 5702 5703 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 5704 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 5705 OPLEN); 5706 (void) strlcat(x->d86_mnem, 5707 dp->it_name + strlen(dp->it_name) - 2, 5708 OPLEN); 5709 x->d86_opnd[0] = x->d86_opnd[1]; 5710 x->d86_opnd[1] = x->d86_opnd[2]; 5711 x->d86_numopnds = 2; 5712 } 5713 5714 /* 5715 * The pclmulqdq instruction has a series of alternate names for 5716 * various encodings of the immediate byte. As such, if we 5717 * happen to find it and the immediate value matches, we'll 5718 * rewrite the mnemonic. 5719 */ 5720 if (strcmp(dp->it_name, "pclmulqdq") == 0) { 5721 boolean_t changed = B_TRUE; 5722 switch (x->d86_opnd[0].d86_value) { 5723 case 0x00: 5724 (void) strncpy(x->d86_mnem, "pclmullqlqdq", 5725 OPLEN); 5726 break; 5727 case 0x01: 5728 (void) strncpy(x->d86_mnem, "pclmulhqlqdq", 5729 OPLEN); 5730 break; 5731 case 0x10: 5732 (void) strncpy(x->d86_mnem, "pclmullqhqdq", 5733 OPLEN); 5734 break; 5735 case 0x11: 5736 (void) strncpy(x->d86_mnem, "pclmulhqhqdq", 5737 OPLEN); 5738 break; 5739 default: 5740 changed = B_FALSE; 5741 break; 5742 } 5743 5744 if (changed == B_TRUE) { 5745 x->d86_opnd[0].d86_value_size = 0; 5746 x->d86_opnd[0] = x->d86_opnd[1]; 5747 x->d86_opnd[1] = x->d86_opnd[2]; 5748 x->d86_numopnds = 2; 5749 } 5750 } 5751 #endif 5752 break; 5753 5754 case XMMX2I: 5755 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 5756 1); 5757 NOMEM; 5758 break; 5759 5760 case XMM2I: 5761 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 5762 NOMEM; 5763 break; 5764 5765 /* immediate operand to accumulator */ 5766 case IA: 5767 wbit = WBIT(opcode2); 5768 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5769 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 5770 NOMEM; 5771 break; 5772 5773 /* memory or register operand to accumulator */ 5774 case MA: 5775 wbit = WBIT(opcode2); 5776 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5777 dtrace_get_operand(x, mode, r_m, wbit, 0); 5778 break; 5779 5780 /* si register to di register used to reference memory */ 5781 case SD: 5782 #ifdef DIS_TEXT 5783 dtrace_check_override(x, 0); 5784 x->d86_numopnds = 2; 5785 if (addr_size == SIZE64) { 5786 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5787 OPLEN); 5788 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5789 OPLEN); 5790 } else if (addr_size == SIZE32) { 5791 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5792 OPLEN); 5793 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5794 OPLEN); 5795 } else { 5796 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5797 OPLEN); 5798 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5799 OPLEN); 5800 } 5801 #endif 5802 wbit = LONG_OPND; 5803 break; 5804 5805 /* accumulator to di register */ 5806 case AD: 5807 wbit = WBIT(opcode2); 5808 #ifdef DIS_TEXT 5809 dtrace_check_override(x, 1); 5810 x->d86_numopnds = 2; 5811 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 5812 if (addr_size == SIZE64) 5813 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5814 OPLEN); 5815 else if (addr_size == SIZE32) 5816 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5817 OPLEN); 5818 else 5819 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5820 OPLEN); 5821 #endif 5822 break; 5823 5824 /* si register to accumulator */ 5825 case SA: 5826 wbit = WBIT(opcode2); 5827 #ifdef DIS_TEXT 5828 dtrace_check_override(x, 0); 5829 x->d86_numopnds = 2; 5830 if (addr_size == SIZE64) 5831 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5832 OPLEN); 5833 else if (addr_size == SIZE32) 5834 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5835 OPLEN); 5836 else 5837 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5838 OPLEN); 5839 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5840 #endif 5841 break; 5842 5843 /* 5844 * single operand, a 16/32 bit displacement 5845 */ 5846 case D: 5847 wbit = LONG_OPND; 5848 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5849 NOMEM; 5850 break; 5851 5852 /* jmp/call indirect to memory or register operand */ 5853 case INM: 5854 #ifdef DIS_TEXT 5855 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 5856 #endif 5857 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5858 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5859 wbit = LONG_OPND; 5860 break; 5861 5862 /* 5863 * for long jumps and long calls -- a new code segment 5864 * register and an offset in IP -- stored in object 5865 * code in reverse order. Note - not valid in amd64 5866 */ 5867 case SO: 5868 dtrace_check_override(x, 1); 5869 wbit = LONG_OPND; 5870 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 5871 #ifdef DIS_TEXT 5872 x->d86_opnd[1].d86_mode = MODE_SIGNED; 5873 #endif 5874 /* will now get segment operand */ 5875 dtrace_imm_opnd(x, wbit, 2, 0); 5876 break; 5877 5878 /* 5879 * jmp/call. single operand, 8 bit displacement. 5880 * added to current EIP in 'compofff' 5881 */ 5882 case BD: 5883 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 5884 NOMEM; 5885 break; 5886 5887 /* single 32/16 bit immediate operand */ 5888 case I: 5889 wbit = LONG_OPND; 5890 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5891 break; 5892 5893 /* single 8 bit immediate operand */ 5894 case Ib: 5895 wbit = LONG_OPND; 5896 dtrace_imm_opnd(x, wbit, 1, 0); 5897 break; 5898 5899 case ENTER: 5900 wbit = LONG_OPND; 5901 dtrace_imm_opnd(x, wbit, 2, 0); 5902 dtrace_imm_opnd(x, wbit, 1, 1); 5903 switch (opnd_size) { 5904 case SIZE64: 5905 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 5906 break; 5907 case SIZE32: 5908 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 5909 break; 5910 case SIZE16: 5911 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 5912 break; 5913 } 5914 5915 break; 5916 5917 /* 16-bit immediate operand */ 5918 case RET: 5919 wbit = LONG_OPND; 5920 dtrace_imm_opnd(x, wbit, 2, 0); 5921 break; 5922 5923 /* single 8 bit port operand */ 5924 case P: 5925 dtrace_check_override(x, 0); 5926 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5927 NOMEM; 5928 break; 5929 5930 /* single operand, dx register (variable port instruction) */ 5931 case V: 5932 x->d86_numopnds = 1; 5933 dtrace_check_override(x, 0); 5934 #ifdef DIS_TEXT 5935 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 5936 #endif 5937 NOMEM; 5938 break; 5939 5940 /* 5941 * The int instruction, which has two forms: 5942 * int 3 (breakpoint) or 5943 * int n, where n is indicated in the subsequent 5944 * byte (format Ib). The int 3 instruction (opcode 0xCC), 5945 * where, although the 3 looks like an operand, 5946 * it is implied by the opcode. It must be converted 5947 * to the correct base and output. 5948 */ 5949 case INT3: 5950 #ifdef DIS_TEXT 5951 x->d86_numopnds = 1; 5952 x->d86_opnd[0].d86_mode = MODE_SIGNED; 5953 x->d86_opnd[0].d86_value_size = 1; 5954 x->d86_opnd[0].d86_value = 3; 5955 #endif 5956 NOMEM; 5957 break; 5958 5959 /* single 8 bit immediate operand */ 5960 case INTx: 5961 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5962 NOMEM; 5963 break; 5964 5965 /* an unused byte must be discarded */ 5966 case U: 5967 if (x->d86_get_byte(x->d86_data) < 0) 5968 goto error; 5969 x->d86_len++; 5970 NOMEM; 5971 break; 5972 5973 case CBW: 5974 #ifdef DIS_TEXT 5975 if (opnd_size == SIZE16) 5976 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 5977 else if (opnd_size == SIZE32) 5978 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 5979 else 5980 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 5981 #endif 5982 wbit = LONG_OPND; 5983 NOMEM; 5984 break; 5985 5986 case CWD: 5987 #ifdef DIS_TEXT 5988 if (opnd_size == SIZE16) 5989 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 5990 else if (opnd_size == SIZE32) 5991 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 5992 else 5993 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 5994 #endif 5995 wbit = LONG_OPND; 5996 NOMEM; 5997 break; 5998 5999 case XMMSFNC: 6000 /* 6001 * sfence is sfence if mode is REG_ONLY. If mode isn't 6002 * REG_ONLY, mnemonic should be 'clflush'. 6003 */ 6004 dtrace_get_modrm(x, &mode, ®, &r_m); 6005 6006 /* sfence doesn't take operands */ 6007 if (mode != REG_ONLY) { 6008 if (opnd_size_prefix == 0x66) { 6009 #ifdef DIS_TEXT 6010 (void) strlcat(x->d86_mnem, "clflushopt", 6011 OPLEN); 6012 #endif 6013 } else if (opnd_size_prefix == 0) { 6014 #ifdef DIS_TEXT 6015 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 6016 #endif 6017 } else { 6018 /* Unknown instruction */ 6019 goto error; 6020 } 6021 6022 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 6023 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 6024 NOMEM; 6025 #ifdef DIS_TEXT 6026 } else { 6027 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 6028 #endif 6029 } 6030 break; 6031 6032 case FSGS: 6033 /* 6034 * The FSGSBASE instructions are taken only when the mode is set 6035 * to registers. They share opcodes with instructions like 6036 * fxrstor, stmxcsr, etc. We handle the repz prefix earlier. 6037 */ 6038 wbit = WBIT(opcode2); 6039 dtrace_get_modrm(x, &mode, ®, &r_m); 6040 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 6041 dtrace_get_operand(x, mode, r_m, wbit, 0); 6042 if (mode == REG_ONLY) { 6043 NOMEM; 6044 } 6045 break; 6046 6047 /* 6048 * no disassembly, the mnemonic was all there was so go on 6049 */ 6050 case NORM: 6051 if (dp->it_invalid32 && cpu_mode != SIZE64) 6052 goto error; 6053 NOMEM; 6054 /*FALLTHROUGH*/ 6055 case IMPLMEM: 6056 break; 6057 6058 case XMMFENCE: 6059 /* 6060 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but 6061 * differ in mode and reg. 6062 */ 6063 dtrace_get_modrm(x, &mode, ®, &r_m); 6064 6065 if (mode == REG_ONLY) { 6066 /* 6067 * Only the following exact byte sequences are allowed: 6068 * 6069 * 0f ae e8 lfence 6070 * 0f ae f0 mfence 6071 */ 6072 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 6073 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 6074 goto error; 6075 } else { 6076 #ifdef DIS_TEXT 6077 if (reg == 5) { 6078 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 6079 } else if (reg == 6) { 6080 if (opnd_size_prefix == 0x66) { 6081 (void) strncpy(x->d86_mnem, "clwb", 6082 OPLEN); 6083 } else if (opnd_size_prefix == 0x00) { 6084 (void) strncpy(x->d86_mnem, "xsaveopt", 6085 OPLEN); 6086 } else { 6087 goto error; 6088 } 6089 } else { 6090 goto error; 6091 } 6092 #endif 6093 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 6094 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 6095 } 6096 break; 6097 6098 /* float reg */ 6099 case F: 6100 #ifdef DIS_TEXT 6101 x->d86_numopnds = 1; 6102 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 6103 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 6104 #endif 6105 NOMEM; 6106 break; 6107 6108 /* float reg to float reg, with ret bit present */ 6109 case FF: 6110 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 6111 /*FALLTHROUGH*/ 6112 case FFC: /* case for vbit always = 0 */ 6113 #ifdef DIS_TEXT 6114 x->d86_numopnds = 2; 6115 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 6116 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 6117 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 6118 #endif 6119 NOMEM; 6120 break; 6121 6122 /* AVX instructions */ 6123 case VEX_MO: 6124 /* op(ModR/M.r/m) */ 6125 x->d86_numopnds = 1; 6126 dtrace_get_modrm(x, &mode, ®, &r_m); 6127 #ifdef DIS_TEXT 6128 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 6129 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 6130 #endif 6131 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6132 dtrace_get_operand(x, mode, r_m, wbit, 0); 6133 break; 6134 case VEX_RMrX: 6135 case FMA: 6136 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 6137 x->d86_numopnds = 3; 6138 dtrace_get_modrm(x, &mode, ®, &r_m); 6139 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6140 6141 /* 6142 * In classic Intel fashion, the opcodes for all of the FMA 6143 * instructions all have two possible mnemonics which vary by 6144 * one letter, which is selected based on the value of the wbit. 6145 * When wbit is one, they have the 'd' suffix and when 'wbit' is 6146 * 0, they have the 's' suffix. Otherwise, the FMA instructions 6147 * are all a standard VEX_RMrX. 6148 */ 6149 #ifdef DIS_TEXT 6150 if (dp->it_adrmode == FMA) { 6151 size_t len = strlen(dp->it_name); 6152 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 6153 if (len + 1 < OPLEN) { 6154 (void) strncpy(x->d86_mnem + len, 6155 vex_W != 0 ? "d" : "s", OPLEN - len); 6156 } 6157 } 6158 #endif 6159 6160 if (mode != REG_ONLY) { 6161 if ((dp == &dis_opAVXF20F[0x10]) || 6162 (dp == &dis_opAVXF30F[0x10])) { 6163 /* vmovsd <m64>, <xmm> */ 6164 /* or vmovss <m64>, <xmm> */ 6165 x->d86_numopnds = 2; 6166 goto L_VEX_MX; 6167 } 6168 } 6169 6170 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6171 /* 6172 * VEX prefix uses the 1's complement form to encode the 6173 * XMM/YMM regs 6174 */ 6175 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6176 6177 if ((dp == &dis_opAVXF20F[0x2A]) || 6178 (dp == &dis_opAVXF30F[0x2A])) { 6179 /* 6180 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 6181 * <xmm>, <xmm> 6182 */ 6183 wbit = LONG_OPND; 6184 } 6185 #ifdef DIS_TEXT 6186 else if ((mode == REG_ONLY) && 6187 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 6188 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 6189 } else if ((mode == REG_ONLY) && 6190 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 6191 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 6192 } 6193 #endif 6194 dtrace_get_operand(x, mode, r_m, wbit, 0); 6195 6196 break; 6197 6198 case VEX_VRMrX: 6199 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */ 6200 x->d86_numopnds = 3; 6201 dtrace_get_modrm(x, &mode, ®, &r_m); 6202 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6203 6204 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6205 /* 6206 * VEX prefix uses the 1's complement form to encode the 6207 * XMM/YMM regs 6208 */ 6209 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0); 6210 6211 dtrace_get_operand(x, mode, r_m, wbit, 1); 6212 break; 6213 6214 case VEX_SbVM: 6215 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */ 6216 x->d86_numopnds = 3; 6217 x->d86_vsib = 1; 6218 6219 /* 6220 * All instructions that use VSIB are currently a mess. See the 6221 * comment around the dis_gather_regs_t structure definition. 6222 */ 6223 6224 vreg = &dis_vgather[opcode2][vex_W][vex_L]; 6225 6226 #ifdef DIS_TEXT 6227 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 6228 (void) strlcat(x->d86_mnem + strlen(dp->it_name), 6229 vreg->dgr_suffix, OPLEN - strlen(dp->it_name)); 6230 #endif 6231 6232 dtrace_get_modrm(x, &mode, ®, &r_m); 6233 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6234 6235 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2); 6236 /* 6237 * VEX prefix uses the 1's complement form to encode the 6238 * XMM/YMM regs 6239 */ 6240 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0, 6241 0); 6242 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1); 6243 break; 6244 6245 case VEX_RRX: 6246 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 6247 x->d86_numopnds = 3; 6248 6249 dtrace_get_modrm(x, &mode, ®, &r_m); 6250 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6251 6252 if (mode != REG_ONLY) { 6253 if ((dp == &dis_opAVXF20F[0x11]) || 6254 (dp == &dis_opAVXF30F[0x11])) { 6255 /* vmovsd <xmm>, <m64> */ 6256 /* or vmovss <xmm>, <m64> */ 6257 x->d86_numopnds = 2; 6258 goto L_VEX_RM; 6259 } 6260 } 6261 6262 dtrace_get_operand(x, mode, r_m, wbit, 2); 6263 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6264 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6265 break; 6266 6267 case VEX_RMRX: 6268 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 6269 x->d86_numopnds = 4; 6270 6271 dtrace_get_modrm(x, &mode, ®, &r_m); 6272 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6273 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 6274 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 6275 if (dp == &dis_opAVX660F3A[0x18]) { 6276 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 6277 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 6278 } else if ((dp == &dis_opAVX660F3A[0x20]) || 6279 (dp == & dis_opAVX660F[0xC4])) { 6280 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 6281 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 6282 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6283 } else if (dp == &dis_opAVX660F3A[0x22]) { 6284 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 6285 #ifdef DIS_TEXT 6286 if (vex_W) 6287 x->d86_mnem[6] = 'q'; 6288 #endif 6289 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6290 } else { 6291 dtrace_get_operand(x, mode, r_m, wbit, 1); 6292 } 6293 6294 /* one byte immediate number */ 6295 dtrace_imm_opnd(x, wbit, 1, 0); 6296 6297 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 6298 if ((dp == &dis_opAVX660F3A[0x4A]) || 6299 (dp == &dis_opAVX660F3A[0x4B]) || 6300 (dp == &dis_opAVX660F3A[0x4C])) { 6301 #ifdef DIS_TEXT 6302 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 6303 #endif 6304 x->d86_opnd[0].d86_mode = MODE_NONE; 6305 #ifdef DIS_TEXT 6306 if (vex_L) 6307 (void) strncpy(x->d86_opnd[0].d86_opnd, 6308 dis_YMMREG[regnum], OPLEN); 6309 else 6310 (void) strncpy(x->d86_opnd[0].d86_opnd, 6311 dis_XMMREG[regnum], OPLEN); 6312 #endif 6313 } 6314 break; 6315 6316 case VEX_MX: 6317 /* ModR/M.reg := op(ModR/M.rm) */ 6318 x->d86_numopnds = 2; 6319 6320 dtrace_get_modrm(x, &mode, ®, &r_m); 6321 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6322 L_VEX_MX: 6323 6324 if ((dp == &dis_opAVXF20F[0xE6]) || 6325 (dp == &dis_opAVX660F[0x5A]) || 6326 (dp == &dis_opAVX660F[0xE6])) { 6327 /* vcvtpd2dq <ymm>, <xmm> */ 6328 /* or vcvtpd2ps <ymm>, <xmm> */ 6329 /* or vcvttpd2dq <ymm>, <xmm> */ 6330 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 6331 dtrace_get_operand(x, mode, r_m, wbit, 0); 6332 } else if ((dp == &dis_opAVXF30F[0xE6]) || 6333 (dp == &dis_opAVX0F[0x5][0xA]) || 6334 (dp == &dis_opAVX660F38[0x13]) || 6335 (dp == &dis_opAVX660F38[0x18]) || 6336 (dp == &dis_opAVX660F38[0x19]) || 6337 (dp == &dis_opAVX660F38[0x58]) || 6338 (dp == &dis_opAVX660F38[0x78]) || 6339 (dp == &dis_opAVX660F38[0x79]) || 6340 (dp == &dis_opAVX660F38[0x59])) { 6341 /* vcvtdq2pd <xmm>, <ymm> */ 6342 /* or vcvtps2pd <xmm>, <ymm> */ 6343 /* or vcvtph2ps <xmm>, <ymm> */ 6344 /* or vbroadcasts* <xmm>, <ymm> */ 6345 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6346 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 6347 } else if (dp == &dis_opAVX660F[0x6E]) { 6348 /* vmovd/q <reg/mem 32/64>, <xmm> */ 6349 #ifdef DIS_TEXT 6350 if (vex_W) 6351 x->d86_mnem[4] = 'q'; 6352 #endif 6353 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6354 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 6355 } else { 6356 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6357 dtrace_get_operand(x, mode, r_m, wbit, 0); 6358 } 6359 6360 break; 6361 6362 case VEX_MXI: 6363 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 6364 x->d86_numopnds = 3; 6365 6366 dtrace_get_modrm(x, &mode, ®, &r_m); 6367 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6368 6369 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6370 dtrace_get_operand(x, mode, r_m, wbit, 1); 6371 6372 /* one byte immediate number */ 6373 dtrace_imm_opnd(x, wbit, 1, 0); 6374 break; 6375 6376 case VEX_XXI: 6377 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 6378 x->d86_numopnds = 3; 6379 6380 dtrace_get_modrm(x, &mode, ®, &r_m); 6381 #ifdef DIS_TEXT 6382 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 6383 OPLEN); 6384 #endif 6385 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6386 6387 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 6388 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 6389 6390 /* one byte immediate number */ 6391 dtrace_imm_opnd(x, wbit, 1, 0); 6392 break; 6393 6394 case VEX_MR: 6395 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 6396 if (dp == &dis_opAVX660F[0xC5]) { 6397 /* vpextrw <imm8>, <xmm>, <reg> */ 6398 x->d86_numopnds = 2; 6399 vbit = 2; 6400 } else { 6401 x->d86_numopnds = 2; 6402 vbit = 1; 6403 } 6404 6405 dtrace_get_modrm(x, &mode, ®, &r_m); 6406 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6407 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 6408 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 6409 6410 if (vbit == 2) 6411 dtrace_imm_opnd(x, wbit, 1, 0); 6412 6413 break; 6414 6415 case VEX_KMR: 6416 /* opmask: mod_rm := %k */ 6417 x->d86_numopnds = 2; 6418 dtrace_get_modrm(x, &mode, ®, &r_m); 6419 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6420 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6421 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6422 break; 6423 6424 case VEX_KRM: 6425 /* opmask: mod_reg := mod_rm */ 6426 x->d86_numopnds = 2; 6427 dtrace_get_modrm(x, &mode, ®, &r_m); 6428 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6429 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6430 if (mode == REG_ONLY) { 6431 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0); 6432 } else { 6433 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 6434 } 6435 break; 6436 6437 case VEX_KRR: 6438 /* opmask: mod_reg := mod_rm */ 6439 x->d86_numopnds = 2; 6440 dtrace_get_modrm(x, &mode, ®, &r_m); 6441 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6442 dtrace_get_operand(x, mode, reg, wbit, 1); 6443 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0); 6444 break; 6445 6446 case VEX_RRI: 6447 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 6448 x->d86_numopnds = 2; 6449 6450 dtrace_get_modrm(x, &mode, ®, &r_m); 6451 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6452 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6453 dtrace_get_operand(x, mode, r_m, wbit, 0); 6454 break; 6455 6456 case VEX_RX: 6457 /* ModR/M.rm := op(ModR/M.reg) */ 6458 /* vextractf128 || vcvtps2ph */ 6459 if (dp == &dis_opAVX660F3A[0x19] || 6460 dp == &dis_opAVX660F3A[0x1d]) { 6461 x->d86_numopnds = 3; 6462 6463 dtrace_get_modrm(x, &mode, ®, &r_m); 6464 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6465 6466 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 6467 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6468 6469 /* one byte immediate number */ 6470 dtrace_imm_opnd(x, wbit, 1, 0); 6471 break; 6472 } 6473 6474 x->d86_numopnds = 2; 6475 6476 dtrace_get_modrm(x, &mode, ®, &r_m); 6477 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6478 dtrace_get_operand(x, mode, r_m, wbit, 1); 6479 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6480 break; 6481 6482 case VEX_RR: 6483 /* ModR/M.rm := op(ModR/M.reg) */ 6484 x->d86_numopnds = 2; 6485 6486 dtrace_get_modrm(x, &mode, ®, &r_m); 6487 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6488 6489 if (dp == &dis_opAVX660F[0x7E]) { 6490 /* vmovd/q <reg/mem 32/64>, <xmm> */ 6491 #ifdef DIS_TEXT 6492 if (vex_W) 6493 x->d86_mnem[4] = 'q'; 6494 #endif 6495 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6496 } else 6497 dtrace_get_operand(x, mode, r_m, wbit, 1); 6498 6499 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6500 break; 6501 6502 case VEX_RRi: 6503 /* ModR/M.rm := op(ModR/M.reg, imm) */ 6504 x->d86_numopnds = 3; 6505 6506 dtrace_get_modrm(x, &mode, ®, &r_m); 6507 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6508 6509 #ifdef DIS_TEXT 6510 if (dp == &dis_opAVX660F3A[0x16]) { 6511 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 6512 if (vex_W) 6513 x->d86_mnem[6] = 'q'; 6514 } 6515 #endif 6516 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 6517 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6518 6519 /* one byte immediate number */ 6520 dtrace_imm_opnd(x, wbit, 1, 0); 6521 break; 6522 case VEX_RIM: 6523 /* ModR/M.rm := op(ModR/M.reg, imm) */ 6524 x->d86_numopnds = 3; 6525 6526 dtrace_get_modrm(x, &mode, ®, &r_m); 6527 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6528 6529 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 6530 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6531 /* one byte immediate number */ 6532 dtrace_imm_opnd(x, wbit, 1, 0); 6533 break; 6534 6535 case VEX_RM: 6536 /* ModR/M.rm := op(ModR/M.reg) */ 6537 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 6538 x->d86_numopnds = 3; 6539 6540 dtrace_get_modrm(x, &mode, ®, &r_m); 6541 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6542 6543 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 6544 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6545 /* one byte immediate number */ 6546 dtrace_imm_opnd(x, wbit, 1, 0); 6547 break; 6548 } 6549 x->d86_numopnds = 2; 6550 6551 dtrace_get_modrm(x, &mode, ®, &r_m); 6552 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6553 L_VEX_RM: 6554 vbit = 1; 6555 dtrace_get_operand(x, mode, r_m, wbit, vbit); 6556 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 6557 6558 break; 6559 6560 case VEX_RRM: 6561 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 6562 x->d86_numopnds = 3; 6563 6564 dtrace_get_modrm(x, &mode, ®, &r_m); 6565 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6566 dtrace_get_operand(x, mode, r_m, wbit, 2); 6567 /* VEX use the 1's complement form encode the XMM/YMM regs */ 6568 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6569 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6570 break; 6571 6572 case VEX_RMX: 6573 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 6574 x->d86_numopnds = 3; 6575 6576 dtrace_get_modrm(x, &mode, ®, &r_m); 6577 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6578 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6579 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6580 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 6581 break; 6582 6583 case VEX_NONE: 6584 #ifdef DIS_TEXT 6585 if (vex_L) 6586 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 6587 #endif 6588 break; 6589 case BLS: { 6590 6591 /* 6592 * The BLS instructions are VEX instructions that are based on 6593 * VEX.0F38.F3; however, they are considered special group 17 6594 * and like everything else, they use the bits in 3-5 of the 6595 * MOD R/M to determine the sub instruction. Unlike many others 6596 * like the VMX instructions, these are valid both for memory 6597 * and register forms. 6598 */ 6599 6600 dtrace_get_modrm(x, &mode, ®, &r_m); 6601 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6602 6603 switch (reg) { 6604 case 1: 6605 #ifdef DIS_TEXT 6606 blsinstr = "blsr"; 6607 #endif 6608 break; 6609 case 2: 6610 #ifdef DIS_TEXT 6611 blsinstr = "blsmsk"; 6612 #endif 6613 break; 6614 case 3: 6615 #ifdef DIS_TEXT 6616 blsinstr = "blsi"; 6617 #endif 6618 break; 6619 default: 6620 goto error; 6621 } 6622 6623 x->d86_numopnds = 2; 6624 #ifdef DIS_TEXT 6625 (void) strncpy(x->d86_mnem, blsinstr, OPLEN); 6626 #endif 6627 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6628 dtrace_get_operand(x, mode, r_m, wbit, 0); 6629 break; 6630 } 6631 case EVEX_MX: 6632 /* ModR/M.reg := op(ModR/M.rm) */ 6633 x->d86_numopnds = 2; 6634 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6635 dtrace_get_modrm(x, &mode, ®, &r_m); 6636 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6637 dtrace_evex_adjust_reg(evex_byte1, ®); 6638 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6639 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6640 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6641 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 6642 dtrace_get_operand(x, mode, r_m, wbit, 0); 6643 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6644 break; 6645 case EVEX_MBX: 6646 /* ModR/M.reg := op(ModR/M.rm/M.bcast) */ 6647 x->d86_numopnds = 2; 6648 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6649 dtrace_get_modrm(x, &mode, ®, &r_m); 6650 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6651 dtrace_evex_adjust_reg(evex_byte1, ®); 6652 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6653 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6654 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6655 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 6656 dtrace_get_operand(x, mode, r_m, wbit, 0); 6657 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6658 dtrace_evex_adjust_bcast(x, 0, vex_W, wbit, evex_b); 6659 break; 6660 case EVEX_RX: 6661 /* ModR/M.rm := op(ModR/M.reg) */ 6662 x->d86_numopnds = 2; 6663 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6664 dtrace_get_modrm(x, &mode, ®, &r_m); 6665 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6666 dtrace_evex_adjust_reg(evex_byte1, ®); 6667 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6668 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6669 dtrace_get_operand(x, mode, r_m, wbit, 1); 6670 dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); 6671 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 6672 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6673 break; 6674 case EVEX_RMrX: 6675 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */ 6676 x->d86_numopnds = 3; 6677 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6678 dtrace_get_modrm(x, &mode, ®, &r_m); 6679 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6680 dtrace_evex_adjust_reg(evex_byte1, ®); 6681 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6682 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6683 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6684 /* 6685 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 6686 * register specifier). The EVEX prefix handling uses the vex_v 6687 * variable for these bits. 6688 */ 6689 dtrace_get_operand(x, REG_ONLY, (0x1F - vex_v), wbit, 1); 6690 dtrace_get_operand(x, mode, r_m, wbit, 0); 6691 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6692 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); 6693 break; 6694 case EVEX_RMBrX: 6695 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */ 6696 x->d86_numopnds = 3; 6697 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6698 dtrace_get_modrm(x, &mode, ®, &r_m); 6699 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6700 dtrace_evex_adjust_reg(evex_byte1, ®); 6701 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6702 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6703 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6704 /* 6705 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 6706 * register specifier). The EVEX prefix handling uses the vex_v 6707 * variable for these bits. 6708 */ 6709 dtrace_get_operand(x, REG_ONLY, (0x1F - vex_v), wbit, 1); 6710 dtrace_get_operand(x, mode, r_m, wbit, 0); 6711 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6712 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); 6713 dtrace_evex_adjust_bcast(x, 0, vex_W, wbit, evex_b); 6714 break; 6715 case EVEX_RMrK: 6716 /* opmask := op(EVEX.vvvv, ModR/M.r/m) */ 6717 x->d86_numopnds = 3; 6718 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6719 dtrace_get_modrm(x, &mode, ®, &r_m); 6720 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6721 dtrace_evex_adjust_reg(evex_byte1, ®); 6722 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6723 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6724 dtrace_get_operand(x, REG_ONLY, reg, KOPMASK_OPND, 2); 6725 /* 6726 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 6727 * register specifier). The EVEX prefix handling uses the vex_v 6728 * variable for these bits. 6729 */ 6730 dtrace_get_operand(x, REG_ONLY, (0x1F - vex_v), wbit, 1); 6731 dtrace_get_operand(x, mode, r_m, wbit, 0); 6732 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6733 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); 6734 break; 6735 6736 case EVEX_RMRX: 6737 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r_m, imm8) */ 6738 x->d86_numopnds = 4; 6739 6740 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6741 dtrace_get_modrm(x, &mode, ®, &r_m); 6742 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6743 dtrace_evex_adjust_reg(evex_byte1, ®); 6744 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6745 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6746 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 6747 /* 6748 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 6749 * register specifier). The EVEX prefix handling uses the vex_v 6750 * variable for these bits. 6751 */ 6752 dtrace_get_operand(x, REG_ONLY, (0x1F - vex_v), wbit, 2); 6753 dtrace_get_operand(x, mode, r_m, wbit, 1); 6754 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6755 dtrace_evex_adjust_z_opmask(x, 3, evex_byte3); 6756 6757 dtrace_imm_opnd(x, wbit, 1, 0); 6758 break; 6759 case MOVDIR: 6760 /* 6761 * The semantics of the movdir64b instruction is a little bit 6762 * weird and we need to trick the rest of the engine. In this 6763 * case we change d86_mode to match the operand/address size 6764 * that we overrode to earlier. Basically the standard CPU mode 6765 * doesn't actually influence which register set is used, but 6766 * the 0x67 prefix does. 6767 */ 6768 x->d86_numopnds = 2; 6769 x->d86_mode = x->d86_opnd_size; 6770 dtrace_get_modrm(x, &mode, ®, &r_m); 6771 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 6772 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 6773 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 6774 break; 6775 /* an invalid op code */ 6776 case AM: 6777 case DM: 6778 case OVERRIDE: 6779 case PREFIX: 6780 case UNKNOWN: 6781 NOMEM; 6782 default: 6783 goto error; 6784 } /* end switch */ 6785 if (x->d86_error) 6786 goto error; 6787 6788 done: 6789 #ifdef DIS_MEM 6790 if (dp == NULL) 6791 return (1); 6792 /* 6793 * compute the size of any memory accessed by the instruction 6794 */ 6795 if (x->d86_memsize != 0) { 6796 return (0); 6797 } else if (dp->it_stackop) { 6798 switch (opnd_size) { 6799 case SIZE16: 6800 x->d86_memsize = 2; 6801 break; 6802 case SIZE32: 6803 x->d86_memsize = 4; 6804 break; 6805 case SIZE64: 6806 x->d86_memsize = 8; 6807 break; 6808 } 6809 } else if (nomem || mode == REG_ONLY) { 6810 x->d86_memsize = 0; 6811 6812 } else if (dp->it_size != 0) { 6813 /* 6814 * In 64 bit mode descriptor table entries 6815 * go up to 10 bytes and popf/pushf are always 8 bytes 6816 */ 6817 if (x->d86_mode == SIZE64 && dp->it_size == 6) 6818 x->d86_memsize = 10; 6819 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 6820 (opcode2 == 0xc || opcode2 == 0xd)) 6821 x->d86_memsize = 8; 6822 else 6823 x->d86_memsize = dp->it_size; 6824 6825 } else if (wbit == 0) { 6826 x->d86_memsize = 1; 6827 6828 } else if (wbit == LONG_OPND) { 6829 if (opnd_size == SIZE64) 6830 x->d86_memsize = 8; 6831 else if (opnd_size == SIZE32) 6832 x->d86_memsize = 4; 6833 else 6834 x->d86_memsize = 2; 6835 6836 } else if (wbit == SEG_OPND) { 6837 x->d86_memsize = 4; 6838 6839 } else { 6840 x->d86_memsize = 8; 6841 } 6842 #endif 6843 return (0); 6844 6845 error: 6846 #ifdef DIS_TEXT 6847 (void) strlcat(x->d86_mnem, "undef", OPLEN); 6848 #endif 6849 return (1); 6850 } 6851 6852 #ifdef DIS_TEXT 6853 6854 /* 6855 * Some instructions should have immediate operands printed 6856 * as unsigned integers. We compare against this table. 6857 */ 6858 static char *unsigned_ops[] = { 6859 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 6860 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 6861 0 6862 }; 6863 6864 6865 static int 6866 isunsigned_op(char *opcode) 6867 { 6868 char *where; 6869 int i; 6870 int is_unsigned = 0; 6871 6872 /* 6873 * Work back to start of last mnemonic, since we may have 6874 * prefixes on some opcodes. 6875 */ 6876 where = opcode + strlen(opcode) - 1; 6877 while (where > opcode && *where != ' ') 6878 --where; 6879 if (*where == ' ') 6880 ++where; 6881 6882 for (i = 0; unsigned_ops[i]; ++i) { 6883 if (strncmp(where, unsigned_ops[i], 6884 strlen(unsigned_ops[i]))) 6885 continue; 6886 is_unsigned = 1; 6887 break; 6888 } 6889 return (is_unsigned); 6890 } 6891 6892 /* 6893 * Print a numeric immediate into end of buf, maximum length buflen. 6894 * The immediate may be an address or a displacement. Mask is set 6895 * for address size. If the immediate is a "small negative", or 6896 * if it's a negative displacement of any magnitude, print as -<absval>. 6897 * Respect the "octal" flag. "Small negative" is defined as "in the 6898 * interval [NEG_LIMIT, 0)". 6899 * 6900 * Also, "isunsigned_op()" instructions never print negatives. 6901 * 6902 * Return whether we decided to print a negative value or not. 6903 */ 6904 6905 #define NEG_LIMIT -255 6906 enum {IMM, DISP}; 6907 enum {POS, TRY_NEG}; 6908 6909 static int 6910 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 6911 size_t buflen, int disp, int try_neg) 6912 { 6913 int curlen; 6914 int64_t sv = (int64_t)usv; 6915 int octal = dis->d86_flags & DIS_F_OCTAL; 6916 6917 curlen = strlen(buf); 6918 6919 if (try_neg == TRY_NEG && sv < 0 && 6920 (disp || sv >= NEG_LIMIT) && 6921 !isunsigned_op(dis->d86_mnem)) { 6922 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6923 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 6924 return (1); 6925 } else { 6926 if (disp == DISP) 6927 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6928 octal ? "+0%llo" : "+0x%llx", usv & mask); 6929 else 6930 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6931 octal ? "0%llo" : "0x%llx", usv & mask); 6932 return (0); 6933 6934 } 6935 } 6936 6937 6938 static int 6939 log2(int size) 6940 { 6941 switch (size) { 6942 case 1: return (0); 6943 case 2: return (1); 6944 case 4: return (2); 6945 case 8: return (3); 6946 } 6947 return (0); 6948 } 6949 6950 /* ARGSUSED */ 6951 void 6952 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 6953 size_t buflen) 6954 { 6955 uint64_t reltgt = 0; 6956 uint64_t tgt = 0; 6957 int curlen; 6958 int (*lookup)(void *, uint64_t, char *, size_t); 6959 int i; 6960 int64_t sv; 6961 uint64_t usv, mask, save_mask, save_usv; 6962 static uint64_t masks[] = 6963 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 6964 save_usv = 0; 6965 6966 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 6967 6968 /* 6969 * For PC-relative jumps, the pc is really the next pc after executing 6970 * this instruction, so increment it appropriately. 6971 */ 6972 pc += dis->d86_len; 6973 6974 for (i = 0; i < dis->d86_numopnds; i++) { 6975 d86opnd_t *op = &dis->d86_opnd[i]; 6976 6977 if (i != 0) 6978 (void) strlcat(buf, ",", buflen); 6979 6980 (void) strlcat(buf, op->d86_prefix, buflen); 6981 6982 /* 6983 * sv is for the signed, possibly-truncated immediate or 6984 * displacement; usv retains the original size and 6985 * unsignedness for symbol lookup. 6986 */ 6987 6988 sv = usv = op->d86_value; 6989 6990 /* 6991 * About masks: for immediates that represent 6992 * addresses, the appropriate display size is 6993 * the effective address size of the instruction. 6994 * This includes MODE_OFFSET, MODE_IPREL, and 6995 * MODE_RIPREL. Immediates that are simply 6996 * immediate values should display in the operand's 6997 * size, however, since they don't represent addresses. 6998 */ 6999 7000 /* d86_addr_size is SIZEnn, which is log2(real size) */ 7001 mask = masks[dis->d86_addr_size]; 7002 7003 /* d86_value_size and d86_imm_bytes are in bytes */ 7004 if (op->d86_mode == MODE_SIGNED || 7005 op->d86_mode == MODE_IMPLIED) 7006 mask = masks[log2(op->d86_value_size)]; 7007 7008 switch (op->d86_mode) { 7009 7010 case MODE_NONE: 7011 7012 (void) strlcat(buf, op->d86_opnd, buflen); 7013 break; 7014 7015 case MODE_SIGNED: 7016 case MODE_IMPLIED: 7017 case MODE_OFFSET: 7018 7019 tgt = usv; 7020 7021 if (dis->d86_seg_prefix) 7022 (void) strlcat(buf, dis->d86_seg_prefix, 7023 buflen); 7024 7025 if (op->d86_mode == MODE_SIGNED || 7026 op->d86_mode == MODE_IMPLIED) { 7027 (void) strlcat(buf, "$", buflen); 7028 } 7029 7030 if (print_imm(dis, usv, mask, buf, buflen, 7031 IMM, TRY_NEG) && 7032 (op->d86_mode == MODE_SIGNED || 7033 op->d86_mode == MODE_IMPLIED)) { 7034 7035 /* 7036 * We printed a negative value for an 7037 * immediate that wasn't a 7038 * displacement. Note that fact so we can 7039 * print the positive value as an 7040 * annotation. 7041 */ 7042 7043 save_usv = usv; 7044 save_mask = mask; 7045 } 7046 (void) strlcat(buf, op->d86_opnd, buflen); 7047 break; 7048 7049 case MODE_IPREL: 7050 case MODE_RIPREL: 7051 7052 reltgt = pc + sv; 7053 7054 switch (mode) { 7055 case SIZE16: 7056 reltgt = (uint16_t)reltgt; 7057 break; 7058 case SIZE32: 7059 reltgt = (uint32_t)reltgt; 7060 break; 7061 } 7062 7063 (void) print_imm(dis, usv, mask, buf, buflen, 7064 DISP, TRY_NEG); 7065 7066 if (op->d86_mode == MODE_RIPREL) 7067 (void) strlcat(buf, "(%rip)", buflen); 7068 break; 7069 } 7070 } 7071 7072 /* 7073 * The symbol lookups may result in false positives, 7074 * particularly on object files, where small numbers may match 7075 * the 0-relative non-relocated addresses of symbols. 7076 */ 7077 7078 lookup = dis->d86_sym_lookup; 7079 if (tgt != 0) { 7080 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 7081 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 7082 (void) strlcat(buf, "\t<", buflen); 7083 curlen = strlen(buf); 7084 lookup(dis->d86_data, tgt, buf + curlen, 7085 buflen - curlen); 7086 (void) strlcat(buf, ">", buflen); 7087 } 7088 7089 /* 7090 * If we printed a negative immediate above, print the 7091 * positive in case our heuristic was unhelpful 7092 */ 7093 if (save_usv) { 7094 (void) strlcat(buf, "\t<", buflen); 7095 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 7096 IMM, POS); 7097 (void) strlcat(buf, ">", buflen); 7098 } 7099 } 7100 7101 if (reltgt != 0) { 7102 /* Print symbol or effective address for reltgt */ 7103 7104 (void) strlcat(buf, "\t<", buflen); 7105 curlen = strlen(buf); 7106 lookup(dis->d86_data, reltgt, buf + curlen, 7107 buflen - curlen); 7108 (void) strlcat(buf, ">", buflen); 7109 } 7110 } 7111 7112 #endif /* DIS_TEXT */ 7113