1 /* 2 * 3 * CDDL HEADER START 4 * 5 * The contents of this file are subject to the terms of the 6 * Common Development and Distribution License (the "License"). 7 * You may not use this file except in compliance with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved. 24 * Copyright 2019 Joyent, Inc. 25 * Copyright 2024 Oxide Computer Company 26 */ 27 28 /* 29 * Copyright (c) 2010, Intel Corporation. 30 * All rights reserved. 31 */ 32 33 /* Copyright (c) 1988 AT&T */ 34 /* All Rights Reserved */ 35 36 #include "dis_tables.h" 37 38 /* BEGIN CSTYLED */ 39 40 /* 41 * Disassembly begins in dis_distable, which is equivalent to the One-byte 42 * Opcode Map in the Intel IA32 ISA Reference (page A-6 in my copy). The 43 * decoding loops then traverse out through the other tables as necessary to 44 * decode a given instruction. 45 * 46 * The behavior of this file can be controlled by one of the following flags: 47 * 48 * DIS_TEXT Include text for disassembly 49 * DIS_MEM Include memory-size calculations 50 * 51 * Either or both of these can be defined. 52 * 53 * This file is not, and will never be, cstyled. If anything, the tables should 54 * be taken out another tab stop or two so nothing overlaps. 55 */ 56 57 /* 58 * These functions must be provided for the consumer to do disassembly. 59 */ 60 #ifdef DIS_TEXT 61 extern char *strncpy(char *, const char *, size_t); 62 extern size_t strlen(const char *); 63 extern int strcmp(const char *, const char *); 64 extern int strncmp(const char *, const char *, size_t); 65 extern size_t strlcat(char *, const char *, size_t); 66 #endif 67 68 69 #define TERM 0 /* used to indicate that the 'indirect' */ 70 /* field terminates - no pointer. */ 71 72 /* Used to decode instructions. */ 73 typedef struct instable { 74 struct instable *it_indirect; /* for decode op codes */ 75 uchar_t it_adrmode; 76 #ifdef DIS_TEXT 77 char it_name[NCPS]; 78 uint_t it_suffix:1; /* mnem + "w", "l", or "d" */ 79 #endif 80 #ifdef DIS_MEM 81 uint_t it_size:16; 82 #endif 83 uint_t it_invalid64:1; /* opcode invalid in amd64 */ 84 uint_t it_always64:1; /* 64 bit when in 64 bit mode */ 85 uint_t it_invalid32:1; /* invalid in IA32 */ 86 uint_t it_stackop:1; /* push/pop stack operation */ 87 uint_t it_vexwoxmm:1; /* VEX instructions that don't use XMM/YMM */ 88 uint_t it_avxsuf:2; /* AVX2/AVX512 suffix rqd. */ 89 uint_t it_vexopmask:1; /* VEX inst. that use opmask */ 90 } instable_t; 91 92 /* 93 * Instruction formats. 94 */ 95 enum { 96 UNKNOWN, 97 MRw, 98 IMlw, 99 IMw, 100 IR, 101 OA, 102 AO, 103 MS, 104 SM, 105 Mv, 106 Mw, 107 M, /* register or memory */ 108 MG9, /* register or memory in group 9 (prefix optional) */ 109 Mb, /* register or memory, always byte sized */ 110 MO, /* memory only (no registers) */ 111 PREF, 112 SWAPGS_RDTSCP, 113 MONITOR_MWAIT, 114 R, 115 RA, 116 SEG, 117 MR, 118 RM, 119 RM_66r, /* RM, but with a required 0x66 prefix */ 120 IA, 121 MA, 122 SD, 123 AD, 124 SA, 125 D, 126 INM, 127 SO, 128 BD, 129 I, 130 P, 131 V, 132 DSHIFT, /* for double shift that has an 8-bit immediate */ 133 U, 134 OVERRIDE, 135 NORM, /* instructions w/o ModR/M byte, no memory access */ 136 IMPLMEM, /* instructions w/o ModR/M byte, implicit mem access */ 137 O, /* for call */ 138 JTAB, /* jump table */ 139 IMUL, /* for 186 iimul instr */ 140 CBW, /* so data16 can be evaluated for cbw and variants */ 141 MvI, /* for 186 logicals */ 142 ENTER, /* for 186 enter instr */ 143 RMw, /* for 286 arpl instr */ 144 Ib, /* for push immediate byte */ 145 F, /* for 287 instructions */ 146 FF, /* for 287 instructions */ 147 FFC, /* for 287 instructions */ 148 DM, /* 16-bit data */ 149 AM, /* 16-bit addr */ 150 LSEG, /* for 3-bit seg reg encoding */ 151 MIb, /* for 386 logicals */ 152 SREG, /* for 386 special registers */ 153 PREFIX, /* a REP instruction prefix */ 154 LOCK, /* a LOCK instruction prefix */ 155 INT3, /* The int 3 instruction, which has a fake operand */ 156 INTx, /* The normal int instruction, with explicit int num */ 157 DSHIFTcl, /* for double shift that implicitly uses %cl */ 158 CWD, /* so data16 can be evaluated for cwd and variants */ 159 RET, /* single immediate 16-bit operand */ 160 MOVZ, /* for movs and movz, with different size operands */ 161 CRC32, /* for crc32, with different size operands */ 162 XADDB, /* for xaddb */ 163 MOVSXZ, /* AMD64 mov sign extend 32 to 64 bit instruction */ 164 MOVBE, /* movbe instruction */ 165 MOVDIR, /* movdir64b register semantics m512 -> r16/32/64 */ 166 RMATCH, /* register, but type matches CPU, not prefixes */ 167 168 /* 169 * MMX/SIMD addressing modes. 170 */ 171 172 MMO, /* Prefixable MMX/SIMD-Int mm/mem -> mm */ 173 MMOIMPL, /* Prefixable MMX/SIMD-Int mm -> mm (mem) */ 174 MMO3P, /* Prefixable MMX/SIMD-Int mm -> r32,imm8 */ 175 MMOM3, /* Prefixable MMX/SIMD-Int mm -> r32 */ 176 MMOS, /* Prefixable MMX/SIMD-Int mm -> mm/mem */ 177 MMOMS, /* Prefixable MMX/SIMD-Int mm -> mem */ 178 MMOPM, /* MMX/SIMD-Int mm/mem -> mm,imm8 */ 179 MMOPM_66o, /* MMX/SIMD-Int 0x66 optional mm/mem -> mm,imm8 */ 180 MMOPRM, /* Prefixable MMX/SIMD-Int r32/mem -> mm,imm8 */ 181 MMOSH, /* Prefixable MMX mm,imm8 */ 182 MM, /* MMX/SIMD-Int mm/mem -> mm */ 183 MMS, /* MMX/SIMD-Int mm -> mm/mem */ 184 MMSH, /* MMX mm,imm8 */ 185 XMMO, /* Prefixable SIMD xmm/mem -> xmm */ 186 XMMOS, /* Prefixable SIMD xmm -> xmm/mem */ 187 XMMOPM, /* Prefixable SIMD xmm/mem w/to xmm,imm8 */ 188 XMMOMX, /* Prefixable SIMD mm/mem -> xmm */ 189 XMMOX3, /* Prefixable SIMD xmm -> r32 */ 190 XMMOXMM, /* Prefixable SIMD xmm/mem -> mm */ 191 XMMOM, /* Prefixable SIMD xmm -> mem */ 192 XMMOMS, /* Prefixable SIMD mem -> xmm */ 193 XMM, /* SIMD xmm/mem -> xmm */ 194 XMM_66r, /* SIMD 0x66 prefix required xmm/mem -> xmm */ 195 XMM_66o, /* SIMD 0x66 prefix optional xmm/mem -> xmm */ 196 XMMXIMPL, /* SIMD xmm -> xmm (mem) */ 197 XMM3P, /* SIMD xmm -> r32,imm8 */ 198 XMM3PM_66r, /* SIMD 0x66 prefix required xmm -> r32/mem,imm8 */ 199 XMMP, /* SIMD xmm/mem w/to xmm,imm8 */ 200 XMMP_66o, /* SIMD 0x66 prefix optional xmm/mem w/to xmm,imm8 */ 201 XMMP_66r, /* SIMD 0x66 prefix required xmm/mem w/to xmm,imm8 */ 202 XMMPRM, /* SIMD r32/mem -> xmm,imm8 */ 203 XMMPRM_66r, /* SIMD 0x66 prefix required r32/mem -> xmm,imm8 */ 204 XMMS, /* SIMD xmm -> xmm/mem */ 205 XMMM, /* SIMD mem -> xmm */ 206 XMMM_66r, /* SIMD 0x66 prefix required mem -> xmm */ 207 XMMMS, /* SIMD xmm -> mem */ 208 XMM3MX, /* SIMD r32/mem -> xmm */ 209 XMM3MXS, /* SIMD xmm -> r32/mem */ 210 XMMSH, /* SIMD xmm,imm8 */ 211 XMMXM3, /* SIMD xmm/mem -> r32 */ 212 XMMX3, /* SIMD xmm -> r32 */ 213 XMMXMM, /* SIMD xmm/mem -> mm */ 214 XMMMX, /* SIMD mm -> xmm */ 215 XMMXM, /* SIMD xmm -> mm */ 216 XMMX2I, /* SIMD xmm -> xmm, imm, imm */ 217 XMM2I, /* SIMD xmm, imm, imm */ 218 XMMFENCE, /* SIMD lfence or mfence */ 219 XMMSFNC, /* SIMD sfence (none or mem) */ 220 FSGS, /* FSGSBASE if reg */ 221 XGETBV_XSETBV, 222 VEX_NONE, /* VEX no operand */ 223 VEX_MO, /* VEX mod_rm -> implicit reg */ 224 VEX_RMrX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 225 VEX_VRMrX, /* VEX mod_rm, VEX.vvvv -> mod_rm */ 226 VEX_RRX, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 227 VEX_RMRX, /* VEX VEX.vvvv, mod_rm, imm8[7:4] -> mod_reg */ 228 VEX_MX, /* VEX mod_rm -> mod_reg */ 229 VEX_MXI, /* VEX mod_rm, imm8 -> mod_reg */ 230 VEX_XXI, /* VEX mod_rm, imm8 -> VEX.vvvv */ 231 VEX_MR, /* VEX mod_rm -> mod_reg */ 232 VEX_RRI, /* VEX mod_reg, mod_rm -> implicit(eflags/r32) */ 233 VEX_RX, /* VEX mod_reg -> mod_rm */ 234 VEX_KRR, /* VEX mod_rm -> mod_reg */ 235 VEX_KMR, /* VEX mod_reg -> mod_rm */ 236 VEX_KRM, /* VEX mod_rm -> mod_reg */ 237 VEX_RR, /* VEX mod_rm -> mod_reg */ 238 VEX_RRi, /* VEX mod_rm, imm8 -> mod_reg */ 239 VEX_RM, /* VEX mod_reg -> mod_rm */ 240 VEX_RIM, /* VEX mod_reg, imm8 -> mod_rm */ 241 VEX_RRM, /* VEX VEX.vvvv, mod_reg -> mod_rm */ 242 VEX_RMX, /* VEX VEX.vvvv, mod_rm -> mod_reg */ 243 VEX_SbVM, /* VEX SIB, VEX.vvvv -> mod_rm */ 244 VMx, /* vmcall/vmlaunch/vmresume/vmxoff */ 245 VMxo, /* VMx instruction with optional prefix */ 246 SVM, /* AMD SVM instructions */ 247 BLS, /* BLSR, BLSMSK, BLSI */ 248 FMA, /* FMA instructions, all VEX_RMrX */ 249 ADX, /* ADX instructions, support REX.w, mod_rm->mod_reg */ 250 EVEX_RX, /* EVEX mod_reg -> mod_rm */ 251 EVEX_MX, /* EVEX mod_rm -> mod_reg */ 252 EVEX_RMrX, /* EVEX EVEX.vvvv, mod_rm -> mod_reg */ 253 EVEX_RMRX /* EVEX EVEX.vvvv, mod_rm, imm8 -> mod_reg */ 254 }; 255 256 /* 257 * VEX prefixes 258 */ 259 #define VEX_2bytes 0xC5 /* the first byte of two-byte form */ 260 #define VEX_3bytes 0xC4 /* the first byte of three-byte form */ 261 262 #define FILL 0x90 /* Fill byte used for alignment (nop) */ 263 264 /* 265 ** Register numbers for the i386 266 */ 267 #define EAX_REGNO 0 268 #define ECX_REGNO 1 269 #define EDX_REGNO 2 270 #define EBX_REGNO 3 271 #define ESP_REGNO 4 272 #define EBP_REGNO 5 273 #define ESI_REGNO 6 274 #define EDI_REGNO 7 275 276 /* 277 * modes for immediate values 278 */ 279 #define MODE_NONE 0 280 #define MODE_IPREL 1 /* signed IP relative value */ 281 #define MODE_SIGNED 2 /* sign extended immediate */ 282 #define MODE_IMPLIED 3 /* constant value implied from opcode */ 283 #define MODE_OFFSET 4 /* offset part of an address */ 284 #define MODE_RIPREL 5 /* like IPREL, but from %rip (amd64) */ 285 286 /* 287 * The letters used in these macros are: 288 * IND - indirect to another to another table 289 * "T" - means to Terminate indirections (this is the final opcode) 290 * "S" - means "operand length suffix required" 291 * "Sa" - means AVX2 suffix (q/d) required 292 * "Sq" - means AVX512 suffix (q/d) required 293 * "Sd" - means AVX512 suffix (d/s) required 294 * "NS" - means "no suffix" which is the operand length suffix of the opcode 295 * "Z" - means instruction size arg required 296 * "u" - means the opcode is invalid in IA32 but valid in amd64 297 * "x" - means the opcode is invalid in amd64, but not IA32 298 * "y" - means the operand size is always 64 bits in 64 bit mode 299 * "p" - means push/pop stack operation 300 * "vr" - means VEX instruction that operates on normal registers, not fpu 301 * "vo" - means VEX instruction that operates on opmask registers, not fpu 302 */ 303 304 #define AVS2 (uint_t)1 /* it_avxsuf: AVX2 q/d suffix handling */ 305 #define AVS5Q (uint_t)2 /* it_avxsuf: AVX512 q/d suffix handling */ 306 #define AVS5D (uint_t)3 /* it_avxsuf: AVX512 d/s suffix handling */ 307 308 #if defined(DIS_TEXT) && defined(DIS_MEM) 309 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0, 0} 310 #define INDx(table) {(instable_t *)table, 0, "", 0, 0, 1, 0, 0, 0} 311 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0} 312 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 0, 1, 0} 313 #define TNSx(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0, 0} 314 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 0} 315 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0, 1} 316 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0} 317 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, sz, 0, 1, 0, 0} 318 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, sz, 0, 0, 0, 0, 1} 319 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 0, 1} 320 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0} 321 #define TSx(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0, 0} 322 #define TSy(name, amode) {TERM, amode, name, 1, 0, 0, 1, 0, 0} 323 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 1} 324 #define TSZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0} 325 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, sz, 0, 0, 0, 0, 0, AVS2} 326 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5Q} 327 #define TSd(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, 0, AVS5D} 328 #define TSZx(name, amode, sz) {TERM, amode, name, 1, sz, 1, 0, 0, 0} 329 #define TSZy(name, amode, sz) {TERM, amode, name, 1, sz, 0, 1, 0, 0} 330 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 331 #elif defined(DIS_TEXT) 332 #define IND(table) {(instable_t *)table, 0, "", 0, 0, 0, 0, 0} 333 #define INDx(table) {(instable_t *)table, 0, "", 0, 1, 0, 0, 0} 334 #define TNS(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0} 335 #define TNSu(name, amode) {TERM, amode, name, 0, 0, 0, 1, 0} 336 #define TNSx(name, amode) {TERM, amode, name, 0, 1, 0, 0, 0} 337 #define TNSy(name, amode) {TERM, amode, name, 0, 0, 1, 0, 0} 338 #define TNSyp(name, amode) {TERM, amode, name, 0, 0, 1, 0, 1} 339 #define TNSZ(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0} 340 #define TNSZy(name, amode, sz) {TERM, amode, name, 0, 0, 1, 0, 0} 341 #define TNSZvr(name, amode, sz) {TERM, amode, name, 0, 0, 0, 0, 0, 1} 342 #define TSvo(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0, 0, 0, 1} 343 #define TS(name, amode) {TERM, amode, name, 1, 0, 0, 0, 0} 344 #define TSx(name, amode) {TERM, amode, name, 1, 1, 0, 0, 0} 345 #define TSy(name, amode) {TERM, amode, name, 1, 0, 1, 0, 0} 346 #define TSp(name, amode) {TERM, amode, name, 1, 0, 0, 0, 1} 347 #define TSZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0} 348 #define TSaZ(name, amode, sz) {TERM, amode, name, 1, 0, 0, 0, 0, 0, AVS2} 349 #define TSq(name, amode) {TERM, amode, name, 0, 0, 0, 0, 0, 0, AVS5Q} 350 #define TSZx(name, amode, sz) {TERM, amode, name, 1, 1, 0, 0, 0} 351 #define TSZy(name, amode, sz) {TERM, amode, name, 1, 0, 1, 0, 0} 352 #define INVALID {TERM, UNKNOWN, "", 0, 0, 0, 0, 0} 353 #elif defined(DIS_MEM) 354 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0, 0} 355 #define INDx(table) {(instable_t *)table, 0, 0, 1, 0, 0, 0} 356 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 357 #define TNSu(name, amode) {TERM, amode, 0, 0, 0, 1, 0} 358 #define TNSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 359 #define TNSyp(name, amode) {TERM, amode, 0, 0, 1, 0, 1} 360 #define TNSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 361 #define TNSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 362 #define TNSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 363 #define TNSZvr(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 1} 364 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 0, 1} 365 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0, 0} 366 #define TSx(name, amode) {TERM, amode, 0, 1, 0, 0, 0} 367 #define TSy(name, amode) {TERM, amode, 0, 0, 1, 0, 0} 368 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 0, 1} 369 #define TSZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0} 370 #define TSaZ(name, amode, sz) {TERM, amode, sz, 0, 0, 0, 0, 0, AVS2} 371 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, AVS5Q} 372 #define TSZx(name, amode, sz) {TERM, amode, sz, 1, 0, 0, 0} 373 #define TSZy(name, amode, sz) {TERM, amode, sz, 0, 1, 0, 0} 374 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0, 0} 375 #else 376 #define IND(table) {(instable_t *)table, 0, 0, 0, 0, 0} 377 #define INDx(table) {(instable_t *)table, 0, 1, 0, 0, 0} 378 #define TNS(name, amode) {TERM, amode, 0, 0, 0, 0} 379 #define TNSu(name, amode) {TERM, amode, 0, 0, 1, 0} 380 #define TNSy(name, amode) {TERM, amode, 0, 1, 0, 0} 381 #define TNSyp(name, amode) {TERM, amode, 0, 1, 0, 1} 382 #define TNSx(name, amode) {TERM, amode, 1, 0, 0, 0} 383 #define TNSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 384 #define TNSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 385 #define TNSZvr(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 1} 386 #define TSvo(name, amode) {TERM, amode, 0, 0, 0, 0, 0, 0, 1} 387 #define TS(name, amode) {TERM, amode, 0, 0, 0, 0} 388 #define TSx(name, amode) {TERM, amode, 1, 0, 0, 0} 389 #define TSy(name, amode) {TERM, amode, 0, 1, 0, 0} 390 #define TSp(name, amode) {TERM, amode, 0, 0, 0, 1} 391 #define TSZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0} 392 #define TSaZ(name, amode, sz) {TERM, amode, 0, 0, 0, 0, 0, AVS2} 393 #define TSq(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5Q} 394 #define TSd(name, amode) {TERM, amode, 0, 0, 0, 0, 0, AVS5D} 395 #define TSZx(name, amode, sz) {TERM, amode, 1, 0, 0, 0} 396 #define TSZy(name, amode, sz) {TERM, amode, 0, 1, 0, 0} 397 #define INVALID {TERM, UNKNOWN, 0, 0, 0, 0} 398 #endif 399 400 #ifdef DIS_TEXT 401 /* 402 * this decodes the r_m field for mode's 0, 1, 2 in 16 bit mode 403 */ 404 const char *const dis_addr16[3][8] = { 405 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "", 406 "(%bx)", 407 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di", "(%bp)", 408 "(%bx)", 409 "(%bx,%si)", "(%bx,%di)", "(%bp,%si)", "(%bp,%di)", "(%si)", "(%di)", "(%bp)", 410 "(%bx)", 411 }; 412 413 414 /* 415 * This decodes 32 bit addressing mode r_m field for modes 0, 1, 2 416 */ 417 const char *const dis_addr32_mode0[16] = { 418 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "", "(%esi)", "(%edi)", 419 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "", "(%r14d)", "(%r15d)" 420 }; 421 422 const char *const dis_addr32_mode12[16] = { 423 "(%eax)", "(%ecx)", "(%edx)", "(%ebx)", "", "(%ebp)", "(%esi)", "(%edi)", 424 "(%r8d)", "(%r9d)", "(%r10d)", "(%r11d)", "", "(%r13d)", "(%r14d)", "(%r15d)" 425 }; 426 427 /* 428 * This decodes 64 bit addressing mode r_m field for modes 0, 1, 2 429 */ 430 const char *const dis_addr64_mode0[16] = { 431 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rip)", "(%rsi)", "(%rdi)", 432 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%rip)", "(%r14)", "(%r15)" 433 }; 434 const char *const dis_addr64_mode12[16] = { 435 "(%rax)", "(%rcx)", "(%rdx)", "(%rbx)", "", "(%rbp)", "(%rsi)", "(%rdi)", 436 "(%r8)", "(%r9)", "(%r10)", "(%r11)", "(%r12)", "(%r13)", "(%r14)", "(%r15)" 437 }; 438 439 /* 440 * decode for scale from SIB byte 441 */ 442 const char *const dis_scale_factor[4] = { ")", ",2)", ",4)", ",8)" }; 443 444 /* 445 * decode for scale from VSIB byte, note that we always include the scale factor 446 * to match gas. 447 */ 448 const char *const dis_vscale_factor[4] = { ",1)", ",2)", ",4)", ",8)" }; 449 450 /* 451 * register decoding for normal references to registers (ie. not addressing) 452 */ 453 const char *const dis_REG8[16] = { 454 "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", 455 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 456 }; 457 458 const char *const dis_REG8_REX[16] = { 459 "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", 460 "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" 461 }; 462 463 const char *const dis_REG16[16] = { 464 "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", 465 "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" 466 }; 467 468 const char *const dis_REG32[16] = { 469 "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", 470 "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" 471 }; 472 473 const char *const dis_REG64[16] = { 474 "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", 475 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" 476 }; 477 478 const char *const dis_DEBUGREG[16] = { 479 "%db0", "%db1", "%db2", "%db3", "%db4", "%db5", "%db6", "%db7", 480 "%db8", "%db9", "%db10", "%db11", "%db12", "%db13", "%db14", "%db15" 481 }; 482 483 const char *const dis_CONTROLREG[16] = { 484 "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5?", "%cr6?", "%cr7?", 485 "%cr8", "%cr9?", "%cr10?", "%cr11?", "%cr12?", "%cr13?", "%cr14?", "%cr15?" 486 }; 487 488 const char *const dis_TESTREG[16] = { 489 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7", 490 "%tr0?", "%tr1?", "%tr2?", "%tr3", "%tr4", "%tr5", "%tr6", "%tr7" 491 }; 492 493 const char *const dis_MMREG[16] = { 494 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7", 495 "%mm0", "%mm1", "%mm2", "%mm3", "%mm4", "%mm5", "%mm6", "%mm7" 496 }; 497 498 const char *const dis_XMMREG[32] = { 499 "%xmm0", "%xmm1", "%xmm2", "%xmm3", 500 "%xmm4", "%xmm5", "%xmm6", "%xmm7", 501 "%xmm8", "%xmm9", "%xmm10", "%xmm11", 502 "%xmm12", "%xmm13", "%xmm14", "%xmm15", 503 "%xmm16", "%xmm17", "%xmm18", "%xmm19", 504 "%xmm20", "%xmm21", "%xmm22", "%xmm23", 505 "%xmm24", "%xmm25", "%xmm26", "%xmm27", 506 "%xmm28", "%xmm29", "%xmm30", "%xmm31", 507 }; 508 509 const char *const dis_YMMREG[32] = { 510 "%ymm0", "%ymm1", "%ymm2", "%ymm3", 511 "%ymm4", "%ymm5", "%ymm6", "%ymm7", 512 "%ymm8", "%ymm9", "%ymm10", "%ymm11", 513 "%ymm12", "%ymm13", "%ymm14", "%ymm15", 514 "%ymm16", "%ymm17", "%ymm18", "%ymm19", 515 "%ymm20", "%ymm21", "%ymm22", "%ymm23", 516 "%ymm24", "%ymm25", "%ymm26", "%ymm27", 517 "%ymm28", "%ymm29", "%ymm30", "%ymm31", 518 }; 519 520 const char *const dis_ZMMREG[32] = { 521 "%zmm0", "%zmm1", "%zmm2", "%zmm3", 522 "%zmm4", "%zmm5", "%zmm6", "%zmm7", 523 "%zmm8", "%zmm9", "%zmm10", "%zmm11", 524 "%zmm12", "%zmm13", "%zmm14", "%zmm15", 525 "%zmm16", "%zmm17", "%zmm18", "%zmm19", 526 "%zmm20", "%zmm21", "%zmm22", "%zmm23", 527 "%zmm24", "%zmm25", "%zmm26", "%zmm27", 528 "%zmm28", "%zmm29", "%zmm30", "%zmm31", 529 }; 530 531 const char *const dis_KOPMASKREG[8] = { 532 "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" 533 }; 534 535 const char *const dis_SEGREG[16] = { 536 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>", 537 "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "<reserved>", "<reserved>" 538 }; 539 540 /* 541 * SIMD predicate suffixes 542 */ 543 const char *const dis_PREDSUFFIX[8] = { 544 "eq", "lt", "le", "unord", "neq", "nlt", "nle", "ord" 545 }; 546 547 const char *const dis_AVXvgrp7[3][8] = { 548 /*0 1 2 3 4 5 6 7*/ 549 /*71*/ {"", "", "vpsrlw", "", "vpsraw", "", "vpsllw", ""}, 550 /*72*/ {"", "", "vpsrld", "", "vpsrad", "", "vpslld", ""}, 551 /*73*/ {"", "", "vpsrlq", "vpsrldq", "", "", "vpsllq", "vpslldq"} 552 }; 553 554 #endif /* DIS_TEXT */ 555 556 /* 557 * "decode table" for 64 bit mode MOVSXD instruction (opcode 0x63) 558 */ 559 const instable_t dis_opMOVSLD = TNS("movslq",MOVSXZ); 560 561 /* 562 * "decode table" for pause and clflush instructions 563 */ 564 const instable_t dis_opPause = TNS("pause", NORM); 565 566 /* 567 * "decode table" for wbnoinvd instruction 568 */ 569 const instable_t dis_opWbnoinvd = TNS("wbnoinvd", NORM); 570 571 /* 572 * Decode table for 0x0F00 opcodes 573 */ 574 const instable_t dis_op0F00[8] = { 575 576 /* [0] */ TNS("sldt",M), TNS("str",M), TNSy("lldt",M), TNSy("ltr",M), 577 /* [4] */ TNSZ("verr",M,2), TNSZ("verw",M,2), INVALID, INVALID, 578 }; 579 580 581 /* 582 * Decode table for 0x0F01 opcodes 583 */ 584 const instable_t dis_op0F01[8] = { 585 586 /* [0] */ TNSZ("sgdt",VMx,6), TNSZ("sidt",MONITOR_MWAIT,6), TNSZ("lgdt",XGETBV_XSETBV,6), TNSZ("lidt",SVM,6), 587 /* [4] */ TNSZ("smsw",M,2), INVALID, TNSZ("lmsw",M,2), TNS("invlpg",SWAPGS_RDTSCP), 588 }; 589 590 /* 591 * Decode table for 0x0F18 opcodes -- SIMD prefetch 592 */ 593 const instable_t dis_op0F18[8] = { 594 595 /* [0] */ TNS("prefetchnta",PREF),TNS("prefetcht0",PREF), TNS("prefetcht1",PREF), TNS("prefetcht2",PREF), 596 /* [4] */ INVALID, INVALID, TNSu("prefetchit1",PREF),TNSu("prefetchit0",PREF), 597 }; 598 599 /* 600 * Decode table for 0x0FAE opcodes -- SIMD state save/restore 601 */ 602 const instable_t dis_op0FAE[8] = { 603 /* [0] */ TNSZ("fxsave",FSGS,512),TNSZ("fxrstor",FSGS,512),TNS("ldmxcsr",FSGS), TNS("stmxcsr",FSGS), 604 /* [4] */ TNSZ("xsave",M,512), TNS("lfence",XMMFENCE), TNS("mfence",XMMFENCE), TNS("sfence",XMMSFNC), 605 }; 606 607 /* 608 * Decode table for 0xF30FAE opcodes -- FSGSBASE 609 */ 610 const instable_t dis_opF30FAE[8] = { 611 /* [0] */ TNSx("rdfsbase",FSGS), TNSx("rdgsbase",FSGS), TNSx("wrfsbase",FSGS), TNSx("wrgsbase",FSGS), 612 /* [4] */ INVALID, INVALID, INVALID, INVALID, 613 }; 614 615 /* 616 * Decode table for 0x0FBA opcodes 617 */ 618 619 const instable_t dis_op0FBA[8] = { 620 621 /* [0] */ INVALID, INVALID, INVALID, INVALID, 622 /* [4] */ TS("bt",MIb), TS("bts",MIb), TS("btr",MIb), TS("btc",MIb), 623 }; 624 625 /* 626 * Decode table for 0x0FC7 opcode (group 9) 627 */ 628 629 const instable_t dis_op0FC7[8] = { 630 631 /* [0] */ INVALID, TNS("cmpxchg8b",M), INVALID, TNS("xrstors",MG9), 632 /* [4] */ TNS("xsavec",MG9), TNS("xsaves",MG9), TNS("vmptrld",MG9), TNS("vmptrst",MG9), 633 }; 634 635 /* 636 * Decode table for 0x0FC7 opcode (group 9) mode 3 637 */ 638 639 const instable_t dis_op0FC7m3[8] = { 640 641 /* [0] */ INVALID, INVALID, INVALID, INVALID, 642 /* [4] */ INVALID, INVALID, TNS("rdrand",MG9), TNS("rdseed", MG9), 643 }; 644 645 /* 646 * Decode table for 0x0FC7 opcode with 0x66 prefix 647 */ 648 649 const instable_t dis_op660FC7[8] = { 650 651 /* [0] */ INVALID, INVALID, INVALID, INVALID, 652 /* [4] */ INVALID, INVALID, TNS("vmclear",M), INVALID, 653 }; 654 655 /* 656 * Decode table for 0x0FC7 opcode with 0xF3 prefix -- memory instructions 657 */ 658 659 const instable_t dis_opF30FC7[8] = { 660 661 /* [0] */ INVALID, INVALID, INVALID, INVALID, 662 /* [4] */ INVALID, INVALID, TNS("vmxon",M), INVALID, 663 }; 664 665 /* 666 * Decode table for 0x0FC7 opcode with 0xF3 prefix -- register instructions 667 */ 668 669 const instable_t dis_opF30FC7m3[8] = { 670 671 /* [0] */ INVALID, INVALID, INVALID, INVALID, 672 /* [4] */ INVALID, INVALID, INVALID, TNS("rdpid",RMATCH) 673 }; 674 675 /* 676 * Decode table for 0x0FC8 opcode -- 486 bswap instruction 677 * 678 *bit pattern: 0000 1111 1100 1reg 679 */ 680 const instable_t dis_op0FC8[4] = { 681 /* [0] */ TNS("bswap",R), INVALID, INVALID, INVALID, 682 }; 683 684 /* 685 * Decode table for 0x0F71, 0x0F72, and 0x0F73 opcodes -- MMX instructions 686 */ 687 const instable_t dis_op0F7123[4][8] = { 688 { 689 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 690 /* .4 */ INVALID, INVALID, INVALID, INVALID, 691 }, { 692 /* [71].0 */ INVALID, INVALID, TNS("psrlw",MMOSH), INVALID, 693 /* .4 */ TNS("psraw",MMOSH), INVALID, TNS("psllw",MMOSH), INVALID, 694 }, { 695 /* [72].0 */ INVALID, INVALID, TNS("psrld",MMOSH), INVALID, 696 /* .4 */ TNS("psrad",MMOSH), INVALID, TNS("pslld",MMOSH), INVALID, 697 }, { 698 /* [73].0 */ INVALID, INVALID, TNS("psrlq",MMOSH), TNS("INVALID",MMOSH), 699 /* .4 */ INVALID, INVALID, TNS("psllq",MMOSH), TNS("INVALID",MMOSH), 700 } }; 701 702 /* 703 * Decode table for SIMD extensions to above 0x0F71-0x0F73 opcodes. 704 */ 705 const instable_t dis_opSIMD7123[32] = { 706 /* [70].0 */ INVALID, INVALID, INVALID, INVALID, 707 /* .4 */ INVALID, INVALID, INVALID, INVALID, 708 709 /* [71].0 */ INVALID, INVALID, TNS("psrlw",XMMSH), INVALID, 710 /* .4 */ TNS("psraw",XMMSH), INVALID, TNS("psllw",XMMSH), INVALID, 711 712 /* [72].0 */ INVALID, INVALID, TNS("psrld",XMMSH), INVALID, 713 /* .4 */ TNS("psrad",XMMSH), INVALID, TNS("pslld",XMMSH), INVALID, 714 715 /* [73].0 */ INVALID, INVALID, TNS("psrlq",XMMSH), TNS("psrldq",XMMSH), 716 /* .4 */ INVALID, INVALID, TNS("psllq",XMMSH), TNS("pslldq",XMMSH), 717 }; 718 719 /* 720 * SIMD instructions have been wedged into the existing IA32 instruction 721 * set through the use of prefixes. That is, while 0xf0 0x58 may be 722 * addps, 0xf3 0xf0 0x58 (literally, repz addps) is a completely different 723 * instruction - addss. At present, three prefixes have been coopted in 724 * this manner - address size (0x66), repnz (0xf2) and repz (0xf3). The 725 * following tables are used to provide the prefixed instruction names. 726 * The arrays are sparse, but they're fast. 727 */ 728 729 /* 730 * Decode table for SIMD instructions with the address size (0x66) prefix. 731 */ 732 const instable_t dis_opSIMDdata16[256] = { 733 /* [00] */ INVALID, INVALID, INVALID, INVALID, 734 /* [04] */ INVALID, INVALID, INVALID, INVALID, 735 /* [08] */ INVALID, INVALID, INVALID, INVALID, 736 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 737 738 /* [10] */ TNSZ("movupd",XMM,16), TNSZ("movupd",XMMS,16), TNSZ("movlpd",XMMM,8), TNSZ("movlpd",XMMMS,8), 739 /* [14] */ TNSZ("unpcklpd",XMM,16),TNSZ("unpckhpd",XMM,16),TNSZ("movhpd",XMMM,8), TNSZ("movhpd",XMMMS,8), 740 /* [18] */ INVALID, INVALID, INVALID, INVALID, 741 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 742 743 /* [20] */ INVALID, INVALID, INVALID, INVALID, 744 /* [24] */ INVALID, INVALID, INVALID, INVALID, 745 /* [28] */ TNSZ("movapd",XMM,16), TNSZ("movapd",XMMS,16), TNSZ("cvtpi2pd",XMMOMX,8),TNSZ("movntpd",XMMOMS,16), 746 /* [2C] */ TNSZ("cvttpd2pi",XMMXMM,16),TNSZ("cvtpd2pi",XMMXMM,16),TNSZ("ucomisd",XMM,8),TNSZ("comisd",XMM,8), 747 748 /* [30] */ INVALID, INVALID, INVALID, INVALID, 749 /* [34] */ INVALID, INVALID, INVALID, INVALID, 750 /* [38] */ INVALID, INVALID, INVALID, INVALID, 751 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 752 753 /* [40] */ INVALID, INVALID, INVALID, INVALID, 754 /* [44] */ INVALID, INVALID, INVALID, INVALID, 755 /* [48] */ INVALID, INVALID, INVALID, INVALID, 756 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 757 758 /* [50] */ TNS("movmskpd",XMMOX3), TNSZ("sqrtpd",XMM,16), INVALID, INVALID, 759 /* [54] */ TNSZ("andpd",XMM,16), TNSZ("andnpd",XMM,16), TNSZ("orpd",XMM,16), TNSZ("xorpd",XMM,16), 760 /* [58] */ TNSZ("addpd",XMM,16), TNSZ("mulpd",XMM,16), TNSZ("cvtpd2ps",XMM,16),TNSZ("cvtps2dq",XMM,16), 761 /* [5C] */ TNSZ("subpd",XMM,16), TNSZ("minpd",XMM,16), TNSZ("divpd",XMM,16), TNSZ("maxpd",XMM,16), 762 763 /* [60] */ TNSZ("punpcklbw",XMM,16),TNSZ("punpcklwd",XMM,16),TNSZ("punpckldq",XMM,16),TNSZ("packsswb",XMM,16), 764 /* [64] */ TNSZ("pcmpgtb",XMM,16), TNSZ("pcmpgtw",XMM,16), TNSZ("pcmpgtd",XMM,16), TNSZ("packuswb",XMM,16), 765 /* [68] */ TNSZ("punpckhbw",XMM,16),TNSZ("punpckhwd",XMM,16),TNSZ("punpckhdq",XMM,16),TNSZ("packssdw",XMM,16), 766 /* [6C] */ TNSZ("punpcklqdq",XMM,16),TNSZ("punpckhqdq",XMM,16),TNSZ("movd",XMM3MX,4),TNSZ("movdqa",XMM,16), 767 768 /* [70] */ TNSZ("pshufd",XMMP,16), INVALID, INVALID, INVALID, 769 /* [74] */ TNSZ("pcmpeqb",XMM,16), TNSZ("pcmpeqw",XMM,16), TNSZ("pcmpeqd",XMM,16), INVALID, 770 /* [78] */ TNSZ("extrq",XMM2I,16), TNSZ("extrq",XMM,16), INVALID, INVALID, 771 /* [7C] */ TNSZ("haddpd",XMM,16), TNSZ("hsubpd",XMM,16), TNSZ("movd",XMM3MXS,4), TNSZ("movdqa",XMMS,16), 772 773 /* [80] */ INVALID, INVALID, INVALID, INVALID, 774 /* [84] */ INVALID, INVALID, INVALID, INVALID, 775 /* [88] */ INVALID, INVALID, INVALID, INVALID, 776 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 777 778 /* [90] */ INVALID, INVALID, INVALID, INVALID, 779 /* [94] */ INVALID, INVALID, INVALID, INVALID, 780 /* [98] */ INVALID, INVALID, INVALID, INVALID, 781 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 782 783 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 784 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 785 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 786 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 787 788 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 789 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 790 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 791 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 792 793 /* [C0] */ INVALID, INVALID, TNSZ("cmppd",XMMP,16), INVALID, 794 /* [C4] */ TNSZ("pinsrw",XMMPRM,2),TNS("pextrw",XMM3P), TNSZ("shufpd",XMMP,16), INVALID, 795 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 796 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 797 798 /* [D0] */ TNSZ("addsubpd",XMM,16),TNSZ("psrlw",XMM,16), TNSZ("psrld",XMM,16), TNSZ("psrlq",XMM,16), 799 /* [D4] */ TNSZ("paddq",XMM,16), TNSZ("pmullw",XMM,16), TNSZ("movq",XMMS,8), TNS("pmovmskb",XMMX3), 800 /* [D8] */ TNSZ("psubusb",XMM,16), TNSZ("psubusw",XMM,16), TNSZ("pminub",XMM,16), TNSZ("pand",XMM,16), 801 /* [DC] */ TNSZ("paddusb",XMM,16), TNSZ("paddusw",XMM,16), TNSZ("pmaxub",XMM,16), TNSZ("pandn",XMM,16), 802 803 /* [E0] */ TNSZ("pavgb",XMM,16), TNSZ("psraw",XMM,16), TNSZ("psrad",XMM,16), TNSZ("pavgw",XMM,16), 804 /* [E4] */ TNSZ("pmulhuw",XMM,16), TNSZ("pmulhw",XMM,16), TNSZ("cvttpd2dq",XMM,16),TNSZ("movntdq",XMMS,16), 805 /* [E8] */ TNSZ("psubsb",XMM,16), TNSZ("psubsw",XMM,16), TNSZ("pminsw",XMM,16), TNSZ("por",XMM,16), 806 /* [EC] */ TNSZ("paddsb",XMM,16), TNSZ("paddsw",XMM,16), TNSZ("pmaxsw",XMM,16), TNSZ("pxor",XMM,16), 807 808 /* [F0] */ INVALID, TNSZ("psllw",XMM,16), TNSZ("pslld",XMM,16), TNSZ("psllq",XMM,16), 809 /* [F4] */ TNSZ("pmuludq",XMM,16), TNSZ("pmaddwd",XMM,16), TNSZ("psadbw",XMM,16), TNSZ("maskmovdqu", XMMXIMPL,16), 810 /* [F8] */ TNSZ("psubb",XMM,16), TNSZ("psubw",XMM,16), TNSZ("psubd",XMM,16), TNSZ("psubq",XMM,16), 811 /* [FC] */ TNSZ("paddb",XMM,16), TNSZ("paddw",XMM,16), TNSZ("paddd",XMM,16), INVALID, 812 }; 813 814 const instable_t dis_opAVX660F[256] = { 815 /* [00] */ INVALID, INVALID, INVALID, INVALID, 816 /* [04] */ INVALID, INVALID, INVALID, INVALID, 817 /* [08] */ INVALID, INVALID, INVALID, INVALID, 818 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 819 820 /* [10] */ TNSZ("vmovupd",VEX_MX,16), TNSZ("vmovupd",VEX_RX,16), TNSZ("vmovlpd",VEX_RMrX,8), TNSZ("vmovlpd",VEX_RM,8), 821 /* [14] */ TNSZ("vunpcklpd",VEX_RMrX,16),TNSZ("vunpckhpd",VEX_RMrX,16),TNSZ("vmovhpd",VEX_RMrX,8), TNSZ("vmovhpd",VEX_RM,8), 822 /* [18] */ INVALID, INVALID, INVALID, INVALID, 823 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 824 825 /* [20] */ INVALID, INVALID, INVALID, INVALID, 826 /* [24] */ INVALID, INVALID, INVALID, INVALID, 827 /* [28] */ TNSZ("vmovapd",VEX_MX,16), TNSZ("vmovapd",VEX_RX,16), INVALID, TNSZ("vmovntpd",VEX_RM,16), 828 /* [2C] */ INVALID, INVALID, TNSZ("vucomisd",VEX_MX,8),TNSZ("vcomisd",VEX_MX,8), 829 830 /* [30] */ INVALID, INVALID, INVALID, INVALID, 831 /* [34] */ INVALID, INVALID, INVALID, INVALID, 832 /* [38] */ INVALID, INVALID, INVALID, INVALID, 833 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 834 835 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 836 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 837 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 838 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 839 840 /* [50] */ TNS("vmovmskpd",VEX_MR), TNSZ("vsqrtpd",VEX_MX,16), INVALID, INVALID, 841 /* [54] */ TNSZ("vandpd",VEX_RMrX,16), TNSZ("vandnpd",VEX_RMrX,16), TNSZ("vorpd",VEX_RMrX,16), TNSZ("vxorpd",VEX_RMrX,16), 842 /* [58] */ TNSZ("vaddpd",VEX_RMrX,16), TNSZ("vmulpd",VEX_RMrX,16), TNSZ("vcvtpd2ps",VEX_MX,16),TNSZ("vcvtps2dq",VEX_MX,16), 843 /* [5C] */ TNSZ("vsubpd",VEX_RMrX,16), TNSZ("vminpd",VEX_RMrX,16), TNSZ("vdivpd",VEX_RMrX,16), TNSZ("vmaxpd",VEX_RMrX,16), 844 845 /* [60] */ TNSZ("vpunpcklbw",VEX_RMrX,16),TNSZ("vpunpcklwd",VEX_RMrX,16),TNSZ("vpunpckldq",VEX_RMrX,16),TNSZ("vpacksswb",VEX_RMrX,16), 846 /* [64] */ TNSZ("vpcmpgtb",VEX_RMrX,16), TNSZ("vpcmpgtw",VEX_RMrX,16), TNSZ("vpcmpgtd",VEX_RMrX,16), TNSZ("vpackuswb",VEX_RMrX,16), 847 /* [68] */ TNSZ("vpunpckhbw",VEX_RMrX,16),TNSZ("vpunpckhwd",VEX_RMrX,16),TNSZ("vpunpckhdq",VEX_RMrX,16),TNSZ("vpackssdw",VEX_RMrX,16), 848 /* [6C] */ TNSZ("vpunpcklqdq",VEX_RMrX,16),TNSZ("vpunpckhqdq",VEX_RMrX,16),TNSZ("vmovd",VEX_MX,4),TNSZ("vmovdqa",VEX_MX,16), 849 850 /* [70] */ TNSZ("vpshufd",VEX_MXI,16), TNSZ("vgrp71",VEX_XXI,16), TNSZ("vgrp72",VEX_XXI,16), TNSZ("vgrp73",VEX_XXI,16), 851 /* [74] */ TNSZ("vpcmpeqb",VEX_RMrX,16), TNSZ("vpcmpeqw",VEX_RMrX,16), TNSZ("vpcmpeqd",VEX_RMrX,16), INVALID, 852 /* [78] */ INVALID, INVALID, INVALID, INVALID, 853 /* [7C] */ TNSZ("vhaddpd",VEX_RMrX,16), TNSZ("vhsubpd",VEX_RMrX,16), TNSZ("vmovd",VEX_RR,4), TNSZ("vmovdqa",VEX_RX,16), 854 855 /* [80] */ INVALID, INVALID, INVALID, INVALID, 856 /* [84] */ INVALID, INVALID, INVALID, INVALID, 857 /* [88] */ INVALID, INVALID, INVALID, INVALID, 858 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 859 860 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 861 /* [94] */ INVALID, INVALID, INVALID, INVALID, 862 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 863 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 864 865 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 866 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 867 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 868 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 869 870 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 871 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 872 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 873 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 874 875 /* [C0] */ INVALID, INVALID, TNSZ("vcmppd",VEX_RMRX,16), INVALID, 876 /* [C4] */ TNSZ("vpinsrw",VEX_RMRX,2),TNS("vpextrw",VEX_MR), TNSZ("vshufpd",VEX_RMRX,16), INVALID, 877 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 878 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 879 880 /* [D0] */ TNSZ("vaddsubpd",VEX_RMrX,16),TNSZ("vpsrlw",VEX_RMrX,16), TNSZ("vpsrld",VEX_RMrX,16), TNSZ("vpsrlq",VEX_RMrX,16), 881 /* [D4] */ TNSZ("vpaddq",VEX_RMrX,16), TNSZ("vpmullw",VEX_RMrX,16), TNSZ("vmovq",VEX_RX,8), TNS("vpmovmskb",VEX_MR), 882 /* [D8] */ TNSZ("vpsubusb",VEX_RMrX,16), TNSZ("vpsubusw",VEX_RMrX,16), TNSZ("vpminub",VEX_RMrX,16), TNSZ("vpand",VEX_RMrX,16), 883 /* [DC] */ TNSZ("vpaddusb",VEX_RMrX,16), TNSZ("vpaddusw",VEX_RMrX,16), TNSZ("vpmaxub",VEX_RMrX,16), TNSZ("vpandn",VEX_RMrX,16), 884 885 /* [E0] */ TNSZ("vpavgb",VEX_RMrX,16), TNSZ("vpsraw",VEX_RMrX,16), TNSZ("vpsrad",VEX_RMrX,16), TNSZ("vpavgw",VEX_RMrX,16), 886 /* [E4] */ TNSZ("vpmulhuw",VEX_RMrX,16), TNSZ("vpmulhw",VEX_RMrX,16), TNSZ("vcvttpd2dq",VEX_MX,16),TNSZ("vmovntdq",VEX_RM,16), 887 /* [E8] */ TNSZ("vpsubsb",VEX_RMrX,16), TNSZ("vpsubsw",VEX_RMrX,16), TNSZ("vpminsw",VEX_RMrX,16), TNSZ("vpor",VEX_RMrX,16), 888 /* [EC] */ TNSZ("vpaddsb",VEX_RMrX,16), TNSZ("vpaddsw",VEX_RMrX,16), TNSZ("vpmaxsw",VEX_RMrX,16), TNSZ("vpxor",VEX_RMrX,16), 889 890 /* [F0] */ INVALID, TNSZ("vpsllw",VEX_RMrX,16), TNSZ("vpslld",VEX_RMrX,16), TNSZ("vpsllq",VEX_RMrX,16), 891 /* [F4] */ TNSZ("vpmuludq",VEX_RMrX,16), TNSZ("vpmaddwd",VEX_RMrX,16), TNSZ("vpsadbw",VEX_RMrX,16), TNS("vmaskmovdqu",VEX_MX), 892 /* [F8] */ TNSZ("vpsubb",VEX_RMrX,16), TNSZ("vpsubw",VEX_RMrX,16), TNSZ("vpsubd",VEX_RMrX,16), TNSZ("vpsubq",VEX_RMrX,16), 893 /* [FC] */ TNSZ("vpaddb",VEX_RMrX,16), TNSZ("vpaddw",VEX_RMrX,16), TNSZ("vpaddd",VEX_RMrX,16), INVALID, 894 }; 895 896 /* 897 * Decode table for SIMD instructions with the repnz (0xf2) prefix. 898 */ 899 const instable_t dis_opSIMDrepnz[256] = { 900 /* [00] */ INVALID, INVALID, INVALID, INVALID, 901 /* [04] */ INVALID, INVALID, INVALID, INVALID, 902 /* [08] */ INVALID, INVALID, INVALID, INVALID, 903 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 904 905 /* [10] */ TNSZ("movsd",XMM,8), TNSZ("movsd",XMMS,8), TNSZ("movddup",XMM,8), INVALID, 906 /* [14] */ INVALID, INVALID, INVALID, INVALID, 907 /* [18] */ INVALID, INVALID, INVALID, INVALID, 908 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 909 910 /* [20] */ INVALID, INVALID, INVALID, INVALID, 911 /* [24] */ INVALID, INVALID, INVALID, INVALID, 912 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2sd",XMM3MX,4),TNSZ("movntsd",XMMMS,8), 913 /* [2C] */ TNSZ("cvttsd2si",XMMXM3,8),TNSZ("cvtsd2si",XMMXM3,8),INVALID, INVALID, 914 915 /* [30] */ INVALID, INVALID, INVALID, INVALID, 916 /* [34] */ INVALID, INVALID, INVALID, INVALID, 917 /* [38] */ INVALID, INVALID, INVALID, INVALID, 918 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 919 920 /* [40] */ INVALID, INVALID, INVALID, INVALID, 921 /* [44] */ INVALID, INVALID, INVALID, INVALID, 922 /* [48] */ INVALID, INVALID, INVALID, INVALID, 923 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 924 925 /* [50] */ INVALID, TNSZ("sqrtsd",XMM,8), INVALID, INVALID, 926 /* [54] */ INVALID, INVALID, INVALID, INVALID, 927 /* [58] */ TNSZ("addsd",XMM,8), TNSZ("mulsd",XMM,8), TNSZ("cvtsd2ss",XMM,8), INVALID, 928 /* [5C] */ TNSZ("subsd",XMM,8), TNSZ("minsd",XMM,8), TNSZ("divsd",XMM,8), TNSZ("maxsd",XMM,8), 929 930 /* [60] */ INVALID, INVALID, INVALID, INVALID, 931 /* [64] */ INVALID, INVALID, INVALID, INVALID, 932 /* [68] */ INVALID, INVALID, INVALID, INVALID, 933 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 934 935 /* [70] */ TNSZ("pshuflw",XMMP,16),INVALID, INVALID, INVALID, 936 /* [74] */ INVALID, INVALID, INVALID, INVALID, 937 /* [78] */ TNSZ("insertq",XMMX2I,16),TNSZ("insertq",XMM,8),INVALID, INVALID, 938 /* [7C] */ TNSZ("haddps",XMM,16), TNSZ("hsubps",XMM,16), INVALID, INVALID, 939 940 /* [80] */ INVALID, INVALID, INVALID, INVALID, 941 /* [84] */ INVALID, INVALID, INVALID, INVALID, 942 /* [88] */ INVALID, INVALID, INVALID, INVALID, 943 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 944 945 /* [90] */ INVALID, INVALID, INVALID, INVALID, 946 /* [94] */ INVALID, INVALID, INVALID, INVALID, 947 /* [98] */ INVALID, INVALID, INVALID, INVALID, 948 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 949 950 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 951 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 952 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 953 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 954 955 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 956 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 957 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 958 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 959 960 /* [C0] */ INVALID, INVALID, TNSZ("cmpsd",XMMP,8), INVALID, 961 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 962 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 963 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 964 965 /* [D0] */ TNSZ("addsubps",XMM,16),INVALID, INVALID, INVALID, 966 /* [D4] */ INVALID, INVALID, TNS("movdq2q",XMMXM), INVALID, 967 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 968 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 969 970 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 971 /* [E4] */ INVALID, INVALID, TNSZ("cvtpd2dq",XMM,16),INVALID, 972 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 973 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 974 975 /* [F0] */ TNS("lddqu",XMMM), INVALID, INVALID, INVALID, 976 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 977 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 978 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 979 }; 980 981 const instable_t dis_opAVXF20F[256] = { 982 /* [00] */ INVALID, INVALID, INVALID, INVALID, 983 /* [04] */ INVALID, INVALID, INVALID, INVALID, 984 /* [08] */ INVALID, INVALID, INVALID, INVALID, 985 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 986 987 /* [10] */ TNSZ("vmovsd",VEX_RMrX,8), TNSZ("vmovsd",VEX_RRX,8), TNSZ("vmovddup",VEX_MX,8), INVALID, 988 /* [14] */ INVALID, INVALID, INVALID, INVALID, 989 /* [18] */ INVALID, INVALID, INVALID, INVALID, 990 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 991 992 /* [20] */ INVALID, INVALID, INVALID, INVALID, 993 /* [24] */ INVALID, INVALID, INVALID, INVALID, 994 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2sd",VEX_RMrX,4),INVALID, 995 /* [2C] */ TNSZ("vcvttsd2si",VEX_MR,8),TNSZ("vcvtsd2si",VEX_MR,8),INVALID, INVALID, 996 997 /* [30] */ INVALID, INVALID, INVALID, INVALID, 998 /* [34] */ INVALID, INVALID, INVALID, INVALID, 999 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1000 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1001 1002 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1003 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1004 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1005 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1006 1007 /* [50] */ INVALID, TNSZ("vsqrtsd",VEX_RMrX,8), INVALID, INVALID, 1008 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1009 /* [58] */ TNSZ("vaddsd",VEX_RMrX,8), TNSZ("vmulsd",VEX_RMrX,8), TNSZ("vcvtsd2ss",VEX_RMrX,8), INVALID, 1010 /* [5C] */ TNSZ("vsubsd",VEX_RMrX,8), TNSZ("vminsd",VEX_RMrX,8), TNSZ("vdivsd",VEX_RMrX,8), TNSZ("vmaxsd",VEX_RMrX,8), 1011 1012 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1013 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1014 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1015 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1016 1017 /* [70] */ TNSZ("vpshuflw",VEX_MXI,16),INVALID, INVALID, INVALID, 1018 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1019 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1020 /* [7C] */ TNSZ("vhaddps",VEX_RMrX,8), TNSZ("vhsubps",VEX_RMrX,8), INVALID, INVALID, 1021 1022 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1023 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1024 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1025 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1026 1027 /* [90] */ INVALID, INVALID, TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 1028 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1029 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1030 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1031 1032 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1033 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1034 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1035 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1036 1037 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1038 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1039 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1040 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1041 1042 /* [C0] */ INVALID, INVALID, TNSZ("vcmpsd",VEX_RMRX,8), INVALID, 1043 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1044 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1045 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1046 1047 /* [D0] */ TNSZ("vaddsubps",VEX_RMrX,8), INVALID, INVALID, INVALID, 1048 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1049 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1050 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1051 1052 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1053 /* [E4] */ INVALID, INVALID, TNSZ("vcvtpd2dq",VEX_MX,16),INVALID, 1054 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1055 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1056 1057 /* [F0] */ TNSZ("vlddqu",VEX_MX,16), INVALID, INVALID, INVALID, 1058 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1059 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1060 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1061 }; 1062 1063 const instable_t dis_opAVXF20F3A[256] = { 1064 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1065 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1066 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1067 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1068 1069 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1070 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1071 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1072 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1073 1074 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1075 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1076 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1077 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1078 1079 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1080 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1081 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1082 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1083 1084 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1085 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1086 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1087 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1088 1089 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1090 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1091 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1092 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1093 1094 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1095 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1096 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1097 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1098 1099 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1100 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1101 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1102 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1103 1104 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1105 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1106 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1107 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1108 1109 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1110 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1111 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1112 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1113 1114 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1115 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1116 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1117 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1118 1119 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1120 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1121 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1122 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1123 1124 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1125 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1126 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1127 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1128 1129 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1130 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1131 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1132 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1133 1134 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1135 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1136 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1137 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1138 1139 /* [F0] */ TNSZvr("rorx",VEX_MXI,6),INVALID, INVALID, INVALID, 1140 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1141 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1142 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1143 }; 1144 1145 const instable_t dis_opAVXF20F38[256] = { 1146 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1147 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1148 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1149 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1150 1151 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1152 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1153 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1154 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1155 1156 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1157 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1158 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1159 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1160 1161 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1162 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1163 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1164 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1165 1166 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1167 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1168 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1169 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1170 1171 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1172 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1173 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1174 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1175 1176 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1177 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1178 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1179 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1180 1181 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1182 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1183 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1184 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1185 1186 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1187 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1188 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1189 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1190 1191 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1192 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1193 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1194 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1195 1196 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1197 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1198 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1199 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1200 1201 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1202 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1203 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1204 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1205 1206 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1207 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1208 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1209 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1210 1211 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1212 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1213 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1214 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1215 1216 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1217 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1218 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1219 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1220 1221 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1222 /* [F4] */ INVALID, TNSZvr("pdep",VEX_RMrX,5),TNSZvr("mulx",VEX_RMrX,5),TNSZvr("shrx",VEX_VRMrX,5), 1223 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1224 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1225 }; 1226 1227 const instable_t dis_opAVXF30F38[256] = { 1228 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1229 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1230 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1231 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1232 1233 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1234 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1235 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1236 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1237 1238 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1239 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1240 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1241 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1242 1243 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1244 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1245 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1246 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1247 1248 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1249 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1250 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1251 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1252 1253 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1254 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1255 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1256 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1257 1258 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1259 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1260 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1261 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1262 1263 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1264 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1265 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1266 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1267 1268 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1269 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1270 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1271 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1272 1273 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1274 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1275 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1276 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1277 1278 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1279 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1280 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1281 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1282 1283 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1284 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1285 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1286 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1287 1288 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1289 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1290 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1291 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1292 1293 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1294 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1295 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1296 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1297 1298 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1299 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1300 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1301 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1302 1303 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1304 /* [F4] */ INVALID, TNSZvr("pext",VEX_RMrX,5),INVALID, TNSZvr("sarx",VEX_VRMrX,5), 1305 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1306 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1307 }; 1308 /* 1309 * Decode table for SIMD instructions with the repz (0xf3) prefix. 1310 */ 1311 const instable_t dis_opSIMDrepz[256] = { 1312 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1313 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1314 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1315 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1316 1317 /* [10] */ TNSZ("movss",XMM,4), TNSZ("movss",XMMS,4), TNSZ("movsldup",XMM,16),INVALID, 1318 /* [14] */ INVALID, INVALID, TNSZ("movshdup",XMM,16),INVALID, 1319 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1320 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1321 1322 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1323 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1324 /* [28] */ INVALID, INVALID, TNSZ("cvtsi2ss",XMM3MX,4),TNSZ("movntss",XMMMS,4), 1325 /* [2C] */ TNSZ("cvttss2si",XMMXM3,4),TNSZ("cvtss2si",XMMXM3,4),INVALID, INVALID, 1326 1327 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1328 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1329 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1330 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1331 1332 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1333 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1334 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1335 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1336 1337 /* [50] */ INVALID, TNSZ("sqrtss",XMM,4), TNSZ("rsqrtss",XMM,4), TNSZ("rcpss",XMM,4), 1338 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1339 /* [58] */ TNSZ("addss",XMM,4), TNSZ("mulss",XMM,4), TNSZ("cvtss2sd",XMM,4), TNSZ("cvttps2dq",XMM,16), 1340 /* [5C] */ TNSZ("subss",XMM,4), TNSZ("minss",XMM,4), TNSZ("divss",XMM,4), TNSZ("maxss",XMM,4), 1341 1342 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1343 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1344 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1345 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("movdqu",XMM,16), 1346 1347 /* [70] */ TNSZ("pshufhw",XMMP,16),INVALID, INVALID, INVALID, 1348 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1349 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1350 /* [7C] */ INVALID, INVALID, TNSZ("movq",XMM,8), TNSZ("movdqu",XMMS,16), 1351 1352 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1353 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1354 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1355 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1356 1357 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1358 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1359 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1360 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1361 1362 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1363 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1364 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1365 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1366 1367 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1368 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1369 /* [B8] */ TS("popcnt",MRw), INVALID, INVALID, INVALID, 1370 /* [BC] */ TNSZ("tzcnt",MRw,5), TS("lzcnt",MRw), INVALID, INVALID, 1371 1372 /* [C0] */ INVALID, INVALID, TNSZ("cmpss",XMMP,4), INVALID, 1373 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1374 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1375 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1376 1377 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1378 /* [D4] */ INVALID, INVALID, TNS("movq2dq",XMMMX), INVALID, 1379 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1380 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1381 1382 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1383 /* [E4] */ INVALID, INVALID, TNSZ("cvtdq2pd",XMM,8), INVALID, 1384 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1385 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1386 1387 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1388 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1389 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1390 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1391 }; 1392 1393 const instable_t dis_opAVXF30F[256] = { 1394 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1395 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1396 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1397 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1398 1399 /* [10] */ TNSZ("vmovss",VEX_RMrX,4), TNSZ("vmovss",VEX_RRX,4), TNSZ("vmovsldup",VEX_MX,4), INVALID, 1400 /* [14] */ INVALID, INVALID, TNSZ("vmovshdup",VEX_MX,4), INVALID, 1401 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1402 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1403 1404 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1405 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1406 /* [28] */ INVALID, INVALID, TNSZ("vcvtsi2ss",VEX_RMrX,4),INVALID, 1407 /* [2C] */ TNSZ("vcvttss2si",VEX_MR,4),TNSZ("vcvtss2si",VEX_MR,4),INVALID, INVALID, 1408 1409 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1410 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1411 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1412 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1413 1414 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1415 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1416 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1417 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1418 1419 /* [50] */ INVALID, TNSZ("vsqrtss",VEX_RMrX,4), TNSZ("vrsqrtss",VEX_RMrX,4), TNSZ("vrcpss",VEX_RMrX,4), 1420 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1421 /* [58] */ TNSZ("vaddss",VEX_RMrX,4), TNSZ("vmulss",VEX_RMrX,4), TNSZ("vcvtss2sd",VEX_RMrX,4), TNSZ("vcvttps2dq",VEX_MX,16), 1422 /* [5C] */ TNSZ("vsubss",VEX_RMrX,4), TNSZ("vminss",VEX_RMrX,4), TNSZ("vdivss",VEX_RMrX,4), TNSZ("vmaxss",VEX_RMrX,4), 1423 1424 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1425 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1426 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1427 /* [6C] */ INVALID, INVALID, INVALID, TNSZ("vmovdqu",VEX_MX,16), 1428 1429 /* [70] */ TNSZ("vpshufhw",VEX_MXI,16),INVALID, INVALID, INVALID, 1430 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1431 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1432 /* [7C] */ INVALID, INVALID, TNSZ("vmovq",VEX_MX,8), TNSZ("vmovdqu",VEX_RX,16), 1433 1434 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1435 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1436 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1437 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1438 1439 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1440 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1441 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1442 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1443 1444 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1445 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1446 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1447 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1448 1449 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1450 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1451 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1452 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1453 1454 /* [C0] */ INVALID, INVALID, TNSZ("vcmpss",VEX_RMRX,4), INVALID, 1455 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1456 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1457 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1458 1459 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1460 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1461 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1462 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1463 1464 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1465 /* [E4] */ INVALID, INVALID, TNSZ("vcvtdq2pd",VEX_MX,8), INVALID, 1466 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1467 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1468 1469 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1470 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1471 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1472 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1473 }; 1474 1475 /* 1476 * Table for instructions with an EVEX prefix followed by 0F. 1477 */ 1478 const instable_t dis_opEVEX0F[256] = { 1479 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1480 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1481 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1482 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1483 1484 /* [10] */ TNS("vmovups",EVEX_MX), TNS("vmovups",EVEX_RX), INVALID, INVALID, 1485 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1486 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1487 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1488 1489 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1490 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1491 /* [28] */ TNS("vmovaps",EVEX_MX), TNS("vmovaps",EVEX_RX), INVALID, INVALID, 1492 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1493 1494 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1495 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1496 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1497 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1498 1499 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1500 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1501 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1502 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1503 1504 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1505 /* [54] */ TNS("vandps",EVEX_RMrX),TNS("vandnps",EVEX_RMrX),TNS("vorps",EVEX_RMrX),TNS("vxorps",EVEX_RMrX), 1506 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1507 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1508 1509 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1510 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1511 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1512 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1513 1514 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1515 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1516 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1517 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1518 1519 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1520 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1521 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1522 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1523 1524 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1525 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1526 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1527 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1528 1529 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1530 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1531 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1532 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1533 1534 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1535 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1536 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1537 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1538 1539 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1540 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1541 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1542 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1543 1544 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1545 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1546 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1547 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1548 1549 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1550 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1551 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1552 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1553 1554 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1555 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1556 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1557 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1558 }; 1559 1560 /* 1561 * Decode tables for EVEX 66 0F 1562 */ 1563 const instable_t dis_opEVEX660F[256] = { 1564 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1565 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1566 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1567 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1568 1569 /* [10] */ TNS("vmovupd",EVEX_MX), TNS("vmovupd",EVEX_RX), INVALID, INVALID, 1570 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1571 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1572 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1573 1574 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1575 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1576 /* [28] */ TNS("vmovapd",EVEX_MX), TNS("vmovapd",EVEX_RX), INVALID, INVALID, 1577 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1578 1579 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1580 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1581 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1582 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1583 1584 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1585 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1586 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1587 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1588 1589 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1590 /* [54] */ TNS("vandpd",EVEX_RMrX),TNS("vandnpd",EVEX_RMrX),TNS("vorpd",EVEX_RMrX),TNS("vxorpd",EVEX_RMrX), 1591 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1592 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1593 1594 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1595 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1596 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1597 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqa",EVEX_MX), 1598 1599 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1600 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1601 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1602 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqa",EVEX_RX), 1603 1604 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1605 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1606 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1607 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1608 1609 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1610 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1611 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1612 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1613 1614 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1615 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1616 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1617 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1618 1619 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1620 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1621 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1622 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1623 1624 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1625 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1626 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1627 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1628 1629 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1630 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1631 /* [D8] */ INVALID, INVALID, INVALID, TSq("vpand",EVEX_RMrX), 1632 /* [DC] */ INVALID, INVALID, INVALID, TSq("vpandn",EVEX_RMrX), 1633 1634 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1635 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1636 /* [E8] */ INVALID, INVALID, INVALID, TSq("vpor",EVEX_RMrX), 1637 /* [EC] */ INVALID, INVALID, INVALID, TSq("vpxor",EVEX_RMrX), 1638 1639 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1640 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1641 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1642 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1643 }; 1644 1645 const instable_t dis_opEVEX660F38[256] = { 1646 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1647 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1648 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1649 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1650 1651 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1652 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1653 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1654 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1655 1656 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1657 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1658 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1659 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1660 1661 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1662 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1663 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1664 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1665 1666 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1667 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1668 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1669 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1670 1671 /* [50] */ TNSZ("vpdpbusd",EVEX_RMrX,16),TNSZ("vpdpbusds",EVEX_RMrX,16),TNSZ("vpdpwssd",EVEX_RMrX,16),TNSZ("vpdpwssds",EVEX_RMrX,16), 1672 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1673 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1674 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1675 1676 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1677 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1678 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1679 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1680 1681 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1682 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1683 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1684 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1685 1686 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1687 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1688 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1689 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1690 1691 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1692 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1693 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1694 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1695 1696 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1697 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1698 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1699 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1700 1701 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1702 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1703 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1704 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1705 1706 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1707 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1708 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1709 /* [CC] */ INVALID, INVALID, INVALID, TNS("vgf2p8mulb",EVEX_RMrX), 1710 1711 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1712 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1713 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1714 /* [DC] */ TNSZ("vaesenc",EVEX_RMrX,16),TNSZ("vaesenclast",EVEX_RMrX,16),TNSZ("vaesdec",EVEX_RMrX,16),TNSZ("vaesdeclast",EVEX_RMrX,16), 1715 1716 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1717 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1718 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1719 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1720 1721 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1722 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1723 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1724 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1725 }; 1726 1727 const instable_t dis_opEVEX660F3A[256] = { 1728 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1729 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1730 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1731 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1732 1733 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1734 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1735 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1736 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1737 1738 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1739 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1740 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1741 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1742 1743 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1744 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1745 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1746 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1747 1748 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1749 /* [44] */ TNSZ("vpclmulqdq",EVEX_RMRX,16),INVALID, INVALID, INVALID, 1750 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1751 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1752 1753 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1754 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1755 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1756 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1757 1758 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1759 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1760 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1761 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 1762 1763 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1764 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1765 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1766 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 1767 1768 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1769 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1770 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1771 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 1772 1773 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1774 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1775 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1776 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1777 1778 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1779 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1780 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1781 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1782 1783 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1784 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1785 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1786 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1787 1788 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1789 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1790 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1791 /* [CC] */ INVALID, INVALID, TNS("vgf2p8affineqb",EVEX_RMRX),TNS("vgf2p8affineinvqb",EVEX_RMRX), 1792 1793 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1794 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1795 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1796 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1797 1798 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1799 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1800 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1801 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1802 1803 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1804 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1805 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1806 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1807 }; 1808 1809 1810 const instable_t dis_opEVEXF20F[256] = { 1811 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1812 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1813 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1814 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1815 1816 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1817 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1818 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1819 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1820 1821 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1822 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1823 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1824 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1825 1826 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1827 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1828 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1829 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1830 1831 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1832 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1833 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1834 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1835 1836 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1837 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1838 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1839 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1840 1841 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1842 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1843 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1844 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_MX), 1845 1846 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1847 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1848 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1849 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_RX), 1850 1851 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1852 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1853 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1854 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1855 1856 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1857 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1858 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1859 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1860 1861 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1862 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1863 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1864 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1865 1866 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1867 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1868 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1869 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1870 1871 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1872 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1873 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1874 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1875 1876 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1877 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1878 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1879 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1880 1881 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1882 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1883 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1884 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1885 1886 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1887 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1888 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1889 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1890 }; 1891 1892 const instable_t dis_opEVEXF30F[256] = { 1893 /* [00] */ INVALID, INVALID, INVALID, INVALID, 1894 /* [04] */ INVALID, INVALID, INVALID, INVALID, 1895 /* [08] */ INVALID, INVALID, INVALID, INVALID, 1896 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1897 1898 /* [10] */ INVALID, INVALID, INVALID, INVALID, 1899 /* [14] */ INVALID, INVALID, INVALID, INVALID, 1900 /* [18] */ INVALID, INVALID, INVALID, INVALID, 1901 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 1902 1903 /* [20] */ INVALID, INVALID, INVALID, INVALID, 1904 /* [24] */ INVALID, INVALID, INVALID, INVALID, 1905 /* [28] */ INVALID, INVALID, INVALID, INVALID, 1906 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 1907 1908 /* [30] */ INVALID, INVALID, INVALID, INVALID, 1909 /* [34] */ INVALID, INVALID, INVALID, INVALID, 1910 /* [38] */ INVALID, INVALID, INVALID, INVALID, 1911 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 1912 1913 /* [40] */ INVALID, INVALID, INVALID, INVALID, 1914 /* [44] */ INVALID, INVALID, INVALID, INVALID, 1915 /* [48] */ INVALID, INVALID, INVALID, INVALID, 1916 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 1917 1918 /* [50] */ INVALID, INVALID, INVALID, INVALID, 1919 /* [54] */ INVALID, INVALID, INVALID, INVALID, 1920 /* [58] */ INVALID, INVALID, INVALID, INVALID, 1921 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 1922 1923 /* [60] */ INVALID, INVALID, INVALID, INVALID, 1924 /* [64] */ INVALID, INVALID, INVALID, INVALID, 1925 /* [68] */ INVALID, INVALID, INVALID, INVALID, 1926 /* [6C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_MX), 1927 1928 /* [70] */ INVALID, INVALID, INVALID, INVALID, 1929 /* [74] */ INVALID, INVALID, INVALID, INVALID, 1930 /* [78] */ INVALID, INVALID, INVALID, INVALID, 1931 /* [7C] */ INVALID, INVALID, INVALID, TNS("vmovdqu",EVEX_RX), 1932 1933 /* [80] */ INVALID, INVALID, INVALID, INVALID, 1934 /* [84] */ INVALID, INVALID, INVALID, INVALID, 1935 /* [88] */ INVALID, INVALID, INVALID, INVALID, 1936 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 1937 1938 /* [90] */ INVALID, INVALID, INVALID, INVALID, 1939 /* [94] */ INVALID, INVALID, INVALID, INVALID, 1940 /* [98] */ INVALID, INVALID, INVALID, INVALID, 1941 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 1942 1943 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 1944 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 1945 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 1946 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 1947 1948 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 1949 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 1950 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 1951 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 1952 1953 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 1954 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 1955 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 1956 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 1957 1958 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 1959 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 1960 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 1961 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 1962 1963 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 1964 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 1965 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 1966 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 1967 1968 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 1969 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 1970 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 1971 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 1972 }; 1973 /* 1974 * The following two tables are used to encode crc32 and movbe 1975 * since they share the same opcodes. 1976 */ 1977 const instable_t dis_op0F38F0[2] = { 1978 /* [00] */ TNS("crc32b",CRC32), 1979 TS("movbe",MOVBE), 1980 }; 1981 1982 const instable_t dis_op0F38F1[2] = { 1983 /* [00] */ TS("crc32",CRC32), 1984 TS("movbe",MOVBE), 1985 }; 1986 1987 /* 1988 * The following table is used to distinguish between adox and adcx which share 1989 * the same opcodes. 1990 */ 1991 const instable_t dis_op0F38F6[2] = { 1992 /* [00] */ TNS("adcx",ADX), 1993 TNS("adox",ADX), 1994 }; 1995 1996 const instable_t dis_op0F38[256] = { 1997 /* [00] */ TNSZ("pshufb",XMM_66o,16),TNSZ("phaddw",XMM_66o,16),TNSZ("phaddd",XMM_66o,16),TNSZ("phaddsw",XMM_66o,16), 1998 /* [04] */ TNSZ("pmaddubsw",XMM_66o,16),TNSZ("phsubw",XMM_66o,16), TNSZ("phsubd",XMM_66o,16),TNSZ("phsubsw",XMM_66o,16), 1999 /* [08] */ TNSZ("psignb",XMM_66o,16),TNSZ("psignw",XMM_66o,16),TNSZ("psignd",XMM_66o,16),TNSZ("pmulhrsw",XMM_66o,16), 2000 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 2001 2002 /* [10] */ TNSZ("pblendvb",XMM_66r,16),INVALID, INVALID, INVALID, 2003 /* [14] */ TNSZ("blendvps",XMM_66r,16),TNSZ("blendvpd",XMM_66r,16),INVALID, TNSZ("ptest",XMM_66r,16), 2004 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2005 /* [1C] */ TNSZ("pabsb",XMM_66o,16),TNSZ("pabsw",XMM_66o,16),TNSZ("pabsd",XMM_66o,16),INVALID, 2006 2007 /* [20] */ TNSZ("pmovsxbw",XMM_66r,16),TNSZ("pmovsxbd",XMM_66r,16),TNSZ("pmovsxbq",XMM_66r,16),TNSZ("pmovsxwd",XMM_66r,16), 2008 /* [24] */ TNSZ("pmovsxwq",XMM_66r,16),TNSZ("pmovsxdq",XMM_66r,16),INVALID, INVALID, 2009 /* [28] */ TNSZ("pmuldq",XMM_66r,16),TNSZ("pcmpeqq",XMM_66r,16),TNSZ("movntdqa",XMMM_66r,16),TNSZ("packusdw",XMM_66r,16), 2010 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2011 2012 /* [30] */ TNSZ("pmovzxbw",XMM_66r,16),TNSZ("pmovzxbd",XMM_66r,16),TNSZ("pmovzxbq",XMM_66r,16),TNSZ("pmovzxwd",XMM_66r,16), 2013 /* [34] */ TNSZ("pmovzxwq",XMM_66r,16),TNSZ("pmovzxdq",XMM_66r,16),INVALID, TNSZ("pcmpgtq",XMM_66r,16), 2014 /* [38] */ TNSZ("pminsb",XMM_66r,16),TNSZ("pminsd",XMM_66r,16),TNSZ("pminuw",XMM_66r,16),TNSZ("pminud",XMM_66r,16), 2015 /* [3C] */ TNSZ("pmaxsb",XMM_66r,16),TNSZ("pmaxsd",XMM_66r,16),TNSZ("pmaxuw",XMM_66r,16),TNSZ("pmaxud",XMM_66r,16), 2016 2017 /* [40] */ TNSZ("pmulld",XMM_66r,16),TNSZ("phminposuw",XMM_66r,16),INVALID, INVALID, 2018 /* [44] */ INVALID, INVALID, INVALID, INVALID, 2019 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2020 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2021 2022 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2023 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2024 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2025 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2026 2027 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2028 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2029 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2030 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2031 2032 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2033 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2034 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2035 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2036 2037 /* [80] */ TNSy("invept", RM_66r), TNSy("invvpid", RM_66r),TNSy("invpcid", RM_66r),INVALID, 2038 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2039 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2040 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2041 2042 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2043 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2044 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2045 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2046 2047 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2048 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2049 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2050 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2051 2052 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2053 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2054 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2055 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2056 2057 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2058 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2059 /* [C8] */ TNSZ("sha1nexte",XMM,16),TNSZ("sha1msg1",XMM,16),TNSZ("sha1msg2",XMM,16),TNSZ("sha256rnds2",XMM,16), 2060 /* [CC] */ TNSZ("sha256msg1",XMM,16),TNSZ("sha256msg2",XMM,16),INVALID, TNS("gf2p8mulb",XMM_66r), 2061 2062 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2063 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2064 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("aesimc",XMM_66r,16), 2065 /* [DC] */ TNSZ("aesenc",XMM_66r,16),TNSZ("aesenclast",XMM_66r,16),TNSZ("aesdec",XMM_66r,16),TNSZ("aesdeclast",XMM_66r,16), 2066 2067 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2068 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2069 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2070 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2071 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 2072 /* [F4] */ INVALID, INVALID, IND(dis_op0F38F6), INVALID, 2073 /* [F8] */ TNS("movdir64b",MOVDIR),TNS("movdiri",RM), INVALID, INVALID, 2074 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2075 }; 2076 2077 const instable_t dis_opAVX660F38[256] = { 2078 /* [00] */ TNSZ("vpshufb",VEX_RMrX,16),TNSZ("vphaddw",VEX_RMrX,16),TNSZ("vphaddd",VEX_RMrX,16),TNSZ("vphaddsw",VEX_RMrX,16), 2079 /* [04] */ TNSZ("vpmaddubsw",VEX_RMrX,16),TNSZ("vphsubw",VEX_RMrX,16), TNSZ("vphsubd",VEX_RMrX,16),TNSZ("vphsubsw",VEX_RMrX,16), 2080 /* [08] */ TNSZ("vpsignb",VEX_RMrX,16),TNSZ("vpsignw",VEX_RMrX,16),TNSZ("vpsignd",VEX_RMrX,16),TNSZ("vpmulhrsw",VEX_RMrX,16), 2081 /* [0C] */ TNSZ("vpermilps",VEX_RMrX,8),TNSZ("vpermilpd",VEX_RMrX,16),TNSZ("vtestps",VEX_RRI,8), TNSZ("vtestpd",VEX_RRI,16), 2082 2083 /* [10] */ INVALID, INVALID, INVALID, TNSZ("vcvtph2ps",VEX_MX,16), 2084 /* [14] */ INVALID, INVALID, TNSZ("vpermps",VEX_RMrX,16),TNSZ("vptest",VEX_RRI,16), 2085 /* [18] */ TNSZ("vbroadcastss",VEX_MX,4),TNSZ("vbroadcastsd",VEX_MX,8),TNSZ("vbroadcastf128",VEX_MX,16),INVALID, 2086 /* [1C] */ TNSZ("vpabsb",VEX_MX,16),TNSZ("vpabsw",VEX_MX,16),TNSZ("vpabsd",VEX_MX,16),INVALID, 2087 2088 /* [20] */ TNSZ("vpmovsxbw",VEX_MX,16),TNSZ("vpmovsxbd",VEX_MX,16),TNSZ("vpmovsxbq",VEX_MX,16),TNSZ("vpmovsxwd",VEX_MX,16), 2089 /* [24] */ TNSZ("vpmovsxwq",VEX_MX,16),TNSZ("vpmovsxdq",VEX_MX,16),INVALID, INVALID, 2090 /* [28] */ TNSZ("vpmuldq",VEX_RMrX,16),TNSZ("vpcmpeqq",VEX_RMrX,16),TNSZ("vmovntdqa",VEX_MX,16),TNSZ("vpackusdw",VEX_RMrX,16), 2091 /* [2C] */ TNSZ("vmaskmovps",VEX_RMrX,8),TNSZ("vmaskmovpd",VEX_RMrX,16),TNSZ("vmaskmovps",VEX_RRM,8),TNSZ("vmaskmovpd",VEX_RRM,16), 2092 2093 /* [30] */ TNSZ("vpmovzxbw",VEX_MX,16),TNSZ("vpmovzxbd",VEX_MX,16),TNSZ("vpmovzxbq",VEX_MX,16),TNSZ("vpmovzxwd",VEX_MX,16), 2094 /* [34] */ TNSZ("vpmovzxwq",VEX_MX,16),TNSZ("vpmovzxdq",VEX_MX,16),TNSZ("vpermd",VEX_RMrX,16),TNSZ("vpcmpgtq",VEX_RMrX,16), 2095 /* [38] */ TNSZ("vpminsb",VEX_RMrX,16),TNSZ("vpminsd",VEX_RMrX,16),TNSZ("vpminuw",VEX_RMrX,16),TNSZ("vpminud",VEX_RMrX,16), 2096 /* [3C] */ TNSZ("vpmaxsb",VEX_RMrX,16),TNSZ("vpmaxsd",VEX_RMrX,16),TNSZ("vpmaxuw",VEX_RMrX,16),TNSZ("vpmaxud",VEX_RMrX,16), 2097 2098 /* [40] */ TNSZ("vpmulld",VEX_RMrX,16),TNSZ("vphminposuw",VEX_MX,16),INVALID, INVALID, 2099 /* [44] */ INVALID, TSaZ("vpsrlv",VEX_RMrX,16),TNSZ("vpsravd",VEX_RMrX,16),TSaZ("vpsllv",VEX_RMrX,16), 2100 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2101 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2102 2103 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2104 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2105 /* [58] */ TNSZ("vpbroadcastd",VEX_MX,16),TNSZ("vpbroadcastq",VEX_MX,16),TNSZ("vbroadcasti128",VEX_MX,16),INVALID, 2106 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2107 2108 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2109 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2110 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2111 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2112 2113 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2114 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2115 /* [78] */ TNSZ("vpbroadcastb",VEX_MX,16),TNSZ("vpbroadcastw",VEX_MX,16),INVALID, INVALID, 2116 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2117 2118 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2119 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2120 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2121 /* [8C] */ TSaZ("vpmaskmov",VEX_RMrX,16),INVALID, TSaZ("vpmaskmov",VEX_RRM,16),INVALID, 2122 2123 /* [90] */ TNSZ("vpgatherd",VEX_SbVM,16),TNSZ("vpgatherq",VEX_SbVM,16),TNSZ("vgatherdp",VEX_SbVM,16),TNSZ("vgatherqp",VEX_SbVM,16), 2124 /* [94] */ INVALID, INVALID, TNSZ("vfmaddsub132p",FMA,16),TNSZ("vfmsubadd132p",FMA,16), 2125 /* [98] */ TNSZ("vfmadd132p",FMA,16),TNSZ("vfmadd132s",FMA,16),TNSZ("vfmsub132p",FMA,16),TNSZ("vfmsub132s",FMA,16), 2126 /* [9C] */ TNSZ("vfnmadd132p",FMA,16),TNSZ("vfnmadd132s",FMA,16),TNSZ("vfnmsub132p",FMA,16),TNSZ("vfnmsub132s",FMA,16), 2127 2128 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2129 /* [A4] */ INVALID, INVALID, TNSZ("vfmaddsub213p",FMA,16),TNSZ("vfmsubadd213p",FMA,16), 2130 /* [A8] */ TNSZ("vfmadd213p",FMA,16),TNSZ("vfmadd213s",FMA,16),TNSZ("vfmsub213p",FMA,16),TNSZ("vfmsub213s",FMA,16), 2131 /* [AC] */ TNSZ("vfnmadd213p",FMA,16),TNSZ("vfnmadd213s",FMA,16),TNSZ("vfnmsub213p",FMA,16),TNSZ("vfnmsub213s",FMA,16), 2132 2133 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2134 /* [B4] */ INVALID, INVALID, TNSZ("vfmaddsub231p",FMA,16),TNSZ("vfmsubadd231p",FMA,16), 2135 /* [B8] */ TNSZ("vfmadd231p",FMA,16),TNSZ("vfmadd231s",FMA,16),TNSZ("vfmsub231p",FMA,16),TNSZ("vfmsub231s",FMA,16), 2136 /* [BC] */ TNSZ("vfnmadd231p",FMA,16),TNSZ("vfnmadd231s",FMA,16),TNSZ("vfnmsub231p",FMA,16),TNSZ("vfnmsub231s",FMA,16), 2137 2138 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2139 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2140 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2141 /* [CC] */ INVALID, INVALID, INVALID, TNS("vgf2p8mulb",VEX_RMrX), 2142 2143 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2144 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2145 /* [D8] */ INVALID, INVALID, INVALID, TNSZ("vaesimc",VEX_MX,16), 2146 /* [DC] */ TNSZ("vaesenc",VEX_RMrX,16),TNSZ("vaesenclast",VEX_RMrX,16),TNSZ("vaesdec",VEX_RMrX,16),TNSZ("vaesdeclast",VEX_RMrX,16), 2147 2148 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2149 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2150 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2151 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2152 /* [F0] */ IND(dis_op0F38F0), IND(dis_op0F38F1), INVALID, INVALID, 2153 /* [F4] */ INVALID, INVALID, INVALID, TNSZvr("shlx",VEX_VRMrX,5), 2154 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2155 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2156 }; 2157 2158 const instable_t dis_op0F3A[256] = { 2159 /* [00] */ INVALID, INVALID, INVALID, INVALID, 2160 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2161 /* [08] */ TNSZ("roundps",XMMP_66r,16),TNSZ("roundpd",XMMP_66r,16),TNSZ("roundss",XMMP_66r,16),TNSZ("roundsd",XMMP_66r,16), 2162 /* [0C] */ TNSZ("blendps",XMMP_66r,16),TNSZ("blendpd",XMMP_66r,16),TNSZ("pblendw",XMMP_66r,16),TNSZ("palignr",XMMP_66o,16), 2163 2164 /* [10] */ INVALID, INVALID, INVALID, INVALID, 2165 /* [14] */ TNSZ("pextrb",XMM3PM_66r,8),TNSZ("pextrw",XMM3PM_66r,16),TSZ("pextr",XMM3PM_66r,16),TNSZ("extractps",XMM3PM_66r,16), 2166 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2167 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 2168 2169 /* [20] */ TNSZ("pinsrb",XMMPRM_66r,8),TNSZ("insertps",XMMP_66r,16),TSZ("pinsr",XMMPRM_66r,16),INVALID, 2170 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2171 /* [28] */ INVALID, INVALID, INVALID, INVALID, 2172 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2173 2174 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2175 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2176 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2177 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2178 2179 /* [40] */ TNSZ("dpps",XMMP_66r,16),TNSZ("dppd",XMMP_66r,16),TNSZ("mpsadbw",XMMP_66r,16),INVALID, 2180 /* [44] */ TNSZ("pclmulqdq",XMMP_66r,16),INVALID, INVALID, INVALID, 2181 /* [48] */ INVALID, INVALID, INVALID, INVALID, 2182 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2183 2184 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2185 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2186 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2187 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2188 2189 /* [60] */ TNSZ("pcmpestrm",XMMP_66r,16),TNSZ("pcmpestri",XMMP_66r,16),TNSZ("pcmpistrm",XMMP_66r,16),TNSZ("pcmpistri",XMMP_66r,16), 2190 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2191 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2192 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2193 2194 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2195 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2196 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2197 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2198 2199 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2200 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2201 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2202 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2203 2204 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2205 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2206 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2207 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2208 2209 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2210 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2211 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2212 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2213 2214 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2215 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2216 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2217 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2218 2219 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2220 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2221 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2222 /* [CC] */ TNSZ("sha1rnds4",XMMP,16),INVALID, TNS("gf2p8affineqb",XMMP_66r),TNS("gf2p8affineinvqb",XMMP_66r), 2223 2224 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2225 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2226 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2227 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("aeskeygenassist",XMMP_66r,16), 2228 2229 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2230 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2231 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2232 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2233 2234 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 2235 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 2236 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2237 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2238 }; 2239 2240 const instable_t dis_opAVX660F3A[256] = { 2241 /* [00] */ TNSZ("vpermq",VEX_MXI,16),TNSZ("vpermpd",VEX_MXI,16),TNSZ("vpblendd",VEX_RMRX,16),INVALID, 2242 /* [04] */ TNSZ("vpermilps",VEX_MXI,8),TNSZ("vpermilpd",VEX_MXI,16),TNSZ("vperm2f128",VEX_RMRX,16),INVALID, 2243 /* [08] */ TNSZ("vroundps",VEX_MXI,16),TNSZ("vroundpd",VEX_MXI,16),TNSZ("vroundss",VEX_RMRX,16),TNSZ("vroundsd",VEX_RMRX,16), 2244 /* [0C] */ TNSZ("vblendps",VEX_RMRX,16),TNSZ("vblendpd",VEX_RMRX,16),TNSZ("vpblendw",VEX_RMRX,16),TNSZ("vpalignr",VEX_RMRX,16), 2245 2246 /* [10] */ INVALID, INVALID, INVALID, INVALID, 2247 /* [14] */ TNSZ("vpextrb",VEX_RRi,8),TNSZ("vpextrw",VEX_RRi,16),TNSZ("vpextrd",VEX_RRi,16),TNSZ("vextractps",VEX_RM,16), 2248 /* [18] */ TNSZ("vinsertf128",VEX_RMRX,16),TNSZ("vextractf128",VEX_RX,16),INVALID, INVALID, 2249 /* [1C] */ INVALID, TNSZ("vcvtps2ph",VEX_RX,16), INVALID, INVALID, 2250 2251 /* [20] */ TNSZ("vpinsrb",VEX_RMRX,8),TNSZ("vinsertps",VEX_RMRX,16),TNSZ("vpinsrd",VEX_RMRX,16),INVALID, 2252 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2253 /* [28] */ INVALID, INVALID, INVALID, INVALID, 2254 /* [2C] */ INVALID, INVALID, INVALID, INVALID, 2255 2256 /* [30] */ TSvo("kshiftr",VEX_MXI), TSvo("kshiftr",VEX_MXI), TSvo("kshiftl",VEX_MXI), TSvo("kshiftl",VEX_MXI), 2257 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2258 /* [38] */ TNSZ("vinserti128",VEX_RMRX,16),TNSZ("vextracti128",VEX_RIM,16),INVALID, INVALID, 2259 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2260 2261 /* [40] */ TNSZ("vdpps",VEX_RMRX,16),TNSZ("vdppd",VEX_RMRX,16),TNSZ("vmpsadbw",VEX_RMRX,16),INVALID, 2262 /* [44] */ TNSZ("vpclmulqdq",VEX_RMRX,16),INVALID, TNSZ("vperm2i128",VEX_RMRX,16),INVALID, 2263 /* [48] */ INVALID, INVALID, TNSZ("vblendvps",VEX_RMRX,8), TNSZ("vblendvpd",VEX_RMRX,16), 2264 /* [4C] */ TNSZ("vpblendvb",VEX_RMRX,16),INVALID, INVALID, INVALID, 2265 2266 /* [50] */ INVALID, INVALID, INVALID, INVALID, 2267 /* [54] */ INVALID, INVALID, INVALID, INVALID, 2268 /* [58] */ INVALID, INVALID, INVALID, INVALID, 2269 /* [5C] */ INVALID, INVALID, INVALID, INVALID, 2270 2271 /* [60] */ TNSZ("vpcmpestrm",VEX_MXI,16),TNSZ("vpcmpestri",VEX_MXI,16),TNSZ("vpcmpistrm",VEX_MXI,16),TNSZ("vpcmpistri",VEX_MXI,16), 2272 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2273 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2274 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2275 2276 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2277 /* [74] */ INVALID, INVALID, INVALID, INVALID, 2278 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2279 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2280 2281 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2282 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2283 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2284 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2285 2286 /* [90] */ INVALID, INVALID, INVALID, INVALID, 2287 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2288 /* [98] */ INVALID, INVALID, INVALID, INVALID, 2289 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2290 2291 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2292 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2293 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2294 /* [AC] */ INVALID, INVALID, INVALID, INVALID, 2295 2296 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2297 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2298 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2299 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2300 2301 /* [C0] */ INVALID, INVALID, INVALID, INVALID, 2302 /* [C4] */ INVALID, INVALID, INVALID, INVALID, 2303 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2304 /* [CC] */ INVALID, INVALID, TNS("vgf2p8affineqb",VEX_RMRX),TNS("vgf2p8affineinvqb",VEX_RMRX), 2305 2306 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2307 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2308 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2309 /* [DC] */ INVALID, INVALID, INVALID, TNSZ("vaeskeygenassist",VEX_MXI,16), 2310 2311 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2312 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2313 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2314 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2315 2316 /* [F0] */ INVALID, INVALID, INVALID, INVALID, 2317 /* [F4] */ INVALID, INVALID, INVALID, INVALID, 2318 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2319 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2320 }; 2321 2322 /* 2323 * Decode table for 0x0F0D which uses the first byte of the mod_rm to 2324 * indicate a sub-code. 2325 */ 2326 const instable_t dis_op0F0D[8] = { 2327 /* [00] */ TNS("prefetch",PREF), TNS("prefetchw",PREF), TNS("prefetchwt1",PREF),INVALID, 2328 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2329 }; 2330 2331 /* 2332 * Decode table for 0x0F opcodes 2333 */ 2334 2335 const instable_t dis_op0F[16][16] = { 2336 { 2337 /* [00] */ IND(dis_op0F00), IND(dis_op0F01), TNS("lar",MR), TNS("lsl",MR), 2338 /* [04] */ INVALID, TNS("syscall",NORM), TNS("clts",NORM), TNS("sysret",NORM), 2339 /* [08] */ TNS("invd",NORM), TNS("wbinvd",NORM), INVALID, TNS("ud2",NORM), 2340 /* [0C] */ INVALID, IND(dis_op0F0D), INVALID, INVALID, 2341 }, { 2342 /* [10] */ TNSZ("movups",XMMO,16), TNSZ("movups",XMMOS,16),TNSZ("movlps",XMMO,8), TNSZ("movlps",XMMOS,8), 2343 /* [14] */ TNSZ("unpcklps",XMMO,16),TNSZ("unpckhps",XMMO,16),TNSZ("movhps",XMMOM,8),TNSZ("movhps",XMMOMS,8), 2344 /* [18] */ IND(dis_op0F18), INVALID, INVALID, INVALID, 2345 /* [1C] */ INVALID, INVALID, INVALID, TS("nop",Mw), 2346 }, { 2347 /* [20] */ TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), TSy("mov",SREG), 2348 /* [24] */ TSx("mov",SREG), INVALID, TSx("mov",SREG), INVALID, 2349 /* [28] */ TNSZ("movaps",XMMO,16), TNSZ("movaps",XMMOS,16),TNSZ("cvtpi2ps",XMMOMX,8),TNSZ("movntps",XMMOS,16), 2350 /* [2C] */ TNSZ("cvttps2pi",XMMOXMM,8),TNSZ("cvtps2pi",XMMOXMM,8),TNSZ("ucomiss",XMMO,4),TNSZ("comiss",XMMO,4), 2351 }, { 2352 /* [30] */ TNS("wrmsr",NORM), TNS("rdtsc",NORM), TNS("rdmsr",NORM), TNS("rdpmc",NORM), 2353 /* [34] */ TNS("sysenter",NORM), TNS("sysexit",NORM), INVALID, INVALID, 2354 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2355 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2356 }, { 2357 /* [40] */ TS("cmovx.o",MR), TS("cmovx.no",MR), TS("cmovx.b",MR), TS("cmovx.ae",MR), 2358 /* [44] */ TS("cmovx.e",MR), TS("cmovx.ne",MR), TS("cmovx.be",MR), TS("cmovx.a",MR), 2359 /* [48] */ TS("cmovx.s",MR), TS("cmovx.ns",MR), TS("cmovx.pe",MR), TS("cmovx.po",MR), 2360 /* [4C] */ TS("cmovx.l",MR), TS("cmovx.ge",MR), TS("cmovx.le",MR), TS("cmovx.g",MR), 2361 }, { 2362 /* [50] */ TNS("movmskps",XMMOX3), TNSZ("sqrtps",XMMO,16), TNSZ("rsqrtps",XMMO,16),TNSZ("rcpps",XMMO,16), 2363 /* [54] */ TNSZ("andps",XMMO,16), TNSZ("andnps",XMMO,16), TNSZ("orps",XMMO,16), TNSZ("xorps",XMMO,16), 2364 /* [58] */ TNSZ("addps",XMMO,16), TNSZ("mulps",XMMO,16), TNSZ("cvtps2pd",XMMO,8),TNSZ("cvtdq2ps",XMMO,16), 2365 /* [5C] */ TNSZ("subps",XMMO,16), TNSZ("minps",XMMO,16), TNSZ("divps",XMMO,16), TNSZ("maxps",XMMO,16), 2366 }, { 2367 /* [60] */ TNSZ("punpcklbw",MMO,4),TNSZ("punpcklwd",MMO,4),TNSZ("punpckldq",MMO,4),TNSZ("packsswb",MMO,8), 2368 /* [64] */ TNSZ("pcmpgtb",MMO,8), TNSZ("pcmpgtw",MMO,8), TNSZ("pcmpgtd",MMO,8), TNSZ("packuswb",MMO,8), 2369 /* [68] */ TNSZ("punpckhbw",MMO,8),TNSZ("punpckhwd",MMO,8),TNSZ("punpckhdq",MMO,8),TNSZ("packssdw",MMO,8), 2370 /* [6C] */ TNSZ("INVALID",MMO,0), TNSZ("INVALID",MMO,0), TNSZ("movd",MMO,4), TNSZ("movq",MMO,8), 2371 }, { 2372 /* [70] */ TNSZ("pshufw",MMOPM,8), TNS("psrXXX",MR), TNS("psrXXX",MR), TNS("psrXXX",MR), 2373 /* [74] */ TNSZ("pcmpeqb",MMO,8), TNSZ("pcmpeqw",MMO,8), TNSZ("pcmpeqd",MMO,8), TNS("emms",NORM), 2374 /* [78] */ TNSy("vmread",RM), TNSy("vmwrite",MR), INVALID, INVALID, 2375 /* [7C] */ INVALID, INVALID, TNSZ("movd",MMOS,4), TNSZ("movq",MMOS,8), 2376 }, { 2377 /* [80] */ TNS("jo",D), TNS("jno",D), TNS("jb",D), TNS("jae",D), 2378 /* [84] */ TNS("je",D), TNS("jne",D), TNS("jbe",D), TNS("ja",D), 2379 /* [88] */ TNS("js",D), TNS("jns",D), TNS("jp",D), TNS("jnp",D), 2380 /* [8C] */ TNS("jl",D), TNS("jge",D), TNS("jle",D), TNS("jg",D), 2381 }, { 2382 /* [90] */ TNS("seto",Mb), TNS("setno",Mb), TNS("setb",Mb), TNS("setae",Mb), 2383 /* [94] */ TNS("sete",Mb), TNS("setne",Mb), TNS("setbe",Mb), TNS("seta",Mb), 2384 /* [98] */ TNS("sets",Mb), TNS("setns",Mb), TNS("setp",Mb), TNS("setnp",Mb), 2385 /* [9C] */ TNS("setl",Mb), TNS("setge",Mb), TNS("setle",Mb), TNS("setg",Mb), 2386 }, { 2387 /* [A0] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("cpuid",NORM), TS("bt",RMw), 2388 /* [A4] */ TS("shld",DSHIFT), TS("shld",DSHIFTcl), INVALID, INVALID, 2389 /* [A8] */ TSp("push",LSEG), TSp("pop",LSEG), TNS("rsm",NORM), TS("bts",RMw), 2390 /* [AC] */ TS("shrd",DSHIFT), TS("shrd",DSHIFTcl), IND(dis_op0FAE), TS("imul",MRw), 2391 }, { 2392 /* [B0] */ TNS("cmpxchgb",RMw), TS("cmpxchg",RMw), TS("lss",MR), TS("btr",RMw), 2393 /* [B4] */ TS("lfs",MR), TS("lgs",MR), TS("movzb",MOVZ), TNS("movzwl",MOVZ), 2394 /* [B8] */ TNS("INVALID",MRw), INVALID, IND(dis_op0FBA), TS("btc",RMw), 2395 /* [BC] */ TS("bsf",MRw), TS("bsr",MRw), TS("movsb",MOVZ), TNS("movswl",MOVZ), 2396 }, { 2397 /* [C0] */ TNS("xaddb",XADDB), TS("xadd",RMw), TNSZ("cmpps",XMMOPM,16),TNS("movnti",RM), 2398 /* [C4] */ TNSZ("pinsrw",MMOPRM,2),TNS("pextrw",MMO3P), TNSZ("shufps",XMMOPM,16),IND(dis_op0FC7), 2399 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2400 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2401 }, { 2402 /* [D0] */ INVALID, TNSZ("psrlw",MMO,8), TNSZ("psrld",MMO,8), TNSZ("psrlq",MMO,8), 2403 /* [D4] */ TNSZ("paddq",MMO,8), TNSZ("pmullw",MMO,8), TNSZ("INVALID",MMO,0), TNS("pmovmskb",MMOM3), 2404 /* [D8] */ TNSZ("psubusb",MMO,8), TNSZ("psubusw",MMO,8), TNSZ("pminub",MMO,8), TNSZ("pand",MMO,8), 2405 /* [DC] */ TNSZ("paddusb",MMO,8), TNSZ("paddusw",MMO,8), TNSZ("pmaxub",MMO,8), TNSZ("pandn",MMO,8), 2406 }, { 2407 /* [E0] */ TNSZ("pavgb",MMO,8), TNSZ("psraw",MMO,8), TNSZ("psrad",MMO,8), TNSZ("pavgw",MMO,8), 2408 /* [E4] */ TNSZ("pmulhuw",MMO,8), TNSZ("pmulhw",MMO,8), TNS("INVALID",XMMO), TNSZ("movntq",MMOMS,8), 2409 /* [E8] */ TNSZ("psubsb",MMO,8), TNSZ("psubsw",MMO,8), TNSZ("pminsw",MMO,8), TNSZ("por",MMO,8), 2410 /* [EC] */ TNSZ("paddsb",MMO,8), TNSZ("paddsw",MMO,8), TNSZ("pmaxsw",MMO,8), TNSZ("pxor",MMO,8), 2411 }, { 2412 /* [F0] */ INVALID, TNSZ("psllw",MMO,8), TNSZ("pslld",MMO,8), TNSZ("psllq",MMO,8), 2413 /* [F4] */ TNSZ("pmuludq",MMO,8), TNSZ("pmaddwd",MMO,8), TNSZ("psadbw",MMO,8), TNSZ("maskmovq",MMOIMPL,8), 2414 /* [F8] */ TNSZ("psubb",MMO,8), TNSZ("psubw",MMO,8), TNSZ("psubd",MMO,8), TNSZ("psubq",MMO,8), 2415 /* [FC] */ TNSZ("paddb",MMO,8), TNSZ("paddw",MMO,8), TNSZ("paddd",MMO,8), INVALID, 2416 } }; 2417 2418 const instable_t dis_opAVX0F[16][16] = { 2419 { 2420 /* [00] */ INVALID, INVALID, INVALID, INVALID, 2421 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2422 /* [08] */ INVALID, INVALID, INVALID, INVALID, 2423 /* [0C] */ INVALID, INVALID, INVALID, INVALID, 2424 }, { 2425 /* [10] */ TNSZ("vmovups",VEX_MX,16), TNSZ("vmovups",VEX_RM,16),TNSZ("vmovlps",VEX_RMrX,8), TNSZ("vmovlps",VEX_RM,8), 2426 /* [14] */ TNSZ("vunpcklps",VEX_RMrX,16),TNSZ("vunpckhps",VEX_RMrX,16),TNSZ("vmovhps",VEX_RMrX,8),TNSZ("vmovhps",VEX_RM,8), 2427 /* [18] */ INVALID, INVALID, INVALID, INVALID, 2428 /* [1C] */ INVALID, INVALID, INVALID, INVALID, 2429 }, { 2430 /* [20] */ INVALID, INVALID, INVALID, INVALID, 2431 /* [24] */ INVALID, INVALID, INVALID, INVALID, 2432 /* [28] */ TNSZ("vmovaps",VEX_MX,16), TNSZ("vmovaps",VEX_RX,16),INVALID, TNSZ("vmovntps",VEX_RM,16), 2433 /* [2C] */ INVALID, INVALID, TNSZ("vucomiss",VEX_MX,4),TNSZ("vcomiss",VEX_MX,4), 2434 }, { 2435 /* [30] */ INVALID, INVALID, INVALID, INVALID, 2436 /* [34] */ INVALID, INVALID, INVALID, INVALID, 2437 /* [38] */ INVALID, INVALID, INVALID, INVALID, 2438 /* [3C] */ INVALID, INVALID, INVALID, INVALID, 2439 }, { 2440 /* [40] */ INVALID, TSvo("kand",VEX_RMX), TSvo("kandn",VEX_RMX), INVALID, 2441 /* [44] */ TSvo("knot",VEX_MX), TSvo("kor",VEX_RMX), TSvo("kxnor",VEX_RMX), TSvo("kxor",VEX_RMX), 2442 /* [48] */ INVALID, INVALID, TSvo("kadd",VEX_RMX), TSvo("kunpck",VEX_RMX), 2443 /* [4C] */ INVALID, INVALID, INVALID, INVALID, 2444 }, { 2445 /* [50] */ TNS("vmovmskps",VEX_MR), TNSZ("vsqrtps",VEX_MX,16), TNSZ("vrsqrtps",VEX_MX,16),TNSZ("vrcpps",VEX_MX,16), 2446 /* [54] */ TNSZ("vandps",VEX_RMrX,16), TNSZ("vandnps",VEX_RMrX,16), TNSZ("vorps",VEX_RMrX,16), TNSZ("vxorps",VEX_RMrX,16), 2447 /* [58] */ TNSZ("vaddps",VEX_RMrX,16), TNSZ("vmulps",VEX_RMrX,16), TNSZ("vcvtps2pd",VEX_MX,8),TNSZ("vcvtdq2ps",VEX_MX,16), 2448 /* [5C] */ TNSZ("vsubps",VEX_RMrX,16), TNSZ("vminps",VEX_RMrX,16), TNSZ("vdivps",VEX_RMrX,16), TNSZ("vmaxps",VEX_RMrX,16), 2449 }, { 2450 /* [60] */ INVALID, INVALID, INVALID, INVALID, 2451 /* [64] */ INVALID, INVALID, INVALID, INVALID, 2452 /* [68] */ INVALID, INVALID, INVALID, INVALID, 2453 /* [6C] */ INVALID, INVALID, INVALID, INVALID, 2454 }, { 2455 /* [70] */ INVALID, INVALID, INVALID, INVALID, 2456 /* [74] */ INVALID, INVALID, INVALID, TNS("vzeroupper", VEX_NONE), 2457 /* [78] */ INVALID, INVALID, INVALID, INVALID, 2458 /* [7C] */ INVALID, INVALID, INVALID, INVALID, 2459 }, { 2460 /* [80] */ INVALID, INVALID, INVALID, INVALID, 2461 /* [84] */ INVALID, INVALID, INVALID, INVALID, 2462 /* [88] */ INVALID, INVALID, INVALID, INVALID, 2463 /* [8C] */ INVALID, INVALID, INVALID, INVALID, 2464 }, { 2465 /* [90] */ TSvo("kmov",VEX_KRM), TSvo("kmov",VEX_KMR), TSvo("kmov",VEX_KRR), TSvo("kmov",VEX_MR), 2466 /* [94] */ INVALID, INVALID, INVALID, INVALID, 2467 /* [98] */ TSvo("kortest",VEX_MX), TSvo("ktest",VEX_MX), INVALID, INVALID, 2468 /* [9C] */ INVALID, INVALID, INVALID, INVALID, 2469 }, { 2470 /* [A0] */ INVALID, INVALID, INVALID, INVALID, 2471 /* [A4] */ INVALID, INVALID, INVALID, INVALID, 2472 /* [A8] */ INVALID, INVALID, INVALID, INVALID, 2473 /* [AC] */ INVALID, INVALID, TNSZ("vldmxcsr",VEX_MO,2), INVALID, 2474 }, { 2475 /* [B0] */ INVALID, INVALID, INVALID, INVALID, 2476 /* [B4] */ INVALID, INVALID, INVALID, INVALID, 2477 /* [B8] */ INVALID, INVALID, INVALID, INVALID, 2478 /* [BC] */ INVALID, INVALID, INVALID, INVALID, 2479 }, { 2480 /* [C0] */ INVALID, INVALID, TNSZ("vcmpps",VEX_RMRX,16),INVALID, 2481 /* [C4] */ INVALID, INVALID, TNSZ("vshufps",VEX_RMRX,16),INVALID, 2482 /* [C8] */ INVALID, INVALID, INVALID, INVALID, 2483 /* [CC] */ INVALID, INVALID, INVALID, INVALID, 2484 }, { 2485 /* [D0] */ INVALID, INVALID, INVALID, INVALID, 2486 /* [D4] */ INVALID, INVALID, INVALID, INVALID, 2487 /* [D8] */ INVALID, INVALID, INVALID, INVALID, 2488 /* [DC] */ INVALID, INVALID, INVALID, INVALID, 2489 }, { 2490 /* [E0] */ INVALID, INVALID, INVALID, INVALID, 2491 /* [E4] */ INVALID, INVALID, INVALID, INVALID, 2492 /* [E8] */ INVALID, INVALID, INVALID, INVALID, 2493 /* [EC] */ INVALID, INVALID, INVALID, INVALID, 2494 }, { 2495 /* [F0] */ INVALID, INVALID, TNSZvr("andn",VEX_RMrX,5),TNSZvr("bls",BLS,5), 2496 /* [F4] */ INVALID, TNSZvr("bzhi",VEX_VRMrX,5),INVALID, TNSZvr("bextr",VEX_VRMrX,5), 2497 /* [F8] */ INVALID, INVALID, INVALID, INVALID, 2498 /* [FC] */ INVALID, INVALID, INVALID, INVALID, 2499 } }; 2500 2501 /* 2502 * Decode table for 0x80 opcodes 2503 */ 2504 2505 const instable_t dis_op80[8] = { 2506 2507 /* [0] */ TNS("addb",IMlw), TNS("orb",IMw), TNS("adcb",IMlw), TNS("sbbb",IMlw), 2508 /* [4] */ TNS("andb",IMw), TNS("subb",IMlw), TNS("xorb",IMw), TNS("cmpb",IMlw), 2509 }; 2510 2511 2512 /* 2513 * Decode table for 0x81 opcodes. 2514 */ 2515 2516 const instable_t dis_op81[8] = { 2517 2518 /* [0] */ TS("add",IMlw), TS("or",IMw), TS("adc",IMlw), TS("sbb",IMlw), 2519 /* [4] */ TS("and",IMw), TS("sub",IMlw), TS("xor",IMw), TS("cmp",IMlw), 2520 }; 2521 2522 2523 /* 2524 * Decode table for 0x82 opcodes. 2525 */ 2526 2527 const instable_t dis_op82[8] = { 2528 2529 /* [0] */ TNSx("addb",IMlw), TNSx("orb",IMlw), TNSx("adcb",IMlw), TNSx("sbbb",IMlw), 2530 /* [4] */ TNSx("andb",IMlw), TNSx("subb",IMlw), TNSx("xorb",IMlw), TNSx("cmpb",IMlw), 2531 }; 2532 /* 2533 * Decode table for 0x83 opcodes. 2534 */ 2535 2536 const instable_t dis_op83[8] = { 2537 2538 /* [0] */ TS("add",IMlw), TS("or",IMlw), TS("adc",IMlw), TS("sbb",IMlw), 2539 /* [4] */ TS("and",IMlw), TS("sub",IMlw), TS("xor",IMlw), TS("cmp",IMlw), 2540 }; 2541 2542 /* 2543 * Decode table for 0xC0 opcodes. 2544 */ 2545 2546 const instable_t dis_opC0[8] = { 2547 2548 /* [0] */ TNS("rolb",MvI), TNS("rorb",MvI), TNS("rclb",MvI), TNS("rcrb",MvI), 2549 /* [4] */ TNS("shlb",MvI), TNS("shrb",MvI), INVALID, TNS("sarb",MvI), 2550 }; 2551 2552 /* 2553 * Decode table for 0xD0 opcodes. 2554 */ 2555 2556 const instable_t dis_opD0[8] = { 2557 2558 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2559 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2560 }; 2561 2562 /* 2563 * Decode table for 0xC1 opcodes. 2564 * 186 instruction set 2565 */ 2566 2567 const instable_t dis_opC1[8] = { 2568 2569 /* [0] */ TS("rol",MvI), TS("ror",MvI), TS("rcl",MvI), TS("rcr",MvI), 2570 /* [4] */ TS("shl",MvI), TS("shr",MvI), TS("sal",MvI), TS("sar",MvI), 2571 }; 2572 2573 /* 2574 * Decode table for 0xD1 opcodes. 2575 */ 2576 2577 const instable_t dis_opD1[8] = { 2578 2579 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2580 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("sal",Mv), TS("sar",Mv), 2581 }; 2582 2583 2584 /* 2585 * Decode table for 0xD2 opcodes. 2586 */ 2587 2588 const instable_t dis_opD2[8] = { 2589 2590 /* [0] */ TNS("rolb",Mv), TNS("rorb",Mv), TNS("rclb",Mv), TNS("rcrb",Mv), 2591 /* [4] */ TNS("shlb",Mv), TNS("shrb",Mv), TNS("salb",Mv), TNS("sarb",Mv), 2592 }; 2593 /* 2594 * Decode table for 0xD3 opcodes. 2595 */ 2596 2597 const instable_t dis_opD3[8] = { 2598 2599 /* [0] */ TS("rol",Mv), TS("ror",Mv), TS("rcl",Mv), TS("rcr",Mv), 2600 /* [4] */ TS("shl",Mv), TS("shr",Mv), TS("salb",Mv), TS("sar",Mv), 2601 }; 2602 2603 2604 /* 2605 * Decode table for 0xF6 opcodes. 2606 */ 2607 2608 const instable_t dis_opF6[8] = { 2609 2610 /* [0] */ TNS("testb",IMw), TNS("testb",IMw), TNS("notb",Mw), TNS("negb",Mw), 2611 /* [4] */ TNS("mulb",MA), TNS("imulb",MA), TNS("divb",MA), TNS("idivb",MA), 2612 }; 2613 2614 2615 /* 2616 * Decode table for 0xF7 opcodes. 2617 */ 2618 2619 const instable_t dis_opF7[8] = { 2620 2621 /* [0] */ TS("test",IMw), TS("test",IMw), TS("not",Mw), TS("neg",Mw), 2622 /* [4] */ TS("mul",MA), TS("imul",MA), TS("div",MA), TS("idiv",MA), 2623 }; 2624 2625 2626 /* 2627 * Decode table for 0xFE opcodes. 2628 */ 2629 2630 const instable_t dis_opFE[8] = { 2631 2632 /* [0] */ TNS("incb",Mw), TNS("decb",Mw), INVALID, INVALID, 2633 /* [4] */ INVALID, INVALID, INVALID, INVALID, 2634 }; 2635 /* 2636 * Decode table for 0xFF opcodes. 2637 */ 2638 2639 const instable_t dis_opFF[8] = { 2640 2641 /* [0] */ TS("inc",Mw), TS("dec",Mw), TNSyp("call",INM), TNS("lcall",INM), 2642 /* [4] */ TNSy("jmp",INM), TNS("ljmp",INM), TSp("push",M), INVALID, 2643 }; 2644 2645 /* for 287 instructions, which are a mess to decode */ 2646 2647 const instable_t dis_opFP1n2[8][8] = { 2648 { 2649 /* bit pattern: 1101 1xxx MODxx xR/M */ 2650 /* [0,0] */ TNS("fadds",M), TNS("fmuls",M), TNS("fcoms",M), TNS("fcomps",M), 2651 /* [0,4] */ TNS("fsubs",M), TNS("fsubrs",M), TNS("fdivs",M), TNS("fdivrs",M), 2652 }, { 2653 /* [1,0] */ TNS("flds",M), INVALID, TNS("fsts",M), TNS("fstps",M), 2654 /* [1,4] */ TNSZ("fldenv",M,28), TNSZ("fldcw",M,2), TNSZ("fnstenv",M,28), TNSZ("fnstcw",M,2), 2655 }, { 2656 /* [2,0] */ TNS("fiaddl",M), TNS("fimull",M), TNS("ficoml",M), TNS("ficompl",M), 2657 /* [2,4] */ TNS("fisubl",M), TNS("fisubrl",M), TNS("fidivl",M), TNS("fidivrl",M), 2658 }, { 2659 /* [3,0] */ TNS("fildl",M), TNSZ("tisttpl",M,4), TNS("fistl",M), TNS("fistpl",M), 2660 /* [3,4] */ INVALID, TNSZ("fldt",M,10), INVALID, TNSZ("fstpt",M,10), 2661 }, { 2662 /* [4,0] */ TNSZ("faddl",M,8), TNSZ("fmull",M,8), TNSZ("fcoml",M,8), TNSZ("fcompl",M,8), 2663 /* [4,1] */ TNSZ("fsubl",M,8), TNSZ("fsubrl",M,8), TNSZ("fdivl",M,8), TNSZ("fdivrl",M,8), 2664 }, { 2665 /* [5,0] */ TNSZ("fldl",M,8), TNSZ("fisttpll",M,8), TNSZ("fstl",M,8), TNSZ("fstpl",M,8), 2666 /* [5,4] */ TNSZ("frstor",M,108), INVALID, TNSZ("fnsave",M,108), TNSZ("fnstsw",M,2), 2667 }, { 2668 /* [6,0] */ TNSZ("fiadd",M,2), TNSZ("fimul",M,2), TNSZ("ficom",M,2), TNSZ("ficomp",M,2), 2669 /* [6,4] */ TNSZ("fisub",M,2), TNSZ("fisubr",M,2), TNSZ("fidiv",M,2), TNSZ("fidivr",M,2), 2670 }, { 2671 /* [7,0] */ TNSZ("fild",M,2), TNSZ("fisttp",M,2), TNSZ("fist",M,2), TNSZ("fistp",M,2), 2672 /* [7,4] */ TNSZ("fbld",M,10), TNSZ("fildll",M,8), TNSZ("fbstp",M,10), TNSZ("fistpll",M,8), 2673 } }; 2674 2675 const instable_t dis_opFP3[8][8] = { 2676 { 2677 /* bit pattern: 1101 1xxx 11xx xREG */ 2678 /* [0,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2679 /* [0,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2680 }, { 2681 /* [1,0] */ TNS("fld",F), TNS("fxch",F), TNS("fnop",NORM), TNS("fstp",F), 2682 /* [1,4] */ INVALID, INVALID, INVALID, INVALID, 2683 }, { 2684 /* [2,0] */ INVALID, INVALID, INVALID, INVALID, 2685 /* [2,4] */ INVALID, TNS("fucompp",NORM), INVALID, INVALID, 2686 }, { 2687 /* [3,0] */ INVALID, INVALID, INVALID, INVALID, 2688 /* [3,4] */ INVALID, INVALID, INVALID, INVALID, 2689 }, { 2690 /* [4,0] */ TNS("fadd",FF), TNS("fmul",FF), TNS("fcom",F), TNS("fcomp",F), 2691 /* [4,4] */ TNS("fsub",FF), TNS("fsubr",FF), TNS("fdiv",FF), TNS("fdivr",FF), 2692 }, { 2693 /* [5,0] */ TNS("ffree",F), TNS("fxch",F), TNS("fst",F), TNS("fstp",F), 2694 /* [5,4] */ TNS("fucom",F), TNS("fucomp",F), INVALID, INVALID, 2695 }, { 2696 /* [6,0] */ TNS("faddp",FF), TNS("fmulp",FF), TNS("fcomp",F), TNS("fcompp",NORM), 2697 /* [6,4] */ TNS("fsubp",FF), TNS("fsubrp",FF), TNS("fdivp",FF), TNS("fdivrp",FF), 2698 }, { 2699 /* [7,0] */ TNS("ffreep",F), TNS("fxch",F), TNS("fstp",F), TNS("fstp",F), 2700 /* [7,4] */ TNS("fnstsw",M), TNS("fucomip",FFC), TNS("fcomip",FFC), INVALID, 2701 } }; 2702 2703 const instable_t dis_opFP4[4][8] = { 2704 { 2705 /* bit pattern: 1101 1001 111x xxxx */ 2706 /* [0,0] */ TNS("fchs",NORM), TNS("fabs",NORM), INVALID, INVALID, 2707 /* [0,4] */ TNS("ftst",NORM), TNS("fxam",NORM), TNS("ftstp",NORM), INVALID, 2708 }, { 2709 /* [1,0] */ TNS("fld1",NORM), TNS("fldl2t",NORM), TNS("fldl2e",NORM), TNS("fldpi",NORM), 2710 /* [1,4] */ TNS("fldlg2",NORM), TNS("fldln2",NORM), TNS("fldz",NORM), INVALID, 2711 }, { 2712 /* [2,0] */ TNS("f2xm1",NORM), TNS("fyl2x",NORM), TNS("fptan",NORM), TNS("fpatan",NORM), 2713 /* [2,4] */ TNS("fxtract",NORM), TNS("fprem1",NORM), TNS("fdecstp",NORM), TNS("fincstp",NORM), 2714 }, { 2715 /* [3,0] */ TNS("fprem",NORM), TNS("fyl2xp1",NORM), TNS("fsqrt",NORM), TNS("fsincos",NORM), 2716 /* [3,4] */ TNS("frndint",NORM), TNS("fscale",NORM), TNS("fsin",NORM), TNS("fcos",NORM), 2717 } }; 2718 2719 const instable_t dis_opFP5[8] = { 2720 /* bit pattern: 1101 1011 111x xxxx */ 2721 /* [0] */ TNS("feni",NORM), TNS("fdisi",NORM), TNS("fnclex",NORM), TNS("fninit",NORM), 2722 /* [4] */ TNS("fsetpm",NORM), TNS("frstpm",NORM), INVALID, INVALID, 2723 }; 2724 2725 const instable_t dis_opFP6[8] = { 2726 /* bit pattern: 1101 1011 11yy yxxx */ 2727 /* [00] */ TNS("fcmov.nb",FF), TNS("fcmov.ne",FF), TNS("fcmov.nbe",FF), TNS("fcmov.nu",FF), 2728 /* [04] */ INVALID, TNS("fucomi",F), TNS("fcomi",F), INVALID, 2729 }; 2730 2731 const instable_t dis_opFP7[8] = { 2732 /* bit pattern: 1101 1010 11yy yxxx */ 2733 /* [00] */ TNS("fcmov.b",FF), TNS("fcmov.e",FF), TNS("fcmov.be",FF), TNS("fcmov.u",FF), 2734 /* [04] */ INVALID, INVALID, INVALID, INVALID, 2735 }; 2736 2737 /* 2738 * Main decode table for the op codes. The first two nibbles 2739 * will be used as an index into the table. If there is a 2740 * a need to further decode an instruction, the array to be 2741 * referenced is indicated with the other two entries being 2742 * empty. 2743 */ 2744 2745 const instable_t dis_distable[16][16] = { 2746 { 2747 /* [0,0] */ TNS("addb",RMw), TS("add",RMw), TNS("addb",MRw), TS("add",MRw), 2748 /* [0,4] */ TNS("addb",IA), TS("add",IA), TSx("push",SEG), TSx("pop",SEG), 2749 /* [0,8] */ TNS("orb",RMw), TS("or",RMw), TNS("orb",MRw), TS("or",MRw), 2750 /* [0,C] */ TNS("orb",IA), TS("or",IA), TSx("push",SEG), IND(dis_op0F), 2751 }, { 2752 /* [1,0] */ TNS("adcb",RMw), TS("adc",RMw), TNS("adcb",MRw), TS("adc",MRw), 2753 /* [1,4] */ TNS("adcb",IA), TS("adc",IA), TSx("push",SEG), TSx("pop",SEG), 2754 /* [1,8] */ TNS("sbbb",RMw), TS("sbb",RMw), TNS("sbbb",MRw), TS("sbb",MRw), 2755 /* [1,C] */ TNS("sbbb",IA), TS("sbb",IA), TSx("push",SEG), TSx("pop",SEG), 2756 }, { 2757 /* [2,0] */ TNS("andb",RMw), TS("and",RMw), TNS("andb",MRw), TS("and",MRw), 2758 /* [2,4] */ TNS("andb",IA), TS("and",IA), TNSx("%es:",OVERRIDE), TNSx("daa",NORM), 2759 /* [2,8] */ TNS("subb",RMw), TS("sub",RMw), TNS("subb",MRw), TS("sub",MRw), 2760 /* [2,C] */ TNS("subb",IA), TS("sub",IA), TNS("%cs:",OVERRIDE), TNSx("das",NORM), 2761 }, { 2762 /* [3,0] */ TNS("xorb",RMw), TS("xor",RMw), TNS("xorb",MRw), TS("xor",MRw), 2763 /* [3,4] */ TNS("xorb",IA), TS("xor",IA), TNSx("%ss:",OVERRIDE), TNSx("aaa",NORM), 2764 /* [3,8] */ TNS("cmpb",RMw), TS("cmp",RMw), TNS("cmpb",MRw), TS("cmp",MRw), 2765 /* [3,C] */ TNS("cmpb",IA), TS("cmp",IA), TNSx("%ds:",OVERRIDE), TNSx("aas",NORM), 2766 }, { 2767 /* [4,0] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2768 /* [4,4] */ TSx("inc",R), TSx("inc",R), TSx("inc",R), TSx("inc",R), 2769 /* [4,8] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2770 /* [4,C] */ TSx("dec",R), TSx("dec",R), TSx("dec",R), TSx("dec",R), 2771 }, { 2772 /* [5,0] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2773 /* [5,4] */ TSp("push",R), TSp("push",R), TSp("push",R), TSp("push",R), 2774 /* [5,8] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2775 /* [5,C] */ TSp("pop",R), TSp("pop",R), TSp("pop",R), TSp("pop",R), 2776 }, { 2777 /* [6,0] */ TSZx("pusha",IMPLMEM,28),TSZx("popa",IMPLMEM,28), TSx("bound",RM), TNS("arpl",RMw), 2778 /* [6,4] */ TNS("%fs:",OVERRIDE), TNS("%gs:",OVERRIDE), TNS("data16",DM), TNS("addr16",AM), 2779 /* [6,8] */ TSp("push",I), TS("imul",IMUL), TSp("push",Ib), TS("imul",IMUL), 2780 /* [6,C] */ TNSZ("insb",IMPLMEM,1), TSZ("ins",IMPLMEM,4), TNSZ("outsb",IMPLMEM,1),TSZ("outs",IMPLMEM,4), 2781 }, { 2782 /* [7,0] */ TNSy("jo",BD), TNSy("jno",BD), TNSy("jb",BD), TNSy("jae",BD), 2783 /* [7,4] */ TNSy("je",BD), TNSy("jne",BD), TNSy("jbe",BD), TNSy("ja",BD), 2784 /* [7,8] */ TNSy("js",BD), TNSy("jns",BD), TNSy("jp",BD), TNSy("jnp",BD), 2785 /* [7,C] */ TNSy("jl",BD), TNSy("jge",BD), TNSy("jle",BD), TNSy("jg",BD), 2786 }, { 2787 /* [8,0] */ IND(dis_op80), IND(dis_op81), INDx(dis_op82), IND(dis_op83), 2788 /* [8,4] */ TNS("testb",RMw), TS("test",RMw), TNS("xchgb",RMw), TS("xchg",RMw), 2789 /* [8,8] */ TNS("movb",RMw), TS("mov",RMw), TNS("movb",MRw), TS("mov",MRw), 2790 /* [8,C] */ TNS("movw",SM), TS("lea",MR), TNS("movw",MS), TSp("pop",M), 2791 }, { 2792 /* [9,0] */ TNS("nop",NORM), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2793 /* [9,4] */ TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), TS("xchg",RA), 2794 /* [9,8] */ TNS("cXtX",CBW), TNS("cXtX",CWD), TNSx("lcall",SO), TNS("fwait",NORM), 2795 /* [9,C] */ TSZy("pushf",IMPLMEM,4),TSZy("popf",IMPLMEM,4), TNS("sahf",NORM), TNS("lahf",NORM), 2796 }, { 2797 /* [A,0] */ TNS("movb",OA), TS("mov",OA), TNS("movb",AO), TS("mov",AO), 2798 /* [A,4] */ TNSZ("movsb",SD,1), TS("movs",SD), TNSZ("cmpsb",SD,1), TS("cmps",SD), 2799 /* [A,8] */ TNS("testb",IA), TS("test",IA), TNS("stosb",AD), TS("stos",AD), 2800 /* [A,C] */ TNS("lodsb",SA), TS("lods",SA), TNS("scasb",AD), TS("scas",AD), 2801 }, { 2802 /* [B,0] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2803 /* [B,4] */ TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), TNS("movb",IR), 2804 /* [B,8] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2805 /* [B,C] */ TS("mov",IR), TS("mov",IR), TS("mov",IR), TS("mov",IR), 2806 }, { 2807 /* [C,0] */ IND(dis_opC0), IND(dis_opC1), TNSyp("ret",RET), TNSyp("ret",NORM), 2808 /* [C,4] */ TNSx("les",MR), TNSx("lds",MR), TNS("movb",IMw), TS("mov",IMw), 2809 /* [C,8] */ TNSyp("enter",ENTER), TNSyp("leave",NORM), TNS("lret",RET), TNS("lret",NORM), 2810 /* [C,C] */ TNS("int",INT3), TNS("int",INTx), TNSx("into",NORM), TNS("iret",NORM), 2811 }, { 2812 /* [D,0] */ IND(dis_opD0), IND(dis_opD1), IND(dis_opD2), IND(dis_opD3), 2813 /* [D,4] */ TNSx("aam",U), TNSx("aad",U), TNSx("falc",NORM), TNSZ("xlat",IMPLMEM,1), 2814 2815 /* 287 instructions. Note that although the indirect field */ 2816 /* indicates opFP1n2 for further decoding, this is not necessarily */ 2817 /* the case since the opFP arrays are not partitioned according to key1 */ 2818 /* and key2. opFP1n2 is given only to indicate that we haven't */ 2819 /* finished decoding the instruction. */ 2820 /* [D,8] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2821 /* [D,C] */ IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), IND(dis_opFP1n2), 2822 }, { 2823 /* [E,0] */ TNSy("loopnz",BD), TNSy("loopz",BD), TNSy("loop",BD), TNSy("jcxz",BD), 2824 /* [E,4] */ TNS("inb",P), TS("in",P), TNS("outb",P), TS("out",P), 2825 /* [E,8] */ TNSyp("call",D), TNSy("jmp",D), TNSx("ljmp",SO), TNSy("jmp",BD), 2826 /* [E,C] */ TNS("inb",V), TS("in",V), TNS("outb",V), TS("out",V), 2827 }, { 2828 /* [F,0] */ TNS("lock",LOCK), TNS("icebp", NORM), TNS("repnz",PREFIX), TNS("repz",PREFIX), 2829 /* [F,4] */ TNS("hlt",NORM), TNS("cmc",NORM), IND(dis_opF6), IND(dis_opF7), 2830 /* [F,8] */ TNS("clc",NORM), TNS("stc",NORM), TNS("cli",NORM), TNS("sti",NORM), 2831 /* [F,C] */ TNS("cld",NORM), TNS("std",NORM), IND(dis_opFE), IND(dis_opFF), 2832 } }; 2833 2834 /* END CSTYLED */ 2835 2836 /* 2837 * common functions to decode and disassemble an x86 or amd64 instruction 2838 */ 2839 2840 /* 2841 * These are the individual fields of a REX prefix. Note that a REX 2842 * prefix with none of these set is still needed to: 2843 * - use the MOVSXD (sign extend 32 to 64 bits) instruction 2844 * - access the %sil, %dil, %bpl, %spl registers 2845 */ 2846 #define REX_W 0x08 /* 64 bit operand size when set */ 2847 #define REX_R 0x04 /* high order bit extension of ModRM reg field */ 2848 #define REX_X 0x02 /* high order bit extension of SIB index field */ 2849 #define REX_B 0x01 /* extends ModRM r_m, SIB base, or opcode reg */ 2850 2851 /* 2852 * These are the individual fields of a VEX/EVEX prefix. 2853 */ 2854 #define VEX_R 0x08 /* REX.R in 1's complement form */ 2855 #define VEX_X 0x04 /* REX.X in 1's complement form */ 2856 #define VEX_B 0x02 /* REX.B in 1's complement form */ 2857 2858 /* Additional EVEX prefix definitions */ 2859 #define EVEX_R 0x01 /* REX.R' in 1's complement form */ 2860 #define EVEX_OPREG_MASK 0x7 /* bit mask for selecting opmask register number */ 2861 #define EVEX_ZERO_MASK 0x80 /* bit mask for selecting zeroing */ 2862 2863 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector */ 2864 #define VEX_L 0x04 2865 /* Vector Length, 0: scalar or 128-bit vector, 1: 256-bit vector, 2: 512-bit */ 2866 #define EVEX_L 0x06 /* bit mask for EVEX.L'L vector length/RC */ 2867 #define VEX_W 0x08 /* opcode specific, use like REX.W */ 2868 #define VEX_m 0x1F /* VEX m-mmmm field */ 2869 #define EVEX_m 0x3 /* EVEX mm field */ 2870 #define VEX_v 0x78 /* VEX/EVEX register specifier */ 2871 #define VEX_p 0x03 /* VEX pp field, opcode extension */ 2872 2873 /* VEX m-mmmm field, only used by three bytes prefix */ 2874 #define VEX_m_0F 0x01 /* implied 0F leading opcode byte */ 2875 #define VEX_m_0F38 0x02 /* implied 0F 38 leading opcode byte */ 2876 #define VEX_m_0F3A 0x03 /* implied 0F 3A leading opcode byte */ 2877 2878 /* VEX pp field, providing equivalent functionality of a SIMD prefix */ 2879 #define VEX_p_66 0x01 2880 #define VEX_p_F3 0x02 2881 #define VEX_p_F2 0x03 2882 2883 /* 2884 * Even in 64 bit mode, usually only 4 byte immediate operands are supported. 2885 */ 2886 static int isize[] = {1, 2, 4, 4}; 2887 static int isize64[] = {1, 2, 4, 8}; 2888 2889 /* 2890 * Just a bunch of useful macros. 2891 */ 2892 #define WBIT(x) (x & 0x1) /* to get w bit */ 2893 #define REGNO(x) (x & 0x7) /* to get 3 bit register */ 2894 #define VBIT(x) ((x)>>1 & 0x1) /* to get 'v' bit */ 2895 #define OPSIZE(osize, wbit) ((wbit) ? isize[osize] : 1) 2896 #define OPSIZE64(osize, wbit) ((wbit) ? isize64[osize] : 1) 2897 2898 #define REG_ONLY 3 /* mode to indicate a register operand (not memory) */ 2899 2900 #define BYTE_OPND 0 /* w-bit value indicating byte register */ 2901 #define LONG_OPND 1 /* w-bit value indicating opnd_size register */ 2902 #define MM_OPND 2 /* "value" used to indicate a mmx reg */ 2903 #define XMM_OPND 3 /* "value" used to indicate a xmm reg */ 2904 #define SEG_OPND 4 /* "value" used to indicate a segment reg */ 2905 #define CONTROL_OPND 5 /* "value" used to indicate a control reg */ 2906 #define DEBUG_OPND 6 /* "value" used to indicate a debug reg */ 2907 #define TEST_OPND 7 /* "value" used to indicate a test reg */ 2908 #define WORD_OPND 8 /* w-bit value indicating word size reg */ 2909 #define YMM_OPND 9 /* "value" used to indicate a ymm reg */ 2910 #define KOPMASK_OPND 10 /* "value" used to indicate an opmask reg */ 2911 #define ZMM_OPND 11 /* "value" used to indicate a zmm reg */ 2912 2913 /* 2914 * The AVX2 gather instructions are a bit of a mess. While there's a pattern, 2915 * there's not really a consistent scheme that we can use to know what the mode 2916 * is supposed to be for a given type. Various instructions, like VPGATHERDD, 2917 * always match the value of VEX_L. Other instructions like VPGATHERDQ, have 2918 * some registers match VEX_L, but the VSIB is always XMM. 2919 * 2920 * The simplest way to deal with this is to just define a table based on the 2921 * instruction opcodes, which are 0x90-0x93, so we subtract 0x90 to index into 2922 * them. 2923 * 2924 * We further have to subdivide this based on the value of VEX_W and the value 2925 * of VEX_L. The array is constructed to be indexed as: 2926 * [opcode - 0x90][VEX_W][VEX_L]. 2927 */ 2928 /* w = 0, 0x90 */ 2929 typedef struct dis_gather_regs { 2930 uint_t dgr_arg0; /* src reg */ 2931 uint_t dgr_arg1; /* vsib reg */ 2932 uint_t dgr_arg2; /* dst reg */ 2933 char *dgr_suffix; /* suffix to append */ 2934 } dis_gather_regs_t; 2935 2936 static dis_gather_regs_t dis_vgather[4][2][2] = { 2937 { 2938 /* op 0x90, W.0 */ 2939 { 2940 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2941 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2942 }, 2943 /* op 0x90, W.1 */ 2944 { 2945 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2946 { YMM_OPND, XMM_OPND, YMM_OPND, "q" } 2947 } 2948 }, 2949 { 2950 /* op 0x91, W.0 */ 2951 { 2952 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2953 { XMM_OPND, YMM_OPND, XMM_OPND, "d" }, 2954 }, 2955 /* op 0x91, W.1 */ 2956 { 2957 { XMM_OPND, XMM_OPND, XMM_OPND, "q" }, 2958 { YMM_OPND, YMM_OPND, YMM_OPND, "q" }, 2959 } 2960 }, 2961 { 2962 /* op 0x92, W.0 */ 2963 { 2964 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2965 { YMM_OPND, YMM_OPND, YMM_OPND, "s" } 2966 }, 2967 /* op 0x92, W.1 */ 2968 { 2969 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2970 { YMM_OPND, XMM_OPND, YMM_OPND, "d" } 2971 } 2972 }, 2973 { 2974 /* op 0x93, W.0 */ 2975 { 2976 { XMM_OPND, XMM_OPND, XMM_OPND, "s" }, 2977 { XMM_OPND, YMM_OPND, XMM_OPND, "s" } 2978 }, 2979 /* op 0x93, W.1 */ 2980 { 2981 { XMM_OPND, XMM_OPND, XMM_OPND, "d" }, 2982 { YMM_OPND, YMM_OPND, YMM_OPND, "d" } 2983 } 2984 } 2985 }; 2986 2987 /* 2988 * Get the next byte and separate the op code into the high and low nibbles. 2989 */ 2990 static int 2991 dtrace_get_opcode(dis86_t *x, uint_t *high, uint_t *low) 2992 { 2993 int byte; 2994 2995 /* 2996 * x86 instructions have a maximum length of 15 bytes. Bail out if 2997 * we try to read more. 2998 */ 2999 if (x->d86_len >= 15) 3000 return (x->d86_error = 1); 3001 3002 if (x->d86_error) 3003 return (1); 3004 byte = x->d86_get_byte(x->d86_data); 3005 if (byte < 0) 3006 return (x->d86_error = 1); 3007 x->d86_bytes[x->d86_len++] = byte; 3008 *low = byte & 0xf; /* ----xxxx low 4 bits */ 3009 *high = byte >> 4 & 0xf; /* xxxx---- bits 7 to 4 */ 3010 return (0); 3011 } 3012 3013 /* 3014 * Get and decode an SIB (scaled index base) byte 3015 */ 3016 static void 3017 dtrace_get_SIB(dis86_t *x, uint_t *ss, uint_t *index, uint_t *base) 3018 { 3019 int byte; 3020 3021 if (x->d86_error) 3022 return; 3023 3024 byte = x->d86_get_byte(x->d86_data); 3025 if (byte < 0) { 3026 x->d86_error = 1; 3027 return; 3028 } 3029 x->d86_bytes[x->d86_len++] = byte; 3030 3031 *base = byte & 0x7; 3032 *index = (byte >> 3) & 0x7; 3033 *ss = (byte >> 6) & 0x3; 3034 } 3035 3036 /* 3037 * Get the byte following the op code and separate it into the 3038 * mode, register, and r/m fields. 3039 */ 3040 static void 3041 dtrace_get_modrm(dis86_t *x, uint_t *mode, uint_t *reg, uint_t *r_m) 3042 { 3043 if (x->d86_got_modrm == 0) { 3044 if (x->d86_rmindex == -1) 3045 x->d86_rmindex = x->d86_len; 3046 dtrace_get_SIB(x, mode, reg, r_m); 3047 x->d86_got_modrm = 1; 3048 } 3049 } 3050 3051 /* 3052 * Adjust register selection based on any REX prefix bits present. 3053 */ 3054 /*ARGSUSED*/ 3055 static void 3056 dtrace_rex_adjust(uint_t rex_prefix, uint_t mode, uint_t *reg, uint_t *r_m) 3057 { 3058 if (reg != NULL && r_m == NULL) { 3059 if (rex_prefix & REX_B) 3060 *reg += 8; 3061 } else { 3062 if (reg != NULL && (REX_R & rex_prefix) != 0) 3063 *reg += 8; 3064 if (r_m != NULL && (REX_B & rex_prefix) != 0) 3065 *r_m += 8; 3066 } 3067 } 3068 3069 /* 3070 * Adjust register selection based on any VEX prefix bits present. 3071 * Notes: VEX.R, VEX.X and VEX.B use the inverted form compared with REX prefix 3072 */ 3073 /*ARGSUSED*/ 3074 static void 3075 dtrace_vex_adjust(uint_t vex_byte1, uint_t mode, uint_t *reg, uint_t *r_m) 3076 { 3077 if (reg != NULL && r_m == NULL) { 3078 if (!(vex_byte1 & VEX_B)) 3079 *reg += 8; 3080 } else { 3081 if (reg != NULL && ((VEX_R & vex_byte1) == 0)) 3082 *reg += 8; 3083 if (r_m != NULL && ((VEX_B & vex_byte1) == 0)) 3084 *r_m += 8; 3085 } 3086 } 3087 3088 /* 3089 * Adjust the instruction mnemonic with the appropriate suffix. 3090 */ 3091 /* ARGSUSED */ 3092 static void 3093 dtrace_evex_mnem_adjust(dis86_t *x, const instable_t *dp, uint_t vex_W, 3094 uint_t evex_byte2) 3095 { 3096 #ifdef DIS_TEXT 3097 if (dp == &dis_opEVEX660F[0x7f] || /* vmovdqa */ 3098 dp == &dis_opEVEX660F[0x6f]) { 3099 (void) strlcat(x->d86_mnem, vex_W != 0 ? "64" : "32", 3100 OPLEN); 3101 } 3102 3103 if (dp == &dis_opEVEXF20F[0x7f] || /* vmovdqu */ 3104 dp == &dis_opEVEXF20F[0x6f] || 3105 dp == &dis_opEVEXF30F[0x7f] || 3106 dp == &dis_opEVEXF30F[0x6f]) { 3107 switch (evex_byte2 & 0x81) { 3108 case 0x0: 3109 (void) strlcat(x->d86_mnem, "32", OPLEN); 3110 break; 3111 case 0x1: 3112 (void) strlcat(x->d86_mnem, "8", OPLEN); 3113 break; 3114 case 0x80: 3115 (void) strlcat(x->d86_mnem, "64", OPLEN); 3116 break; 3117 case 0x81: 3118 (void) strlcat(x->d86_mnem, "16", OPLEN); 3119 break; 3120 } 3121 } 3122 3123 if (dp->it_avxsuf == AVS5Q) { 3124 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 3125 OPLEN); 3126 } 3127 #endif 3128 } 3129 3130 /* 3131 * The following three functions adjust the register selection based on any 3132 * EVEX prefix bits present. See Intel 64 and IA-32 Architectures Software 3133 * Developer’s Manual Volume 2 (IASDv2), section 2.6.1 Table 2-30 and 3134 * section 2.6.2 Table 2-31. 3135 */ 3136 static void 3137 dtrace_evex_adjust_reg(uint_t evex_byte1, uint_t *reg) 3138 { 3139 if (reg != NULL) { 3140 if ((VEX_R & evex_byte1) == 0) { 3141 *reg += 8; 3142 } 3143 if ((EVEX_R & evex_byte1) == 0) { 3144 *reg += 16; 3145 } 3146 } 3147 } 3148 3149 static void 3150 dtrace_evex_adjust_rm(uint_t evex_byte1, uint_t *r_m) 3151 { 3152 if (r_m != NULL) { 3153 if ((VEX_B & evex_byte1) == 0) { 3154 *r_m += 8; 3155 } 3156 if ((VEX_X & evex_byte1) == 0) { 3157 *r_m += 16; 3158 } 3159 } 3160 } 3161 3162 /* 3163 * Use evex_L to set wbit. See IASDv2 Section 2.6.10 and Table 2-36. 3164 */ 3165 static void 3166 dtrace_evex_adjust_reg_name(uint_t evex_L, uint_t *wbitp) 3167 { 3168 switch (evex_L) { 3169 case 0x0: 3170 *wbitp = XMM_OPND; 3171 break; 3172 case 0x1: 3173 *wbitp = YMM_OPND; 3174 break; 3175 case 0x2: 3176 *wbitp = ZMM_OPND; 3177 break; 3178 } 3179 } 3180 3181 /* 3182 * Adjust operand value for disp8*N immediate. See IASDv2 Section 2.6.5. 3183 * This currently only handles a subset of the possibilities. 3184 */ 3185 static void 3186 dtrace_evex_adjust_disp8_n(dis86_t *x, int opindex, uint_t L, uint_t modrm) 3187 { 3188 d86opnd_t *opnd = &x->d86_opnd[opindex]; 3189 3190 if (x->d86_error) 3191 return; 3192 3193 /* Check disp8 bit in the ModR/M byte */ 3194 if ((modrm & 0x80) == 0x80) 3195 return; 3196 3197 /* use evex_L to adjust the value */ 3198 switch (L) { 3199 case 0x0: 3200 opnd->d86_value *= 16; 3201 break; 3202 case 0x1: 3203 opnd->d86_value *= 32; 3204 break; 3205 case 0x2: 3206 opnd->d86_value *= 64; 3207 break; 3208 } 3209 } 3210 3211 /* 3212 * Adjust target for opmask and zeroing. See IASDv2 Section 2.6.1 Table 2-30. 3213 */ 3214 /* ARGSUSED */ 3215 static void 3216 dtrace_evex_adjust_z_opmask(dis86_t *x, uint_t tgtop, uint_t evex_byte3) 3217 { 3218 #ifdef DIS_TEXT 3219 char *opnd = x->d86_opnd[tgtop].d86_opnd; 3220 int opmask_reg = evex_byte3 & EVEX_OPREG_MASK; 3221 #endif 3222 if (x->d86_error) 3223 return; 3224 3225 #ifdef DIS_TEXT 3226 if (opmask_reg != 0) { 3227 /* Append the opmask register to operand 1 */ 3228 (void) strlcat(opnd, "{", OPLEN); 3229 (void) strlcat(opnd, dis_KOPMASKREG[opmask_reg], OPLEN); 3230 (void) strlcat(opnd, "}", OPLEN); 3231 } 3232 if ((evex_byte3 & EVEX_ZERO_MASK) != 0) { 3233 /* Append the 'zeroing' modifier to operand 1 */ 3234 (void) strlcat(opnd, "{z}", OPLEN); 3235 } 3236 #endif /* DIS_TEXT */ 3237 } 3238 3239 /* 3240 * Get an immediate operand of the given size, with sign extension. 3241 */ 3242 static void 3243 dtrace_imm_opnd(dis86_t *x, int wbit, int size, int opindex) 3244 { 3245 int i; 3246 int byte; 3247 int valsize; 3248 3249 if (x->d86_numopnds < opindex + 1) 3250 x->d86_numopnds = opindex + 1; 3251 3252 switch (wbit) { 3253 case BYTE_OPND: 3254 valsize = 1; 3255 break; 3256 case LONG_OPND: 3257 if (x->d86_opnd_size == SIZE16) 3258 valsize = 2; 3259 else if (x->d86_opnd_size == SIZE32) 3260 valsize = 4; 3261 else 3262 valsize = 8; 3263 break; 3264 case MM_OPND: 3265 case XMM_OPND: 3266 case YMM_OPND: 3267 case ZMM_OPND: 3268 case SEG_OPND: 3269 case CONTROL_OPND: 3270 case DEBUG_OPND: 3271 case TEST_OPND: 3272 valsize = size; 3273 break; 3274 case WORD_OPND: 3275 valsize = 2; 3276 break; 3277 } 3278 if (valsize < size) 3279 valsize = size; 3280 3281 if (x->d86_error) 3282 return; 3283 x->d86_opnd[opindex].d86_value = 0; 3284 for (i = 0; i < size; ++i) { 3285 byte = x->d86_get_byte(x->d86_data); 3286 if (byte < 0) { 3287 x->d86_error = 1; 3288 return; 3289 } 3290 x->d86_bytes[x->d86_len++] = byte; 3291 x->d86_opnd[opindex].d86_value |= (uint64_t)byte << (i * 8); 3292 } 3293 /* Do sign extension */ 3294 if (x->d86_bytes[x->d86_len - 1] & 0x80) { 3295 for (; i < sizeof (uint64_t); i++) 3296 x->d86_opnd[opindex].d86_value |= 3297 (uint64_t)0xff << (i * 8); 3298 } 3299 #ifdef DIS_TEXT 3300 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3301 x->d86_opnd[opindex].d86_value_size = valsize; 3302 x->d86_imm_bytes += size; 3303 #endif 3304 } 3305 3306 /* 3307 * Get an ip relative operand of the given size, with sign extension. 3308 */ 3309 static void 3310 dtrace_disp_opnd(dis86_t *x, int wbit, int size, int opindex) 3311 { 3312 dtrace_imm_opnd(x, wbit, size, opindex); 3313 #ifdef DIS_TEXT 3314 x->d86_opnd[opindex].d86_mode = MODE_IPREL; 3315 #endif 3316 } 3317 3318 /* 3319 * Check to see if there is a segment override prefix pending. 3320 * If so, print it in the current 'operand' location and set 3321 * the override flag back to false. 3322 */ 3323 /*ARGSUSED*/ 3324 static void 3325 dtrace_check_override(dis86_t *x, int opindex) 3326 { 3327 #ifdef DIS_TEXT 3328 if (x->d86_seg_prefix) { 3329 (void) strlcat(x->d86_opnd[opindex].d86_prefix, 3330 x->d86_seg_prefix, PFIXLEN); 3331 } 3332 #endif 3333 x->d86_seg_prefix = NULL; 3334 } 3335 3336 3337 /* 3338 * Process a single instruction Register or Memory operand. 3339 * 3340 * mode = addressing mode from ModRM byte 3341 * r_m = r_m (or reg if mode == 3) field from ModRM byte 3342 * wbit = indicates which register (8bit, 16bit, ... MMX, etc.) set to use. 3343 * o = index of operand that we are processing (0, 1 or 2) 3344 * 3345 * the value of reg or r_m must have already been adjusted for any REX prefix. 3346 */ 3347 /*ARGSUSED*/ 3348 static void 3349 dtrace_get_operand(dis86_t *x, uint_t mode, uint_t r_m, int wbit, int opindex) 3350 { 3351 int have_SIB = 0; /* flag presence of scale-index-byte */ 3352 uint_t ss; /* scale-factor from opcode */ 3353 uint_t index; /* index register number */ 3354 uint_t base; /* base register number */ 3355 int dispsize; /* size of displacement in bytes */ 3356 #ifdef DIS_TEXT 3357 char *opnd = x->d86_opnd[opindex].d86_opnd; 3358 #endif 3359 3360 if (x->d86_numopnds < opindex + 1) 3361 x->d86_numopnds = opindex + 1; 3362 3363 if (x->d86_error) 3364 return; 3365 3366 /* 3367 * first handle a simple register 3368 */ 3369 if (mode == REG_ONLY) { 3370 #ifdef DIS_TEXT 3371 switch (wbit) { 3372 case MM_OPND: 3373 (void) strlcat(opnd, dis_MMREG[r_m], OPLEN); 3374 break; 3375 case XMM_OPND: 3376 (void) strlcat(opnd, dis_XMMREG[r_m], OPLEN); 3377 break; 3378 case YMM_OPND: 3379 (void) strlcat(opnd, dis_YMMREG[r_m], OPLEN); 3380 break; 3381 case ZMM_OPND: 3382 (void) strlcat(opnd, dis_ZMMREG[r_m], OPLEN); 3383 break; 3384 case KOPMASK_OPND: 3385 (void) strlcat(opnd, dis_KOPMASKREG[r_m], OPLEN); 3386 break; 3387 case SEG_OPND: 3388 (void) strlcat(opnd, dis_SEGREG[r_m], OPLEN); 3389 break; 3390 case CONTROL_OPND: 3391 (void) strlcat(opnd, dis_CONTROLREG[r_m], OPLEN); 3392 break; 3393 case DEBUG_OPND: 3394 (void) strlcat(opnd, dis_DEBUGREG[r_m], OPLEN); 3395 break; 3396 case TEST_OPND: 3397 (void) strlcat(opnd, dis_TESTREG[r_m], OPLEN); 3398 break; 3399 case BYTE_OPND: 3400 if (x->d86_rex_prefix == 0) 3401 (void) strlcat(opnd, dis_REG8[r_m], OPLEN); 3402 else 3403 (void) strlcat(opnd, dis_REG8_REX[r_m], OPLEN); 3404 break; 3405 case WORD_OPND: 3406 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 3407 break; 3408 case LONG_OPND: 3409 if (x->d86_opnd_size == SIZE16) 3410 (void) strlcat(opnd, dis_REG16[r_m], OPLEN); 3411 else if (x->d86_opnd_size == SIZE32) 3412 (void) strlcat(opnd, dis_REG32[r_m], OPLEN); 3413 else 3414 (void) strlcat(opnd, dis_REG64[r_m], OPLEN); 3415 break; 3416 } 3417 #endif /* DIS_TEXT */ 3418 return; 3419 } 3420 3421 /* 3422 * if symbolic representation, skip override prefix, if any 3423 */ 3424 dtrace_check_override(x, opindex); 3425 3426 /* 3427 * Handle 16 bit memory references first, since they decode 3428 * the mode values more simply. 3429 * mode 1 is r_m + 8 bit displacement 3430 * mode 2 is r_m + 16 bit displacement 3431 * mode 0 is just r_m, unless r_m is 6 which is 16 bit disp 3432 */ 3433 if (x->d86_addr_size == SIZE16) { 3434 if ((mode == 0 && r_m == 6) || mode == 2) 3435 dtrace_imm_opnd(x, WORD_OPND, 2, opindex); 3436 else if (mode == 1) 3437 dtrace_imm_opnd(x, BYTE_OPND, 1, opindex); 3438 #ifdef DIS_TEXT 3439 if (mode == 0 && r_m == 6) 3440 x->d86_opnd[opindex].d86_mode = MODE_SIGNED; 3441 else if (mode == 0) 3442 x->d86_opnd[opindex].d86_mode = MODE_NONE; 3443 else 3444 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3445 (void) strlcat(opnd, dis_addr16[mode][r_m], OPLEN); 3446 #endif 3447 return; 3448 } 3449 3450 /* 3451 * 32 and 64 bit addressing modes are more complex since they can 3452 * involve an SIB (scaled index and base) byte to decode. When using VEX 3453 * and EVEX encodings, the r_m indicator for a SIB may be offset by 8 3454 * and 24 (8 + 16) respectively. 3455 */ 3456 if (r_m == ESP_REGNO || r_m == ESP_REGNO + 8 || r_m == ESP_REGNO + 24) { 3457 have_SIB = 1; 3458 dtrace_get_SIB(x, &ss, &index, &base); 3459 if (x->d86_error) 3460 return; 3461 if (base != 5 || mode != 0) 3462 if (x->d86_rex_prefix & REX_B) 3463 base += 8; 3464 if (x->d86_rex_prefix & REX_X) 3465 index += 8; 3466 } else { 3467 base = r_m; 3468 } 3469 3470 /* 3471 * Compute the displacement size and get its bytes 3472 */ 3473 dispsize = 0; 3474 3475 if (mode == 1) 3476 dispsize = 1; 3477 else if (mode == 2) 3478 dispsize = 4; 3479 else if ((r_m & 7) == EBP_REGNO || 3480 (have_SIB && (base & 7) == EBP_REGNO)) 3481 dispsize = 4; 3482 3483 if (dispsize > 0) { 3484 dtrace_imm_opnd(x, dispsize == 4 ? LONG_OPND : BYTE_OPND, 3485 dispsize, opindex); 3486 if (x->d86_error) 3487 return; 3488 } 3489 3490 #ifdef DIS_TEXT 3491 if (dispsize > 0) 3492 x->d86_opnd[opindex].d86_mode = MODE_OFFSET; 3493 3494 if (have_SIB == 0) { 3495 if (x->d86_mode == SIZE32) { 3496 if (mode == 0) 3497 (void) strlcat(opnd, dis_addr32_mode0[r_m], 3498 OPLEN); 3499 else 3500 (void) strlcat(opnd, dis_addr32_mode12[r_m], 3501 OPLEN); 3502 } else { 3503 if (mode == 0) { 3504 (void) strlcat(opnd, dis_addr64_mode0[r_m], 3505 OPLEN); 3506 if (r_m == 5) { 3507 x->d86_opnd[opindex].d86_mode = 3508 MODE_RIPREL; 3509 } 3510 } else { 3511 (void) strlcat(opnd, dis_addr64_mode12[r_m], 3512 OPLEN); 3513 } 3514 } 3515 } else { 3516 uint_t need_paren = 0; 3517 char **regs; 3518 char **bregs; 3519 const char *const *sf; 3520 if (x->d86_mode == SIZE32) /* NOTE this is not addr_size! */ 3521 regs = (char **)dis_REG32; 3522 else 3523 regs = (char **)dis_REG64; 3524 3525 if (x->d86_vsib != 0) { 3526 if (wbit == YMM_OPND) { /* NOTE this is not addr_size */ 3527 bregs = (char **)dis_YMMREG; 3528 } else if (wbit == XMM_OPND) { 3529 bregs = (char **)dis_XMMREG; 3530 } else { 3531 bregs = (char **)dis_ZMMREG; 3532 } 3533 sf = dis_vscale_factor; 3534 } else { 3535 bregs = regs; 3536 sf = dis_scale_factor; 3537 } 3538 3539 /* 3540 * print the base (if any) 3541 */ 3542 if (base == EBP_REGNO && mode == 0) { 3543 if (index != ESP_REGNO || x->d86_vsib != 0) { 3544 (void) strlcat(opnd, "(", OPLEN); 3545 need_paren = 1; 3546 } 3547 } else { 3548 (void) strlcat(opnd, "(", OPLEN); 3549 (void) strlcat(opnd, regs[base], OPLEN); 3550 need_paren = 1; 3551 } 3552 3553 /* 3554 * print the index (if any) 3555 */ 3556 if (index != ESP_REGNO || x->d86_vsib) { 3557 (void) strlcat(opnd, ",", OPLEN); 3558 (void) strlcat(opnd, bregs[index], OPLEN); 3559 (void) strlcat(opnd, sf[ss], OPLEN); 3560 } else 3561 if (need_paren) 3562 (void) strlcat(opnd, ")", OPLEN); 3563 } 3564 #endif 3565 } 3566 3567 /* 3568 * Operand sequence for standard instruction involving one register 3569 * and one register/memory operand. 3570 * wbit indicates a byte(0) or opnd_size(1) operation 3571 * vbit indicates direction (0 for "opcode r,r_m") or (1 for "opcode r_m, r") 3572 */ 3573 #define STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, vbit) { \ 3574 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3575 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3576 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3577 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1 - vbit); \ 3578 } 3579 3580 /* 3581 * Similar to above, but allows for the two operands to be of different 3582 * classes (ie. wbit). 3583 * wbit is for the r_m operand 3584 * w2 is for the reg operand 3585 */ 3586 #define MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, w2, vbit) { \ 3587 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3588 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3589 dtrace_get_operand(x, mode, r_m, wbit, vbit); \ 3590 dtrace_get_operand(x, REG_ONLY, reg, w2, 1 - vbit); \ 3591 } 3592 3593 /* 3594 * Similar, but for 2 operands plus an immediate. 3595 * vbit indicates direction 3596 * 0 for "opcode imm, r, r_m" or 3597 * 1 for "opcode imm, r_m, r" 3598 */ 3599 #define THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize, vbit) { \ 3600 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3601 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3602 dtrace_get_operand(x, mode, r_m, wbit, 2-vbit); \ 3603 dtrace_get_operand(x, REG_ONLY, reg, w2, 1+vbit); \ 3604 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3605 } 3606 3607 /* 3608 * Similar, but for 2 operands plus two immediates. 3609 */ 3610 #define FOUROPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, immsize) { \ 3611 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3612 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3613 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3614 dtrace_get_operand(x, REG_ONLY, reg, w2, 3); \ 3615 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3616 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3617 } 3618 3619 /* 3620 * 1 operands plus two immediates. 3621 */ 3622 #define ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, wbit, immsize) { \ 3623 dtrace_get_modrm(x, &mode, ®, &r_m); \ 3624 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); \ 3625 dtrace_get_operand(x, mode, r_m, wbit, 2); \ 3626 dtrace_imm_opnd(x, wbit, immsize, 1); \ 3627 dtrace_imm_opnd(x, wbit, immsize, 0); \ 3628 } 3629 3630 /* 3631 * Dissassemble a single x86 or amd64 instruction. 3632 * 3633 * Mode determines the default operating mode (SIZE16, SIZE32 or SIZE64) 3634 * for interpreting instructions. 3635 * 3636 * returns non-zero for bad opcode 3637 */ 3638 int 3639 dtrace_disx86(dis86_t *x, uint_t cpu_mode) 3640 { 3641 const instable_t *dp = NULL; /* decode table being used */ 3642 #ifdef DIS_TEXT 3643 uint_t i; 3644 #endif 3645 #ifdef DIS_MEM 3646 uint_t nomem = 0; 3647 #define NOMEM (nomem = 1) 3648 #else 3649 #define NOMEM /* nothing */ 3650 #endif 3651 uint_t opnd_size; /* SIZE16, SIZE32 or SIZE64 */ 3652 uint_t addr_size; /* SIZE16, SIZE32 or SIZE64 */ 3653 uint_t wbit; /* opcode wbit, 0 is 8 bit, !0 for opnd_size */ 3654 uint_t w2; /* wbit value for second operand */ 3655 uint_t vbit; 3656 uint_t mode = 0; /* mode value from ModRM byte */ 3657 uint_t reg; /* reg value from ModRM byte */ 3658 uint_t r_m; /* r_m value from ModRM byte */ 3659 3660 uint_t opcode1; /* high nibble of 1st byte */ 3661 uint_t opcode2; /* low nibble of 1st byte */ 3662 uint_t opcode3; /* extra opcode bits usually from ModRM byte */ 3663 uint_t opcode4; /* high nibble of 2nd byte */ 3664 uint_t opcode5; /* low nibble of 2nd byte */ 3665 uint_t opcode6; /* high nibble of 3rd byte */ 3666 uint_t opcode7; /* low nibble of 3rd byte */ 3667 uint_t opcode8; /* high nibble of 4th byte */ 3668 uint_t opcode9; /* low nibble of 4th byte */ 3669 uint_t opcode_bytes = 1; 3670 3671 /* 3672 * legacy prefixes come in 5 flavors, you should have only one of each 3673 */ 3674 uint_t opnd_size_prefix = 0; 3675 uint_t addr_size_prefix = 0; 3676 uint_t segment_prefix = 0; 3677 uint_t lock_prefix = 0; 3678 uint_t rep_prefix = 0; 3679 uint_t rex_prefix = 0; /* amd64 register extension prefix */ 3680 3681 /* 3682 * Intel VEX instruction encoding prefix and fields 3683 */ 3684 3685 /* 0xC4 means 3 bytes prefix, 0xC5 means 2 bytes prefix */ 3686 uint_t vex_prefix = 0; 3687 3688 /* 3689 * VEX prefix byte 1, includes vex.r, vex.x and vex.b 3690 * (for 3 bytes prefix) 3691 */ 3692 uint_t vex_byte1 = 0; 3693 3694 /* 3695 * EVEX prefix byte 1 includes vex.r, vex.x, vex.b and evex.r. 3696 */ 3697 uint_t evex_byte1 = 0; 3698 uint_t evex_byte2 = 0; 3699 uint_t evex_byte3 = 0; 3700 3701 /* 3702 * For 32-bit mode, it should prefetch the next byte to 3703 * distinguish between AVX and les/lds 3704 */ 3705 uint_t vex_prefetch = 0; 3706 3707 uint_t vex_m = 0; 3708 uint_t vex_v = 0; 3709 uint_t vex_p = 0; 3710 uint_t vex_R = 1; 3711 uint_t vex_X = 1; 3712 uint_t vex_B = 1; 3713 uint_t vex_W = 0; 3714 uint_t vex_L = 0; 3715 uint_t evex_L = 0; 3716 uint_t evex_modrm = 0; 3717 uint_t evex_prefix = 0; 3718 dis_gather_regs_t *vreg; 3719 3720 #ifdef DIS_TEXT 3721 /* Instruction name for BLS* family of instructions */ 3722 char *blsinstr; 3723 #endif 3724 3725 size_t off; 3726 3727 instable_t dp_mmx; 3728 3729 x->d86_len = 0; 3730 x->d86_rmindex = -1; 3731 x->d86_error = 0; 3732 #ifdef DIS_TEXT 3733 x->d86_numopnds = 0; 3734 x->d86_seg_prefix = NULL; 3735 x->d86_mnem[0] = 0; 3736 for (i = 0; i < 4; ++i) { 3737 x->d86_opnd[i].d86_opnd[0] = 0; 3738 x->d86_opnd[i].d86_prefix[0] = 0; 3739 x->d86_opnd[i].d86_value_size = 0; 3740 x->d86_opnd[i].d86_value = 0; 3741 x->d86_opnd[i].d86_mode = MODE_NONE; 3742 } 3743 #endif 3744 x->d86_rex_prefix = 0; 3745 x->d86_got_modrm = 0; 3746 x->d86_memsize = 0; 3747 x->d86_vsib = 0; 3748 3749 if (cpu_mode == SIZE16) { 3750 opnd_size = SIZE16; 3751 addr_size = SIZE16; 3752 } else if (cpu_mode == SIZE32) { 3753 opnd_size = SIZE32; 3754 addr_size = SIZE32; 3755 } else { 3756 opnd_size = SIZE32; 3757 addr_size = SIZE64; 3758 } 3759 3760 /* 3761 * Get one opcode byte and check for zero padding that follows 3762 * jump tables. 3763 */ 3764 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3765 goto error; 3766 3767 if (opcode1 == 0 && opcode2 == 0 && 3768 x->d86_check_func != NULL && x->d86_check_func(x->d86_data)) { 3769 #ifdef DIS_TEXT 3770 (void) strncpy(x->d86_mnem, ".byte\t0", OPLEN); 3771 #endif 3772 goto done; 3773 } 3774 3775 /* 3776 * Gather up legacy x86 prefix bytes. 3777 */ 3778 for (;;) { 3779 uint_t *which_prefix = NULL; 3780 3781 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3782 3783 switch (dp->it_adrmode) { 3784 case PREFIX: 3785 which_prefix = &rep_prefix; 3786 break; 3787 case LOCK: 3788 which_prefix = &lock_prefix; 3789 break; 3790 case OVERRIDE: 3791 which_prefix = &segment_prefix; 3792 #ifdef DIS_TEXT 3793 x->d86_seg_prefix = (char *)dp->it_name; 3794 #endif 3795 if (dp->it_invalid64 && cpu_mode == SIZE64) 3796 goto error; 3797 break; 3798 case AM: 3799 which_prefix = &addr_size_prefix; 3800 break; 3801 case DM: 3802 which_prefix = &opnd_size_prefix; 3803 break; 3804 } 3805 if (which_prefix == NULL) 3806 break; 3807 *which_prefix = (opcode1 << 4) | opcode2; 3808 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3809 goto error; 3810 } 3811 3812 /* 3813 * Handle amd64 mode PREFIX values. 3814 * Some of the segment prefixes are no-ops. (only FS/GS actually work) 3815 * We might have a REX prefix (opcodes 0x40-0x4f) 3816 */ 3817 if (cpu_mode == SIZE64) { 3818 if (segment_prefix != 0x64 && segment_prefix != 0x65) 3819 segment_prefix = 0; 3820 3821 if (opcode1 == 0x4) { 3822 rex_prefix = (opcode1 << 4) | opcode2; 3823 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3824 goto error; 3825 dp = (instable_t *)&dis_distable[opcode1][opcode2]; 3826 } else if (opcode1 == 0xC && 3827 (opcode2 == 0x4 || opcode2 == 0x5)) { 3828 /* AVX instructions */ 3829 vex_prefix = (opcode1 << 4) | opcode2; 3830 x->d86_rex_prefix = 0x40; 3831 } 3832 } else if (opcode1 == 0xC && (opcode2 == 0x4 || opcode2 == 0x5)) { 3833 /* LDS, LES or AVX */ 3834 dtrace_get_modrm(x, &mode, ®, &r_m); 3835 vex_prefetch = 1; 3836 3837 if (mode == REG_ONLY) { 3838 /* AVX */ 3839 vex_prefix = (opcode1 << 4) | opcode2; 3840 x->d86_rex_prefix = 0x40; 3841 opcode3 = (((mode << 3) | reg)>>1) & 0x0F; 3842 opcode4 = ((reg << 3) | r_m) & 0x0F; 3843 } 3844 } 3845 3846 /* 3847 * The EVEX prefix and "bound" instruction share the same first byte. 3848 * "bound" is only valid for 32-bit. For 64-bit this byte begins the 3849 * EVEX prefix and the 2nd byte must have bits 2 & 3 set to 0. 3850 */ 3851 if (opcode1 == 0x6 && opcode2 == 0x2) { 3852 evex_prefix = 0x62; 3853 3854 /* 3855 * An EVEX prefix is 4 bytes long, get the next 3 bytes. 3856 */ 3857 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 3858 goto error; 3859 3860 if (addr_size == SIZE32 && (opcode4 & 0xf) == 0) { 3861 /* 3862 * Upper bits in 2nd byte == 0 is 'bound' instn. 3863 * 3864 * We've already read the byte so perform the 3865 * equivalent of dtrace_get_modrm on the byte and set 3866 * the flag to indicate we've already read it. 3867 */ 3868 char b = (opcode4 << 4) | opcode5; 3869 3870 r_m = b & 0x7; 3871 reg = (b >> 3) & 0x7; 3872 mode = (b >> 6) & 0x3; 3873 vex_prefetch = 1; 3874 goto not_avx512; 3875 } 3876 3877 /* check for correct bits being 0 in 2nd byte */ 3878 if ((opcode5 & 0xc) != 0) 3879 goto error; 3880 3881 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 3882 goto error; 3883 /* check for correct bit being 1 in 3rd byte */ 3884 if ((opcode7 & 0x4) == 0) 3885 goto error; 3886 3887 if (dtrace_get_opcode(x, &opcode8, &opcode9) != 0) 3888 goto error; 3889 3890 /* Reuse opcode1 & opcode2 to get the real opcode now */ 3891 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3892 goto error; 3893 3894 /* 3895 * We only use the high nibble from the 2nd byte of the prefix 3896 * and save it in the low bits of evex_byte1. This is because 3897 * two of the bits in opcode5 are constant 0 (checked above), 3898 * and the other two bits are captured in vex_m. Also, the VEX 3899 * constants we check in evex_byte1 are against the low bits. 3900 */ 3901 evex_byte1 = opcode4; 3902 evex_byte2 = (opcode6 << 4) | opcode7; 3903 evex_byte3 = (opcode8 << 4) | opcode9; 3904 3905 vex_m = opcode5 & EVEX_m; 3906 vex_v = (((opcode6 << 4) | opcode7) & VEX_v) >> 3; 3907 vex_W = (opcode6 & VEX_W) >> 3; 3908 vex_p = opcode7 & VEX_p; 3909 3910 /* 3911 * Store the corresponding prefix information for later use when 3912 * calculating the SIB. 3913 */ 3914 if ((evex_byte1 & VEX_R) == 0) 3915 x->d86_rex_prefix |= REX_R; 3916 if ((evex_byte1 & VEX_X) == 0) 3917 x->d86_rex_prefix |= REX_X; 3918 if ((evex_byte1 & VEX_B) == 0) 3919 x->d86_rex_prefix |= REX_B; 3920 3921 /* Currently only 3 valid values for evex L'L: 00, 01, 10 */ 3922 evex_L = (opcode8 & EVEX_L) >> 1; 3923 3924 switch (vex_p) { 3925 case VEX_p_66: 3926 switch (vex_m) { 3927 case VEX_m_0F: 3928 dp = &dis_opEVEX660F[(opcode1 << 4) | opcode2]; 3929 break; 3930 case VEX_m_0F38: 3931 dp = &dis_opEVEX660F38[(opcode1 << 4) | 3932 opcode2]; 3933 break; 3934 case VEX_m_0F3A: 3935 dp = &dis_opEVEX660F3A[(opcode1 << 4) | 3936 opcode2]; 3937 break; 3938 default: 3939 goto error; 3940 } 3941 break; 3942 case VEX_p_F3: 3943 switch (vex_m) { 3944 case VEX_m_0F: 3945 dp = &dis_opEVEXF30F[(opcode1 << 4) | opcode2]; 3946 break; 3947 default: 3948 goto error; 3949 } 3950 break; 3951 case VEX_p_F2: 3952 switch (vex_m) { 3953 case VEX_m_0F: 3954 dp = &dis_opEVEXF20F[(opcode1 << 4) | opcode2]; 3955 break; 3956 default: 3957 goto error; 3958 } 3959 break; 3960 default: 3961 dp = &dis_opEVEX0F[(opcode1 << 4) | opcode2]; 3962 break; 3963 } 3964 } 3965 not_avx512: 3966 3967 if (vex_prefix == VEX_2bytes) { 3968 if (!vex_prefetch) { 3969 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 3970 goto error; 3971 } 3972 vex_R = ((opcode3 & VEX_R) & 0x0F) >> 3; 3973 vex_L = ((opcode4 & VEX_L) & 0x0F) >> 2; 3974 vex_v = (((opcode3 << 4) | opcode4) & VEX_v) >> 3; 3975 vex_p = opcode4 & VEX_p; 3976 /* 3977 * The vex.x and vex.b bits are not defined in two bytes 3978 * mode vex prefix, their default values are 1 3979 */ 3980 vex_byte1 = (opcode3 & VEX_R) | VEX_X | VEX_B; 3981 3982 if (vex_R == 0) 3983 x->d86_rex_prefix |= REX_R; 3984 3985 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 3986 goto error; 3987 3988 switch (vex_p) { 3989 case VEX_p_66: 3990 dp = (instable_t *) 3991 &dis_opAVX660F[(opcode1 << 4) | opcode2]; 3992 break; 3993 case VEX_p_F3: 3994 dp = (instable_t *) 3995 &dis_opAVXF30F[(opcode1 << 4) | opcode2]; 3996 break; 3997 case VEX_p_F2: 3998 dp = (instable_t *) 3999 &dis_opAVXF20F [(opcode1 << 4) | opcode2]; 4000 break; 4001 default: 4002 dp = (instable_t *) 4003 &dis_opAVX0F[opcode1][opcode2]; 4004 4005 } 4006 4007 } else if (vex_prefix == VEX_3bytes) { 4008 if (!vex_prefetch) { 4009 if (dtrace_get_opcode(x, &opcode3, &opcode4) != 0) 4010 goto error; 4011 } 4012 vex_R = (opcode3 & VEX_R) >> 3; 4013 vex_X = (opcode3 & VEX_X) >> 2; 4014 vex_B = (opcode3 & VEX_B) >> 1; 4015 vex_m = (((opcode3 << 4) | opcode4) & VEX_m); 4016 vex_byte1 = opcode3 & (VEX_R | VEX_X | VEX_B); 4017 4018 if (vex_R == 0) 4019 x->d86_rex_prefix |= REX_R; 4020 if (vex_X == 0) 4021 x->d86_rex_prefix |= REX_X; 4022 if (vex_B == 0) 4023 x->d86_rex_prefix |= REX_B; 4024 4025 if (dtrace_get_opcode(x, &opcode5, &opcode6) != 0) 4026 goto error; 4027 vex_W = (opcode5 & VEX_W) >> 3; 4028 vex_L = (opcode6 & VEX_L) >> 2; 4029 vex_v = (((opcode5 << 4) | opcode6) & VEX_v) >> 3; 4030 vex_p = opcode6 & VEX_p; 4031 4032 if (vex_W) 4033 x->d86_rex_prefix |= REX_W; 4034 4035 /* Only these three vex_m values valid; others are reserved */ 4036 if ((vex_m != VEX_m_0F) && (vex_m != VEX_m_0F38) && 4037 (vex_m != VEX_m_0F3A)) 4038 goto error; 4039 4040 if (dtrace_get_opcode(x, &opcode1, &opcode2) != 0) 4041 goto error; 4042 4043 switch (vex_p) { 4044 case VEX_p_66: 4045 if (vex_m == VEX_m_0F) { 4046 dp = (instable_t *) 4047 &dis_opAVX660F 4048 [(opcode1 << 4) | opcode2]; 4049 } else if (vex_m == VEX_m_0F38) { 4050 dp = (instable_t *) 4051 &dis_opAVX660F38 4052 [(opcode1 << 4) | opcode2]; 4053 } else if (vex_m == VEX_m_0F3A) { 4054 dp = (instable_t *) 4055 &dis_opAVX660F3A 4056 [(opcode1 << 4) | opcode2]; 4057 } else { 4058 goto error; 4059 } 4060 break; 4061 case VEX_p_F3: 4062 if (vex_m == VEX_m_0F) { 4063 dp = (instable_t *) 4064 &dis_opAVXF30F 4065 [(opcode1 << 4) | opcode2]; 4066 } else if (vex_m == VEX_m_0F38) { 4067 dp = (instable_t *) 4068 &dis_opAVXF30F38 4069 [(opcode1 << 4) | opcode2]; 4070 } else { 4071 goto error; 4072 } 4073 break; 4074 case VEX_p_F2: 4075 if (vex_m == VEX_m_0F) { 4076 dp = (instable_t *) 4077 &dis_opAVXF20F 4078 [(opcode1 << 4) | opcode2]; 4079 } else if (vex_m == VEX_m_0F3A) { 4080 dp = (instable_t *) 4081 &dis_opAVXF20F3A 4082 [(opcode1 << 4) | opcode2]; 4083 } else if (vex_m == VEX_m_0F38) { 4084 dp = (instable_t *) 4085 &dis_opAVXF20F38 4086 [(opcode1 << 4) | opcode2]; 4087 } else { 4088 goto error; 4089 } 4090 break; 4091 default: 4092 dp = (instable_t *) 4093 &dis_opAVX0F[opcode1][opcode2]; 4094 4095 } 4096 } 4097 if (vex_prefix) { 4098 if (dp->it_vexwoxmm) { 4099 wbit = LONG_OPND; 4100 } else if (dp->it_vexopmask) { 4101 wbit = KOPMASK_OPND; 4102 } else { 4103 if (vex_L) { 4104 wbit = YMM_OPND; 4105 } else { 4106 wbit = XMM_OPND; 4107 } 4108 } 4109 } 4110 4111 /* 4112 * Deal with selection of operand and address size now. 4113 * Note that the REX.W bit being set causes opnd_size_prefix to be 4114 * ignored. 4115 */ 4116 if (cpu_mode == SIZE64) { 4117 if ((rex_prefix & REX_W) || vex_W) 4118 opnd_size = SIZE64; 4119 else if (opnd_size_prefix) 4120 opnd_size = SIZE16; 4121 4122 if (addr_size_prefix) 4123 addr_size = SIZE32; 4124 } else if (cpu_mode == SIZE32) { 4125 if (opnd_size_prefix) 4126 opnd_size = SIZE16; 4127 if (addr_size_prefix) 4128 addr_size = SIZE16; 4129 } else { 4130 if (opnd_size_prefix) 4131 opnd_size = SIZE32; 4132 if (addr_size_prefix) 4133 addr_size = SIZE32; 4134 } 4135 /* 4136 * The pause instruction - a repz'd nop. This doesn't fit 4137 * with any of the other prefix goop added for SSE, so we'll 4138 * special-case it here. 4139 */ 4140 if (rep_prefix == 0xf3 && opcode1 == 0x9 && opcode2 == 0x0) { 4141 rep_prefix = 0; 4142 dp = (instable_t *)&dis_opPause; 4143 } 4144 4145 /* 4146 * Some 386 instructions have 2 bytes of opcode before the mod_r/m 4147 * byte so we may need to perform a table indirection. 4148 */ 4149 if (dp->it_indirect == (instable_t *)dis_op0F) { 4150 if (dtrace_get_opcode(x, &opcode4, &opcode5) != 0) 4151 goto error; 4152 opcode_bytes = 2; 4153 if (opcode4 == 0x7 && opcode5 >= 0x1 && opcode5 <= 0x3) { 4154 uint_t subcode; 4155 4156 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4157 goto error; 4158 opcode_bytes = 3; 4159 subcode = ((opcode6 & 0x3) << 1) | 4160 ((opcode7 & 0x8) >> 3); 4161 dp = (instable_t *)&dis_op0F7123[opcode5][subcode]; 4162 } else if ((opcode4 == 0xc) && (opcode5 >= 0x8)) { 4163 dp = (instable_t *)&dis_op0FC8[0]; 4164 } else if ((opcode4 == 0x3) && (opcode5 == 0xA)) { 4165 opcode_bytes = 3; 4166 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4167 goto error; 4168 if (opnd_size == SIZE16) 4169 opnd_size = SIZE32; 4170 4171 dp = (instable_t *)&dis_op0F3A[(opcode6<<4)|opcode7]; 4172 #ifdef DIS_TEXT 4173 if (strcmp(dp->it_name, "INVALID") == 0) 4174 goto error; 4175 #endif 4176 switch (dp->it_adrmode) { 4177 case XMMP: 4178 break; 4179 case XMMP_66r: 4180 case XMMPRM_66r: 4181 case XMM3PM_66r: 4182 if (opnd_size_prefix == 0) { 4183 goto error; 4184 } 4185 4186 break; 4187 case XMMP_66o: 4188 if (opnd_size_prefix == 0) { 4189 /* SSSE3 MMX instructions */ 4190 dp_mmx = *dp; 4191 dp_mmx.it_adrmode = MMOPM_66o; 4192 #ifdef DIS_MEM 4193 dp_mmx.it_size = 8; 4194 #endif 4195 dp = &dp_mmx; 4196 } 4197 break; 4198 default: 4199 goto error; 4200 } 4201 } else if ((opcode4 == 0x3) && (opcode5 == 0x8)) { 4202 opcode_bytes = 3; 4203 if (dtrace_get_opcode(x, &opcode6, &opcode7) != 0) 4204 goto error; 4205 dp = (instable_t *)&dis_op0F38[(opcode6<<4)|opcode7]; 4206 4207 /* 4208 * Both crc32 and movbe have the same 3rd opcode 4209 * byte of either 0xF0 or 0xF1, so we use another 4210 * indirection to distinguish between the two. 4211 */ 4212 if (dp->it_indirect == (instable_t *)dis_op0F38F0 || 4213 dp->it_indirect == (instable_t *)dis_op0F38F1) { 4214 4215 dp = dp->it_indirect; 4216 if (rep_prefix != 0xF2) { 4217 /* It is movbe */ 4218 dp++; 4219 } 4220 } 4221 4222 /* 4223 * The adx family of instructions (adcx and adox) 4224 * continue the classic Intel tradition of abusing 4225 * arbitrary prefixes without actually meaning the 4226 * prefix bit. Therefore, if we find either the 4227 * opnd_size_prefix or rep_prefix we end up zeroing it 4228 * out after making our determination so as to ensure 4229 * that we don't get confused and accidentally print 4230 * repz prefixes and the like on these instructions. 4231 * 4232 * In addition, these instructions are actually much 4233 * closer to AVX instructions in semantics. Importantly, 4234 * they always default to having 32-bit operands. 4235 * However, if the CPU is in 64-bit mode, then and only 4236 * then, does it use REX.w promotes things to 64-bits 4237 * and REX.r allows 64-bit mode to use register r8-r15. 4238 */ 4239 if (dp->it_indirect == (instable_t *)dis_op0F38F6) { 4240 dp = dp->it_indirect; 4241 if (opnd_size_prefix == 0 && 4242 rep_prefix == 0xf3) { 4243 /* It is adox */ 4244 dp++; 4245 } else if (opnd_size_prefix != 0x66 && 4246 rep_prefix != 0) { 4247 /* It isn't adcx */ 4248 goto error; 4249 } 4250 opnd_size_prefix = 0; 4251 rep_prefix = 0; 4252 opnd_size = SIZE32; 4253 if (rex_prefix & REX_W) 4254 opnd_size = SIZE64; 4255 } 4256 4257 #ifdef DIS_TEXT 4258 if (strcmp(dp->it_name, "INVALID") == 0) 4259 goto error; 4260 #endif 4261 switch (dp->it_adrmode) { 4262 case ADX: 4263 case XMM: 4264 break; 4265 case RM_66r: 4266 case XMM_66r: 4267 case XMMM_66r: 4268 if (opnd_size_prefix == 0) { 4269 goto error; 4270 } 4271 break; 4272 case XMM_66o: 4273 if (opnd_size_prefix == 0) { 4274 /* SSSE3 MMX instructions */ 4275 dp_mmx = *dp; 4276 dp_mmx.it_adrmode = MM; 4277 #ifdef DIS_MEM 4278 dp_mmx.it_size = 8; 4279 #endif 4280 dp = &dp_mmx; 4281 } 4282 break; 4283 case CRC32: 4284 if (rep_prefix != 0xF2) { 4285 goto error; 4286 } 4287 rep_prefix = 0; 4288 break; 4289 case MOVBE: 4290 if (rep_prefix != 0x0) { 4291 goto error; 4292 } 4293 break; 4294 case RM: 4295 /* 4296 * Currently the MOVDIRI instruction is 4297 * the only known case here. It is not 4298 * allowed to have a prefix. 4299 */ 4300 if (rep_prefix != 0x0) { 4301 goto error; 4302 } 4303 break; 4304 case MOVDIR: 4305 /* 4306 * MOVDIR64B requires a opnd size prefix 4307 * of 0x66, but ignores it. This means 4308 * that we need to undo what we did 4309 * earlier and readjust the operator and 4310 * address size prefixes. 4311 */ 4312 if (opnd_size_prefix != 0x66) { 4313 goto error; 4314 } 4315 if (cpu_mode == SIZE64 || 4316 cpu_mode == SIZE16) { 4317 if (addr_size_prefix == 0x67) { 4318 opnd_size = SIZE32; 4319 } else { 4320 opnd_size = cpu_mode; 4321 } 4322 } else { 4323 if (addr_size_prefix == 0x67) { 4324 opnd_size = SIZE16; 4325 } else { 4326 opnd_size = SIZE32; 4327 } 4328 } 4329 addr_size = opnd_size; 4330 addr_size_prefix = 0; 4331 opnd_size_prefix = 0; 4332 break; 4333 default: 4334 goto error; 4335 } 4336 } else if (rep_prefix == 0xf3 && opcode4 == 0 && opcode5 == 9) { 4337 rep_prefix = 0; 4338 dp = (instable_t *)&dis_opWbnoinvd; 4339 } else { 4340 dp = (instable_t *)&dis_op0F[opcode4][opcode5]; 4341 } 4342 } 4343 4344 /* 4345 * If still not at a TERM decode entry, then a ModRM byte 4346 * exists and its fields further decode the instruction. 4347 */ 4348 x->d86_got_modrm = 0; 4349 if (dp->it_indirect != TERM) { 4350 dtrace_get_modrm(x, &mode, &opcode3, &r_m); 4351 if (x->d86_error) 4352 goto error; 4353 reg = opcode3; 4354 4355 /* 4356 * decode 287 instructions (D8-DF) from opcodeN 4357 */ 4358 if (opcode1 == 0xD && opcode2 >= 0x8) { 4359 if (opcode2 == 0xB && mode == 0x3 && opcode3 == 4) 4360 dp = (instable_t *)&dis_opFP5[r_m]; 4361 else if (opcode2 == 0xA && mode == 0x3 && opcode3 < 4) 4362 dp = (instable_t *)&dis_opFP7[opcode3]; 4363 else if (opcode2 == 0xB && mode == 0x3) 4364 dp = (instable_t *)&dis_opFP6[opcode3]; 4365 else if (opcode2 == 0x9 && mode == 0x3 && opcode3 >= 4) 4366 dp = (instable_t *)&dis_opFP4[opcode3 - 4][r_m]; 4367 else if (mode == 0x3) 4368 dp = (instable_t *) 4369 &dis_opFP3[opcode2 - 8][opcode3]; 4370 else 4371 dp = (instable_t *) 4372 &dis_opFP1n2[opcode2 - 8][opcode3]; 4373 } else { 4374 dp = (instable_t *)dp->it_indirect + opcode3; 4375 } 4376 } 4377 4378 /* 4379 * In amd64 bit mode, ARPL opcode is changed to MOVSXD 4380 * (sign extend 32bit to 64 bit) 4381 */ 4382 if ((vex_prefix == 0) && cpu_mode == SIZE64 && 4383 opcode1 == 0x6 && opcode2 == 0x3) 4384 dp = (instable_t *)&dis_opMOVSLD; 4385 4386 /* 4387 * at this point we should have a correct (or invalid) opcode 4388 */ 4389 if ((cpu_mode == SIZE64 && dp->it_invalid64) || 4390 (cpu_mode != SIZE64 && dp->it_invalid32)) 4391 goto error; 4392 if (dp->it_indirect != TERM) 4393 goto error; 4394 4395 /* 4396 * Deal with MMX/SSE opcodes which are changed by prefixes. Note, we do 4397 * need to include UNKNOWN below, as we may have instructions that 4398 * actually have a prefix, but don't exist in any other form. 4399 */ 4400 switch (dp->it_adrmode) { 4401 case UNKNOWN: 4402 case MMO: 4403 case MMOIMPL: 4404 case MMO3P: 4405 case MMOM3: 4406 case MMOMS: 4407 case MMOPM: 4408 case MMOPRM: 4409 case MMOS: 4410 case XMMO: 4411 case XMMOM: 4412 case XMMOMS: 4413 case XMMOPM: 4414 case XMMOS: 4415 case XMMOMX: 4416 case XMMOX3: 4417 case XMMOXMM: 4418 /* 4419 * This is horrible. Some SIMD instructions take the 4420 * form 0x0F 0x?? ..., which is easily decoded using the 4421 * existing tables. Other SIMD instructions use various 4422 * prefix bytes to overload existing instructions. For 4423 * Example, addps is F0, 58, whereas addss is F3 (repz), 4424 * F0, 58. Presumably someone got a raise for this. 4425 * 4426 * If we see one of the instructions which can be 4427 * modified in this way (if we've got one of the SIMDO* 4428 * address modes), we'll check to see if the last prefix 4429 * was a repz. If it was, we strip the prefix from the 4430 * mnemonic, and we indirect using the dis_opSIMDrepz 4431 * table. 4432 */ 4433 4434 /* 4435 * Calculate our offset in dis_op0F 4436 */ 4437 if ((uintptr_t)dp - (uintptr_t)dis_op0F > sizeof (dis_op0F)) 4438 goto error; 4439 4440 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4441 sizeof (instable_t); 4442 4443 /* 4444 * Rewrite if this instruction used one of the magic prefixes. 4445 */ 4446 if (rep_prefix) { 4447 if (rep_prefix == 0xf2) 4448 dp = (instable_t *)&dis_opSIMDrepnz[off]; 4449 else 4450 dp = (instable_t *)&dis_opSIMDrepz[off]; 4451 rep_prefix = 0; 4452 } else if (opnd_size_prefix) { 4453 dp = (instable_t *)&dis_opSIMDdata16[off]; 4454 opnd_size_prefix = 0; 4455 if (opnd_size == SIZE16) 4456 opnd_size = SIZE32; 4457 } 4458 break; 4459 4460 case MG9: 4461 /* 4462 * More horribleness: the group 9 (0xF0 0xC7) instructions are 4463 * allowed an optional prefix of 0x66 or 0xF3. This is similar 4464 * to the SIMD business described above, but with a different 4465 * addressing mode (and an indirect table), so we deal with it 4466 * separately (if similarly). 4467 * 4468 * Intel further complicated this with the release of Ivy Bridge 4469 * where they overloaded these instructions based on the ModR/M 4470 * bytes. The VMX instructions have a mode of 0 since they are 4471 * memory instructions but rdrand instructions have a mode of 4472 * 0b11 (REG_ONLY) because they only operate on registers. 4473 */ 4474 4475 /* 4476 * Calculate our offset in dis_op0FC7 (the group 9 table) 4477 */ 4478 if ((uintptr_t)dp - (uintptr_t)dis_op0FC7 > sizeof (dis_op0FC7)) 4479 goto error; 4480 4481 off = ((uintptr_t)dp - (uintptr_t)dis_op0FC7) / 4482 sizeof (instable_t); 4483 4484 /* 4485 * If we have a mode of 0b11 then we have to rewrite this. We 4486 * must check prefixes first. 4487 */ 4488 dtrace_get_modrm(x, &mode, ®, &r_m); 4489 4490 /* 4491 * Rewrite if this instruction used one of the magic prefixes. 4492 */ 4493 if (rep_prefix) { 4494 if (rep_prefix == 0xf3 && mode == REG_ONLY) 4495 dp = (instable_t *)&dis_opF30FC7m3[off]; 4496 else if (rep_prefix == 0xf3) 4497 dp = (instable_t *)&dis_opF30FC7[off]; 4498 else 4499 goto error; 4500 rep_prefix = 0; 4501 } else if (opnd_size_prefix) { 4502 if (mode == REG_ONLY) { 4503 dp = (instable_t *)&dis_op0FC7m3[reg]; 4504 } else { 4505 dp = (instable_t *)&dis_op660FC7[off]; 4506 opnd_size_prefix = 0; 4507 if (opnd_size == SIZE16) 4508 opnd_size = SIZE32; 4509 } 4510 } else if (mode == REG_ONLY) { 4511 dp = (instable_t *)&dis_op0FC7m3[off]; 4512 } else if (reg == 4 || reg == 5) { 4513 /* 4514 * We have xsavec (4) or xsaves (5), so rewrite. 4515 */ 4516 dp = (instable_t *)&dis_op0FC7[reg]; 4517 } 4518 break; 4519 4520 4521 case MMOSH: 4522 /* 4523 * As with the "normal" SIMD instructions, the MMX 4524 * shuffle instructions are overloaded. These 4525 * instructions, however, are special in that they use 4526 * an extra byte, and thus an extra table. As of this 4527 * writing, they only use the opnd_size prefix. 4528 */ 4529 4530 /* 4531 * Calculate our offset in dis_op0F7123 4532 */ 4533 if ((uintptr_t)dp - (uintptr_t)dis_op0F7123 > 4534 sizeof (dis_op0F7123)) 4535 goto error; 4536 4537 if (opnd_size_prefix) { 4538 off = ((uintptr_t)dp - (uintptr_t)dis_op0F7123) / 4539 sizeof (instable_t); 4540 dp = (instable_t *)&dis_opSIMD7123[off]; 4541 opnd_size_prefix = 0; 4542 if (opnd_size == SIZE16) 4543 opnd_size = SIZE32; 4544 } 4545 break; 4546 case MRw: 4547 if (rep_prefix) { 4548 if (rep_prefix == 0xf3) { 4549 4550 /* 4551 * Calculate our offset in dis_op0F 4552 */ 4553 if ((uintptr_t)dp - (uintptr_t)dis_op0F > 4554 sizeof (dis_op0F)) 4555 goto error; 4556 4557 off = ((uintptr_t)dp - (uintptr_t)dis_op0F) / 4558 sizeof (instable_t); 4559 4560 dp = (instable_t *)&dis_opSIMDrepz[off]; 4561 rep_prefix = 0; 4562 } else { 4563 goto error; 4564 } 4565 } 4566 break; 4567 case FSGS: 4568 if (rep_prefix == 0xf3) { 4569 if ((uintptr_t)dp - (uintptr_t)dis_op0FAE > 4570 sizeof (dis_op0FAE)) 4571 goto error; 4572 4573 off = ((uintptr_t)dp - (uintptr_t)dis_op0FAE) / 4574 sizeof (instable_t); 4575 dp = (instable_t *)&dis_opF30FAE[off]; 4576 rep_prefix = 0; 4577 } else if (rep_prefix != 0x00) { 4578 goto error; 4579 } 4580 } 4581 4582 /* 4583 * In 64 bit mode, some opcodes automatically use opnd_size == SIZE64. 4584 */ 4585 if (cpu_mode == SIZE64) 4586 if (dp->it_always64 || (opnd_size == SIZE32 && dp->it_stackop)) 4587 opnd_size = SIZE64; 4588 4589 #ifdef DIS_TEXT 4590 /* 4591 * At this point most instructions can format the opcode mnemonic 4592 * including the prefixes. 4593 */ 4594 if (lock_prefix) 4595 (void) strlcat(x->d86_mnem, "lock ", OPLEN); 4596 4597 if (rep_prefix == 0xf2) 4598 (void) strlcat(x->d86_mnem, "repnz ", OPLEN); 4599 else if (rep_prefix == 0xf3) 4600 (void) strlcat(x->d86_mnem, "repz ", OPLEN); 4601 4602 if (cpu_mode == SIZE64 && addr_size_prefix) 4603 (void) strlcat(x->d86_mnem, "addr32 ", OPLEN); 4604 4605 if (dp->it_adrmode != CBW && 4606 dp->it_adrmode != CWD && 4607 dp->it_adrmode != XMMSFNC) { 4608 if (strcmp(dp->it_name, "INVALID") == 0) 4609 goto error; 4610 (void) strlcat(x->d86_mnem, dp->it_name, OPLEN); 4611 if (dp->it_avxsuf == AVS2 && dp->it_suffix) { 4612 (void) strlcat(x->d86_mnem, vex_W != 0 ? "q" : "d", 4613 OPLEN); 4614 } else if (dp->it_vexopmask && dp->it_suffix) { 4615 /* opmask instructions */ 4616 4617 if (opcode1 == 4 && opcode2 == 0xb) { 4618 /* It's a kunpck. */ 4619 if (vex_prefix == VEX_2bytes) { 4620 (void) strlcat(x->d86_mnem, 4621 vex_p == 0 ? "wd" : "bw", OPLEN); 4622 } else { 4623 /* vex_prefix == VEX_3bytes */ 4624 (void) strlcat(x->d86_mnem, 4625 "dq", OPLEN); 4626 } 4627 } else if (opcode1 == 3) { 4628 /* It's a kshift[l|r]. */ 4629 if (vex_W == 0) { 4630 (void) strlcat(x->d86_mnem, 4631 opcode2 == 2 || 4632 opcode2 == 0 ? 4633 "b" : "d", OPLEN); 4634 } else { 4635 /* W == 1 */ 4636 (void) strlcat(x->d86_mnem, 4637 opcode2 == 3 || opcode2 == 1 ? 4638 "q" : "w", OPLEN); 4639 } 4640 } else { 4641 /* if (vex_prefix == VEX_2bytes) { */ 4642 if ((cpu_mode == SIZE64 && opnd_size == 2) || 4643 vex_prefix == VEX_2bytes) { 4644 (void) strlcat(x->d86_mnem, 4645 vex_p == 0 ? "w" : 4646 vex_p == 1 ? "b" : "d", 4647 OPLEN); 4648 } else { 4649 /* vex_prefix == VEX_3bytes */ 4650 (void) strlcat(x->d86_mnem, 4651 vex_p == 1 ? "d" : "q", OPLEN); 4652 } 4653 } 4654 } else if (dp->it_suffix) { 4655 char *types[] = {"", "w", "l", "q"}; 4656 if (opcode_bytes == 2 && opcode4 == 4) { 4657 /* It's a cmovx.yy. Replace the suffix x */ 4658 for (i = 5; i < OPLEN; i++) { 4659 if (x->d86_mnem[i] == '.') 4660 break; 4661 } 4662 x->d86_mnem[i - 1] = *types[opnd_size]; 4663 } else if ((opnd_size == 2) && (opcode_bytes == 3) && 4664 ((opcode6 == 1 && opcode7 == 6) || 4665 (opcode6 == 2 && opcode7 == 2))) { 4666 /* 4667 * To handle PINSRD and PEXTRD 4668 */ 4669 (void) strlcat(x->d86_mnem, "d", OPLEN); 4670 } else if (dp != &dis_distable[0x6][0x2]) { 4671 /* bound instructions (0x62) have no suffix */ 4672 (void) strlcat(x->d86_mnem, types[opnd_size], 4673 OPLEN); 4674 } 4675 } 4676 } 4677 #endif 4678 4679 /* 4680 * Process operands based on the addressing modes. 4681 */ 4682 x->d86_mode = cpu_mode; 4683 /* 4684 * In vex mode the rex_prefix has no meaning 4685 */ 4686 if (!vex_prefix && evex_prefix == 0) 4687 x->d86_rex_prefix = rex_prefix; 4688 x->d86_opnd_size = opnd_size; 4689 x->d86_addr_size = addr_size; 4690 vbit = 0; /* initialize for mem/reg -> reg */ 4691 switch (dp->it_adrmode) { 4692 /* 4693 * amd64 instruction to sign extend 32 bit reg/mem operands 4694 * into 64 bit register values 4695 */ 4696 case MOVSXZ: 4697 #ifdef DIS_TEXT 4698 if (rex_prefix == 0) 4699 (void) strncpy(x->d86_mnem, "movzld", OPLEN); 4700 #endif 4701 dtrace_get_modrm(x, &mode, ®, &r_m); 4702 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4703 x->d86_opnd_size = SIZE64; 4704 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4705 x->d86_opnd_size = opnd_size = SIZE32; 4706 wbit = LONG_OPND; 4707 dtrace_get_operand(x, mode, r_m, wbit, 0); 4708 break; 4709 4710 /* 4711 * movsbl movsbw movsbq (0x0FBE) or movswl movswq (0x0FBF) 4712 * movzbl movzbw movzbq (0x0FB6) or movzwl movzwq (0x0FB7) 4713 * wbit lives in 2nd byte, note that operands 4714 * are different sized 4715 */ 4716 case MOVZ: 4717 if (rex_prefix & REX_W) { 4718 /* target register size = 64 bit */ 4719 x->d86_mnem[5] = 'q'; 4720 } 4721 dtrace_get_modrm(x, &mode, ®, &r_m); 4722 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4723 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4724 x->d86_opnd_size = opnd_size = SIZE16; 4725 wbit = WBIT(opcode5); 4726 dtrace_get_operand(x, mode, r_m, wbit, 0); 4727 break; 4728 case CRC32: 4729 opnd_size = SIZE32; 4730 if (rex_prefix & REX_W) 4731 opnd_size = SIZE64; 4732 x->d86_opnd_size = opnd_size; 4733 4734 dtrace_get_modrm(x, &mode, ®, &r_m); 4735 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4736 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4737 wbit = WBIT(opcode7); 4738 if (opnd_size_prefix) 4739 x->d86_opnd_size = opnd_size = SIZE16; 4740 dtrace_get_operand(x, mode, r_m, wbit, 0); 4741 break; 4742 case MOVBE: 4743 opnd_size = SIZE32; 4744 if (rex_prefix & REX_W) 4745 opnd_size = SIZE64; 4746 x->d86_opnd_size = opnd_size; 4747 4748 dtrace_get_modrm(x, &mode, ®, &r_m); 4749 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4750 wbit = WBIT(opcode7); 4751 if (opnd_size_prefix) 4752 x->d86_opnd_size = opnd_size = SIZE16; 4753 if (wbit) { 4754 /* reg -> mem */ 4755 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 4756 dtrace_get_operand(x, mode, r_m, wbit, 1); 4757 } else { 4758 /* mem -> reg */ 4759 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4760 dtrace_get_operand(x, mode, r_m, wbit, 0); 4761 } 4762 break; 4763 4764 /* 4765 * imul instruction, with either 8-bit or longer immediate 4766 * opcode 0x6B for byte, sign-extended displacement, 0x69 for word(s) 4767 */ 4768 case IMUL: 4769 wbit = LONG_OPND; 4770 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 4771 OPSIZE(opnd_size, opcode2 == 0x9), 1); 4772 break; 4773 4774 /* memory or register operand to register, with 'w' bit */ 4775 case MRw: 4776 case ADX: 4777 wbit = WBIT(opcode2); 4778 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 4779 break; 4780 4781 /* register to memory or register operand, with 'w' bit */ 4782 /* arpl happens to fit here also because it is odd */ 4783 case RMw: 4784 if (opcode_bytes == 2) 4785 wbit = WBIT(opcode5); 4786 else 4787 wbit = WBIT(opcode2); 4788 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4789 break; 4790 4791 /* xaddb instruction */ 4792 case XADDB: 4793 wbit = 0; 4794 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4795 break; 4796 4797 /* MMX register to memory or register operand */ 4798 case MMS: 4799 case MMOS: 4800 #ifdef DIS_TEXT 4801 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 4802 #else 4803 wbit = LONG_OPND; 4804 #endif 4805 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4806 break; 4807 4808 /* MMX register to memory */ 4809 case MMOMS: 4810 dtrace_get_modrm(x, &mode, ®, &r_m); 4811 if (mode == REG_ONLY) 4812 goto error; 4813 wbit = MM_OPND; 4814 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 1); 4815 break; 4816 4817 /* Double shift. Has immediate operand specifying the shift. */ 4818 case DSHIFT: 4819 wbit = LONG_OPND; 4820 dtrace_get_modrm(x, &mode, ®, &r_m); 4821 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 4822 dtrace_get_operand(x, mode, r_m, wbit, 2); 4823 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 4824 dtrace_imm_opnd(x, wbit, 1, 0); 4825 break; 4826 4827 /* 4828 * Double shift. With no immediate operand, specifies using %cl. 4829 */ 4830 case DSHIFTcl: 4831 wbit = LONG_OPND; 4832 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 4833 break; 4834 4835 /* immediate to memory or register operand */ 4836 case IMlw: 4837 wbit = WBIT(opcode2); 4838 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4839 dtrace_get_operand(x, mode, r_m, wbit, 1); 4840 /* 4841 * Have long immediate for opcode 0x81, but not 0x80 nor 0x83 4842 */ 4843 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, opcode2 == 1), 0); 4844 break; 4845 4846 /* immediate to memory or register operand with the */ 4847 /* 'w' bit present */ 4848 case IMw: 4849 wbit = WBIT(opcode2); 4850 dtrace_get_modrm(x, &mode, ®, &r_m); 4851 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4852 dtrace_get_operand(x, mode, r_m, wbit, 1); 4853 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 4854 break; 4855 4856 /* immediate to register with register in low 3 bits */ 4857 /* of op code */ 4858 case IR: 4859 /* w-bit here (with regs) is bit 3 */ 4860 wbit = opcode2 >>3 & 0x1; 4861 reg = REGNO(opcode2); 4862 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4863 mode = REG_ONLY; 4864 r_m = reg; 4865 dtrace_get_operand(x, mode, r_m, wbit, 1); 4866 dtrace_imm_opnd(x, wbit, OPSIZE64(opnd_size, wbit), 0); 4867 break; 4868 4869 /* MMX immediate shift of register */ 4870 case MMSH: 4871 case MMOSH: 4872 wbit = MM_OPND; 4873 goto mm_shift; /* in next case */ 4874 4875 /* SIMD immediate shift of register */ 4876 case XMMSH: 4877 wbit = XMM_OPND; 4878 mm_shift: 4879 reg = REGNO(opcode7); 4880 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 4881 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 4882 dtrace_imm_opnd(x, wbit, 1, 0); 4883 NOMEM; 4884 break; 4885 4886 /* accumulator to memory operand */ 4887 case AO: 4888 vbit = 1; 4889 /*FALLTHROUGH*/ 4890 4891 /* memory operand to accumulator */ 4892 case OA: 4893 wbit = WBIT(opcode2); 4894 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1 - vbit); 4895 dtrace_imm_opnd(x, wbit, OPSIZE64(addr_size, LONG_OPND), vbit); 4896 #ifdef DIS_TEXT 4897 x->d86_opnd[vbit].d86_mode = MODE_OFFSET; 4898 #endif 4899 break; 4900 4901 4902 /* segment register to memory or register operand */ 4903 case SM: 4904 vbit = 1; 4905 /*FALLTHROUGH*/ 4906 4907 /* memory or register operand to segment register */ 4908 case MS: 4909 dtrace_get_modrm(x, &mode, ®, &r_m); 4910 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4911 dtrace_get_operand(x, mode, r_m, LONG_OPND, vbit); 4912 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 1 - vbit); 4913 break; 4914 4915 /* 4916 * rotate or shift instructions, which may shift by 1 or 4917 * consult the cl register, depending on the 'v' bit 4918 */ 4919 case Mv: 4920 vbit = VBIT(opcode2); 4921 wbit = WBIT(opcode2); 4922 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4923 dtrace_get_operand(x, mode, r_m, wbit, 1); 4924 #ifdef DIS_TEXT 4925 if (vbit) { 4926 (void) strlcat(x->d86_opnd[0].d86_opnd, "%cl", OPLEN); 4927 } else { 4928 x->d86_opnd[0].d86_mode = MODE_SIGNED; 4929 x->d86_opnd[0].d86_value_size = 1; 4930 x->d86_opnd[0].d86_value = 1; 4931 } 4932 #endif 4933 break; 4934 /* 4935 * immediate rotate or shift instructions 4936 */ 4937 case MvI: 4938 wbit = WBIT(opcode2); 4939 normal_imm_mem: 4940 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4941 dtrace_get_operand(x, mode, r_m, wbit, 1); 4942 dtrace_imm_opnd(x, wbit, 1, 0); 4943 break; 4944 4945 /* bit test instructions */ 4946 case MIb: 4947 wbit = LONG_OPND; 4948 goto normal_imm_mem; 4949 4950 /* single memory or register operand with 'w' bit present */ 4951 case Mw: 4952 wbit = WBIT(opcode2); 4953 just_mem: 4954 dtrace_get_modrm(x, &mode, ®, &r_m); 4955 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 4956 dtrace_get_operand(x, mode, r_m, wbit, 0); 4957 break; 4958 4959 case SWAPGS_RDTSCP: 4960 if (cpu_mode == SIZE64 && mode == 3 && r_m == 0) { 4961 #ifdef DIS_TEXT 4962 (void) strncpy(x->d86_mnem, "swapgs", OPLEN); 4963 #endif 4964 NOMEM; 4965 break; 4966 } else if (mode == 3 && r_m == 1) { 4967 #ifdef DIS_TEXT 4968 (void) strncpy(x->d86_mnem, "rdtscp", OPLEN); 4969 #endif 4970 NOMEM; 4971 break; 4972 } else if (mode == 3 && r_m == 2) { 4973 #ifdef DIS_TEXT 4974 (void) strncpy(x->d86_mnem, "monitorx", OPLEN); 4975 #endif 4976 NOMEM; 4977 break; 4978 } else if (mode == 3 && r_m == 3) { 4979 #ifdef DIS_TEXT 4980 (void) strncpy(x->d86_mnem, "mwaitx", OPLEN); 4981 #endif 4982 NOMEM; 4983 break; 4984 } else if (mode == 3 && r_m == 4) { 4985 #ifdef DIS_TEXT 4986 (void) strncpy(x->d86_mnem, "clzero", OPLEN); 4987 #endif 4988 NOMEM; 4989 break; 4990 } 4991 4992 /*FALLTHROUGH*/ 4993 4994 /* prefetch instruction - memory operand, but no memory acess */ 4995 case PREF: 4996 NOMEM; 4997 /*FALLTHROUGH*/ 4998 4999 /* single memory or register operand */ 5000 case M: 5001 case MG9: 5002 wbit = LONG_OPND; 5003 goto just_mem; 5004 5005 /* single memory or register byte operand */ 5006 case Mb: 5007 wbit = BYTE_OPND; 5008 goto just_mem; 5009 5010 case VMx: 5011 if (mode == 3) { 5012 #ifdef DIS_TEXT 5013 char *vminstr; 5014 5015 switch (r_m) { 5016 case 1: 5017 vminstr = "vmcall"; 5018 break; 5019 case 2: 5020 vminstr = "vmlaunch"; 5021 break; 5022 case 3: 5023 vminstr = "vmresume"; 5024 break; 5025 case 4: 5026 vminstr = "vmxoff"; 5027 break; 5028 default: 5029 goto error; 5030 } 5031 5032 (void) strncpy(x->d86_mnem, vminstr, OPLEN); 5033 #else 5034 if (r_m < 1 || r_m > 4) 5035 goto error; 5036 #endif 5037 5038 NOMEM; 5039 break; 5040 } 5041 /*FALLTHROUGH*/ 5042 case SVM: 5043 if (mode == 3) { 5044 #if DIS_TEXT 5045 char *vinstr; 5046 5047 switch (r_m) { 5048 case 0: 5049 vinstr = "vmrun"; 5050 break; 5051 case 1: 5052 vinstr = "vmmcall"; 5053 break; 5054 case 2: 5055 vinstr = "vmload"; 5056 break; 5057 case 3: 5058 vinstr = "vmsave"; 5059 break; 5060 case 4: 5061 vinstr = "stgi"; 5062 break; 5063 case 5: 5064 vinstr = "clgi"; 5065 break; 5066 case 6: 5067 vinstr = "skinit"; 5068 break; 5069 case 7: 5070 vinstr = "invlpga"; 5071 break; 5072 } 5073 5074 (void) strncpy(x->d86_mnem, vinstr, OPLEN); 5075 #endif 5076 NOMEM; 5077 break; 5078 } 5079 /*FALLTHROUGH*/ 5080 case MONITOR_MWAIT: 5081 if (mode == 3) { 5082 if (r_m == 0) { 5083 #ifdef DIS_TEXT 5084 (void) strncpy(x->d86_mnem, "monitor", OPLEN); 5085 #endif 5086 NOMEM; 5087 break; 5088 } else if (r_m == 1) { 5089 #ifdef DIS_TEXT 5090 (void) strncpy(x->d86_mnem, "mwait", OPLEN); 5091 #endif 5092 NOMEM; 5093 break; 5094 } else if (r_m == 2) { 5095 #ifdef DIS_TEXT 5096 (void) strncpy(x->d86_mnem, "clac", OPLEN); 5097 #endif 5098 NOMEM; 5099 break; 5100 } else if (r_m == 3) { 5101 #ifdef DIS_TEXT 5102 (void) strncpy(x->d86_mnem, "stac", OPLEN); 5103 #endif 5104 NOMEM; 5105 break; 5106 } else { 5107 goto error; 5108 } 5109 } 5110 /*FALLTHROUGH*/ 5111 case XGETBV_XSETBV: 5112 if (mode == 3) { 5113 if (r_m == 0) { 5114 #ifdef DIS_TEXT 5115 (void) strncpy(x->d86_mnem, "xgetbv", OPLEN); 5116 #endif 5117 NOMEM; 5118 break; 5119 } else if (r_m == 1) { 5120 #ifdef DIS_TEXT 5121 (void) strncpy(x->d86_mnem, "xsetbv", OPLEN); 5122 #endif 5123 NOMEM; 5124 break; 5125 } else { 5126 goto error; 5127 } 5128 5129 } 5130 /*FALLTHROUGH*/ 5131 case MO: 5132 /* Similar to M, but only memory (no direct registers) */ 5133 wbit = LONG_OPND; 5134 dtrace_get_modrm(x, &mode, ®, &r_m); 5135 if (mode == 3) 5136 goto error; 5137 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5138 dtrace_get_operand(x, mode, r_m, wbit, 0); 5139 break; 5140 5141 /* move special register to register or reverse if vbit */ 5142 case SREG: 5143 switch (opcode5) { 5144 5145 case 2: 5146 vbit = 1; 5147 /*FALLTHROUGH*/ 5148 case 0: 5149 wbit = CONTROL_OPND; 5150 break; 5151 5152 case 3: 5153 vbit = 1; 5154 /*FALLTHROUGH*/ 5155 case 1: 5156 wbit = DEBUG_OPND; 5157 break; 5158 5159 case 6: 5160 vbit = 1; 5161 /*FALLTHROUGH*/ 5162 case 4: 5163 wbit = TEST_OPND; 5164 break; 5165 5166 } 5167 dtrace_get_modrm(x, &mode, ®, &r_m); 5168 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5169 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit); 5170 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 1 - vbit); 5171 NOMEM; 5172 break; 5173 5174 /* 5175 * single register operand with register in the low 3 5176 * bits of op code 5177 */ 5178 case R: 5179 if (opcode_bytes == 2) 5180 reg = REGNO(opcode5); 5181 else 5182 reg = REGNO(opcode2); 5183 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 5184 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 5185 NOMEM; 5186 break; 5187 5188 /* 5189 * register to accumulator with register in the low 3 5190 * bits of op code, xchg instructions 5191 */ 5192 case RA: 5193 NOMEM; 5194 reg = REGNO(opcode2); 5195 dtrace_rex_adjust(rex_prefix, mode, ®, NULL); 5196 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 0); 5197 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, LONG_OPND, 1); 5198 break; 5199 5200 case RMATCH: 5201 x->d86_opnd_size = x->d86_mode; 5202 dtrace_get_modrm(x, &mode, ®, &r_m); 5203 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5204 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5205 break; 5206 5207 /* 5208 * single segment register operand, with register in 5209 * bits 3-4 of op code byte 5210 */ 5211 case SEG: 5212 NOMEM; 5213 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x3; 5214 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 5215 break; 5216 5217 /* 5218 * single segment register operand, with register in 5219 * bits 3-5 of op code 5220 */ 5221 case LSEG: 5222 NOMEM; 5223 /* long seg reg from opcode */ 5224 reg = (x->d86_bytes[x->d86_len - 1] >> 3) & 0x7; 5225 dtrace_get_operand(x, REG_ONLY, reg, SEG_OPND, 0); 5226 break; 5227 5228 /* memory or register operand to register */ 5229 case MR: 5230 if (vex_prefetch) 5231 x->d86_got_modrm = 1; 5232 wbit = LONG_OPND; 5233 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 5234 break; 5235 5236 case RM: 5237 case RM_66r: 5238 if (vex_prefetch) 5239 x->d86_got_modrm = 1; 5240 wbit = LONG_OPND; 5241 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 1); 5242 break; 5243 5244 /* MMX/SIMD-Int memory or mm reg to mm reg */ 5245 case MM: 5246 case MMO: 5247 #ifdef DIS_TEXT 5248 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 5249 #else 5250 wbit = LONG_OPND; 5251 #endif 5252 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 5253 break; 5254 5255 case MMOIMPL: 5256 #ifdef DIS_TEXT 5257 wbit = strcmp(dp->it_name, "movd") ? MM_OPND : LONG_OPND; 5258 #else 5259 wbit = LONG_OPND; 5260 #endif 5261 dtrace_get_modrm(x, &mode, ®, &r_m); 5262 if (mode != REG_ONLY) 5263 goto error; 5264 5265 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5266 dtrace_get_operand(x, mode, r_m, wbit, 0); 5267 dtrace_get_operand(x, REG_ONLY, reg, MM_OPND, 1); 5268 mode = 0; /* change for memory access size... */ 5269 break; 5270 5271 /* MMX/SIMD-Int and SIMD-FP predicated mm reg to r32 */ 5272 case MMO3P: 5273 wbit = MM_OPND; 5274 goto xmm3p; 5275 case XMM3P: 5276 wbit = XMM_OPND; 5277 xmm3p: 5278 dtrace_get_modrm(x, &mode, ®, &r_m); 5279 if (mode != REG_ONLY) 5280 goto error; 5281 5282 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 1, 5283 1); 5284 NOMEM; 5285 break; 5286 5287 case XMM3PM_66r: 5288 THREEOPERAND(x, mode, reg, r_m, rex_prefix, LONG_OPND, XMM_OPND, 5289 1, 0); 5290 break; 5291 5292 /* MMX/SIMD-Int predicated r32/mem to mm reg */ 5293 case MMOPRM: 5294 wbit = LONG_OPND; 5295 w2 = MM_OPND; 5296 goto xmmprm; 5297 case XMMPRM: 5298 case XMMPRM_66r: 5299 wbit = LONG_OPND; 5300 w2 = XMM_OPND; 5301 xmmprm: 5302 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, w2, 1, 1); 5303 break; 5304 5305 /* MMX/SIMD-Int predicated mm/mem to mm reg */ 5306 case MMOPM: 5307 case MMOPM_66o: 5308 wbit = w2 = MM_OPND; 5309 goto xmmprm; 5310 5311 /* MMX/SIMD-Int mm reg to r32 */ 5312 case MMOM3: 5313 NOMEM; 5314 dtrace_get_modrm(x, &mode, ®, &r_m); 5315 if (mode != REG_ONLY) 5316 goto error; 5317 wbit = MM_OPND; 5318 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 5319 break; 5320 5321 /* SIMD memory or xmm reg operand to xmm reg */ 5322 case XMM: 5323 case XMM_66o: 5324 case XMM_66r: 5325 case XMMO: 5326 case XMMXIMPL: 5327 wbit = XMM_OPND; 5328 STANDARD_MODRM(x, mode, reg, r_m, rex_prefix, wbit, 0); 5329 5330 if (dp->it_adrmode == XMMXIMPL && mode != REG_ONLY) 5331 goto error; 5332 5333 #ifdef DIS_TEXT 5334 /* 5335 * movlps and movhlps share opcodes. They differ in the 5336 * addressing modes allowed for their operands. 5337 * movhps and movlhps behave similarly. 5338 */ 5339 if (mode == REG_ONLY) { 5340 if (strcmp(dp->it_name, "movlps") == 0) 5341 (void) strncpy(x->d86_mnem, "movhlps", OPLEN); 5342 else if (strcmp(dp->it_name, "movhps") == 0) 5343 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 5344 } 5345 #endif 5346 if (dp->it_adrmode == XMMXIMPL) 5347 mode = 0; /* change for memory access size... */ 5348 break; 5349 5350 /* SIMD xmm reg to memory or xmm reg */ 5351 case XMMS: 5352 case XMMOS: 5353 case XMMMS: 5354 case XMMOMS: 5355 dtrace_get_modrm(x, &mode, ®, &r_m); 5356 #ifdef DIS_TEXT 5357 if ((strcmp(dp->it_name, "movlps") == 0 || 5358 strcmp(dp->it_name, "movhps") == 0 || 5359 strcmp(dp->it_name, "movntps") == 0) && 5360 mode == REG_ONLY) 5361 goto error; 5362 #endif 5363 wbit = XMM_OPND; 5364 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 5365 break; 5366 5367 /* SIMD memory to xmm reg */ 5368 case XMMM: 5369 case XMMM_66r: 5370 case XMMOM: 5371 wbit = XMM_OPND; 5372 dtrace_get_modrm(x, &mode, ®, &r_m); 5373 #ifdef DIS_TEXT 5374 if (mode == REG_ONLY) { 5375 if (strcmp(dp->it_name, "movhps") == 0) 5376 (void) strncpy(x->d86_mnem, "movlhps", OPLEN); 5377 else 5378 goto error; 5379 } 5380 #endif 5381 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 5382 break; 5383 5384 /* SIMD memory or r32 to xmm reg */ 5385 case XMM3MX: 5386 wbit = LONG_OPND; 5387 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 5388 break; 5389 5390 case XMM3MXS: 5391 wbit = LONG_OPND; 5392 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1); 5393 break; 5394 5395 /* SIMD memory or mm reg to xmm reg */ 5396 case XMMOMX: 5397 /* SIMD mm to xmm */ 5398 case XMMMX: 5399 wbit = MM_OPND; 5400 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 0); 5401 break; 5402 5403 /* SIMD memory or xmm reg to mm reg */ 5404 case XMMXMM: 5405 case XMMOXMM: 5406 case XMMXM: 5407 wbit = XMM_OPND; 5408 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, MM_OPND, 0); 5409 break; 5410 5411 5412 /* SIMD memory or xmm reg to r32 */ 5413 case XMMXM3: 5414 wbit = XMM_OPND; 5415 MIXED_MM(x, mode, reg, r_m, rex_prefix, wbit, LONG_OPND, 0); 5416 break; 5417 5418 /* SIMD xmm to r32 */ 5419 case XMMX3: 5420 case XMMOX3: 5421 dtrace_get_modrm(x, &mode, ®, &r_m); 5422 if (mode != REG_ONLY) 5423 goto error; 5424 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5425 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 5426 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 5427 NOMEM; 5428 break; 5429 5430 /* SIMD predicated memory or xmm reg with/to xmm reg */ 5431 case XMMP: 5432 case XMMP_66r: 5433 case XMMP_66o: 5434 case XMMOPM: 5435 wbit = XMM_OPND; 5436 THREEOPERAND(x, mode, reg, r_m, rex_prefix, wbit, XMM_OPND, 1, 5437 1); 5438 5439 #ifdef DIS_TEXT 5440 /* 5441 * cmpps and cmpss vary their instruction name based 5442 * on the value of imm8. Other XMMP instructions, 5443 * such as shufps, require explicit specification of 5444 * the predicate. 5445 */ 5446 if (dp->it_name[0] == 'c' && 5447 dp->it_name[1] == 'm' && 5448 dp->it_name[2] == 'p' && 5449 strlen(dp->it_name) == 5) { 5450 uchar_t pred = x->d86_opnd[0].d86_value & 0xff; 5451 5452 if (pred >= (sizeof (dis_PREDSUFFIX) / sizeof (char *))) 5453 goto error; 5454 5455 (void) strncpy(x->d86_mnem, "cmp", OPLEN); 5456 (void) strlcat(x->d86_mnem, dis_PREDSUFFIX[pred], 5457 OPLEN); 5458 (void) strlcat(x->d86_mnem, 5459 dp->it_name + strlen(dp->it_name) - 2, 5460 OPLEN); 5461 x->d86_opnd[0] = x->d86_opnd[1]; 5462 x->d86_opnd[1] = x->d86_opnd[2]; 5463 x->d86_numopnds = 2; 5464 } 5465 5466 /* 5467 * The pclmulqdq instruction has a series of alternate names for 5468 * various encodings of the immediate byte. As such, if we 5469 * happen to find it and the immediate value matches, we'll 5470 * rewrite the mnemonic. 5471 */ 5472 if (strcmp(dp->it_name, "pclmulqdq") == 0) { 5473 boolean_t changed = B_TRUE; 5474 switch (x->d86_opnd[0].d86_value) { 5475 case 0x00: 5476 (void) strncpy(x->d86_mnem, "pclmullqlqdq", 5477 OPLEN); 5478 break; 5479 case 0x01: 5480 (void) strncpy(x->d86_mnem, "pclmulhqlqdq", 5481 OPLEN); 5482 break; 5483 case 0x10: 5484 (void) strncpy(x->d86_mnem, "pclmullqhqdq", 5485 OPLEN); 5486 break; 5487 case 0x11: 5488 (void) strncpy(x->d86_mnem, "pclmulhqhqdq", 5489 OPLEN); 5490 break; 5491 default: 5492 changed = B_FALSE; 5493 break; 5494 } 5495 5496 if (changed == B_TRUE) { 5497 x->d86_opnd[0].d86_value_size = 0; 5498 x->d86_opnd[0] = x->d86_opnd[1]; 5499 x->d86_opnd[1] = x->d86_opnd[2]; 5500 x->d86_numopnds = 2; 5501 } 5502 } 5503 #endif 5504 break; 5505 5506 case XMMX2I: 5507 FOUROPERAND(x, mode, reg, r_m, rex_prefix, XMM_OPND, XMM_OPND, 5508 1); 5509 NOMEM; 5510 break; 5511 5512 case XMM2I: 5513 ONEOPERAND_TWOIMM(x, mode, reg, r_m, rex_prefix, XMM_OPND, 1); 5514 NOMEM; 5515 break; 5516 5517 /* immediate operand to accumulator */ 5518 case IA: 5519 wbit = WBIT(opcode2); 5520 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5521 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, wbit), 0); 5522 NOMEM; 5523 break; 5524 5525 /* memory or register operand to accumulator */ 5526 case MA: 5527 wbit = WBIT(opcode2); 5528 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5529 dtrace_get_operand(x, mode, r_m, wbit, 0); 5530 break; 5531 5532 /* si register to di register used to reference memory */ 5533 case SD: 5534 #ifdef DIS_TEXT 5535 dtrace_check_override(x, 0); 5536 x->d86_numopnds = 2; 5537 if (addr_size == SIZE64) { 5538 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5539 OPLEN); 5540 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5541 OPLEN); 5542 } else if (addr_size == SIZE32) { 5543 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5544 OPLEN); 5545 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5546 OPLEN); 5547 } else { 5548 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5549 OPLEN); 5550 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5551 OPLEN); 5552 } 5553 #endif 5554 wbit = LONG_OPND; 5555 break; 5556 5557 /* accumulator to di register */ 5558 case AD: 5559 wbit = WBIT(opcode2); 5560 #ifdef DIS_TEXT 5561 dtrace_check_override(x, 1); 5562 x->d86_numopnds = 2; 5563 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 0); 5564 if (addr_size == SIZE64) 5565 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%rdi)", 5566 OPLEN); 5567 else if (addr_size == SIZE32) 5568 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%edi)", 5569 OPLEN); 5570 else 5571 (void) strlcat(x->d86_opnd[1].d86_opnd, "(%di)", 5572 OPLEN); 5573 #endif 5574 break; 5575 5576 /* si register to accumulator */ 5577 case SA: 5578 wbit = WBIT(opcode2); 5579 #ifdef DIS_TEXT 5580 dtrace_check_override(x, 0); 5581 x->d86_numopnds = 2; 5582 if (addr_size == SIZE64) 5583 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%rsi)", 5584 OPLEN); 5585 else if (addr_size == SIZE32) 5586 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%esi)", 5587 OPLEN); 5588 else 5589 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%si)", 5590 OPLEN); 5591 dtrace_get_operand(x, REG_ONLY, EAX_REGNO, wbit, 1); 5592 #endif 5593 break; 5594 5595 /* 5596 * single operand, a 16/32 bit displacement 5597 */ 5598 case D: 5599 wbit = LONG_OPND; 5600 dtrace_disp_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5601 NOMEM; 5602 break; 5603 5604 /* jmp/call indirect to memory or register operand */ 5605 case INM: 5606 #ifdef DIS_TEXT 5607 (void) strlcat(x->d86_opnd[0].d86_prefix, "*", OPLEN); 5608 #endif 5609 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5610 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 5611 wbit = LONG_OPND; 5612 break; 5613 5614 /* 5615 * for long jumps and long calls -- a new code segment 5616 * register and an offset in IP -- stored in object 5617 * code in reverse order. Note - not valid in amd64 5618 */ 5619 case SO: 5620 dtrace_check_override(x, 1); 5621 wbit = LONG_OPND; 5622 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 1); 5623 #ifdef DIS_TEXT 5624 x->d86_opnd[1].d86_mode = MODE_SIGNED; 5625 #endif 5626 /* will now get segment operand */ 5627 dtrace_imm_opnd(x, wbit, 2, 0); 5628 break; 5629 5630 /* 5631 * jmp/call. single operand, 8 bit displacement. 5632 * added to current EIP in 'compofff' 5633 */ 5634 case BD: 5635 dtrace_disp_opnd(x, BYTE_OPND, 1, 0); 5636 NOMEM; 5637 break; 5638 5639 /* single 32/16 bit immediate operand */ 5640 case I: 5641 wbit = LONG_OPND; 5642 dtrace_imm_opnd(x, wbit, OPSIZE(opnd_size, LONG_OPND), 0); 5643 break; 5644 5645 /* single 8 bit immediate operand */ 5646 case Ib: 5647 wbit = LONG_OPND; 5648 dtrace_imm_opnd(x, wbit, 1, 0); 5649 break; 5650 5651 case ENTER: 5652 wbit = LONG_OPND; 5653 dtrace_imm_opnd(x, wbit, 2, 0); 5654 dtrace_imm_opnd(x, wbit, 1, 1); 5655 switch (opnd_size) { 5656 case SIZE64: 5657 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 8; 5658 break; 5659 case SIZE32: 5660 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 4; 5661 break; 5662 case SIZE16: 5663 x->d86_memsize = (x->d86_opnd[1].d86_value + 1) * 2; 5664 break; 5665 } 5666 5667 break; 5668 5669 /* 16-bit immediate operand */ 5670 case RET: 5671 wbit = LONG_OPND; 5672 dtrace_imm_opnd(x, wbit, 2, 0); 5673 break; 5674 5675 /* single 8 bit port operand */ 5676 case P: 5677 dtrace_check_override(x, 0); 5678 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5679 NOMEM; 5680 break; 5681 5682 /* single operand, dx register (variable port instruction) */ 5683 case V: 5684 x->d86_numopnds = 1; 5685 dtrace_check_override(x, 0); 5686 #ifdef DIS_TEXT 5687 (void) strlcat(x->d86_opnd[0].d86_opnd, "(%dx)", OPLEN); 5688 #endif 5689 NOMEM; 5690 break; 5691 5692 /* 5693 * The int instruction, which has two forms: 5694 * int 3 (breakpoint) or 5695 * int n, where n is indicated in the subsequent 5696 * byte (format Ib). The int 3 instruction (opcode 0xCC), 5697 * where, although the 3 looks like an operand, 5698 * it is implied by the opcode. It must be converted 5699 * to the correct base and output. 5700 */ 5701 case INT3: 5702 #ifdef DIS_TEXT 5703 x->d86_numopnds = 1; 5704 x->d86_opnd[0].d86_mode = MODE_SIGNED; 5705 x->d86_opnd[0].d86_value_size = 1; 5706 x->d86_opnd[0].d86_value = 3; 5707 #endif 5708 NOMEM; 5709 break; 5710 5711 /* single 8 bit immediate operand */ 5712 case INTx: 5713 dtrace_imm_opnd(x, BYTE_OPND, 1, 0); 5714 NOMEM; 5715 break; 5716 5717 /* an unused byte must be discarded */ 5718 case U: 5719 if (x->d86_get_byte(x->d86_data) < 0) 5720 goto error; 5721 x->d86_len++; 5722 NOMEM; 5723 break; 5724 5725 case CBW: 5726 #ifdef DIS_TEXT 5727 if (opnd_size == SIZE16) 5728 (void) strlcat(x->d86_mnem, "cbtw", OPLEN); 5729 else if (opnd_size == SIZE32) 5730 (void) strlcat(x->d86_mnem, "cwtl", OPLEN); 5731 else 5732 (void) strlcat(x->d86_mnem, "cltq", OPLEN); 5733 #endif 5734 wbit = LONG_OPND; 5735 NOMEM; 5736 break; 5737 5738 case CWD: 5739 #ifdef DIS_TEXT 5740 if (opnd_size == SIZE16) 5741 (void) strlcat(x->d86_mnem, "cwtd", OPLEN); 5742 else if (opnd_size == SIZE32) 5743 (void) strlcat(x->d86_mnem, "cltd", OPLEN); 5744 else 5745 (void) strlcat(x->d86_mnem, "cqtd", OPLEN); 5746 #endif 5747 wbit = LONG_OPND; 5748 NOMEM; 5749 break; 5750 5751 case XMMSFNC: 5752 /* 5753 * sfence is sfence if mode is REG_ONLY. If mode isn't 5754 * REG_ONLY, mnemonic should be 'clflush'. 5755 */ 5756 dtrace_get_modrm(x, &mode, ®, &r_m); 5757 5758 /* sfence doesn't take operands */ 5759 if (mode != REG_ONLY) { 5760 if (opnd_size_prefix == 0x66) { 5761 #ifdef DIS_TEXT 5762 (void) strlcat(x->d86_mnem, "clflushopt", 5763 OPLEN); 5764 #endif 5765 } else if (opnd_size_prefix == 0) { 5766 #ifdef DIS_TEXT 5767 (void) strlcat(x->d86_mnem, "clflush", OPLEN); 5768 #endif 5769 } else { 5770 /* Unknown instruction */ 5771 goto error; 5772 } 5773 5774 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5775 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5776 NOMEM; 5777 #ifdef DIS_TEXT 5778 } else { 5779 (void) strlcat(x->d86_mnem, "sfence", OPLEN); 5780 #endif 5781 } 5782 break; 5783 5784 case FSGS: 5785 /* 5786 * The FSGSBASE instructions are taken only when the mode is set 5787 * to registers. They share opcodes with instructions like 5788 * fxrstor, stmxcsr, etc. We handle the repz prefix earlier. 5789 */ 5790 wbit = WBIT(opcode2); 5791 dtrace_get_modrm(x, &mode, ®, &r_m); 5792 dtrace_rex_adjust(rex_prefix, mode, NULL, &r_m); 5793 dtrace_get_operand(x, mode, r_m, wbit, 0); 5794 if (mode == REG_ONLY) { 5795 NOMEM; 5796 } 5797 break; 5798 5799 /* 5800 * no disassembly, the mnemonic was all there was so go on 5801 */ 5802 case NORM: 5803 if (dp->it_invalid32 && cpu_mode != SIZE64) 5804 goto error; 5805 NOMEM; 5806 /*FALLTHROUGH*/ 5807 case IMPLMEM: 5808 break; 5809 5810 case XMMFENCE: 5811 /* 5812 * XRSTOR, XSAVEOPT and LFENCE share the same opcode but 5813 * differ in mode and reg. 5814 */ 5815 dtrace_get_modrm(x, &mode, ®, &r_m); 5816 5817 if (mode == REG_ONLY) { 5818 /* 5819 * Only the following exact byte sequences are allowed: 5820 * 5821 * 0f ae e8 lfence 5822 * 0f ae f0 mfence 5823 */ 5824 if ((uint8_t)x->d86_bytes[x->d86_len - 1] != 0xe8 && 5825 (uint8_t)x->d86_bytes[x->d86_len - 1] != 0xf0) 5826 goto error; 5827 } else { 5828 #ifdef DIS_TEXT 5829 if (reg == 5) { 5830 (void) strncpy(x->d86_mnem, "xrstor", OPLEN); 5831 } else if (reg == 6) { 5832 if (opnd_size_prefix == 0x66) { 5833 (void) strncpy(x->d86_mnem, "clwb", 5834 OPLEN); 5835 } else if (opnd_size_prefix == 0x00) { 5836 (void) strncpy(x->d86_mnem, "xsaveopt", 5837 OPLEN); 5838 } else { 5839 goto error; 5840 } 5841 } else { 5842 goto error; 5843 } 5844 #endif 5845 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 5846 dtrace_get_operand(x, mode, r_m, BYTE_OPND, 0); 5847 } 5848 break; 5849 5850 /* float reg */ 5851 case F: 5852 #ifdef DIS_TEXT 5853 x->d86_numopnds = 1; 5854 (void) strlcat(x->d86_opnd[0].d86_opnd, "%st(X)", OPLEN); 5855 x->d86_opnd[0].d86_opnd[4] = r_m + '0'; 5856 #endif 5857 NOMEM; 5858 break; 5859 5860 /* float reg to float reg, with ret bit present */ 5861 case FF: 5862 vbit = opcode2 >> 2 & 0x1; /* vbit = 1: st -> st(i) */ 5863 /*FALLTHROUGH*/ 5864 case FFC: /* case for vbit always = 0 */ 5865 #ifdef DIS_TEXT 5866 x->d86_numopnds = 2; 5867 (void) strlcat(x->d86_opnd[1 - vbit].d86_opnd, "%st", OPLEN); 5868 (void) strlcat(x->d86_opnd[vbit].d86_opnd, "%st(X)", OPLEN); 5869 x->d86_opnd[vbit].d86_opnd[4] = r_m + '0'; 5870 #endif 5871 NOMEM; 5872 break; 5873 5874 /* AVX instructions */ 5875 case VEX_MO: 5876 /* op(ModR/M.r/m) */ 5877 x->d86_numopnds = 1; 5878 dtrace_get_modrm(x, &mode, ®, &r_m); 5879 #ifdef DIS_TEXT 5880 if ((dp == &dis_opAVX0F[0xA][0xE]) && (reg == 3)) 5881 (void) strncpy(x->d86_mnem, "vstmxcsr", OPLEN); 5882 #endif 5883 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5884 dtrace_get_operand(x, mode, r_m, wbit, 0); 5885 break; 5886 case VEX_RMrX: 5887 case FMA: 5888 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r/m) */ 5889 x->d86_numopnds = 3; 5890 dtrace_get_modrm(x, &mode, ®, &r_m); 5891 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5892 5893 /* 5894 * In classic Intel fashion, the opcodes for all of the FMA 5895 * instructions all have two possible mnemonics which vary by 5896 * one letter, which is selected based on the value of the wbit. 5897 * When wbit is one, they have the 'd' suffix and when 'wbit' is 5898 * 0, they have the 's' suffix. Otherwise, the FMA instructions 5899 * are all a standard VEX_RMrX. 5900 */ 5901 #ifdef DIS_TEXT 5902 if (dp->it_adrmode == FMA) { 5903 size_t len = strlen(dp->it_name); 5904 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5905 if (len + 1 < OPLEN) { 5906 (void) strncpy(x->d86_mnem + len, 5907 vex_W != 0 ? "d" : "s", OPLEN - len); 5908 } 5909 } 5910 #endif 5911 5912 if (mode != REG_ONLY) { 5913 if ((dp == &dis_opAVXF20F[0x10]) || 5914 (dp == &dis_opAVXF30F[0x10])) { 5915 /* vmovsd <m64>, <xmm> */ 5916 /* or vmovss <m64>, <xmm> */ 5917 x->d86_numopnds = 2; 5918 goto L_VEX_MX; 5919 } 5920 } 5921 5922 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5923 /* 5924 * VEX prefix uses the 1's complement form to encode the 5925 * XMM/YMM regs 5926 */ 5927 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 5928 5929 if ((dp == &dis_opAVXF20F[0x2A]) || 5930 (dp == &dis_opAVXF30F[0x2A])) { 5931 /* 5932 * vcvtsi2si </r,m>, <xmm>, <xmm> or vcvtsi2ss </r,m>, 5933 * <xmm>, <xmm> 5934 */ 5935 wbit = LONG_OPND; 5936 } 5937 #ifdef DIS_TEXT 5938 else if ((mode == REG_ONLY) && 5939 (dp == &dis_opAVX0F[0x1][0x6])) { /* vmovlhps */ 5940 (void) strncpy(x->d86_mnem, "vmovlhps", OPLEN); 5941 } else if ((mode == REG_ONLY) && 5942 (dp == &dis_opAVX0F[0x1][0x2])) { /* vmovhlps */ 5943 (void) strncpy(x->d86_mnem, "vmovhlps", OPLEN); 5944 } 5945 #endif 5946 dtrace_get_operand(x, mode, r_m, wbit, 0); 5947 5948 break; 5949 5950 case VEX_VRMrX: 5951 /* ModR/M.reg := op(MODR/M.r/m, VEX.vvvv) */ 5952 x->d86_numopnds = 3; 5953 dtrace_get_modrm(x, &mode, ®, &r_m); 5954 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5955 5956 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 5957 /* 5958 * VEX prefix uses the 1's complement form to encode the 5959 * XMM/YMM regs 5960 */ 5961 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 0); 5962 5963 dtrace_get_operand(x, mode, r_m, wbit, 1); 5964 break; 5965 5966 case VEX_SbVM: 5967 /* ModR/M.reg := op(MODR/M.r/m, VSIB, VEX.vvvv) */ 5968 x->d86_numopnds = 3; 5969 x->d86_vsib = 1; 5970 5971 /* 5972 * All instructions that use VSIB are currently a mess. See the 5973 * comment around the dis_gather_regs_t structure definition. 5974 */ 5975 5976 vreg = &dis_vgather[opcode2][vex_W][vex_L]; 5977 5978 #ifdef DIS_TEXT 5979 (void) strncpy(x->d86_mnem, dp->it_name, OPLEN); 5980 (void) strlcat(x->d86_mnem + strlen(dp->it_name), 5981 vreg->dgr_suffix, OPLEN - strlen(dp->it_name)); 5982 #endif 5983 5984 dtrace_get_modrm(x, &mode, ®, &r_m); 5985 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 5986 5987 dtrace_get_operand(x, REG_ONLY, reg, vreg->dgr_arg2, 2); 5988 /* 5989 * VEX prefix uses the 1's complement form to encode the 5990 * XMM/YMM regs 5991 */ 5992 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), vreg->dgr_arg0, 5993 0); 5994 dtrace_get_operand(x, mode, r_m, vreg->dgr_arg1, 1); 5995 break; 5996 5997 case VEX_RRX: 5998 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 5999 x->d86_numopnds = 3; 6000 6001 dtrace_get_modrm(x, &mode, ®, &r_m); 6002 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6003 6004 if (mode != REG_ONLY) { 6005 if ((dp == &dis_opAVXF20F[0x11]) || 6006 (dp == &dis_opAVXF30F[0x11])) { 6007 /* vmovsd <xmm>, <m64> */ 6008 /* or vmovss <xmm>, <m64> */ 6009 x->d86_numopnds = 2; 6010 goto L_VEX_RM; 6011 } 6012 } 6013 6014 dtrace_get_operand(x, mode, r_m, wbit, 2); 6015 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6016 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6017 break; 6018 6019 case VEX_RMRX: 6020 /* ModR/M.reg := op(VEX.vvvv, ModR/M.r_m, imm8[7:4]) */ 6021 x->d86_numopnds = 4; 6022 6023 dtrace_get_modrm(x, &mode, ®, &r_m); 6024 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6025 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 6026 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 6027 if (dp == &dis_opAVX660F3A[0x18]) { 6028 /* vinsertf128 <imm8>, <xmm>, <ymm>, <ymm> */ 6029 dtrace_get_operand(x, mode, r_m, XMM_OPND, 1); 6030 } else if ((dp == &dis_opAVX660F3A[0x20]) || 6031 (dp == & dis_opAVX660F[0xC4])) { 6032 /* vpinsrb <imm8>, <reg/mm>, <xmm>, <xmm> */ 6033 /* or vpinsrw <imm8>, <reg/mm>, <xmm>, <xmm> */ 6034 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6035 } else if (dp == &dis_opAVX660F3A[0x22]) { 6036 /* vpinsrd/q <imm8>, <reg/mm>, <xmm>, <xmm> */ 6037 #ifdef DIS_TEXT 6038 if (vex_W) 6039 x->d86_mnem[6] = 'q'; 6040 #endif 6041 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6042 } else { 6043 dtrace_get_operand(x, mode, r_m, wbit, 1); 6044 } 6045 6046 /* one byte immediate number */ 6047 dtrace_imm_opnd(x, wbit, 1, 0); 6048 6049 /* vblendvpd, vblendvps, vblendvb use the imm encode the regs */ 6050 if ((dp == &dis_opAVX660F3A[0x4A]) || 6051 (dp == &dis_opAVX660F3A[0x4B]) || 6052 (dp == &dis_opAVX660F3A[0x4C])) { 6053 #ifdef DIS_TEXT 6054 int regnum = (x->d86_opnd[0].d86_value & 0xF0) >> 4; 6055 #endif 6056 x->d86_opnd[0].d86_mode = MODE_NONE; 6057 #ifdef DIS_TEXT 6058 if (vex_L) 6059 (void) strncpy(x->d86_opnd[0].d86_opnd, 6060 dis_YMMREG[regnum], OPLEN); 6061 else 6062 (void) strncpy(x->d86_opnd[0].d86_opnd, 6063 dis_XMMREG[regnum], OPLEN); 6064 #endif 6065 } 6066 break; 6067 6068 case VEX_MX: 6069 /* ModR/M.reg := op(ModR/M.rm) */ 6070 x->d86_numopnds = 2; 6071 6072 dtrace_get_modrm(x, &mode, ®, &r_m); 6073 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6074 L_VEX_MX: 6075 6076 if ((dp == &dis_opAVXF20F[0xE6]) || 6077 (dp == &dis_opAVX660F[0x5A]) || 6078 (dp == &dis_opAVX660F[0xE6])) { 6079 /* vcvtpd2dq <ymm>, <xmm> */ 6080 /* or vcvtpd2ps <ymm>, <xmm> */ 6081 /* or vcvttpd2dq <ymm>, <xmm> */ 6082 dtrace_get_operand(x, REG_ONLY, reg, XMM_OPND, 1); 6083 dtrace_get_operand(x, mode, r_m, wbit, 0); 6084 } else if ((dp == &dis_opAVXF30F[0xE6]) || 6085 (dp == &dis_opAVX0F[0x5][0xA]) || 6086 (dp == &dis_opAVX660F38[0x13]) || 6087 (dp == &dis_opAVX660F38[0x18]) || 6088 (dp == &dis_opAVX660F38[0x19]) || 6089 (dp == &dis_opAVX660F38[0x58]) || 6090 (dp == &dis_opAVX660F38[0x78]) || 6091 (dp == &dis_opAVX660F38[0x79]) || 6092 (dp == &dis_opAVX660F38[0x59])) { 6093 /* vcvtdq2pd <xmm>, <ymm> */ 6094 /* or vcvtps2pd <xmm>, <ymm> */ 6095 /* or vcvtph2ps <xmm>, <ymm> */ 6096 /* or vbroadcasts* <xmm>, <ymm> */ 6097 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6098 dtrace_get_operand(x, mode, r_m, XMM_OPND, 0); 6099 } else if (dp == &dis_opAVX660F[0x6E]) { 6100 /* vmovd/q <reg/mem 32/64>, <xmm> */ 6101 #ifdef DIS_TEXT 6102 if (vex_W) 6103 x->d86_mnem[4] = 'q'; 6104 #endif 6105 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6106 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 6107 } else { 6108 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6109 dtrace_get_operand(x, mode, r_m, wbit, 0); 6110 } 6111 6112 break; 6113 6114 case VEX_MXI: 6115 /* ModR/M.reg := op(ModR/M.rm, imm8) */ 6116 x->d86_numopnds = 3; 6117 6118 dtrace_get_modrm(x, &mode, ®, &r_m); 6119 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6120 6121 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6122 dtrace_get_operand(x, mode, r_m, wbit, 1); 6123 6124 /* one byte immediate number */ 6125 dtrace_imm_opnd(x, wbit, 1, 0); 6126 break; 6127 6128 case VEX_XXI: 6129 /* VEX.vvvv := op(ModR/M.rm, imm8) */ 6130 x->d86_numopnds = 3; 6131 6132 dtrace_get_modrm(x, &mode, ®, &r_m); 6133 #ifdef DIS_TEXT 6134 (void) strncpy(x->d86_mnem, dis_AVXvgrp7[opcode2 - 1][reg], 6135 OPLEN); 6136 #endif 6137 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6138 6139 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 6140 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 1); 6141 6142 /* one byte immediate number */ 6143 dtrace_imm_opnd(x, wbit, 1, 0); 6144 break; 6145 6146 case VEX_MR: 6147 /* ModR/M.reg (reg32/64) := op(ModR/M.rm) */ 6148 if (dp == &dis_opAVX660F[0xC5]) { 6149 /* vpextrw <imm8>, <xmm>, <reg> */ 6150 x->d86_numopnds = 2; 6151 vbit = 2; 6152 } else { 6153 x->d86_numopnds = 2; 6154 vbit = 1; 6155 } 6156 6157 dtrace_get_modrm(x, &mode, ®, &r_m); 6158 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6159 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, vbit); 6160 dtrace_get_operand(x, mode, r_m, wbit, vbit - 1); 6161 6162 if (vbit == 2) 6163 dtrace_imm_opnd(x, wbit, 1, 0); 6164 6165 break; 6166 6167 case VEX_KMR: 6168 /* opmask: mod_rm := %k */ 6169 x->d86_numopnds = 2; 6170 dtrace_get_modrm(x, &mode, ®, &r_m); 6171 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6172 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6173 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6174 break; 6175 6176 case VEX_KRM: 6177 /* opmask: mod_reg := mod_rm */ 6178 x->d86_numopnds = 2; 6179 dtrace_get_modrm(x, &mode, ®, &r_m); 6180 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6181 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6182 if (mode == REG_ONLY) { 6183 dtrace_get_operand(x, mode, r_m, KOPMASK_OPND, 0); 6184 } else { 6185 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 6186 } 6187 break; 6188 6189 case VEX_KRR: 6190 /* opmask: mod_reg := mod_rm */ 6191 x->d86_numopnds = 2; 6192 dtrace_get_modrm(x, &mode, ®, &r_m); 6193 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6194 dtrace_get_operand(x, mode, reg, wbit, 1); 6195 dtrace_get_operand(x, REG_ONLY, r_m, LONG_OPND, 0); 6196 break; 6197 6198 case VEX_RRI: 6199 /* implicit(eflags/r32) := op(ModR/M.reg, ModR/M.rm) */ 6200 x->d86_numopnds = 2; 6201 6202 dtrace_get_modrm(x, &mode, ®, &r_m); 6203 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6204 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6205 dtrace_get_operand(x, mode, r_m, wbit, 0); 6206 break; 6207 6208 case VEX_RX: 6209 /* ModR/M.rm := op(ModR/M.reg) */ 6210 /* vextractf128 || vcvtps2ph */ 6211 if (dp == &dis_opAVX660F3A[0x19] || 6212 dp == &dis_opAVX660F3A[0x1d]) { 6213 x->d86_numopnds = 3; 6214 6215 dtrace_get_modrm(x, &mode, ®, &r_m); 6216 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6217 6218 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 6219 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6220 6221 /* one byte immediate number */ 6222 dtrace_imm_opnd(x, wbit, 1, 0); 6223 break; 6224 } 6225 6226 x->d86_numopnds = 2; 6227 6228 dtrace_get_modrm(x, &mode, ®, &r_m); 6229 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6230 dtrace_get_operand(x, mode, r_m, wbit, 1); 6231 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6232 break; 6233 6234 case VEX_RR: 6235 /* ModR/M.rm := op(ModR/M.reg) */ 6236 x->d86_numopnds = 2; 6237 6238 dtrace_get_modrm(x, &mode, ®, &r_m); 6239 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6240 6241 if (dp == &dis_opAVX660F[0x7E]) { 6242 /* vmovd/q <reg/mem 32/64>, <xmm> */ 6243 #ifdef DIS_TEXT 6244 if (vex_W) 6245 x->d86_mnem[4] = 'q'; 6246 #endif 6247 dtrace_get_operand(x, mode, r_m, LONG_OPND, 1); 6248 } else 6249 dtrace_get_operand(x, mode, r_m, wbit, 1); 6250 6251 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6252 break; 6253 6254 case VEX_RRi: 6255 /* ModR/M.rm := op(ModR/M.reg, imm) */ 6256 x->d86_numopnds = 3; 6257 6258 dtrace_get_modrm(x, &mode, ®, &r_m); 6259 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6260 6261 #ifdef DIS_TEXT 6262 if (dp == &dis_opAVX660F3A[0x16]) { 6263 /* vpextrd/q <imm>, <xmm>, <reg/mem 32/64> */ 6264 if (vex_W) 6265 x->d86_mnem[6] = 'q'; 6266 } 6267 #endif 6268 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 6269 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6270 6271 /* one byte immediate number */ 6272 dtrace_imm_opnd(x, wbit, 1, 0); 6273 break; 6274 case VEX_RIM: 6275 /* ModR/M.rm := op(ModR/M.reg, imm) */ 6276 x->d86_numopnds = 3; 6277 6278 dtrace_get_modrm(x, &mode, ®, &r_m); 6279 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6280 6281 dtrace_get_operand(x, mode, r_m, XMM_OPND, 2); 6282 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6283 /* one byte immediate number */ 6284 dtrace_imm_opnd(x, wbit, 1, 0); 6285 break; 6286 6287 case VEX_RM: 6288 /* ModR/M.rm := op(ModR/M.reg) */ 6289 if (dp == &dis_opAVX660F3A[0x17]) { /* vextractps */ 6290 x->d86_numopnds = 3; 6291 6292 dtrace_get_modrm(x, &mode, ®, &r_m); 6293 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6294 6295 dtrace_get_operand(x, mode, r_m, LONG_OPND, 2); 6296 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6297 /* one byte immediate number */ 6298 dtrace_imm_opnd(x, wbit, 1, 0); 6299 break; 6300 } 6301 x->d86_numopnds = 2; 6302 6303 dtrace_get_modrm(x, &mode, ®, &r_m); 6304 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6305 L_VEX_RM: 6306 vbit = 1; 6307 dtrace_get_operand(x, mode, r_m, wbit, vbit); 6308 dtrace_get_operand(x, REG_ONLY, reg, wbit, vbit - 1); 6309 6310 break; 6311 6312 case VEX_RRM: 6313 /* ModR/M.rm := op(VEX.vvvv, ModR/M.reg) */ 6314 x->d86_numopnds = 3; 6315 6316 dtrace_get_modrm(x, &mode, ®, &r_m); 6317 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6318 dtrace_get_operand(x, mode, r_m, wbit, 2); 6319 /* VEX use the 1's complement form encode the XMM/YMM regs */ 6320 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6321 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6322 break; 6323 6324 case VEX_RMX: 6325 /* ModR/M.reg := op(VEX.vvvv, ModR/M.rm) */ 6326 x->d86_numopnds = 3; 6327 6328 dtrace_get_modrm(x, &mode, ®, &r_m); 6329 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6330 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6331 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6332 dtrace_get_operand(x, REG_ONLY, r_m, wbit, 0); 6333 break; 6334 6335 case VEX_NONE: 6336 #ifdef DIS_TEXT 6337 if (vex_L) 6338 (void) strncpy(x->d86_mnem, "vzeroall", OPLEN); 6339 #endif 6340 break; 6341 case BLS: { 6342 6343 /* 6344 * The BLS instructions are VEX instructions that are based on 6345 * VEX.0F38.F3; however, they are considered special group 17 6346 * and like everything else, they use the bits in 3-5 of the 6347 * MOD R/M to determine the sub instruction. Unlike many others 6348 * like the VMX instructions, these are valid both for memory 6349 * and register forms. 6350 */ 6351 6352 dtrace_get_modrm(x, &mode, ®, &r_m); 6353 dtrace_vex_adjust(vex_byte1, mode, ®, &r_m); 6354 6355 switch (reg) { 6356 case 1: 6357 #ifdef DIS_TEXT 6358 blsinstr = "blsr"; 6359 #endif 6360 break; 6361 case 2: 6362 #ifdef DIS_TEXT 6363 blsinstr = "blsmsk"; 6364 #endif 6365 break; 6366 case 3: 6367 #ifdef DIS_TEXT 6368 blsinstr = "blsi"; 6369 #endif 6370 break; 6371 default: 6372 goto error; 6373 } 6374 6375 x->d86_numopnds = 2; 6376 #ifdef DIS_TEXT 6377 (void) strncpy(x->d86_mnem, blsinstr, OPLEN); 6378 #endif 6379 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6380 dtrace_get_operand(x, mode, r_m, wbit, 0); 6381 break; 6382 } 6383 case EVEX_MX: 6384 /* ModR/M.reg := op(ModR/M.rm) */ 6385 x->d86_numopnds = 2; 6386 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6387 dtrace_get_modrm(x, &mode, ®, &r_m); 6388 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6389 dtrace_evex_adjust_reg(evex_byte1, ®); 6390 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6391 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6392 dtrace_get_operand(x, REG_ONLY, reg, wbit, 1); 6393 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 6394 dtrace_get_operand(x, mode, r_m, wbit, 0); 6395 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6396 break; 6397 case EVEX_RX: 6398 /* ModR/M.rm := op(ModR/M.reg) */ 6399 x->d86_numopnds = 2; 6400 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6401 dtrace_get_modrm(x, &mode, ®, &r_m); 6402 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6403 dtrace_evex_adjust_reg(evex_byte1, ®); 6404 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6405 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6406 dtrace_get_operand(x, mode, r_m, wbit, 1); 6407 dtrace_evex_adjust_disp8_n(x, 1, evex_L, evex_modrm); 6408 dtrace_evex_adjust_z_opmask(x, 1, evex_byte3); 6409 dtrace_get_operand(x, REG_ONLY, reg, wbit, 0); 6410 break; 6411 case EVEX_RMrX: 6412 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r/m) */ 6413 x->d86_numopnds = 3; 6414 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6415 dtrace_get_modrm(x, &mode, ®, &r_m); 6416 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6417 dtrace_evex_adjust_reg(evex_byte1, ®); 6418 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6419 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6420 dtrace_get_operand(x, REG_ONLY, reg, wbit, 2); 6421 /* 6422 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 6423 * register specifier). The EVEX prefix handling uses the vex_v 6424 * variable for these bits. 6425 */ 6426 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 1); 6427 dtrace_get_operand(x, mode, r_m, wbit, 0); 6428 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6429 dtrace_evex_adjust_z_opmask(x, 2, evex_byte3); 6430 break; 6431 case EVEX_RMRX: 6432 /* ModR/M.reg := op(EVEX.vvvv, ModR/M.r_m, imm8) */ 6433 x->d86_numopnds = 4; 6434 6435 dtrace_evex_mnem_adjust(x, dp, vex_W, evex_byte2); 6436 dtrace_get_modrm(x, &mode, ®, &r_m); 6437 evex_modrm = x->d86_bytes[x->d86_len - 1] & 0xff; 6438 dtrace_evex_adjust_reg(evex_byte1, ®); 6439 dtrace_evex_adjust_rm(evex_byte1, &r_m); 6440 dtrace_evex_adjust_reg_name(evex_L, &wbit); 6441 dtrace_get_operand(x, REG_ONLY, reg, wbit, 3); 6442 /* 6443 * EVEX.vvvv is the same as VEX.vvvv (ones complement of the 6444 * register specifier). The EVEX prefix handling uses the vex_v 6445 * variable for these bits. 6446 */ 6447 dtrace_get_operand(x, REG_ONLY, (0xF - vex_v), wbit, 2); 6448 dtrace_get_operand(x, mode, r_m, wbit, 1); 6449 dtrace_evex_adjust_disp8_n(x, 0, evex_L, evex_modrm); 6450 dtrace_evex_adjust_z_opmask(x, 3, evex_byte3); 6451 6452 dtrace_imm_opnd(x, wbit, 1, 0); 6453 break; 6454 case MOVDIR: 6455 /* 6456 * The semantics of the movdir64b instruction is a little bit 6457 * weird and we need to trick the rest of the engine. In this 6458 * case we change d86_mode to match the operand/address size 6459 * that we overrode to earlier. Basically the standard CPU mode 6460 * doesn't actually influence which register set is used, but 6461 * the 0x67 prefix does. 6462 */ 6463 x->d86_numopnds = 2; 6464 x->d86_mode = x->d86_opnd_size; 6465 dtrace_get_modrm(x, &mode, ®, &r_m); 6466 dtrace_rex_adjust(rex_prefix, mode, ®, &r_m); 6467 dtrace_get_operand(x, REG_ONLY, reg, LONG_OPND, 1); 6468 dtrace_get_operand(x, mode, r_m, LONG_OPND, 0); 6469 break; 6470 /* an invalid op code */ 6471 case AM: 6472 case DM: 6473 case OVERRIDE: 6474 case PREFIX: 6475 case UNKNOWN: 6476 NOMEM; 6477 default: 6478 goto error; 6479 } /* end switch */ 6480 if (x->d86_error) 6481 goto error; 6482 6483 done: 6484 #ifdef DIS_MEM 6485 if (dp == NULL) 6486 return (1); 6487 /* 6488 * compute the size of any memory accessed by the instruction 6489 */ 6490 if (x->d86_memsize != 0) { 6491 return (0); 6492 } else if (dp->it_stackop) { 6493 switch (opnd_size) { 6494 case SIZE16: 6495 x->d86_memsize = 2; 6496 break; 6497 case SIZE32: 6498 x->d86_memsize = 4; 6499 break; 6500 case SIZE64: 6501 x->d86_memsize = 8; 6502 break; 6503 } 6504 } else if (nomem || mode == REG_ONLY) { 6505 x->d86_memsize = 0; 6506 6507 } else if (dp->it_size != 0) { 6508 /* 6509 * In 64 bit mode descriptor table entries 6510 * go up to 10 bytes and popf/pushf are always 8 bytes 6511 */ 6512 if (x->d86_mode == SIZE64 && dp->it_size == 6) 6513 x->d86_memsize = 10; 6514 else if (x->d86_mode == SIZE64 && opcode1 == 0x9 && 6515 (opcode2 == 0xc || opcode2 == 0xd)) 6516 x->d86_memsize = 8; 6517 else 6518 x->d86_memsize = dp->it_size; 6519 6520 } else if (wbit == 0) { 6521 x->d86_memsize = 1; 6522 6523 } else if (wbit == LONG_OPND) { 6524 if (opnd_size == SIZE64) 6525 x->d86_memsize = 8; 6526 else if (opnd_size == SIZE32) 6527 x->d86_memsize = 4; 6528 else 6529 x->d86_memsize = 2; 6530 6531 } else if (wbit == SEG_OPND) { 6532 x->d86_memsize = 4; 6533 6534 } else { 6535 x->d86_memsize = 8; 6536 } 6537 #endif 6538 return (0); 6539 6540 error: 6541 #ifdef DIS_TEXT 6542 (void) strlcat(x->d86_mnem, "undef", OPLEN); 6543 #endif 6544 return (1); 6545 } 6546 6547 #ifdef DIS_TEXT 6548 6549 /* 6550 * Some instructions should have immediate operands printed 6551 * as unsigned integers. We compare against this table. 6552 */ 6553 static char *unsigned_ops[] = { 6554 "or", "and", "xor", "test", "in", "out", "lcall", "ljmp", 6555 "rcr", "rcl", "ror", "rol", "shl", "shr", "sal", "psr", "psl", 6556 0 6557 }; 6558 6559 6560 static int 6561 isunsigned_op(char *opcode) 6562 { 6563 char *where; 6564 int i; 6565 int is_unsigned = 0; 6566 6567 /* 6568 * Work back to start of last mnemonic, since we may have 6569 * prefixes on some opcodes. 6570 */ 6571 where = opcode + strlen(opcode) - 1; 6572 while (where > opcode && *where != ' ') 6573 --where; 6574 if (*where == ' ') 6575 ++where; 6576 6577 for (i = 0; unsigned_ops[i]; ++i) { 6578 if (strncmp(where, unsigned_ops[i], 6579 strlen(unsigned_ops[i]))) 6580 continue; 6581 is_unsigned = 1; 6582 break; 6583 } 6584 return (is_unsigned); 6585 } 6586 6587 /* 6588 * Print a numeric immediate into end of buf, maximum length buflen. 6589 * The immediate may be an address or a displacement. Mask is set 6590 * for address size. If the immediate is a "small negative", or 6591 * if it's a negative displacement of any magnitude, print as -<absval>. 6592 * Respect the "octal" flag. "Small negative" is defined as "in the 6593 * interval [NEG_LIMIT, 0)". 6594 * 6595 * Also, "isunsigned_op()" instructions never print negatives. 6596 * 6597 * Return whether we decided to print a negative value or not. 6598 */ 6599 6600 #define NEG_LIMIT -255 6601 enum {IMM, DISP}; 6602 enum {POS, TRY_NEG}; 6603 6604 static int 6605 print_imm(dis86_t *dis, uint64_t usv, uint64_t mask, char *buf, 6606 size_t buflen, int disp, int try_neg) 6607 { 6608 int curlen; 6609 int64_t sv = (int64_t)usv; 6610 int octal = dis->d86_flags & DIS_F_OCTAL; 6611 6612 curlen = strlen(buf); 6613 6614 if (try_neg == TRY_NEG && sv < 0 && 6615 (disp || sv >= NEG_LIMIT) && 6616 !isunsigned_op(dis->d86_mnem)) { 6617 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6618 octal ? "-0%llo" : "-0x%llx", (-sv) & mask); 6619 return (1); 6620 } else { 6621 if (disp == DISP) 6622 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6623 octal ? "+0%llo" : "+0x%llx", usv & mask); 6624 else 6625 dis->d86_sprintf_func(buf + curlen, buflen - curlen, 6626 octal ? "0%llo" : "0x%llx", usv & mask); 6627 return (0); 6628 6629 } 6630 } 6631 6632 6633 static int 6634 log2(int size) 6635 { 6636 switch (size) { 6637 case 1: return (0); 6638 case 2: return (1); 6639 case 4: return (2); 6640 case 8: return (3); 6641 } 6642 return (0); 6643 } 6644 6645 /* ARGSUSED */ 6646 void 6647 dtrace_disx86_str(dis86_t *dis, uint_t mode, uint64_t pc, char *buf, 6648 size_t buflen) 6649 { 6650 uint64_t reltgt = 0; 6651 uint64_t tgt = 0; 6652 int curlen; 6653 int (*lookup)(void *, uint64_t, char *, size_t); 6654 int i; 6655 int64_t sv; 6656 uint64_t usv, mask, save_mask, save_usv; 6657 static uint64_t masks[] = 6658 {0xffU, 0xffffU, 0xffffffffU, 0xffffffffffffffffULL}; 6659 save_usv = 0; 6660 6661 dis->d86_sprintf_func(buf, buflen, "%-6s ", dis->d86_mnem); 6662 6663 /* 6664 * For PC-relative jumps, the pc is really the next pc after executing 6665 * this instruction, so increment it appropriately. 6666 */ 6667 pc += dis->d86_len; 6668 6669 for (i = 0; i < dis->d86_numopnds; i++) { 6670 d86opnd_t *op = &dis->d86_opnd[i]; 6671 6672 if (i != 0) 6673 (void) strlcat(buf, ",", buflen); 6674 6675 (void) strlcat(buf, op->d86_prefix, buflen); 6676 6677 /* 6678 * sv is for the signed, possibly-truncated immediate or 6679 * displacement; usv retains the original size and 6680 * unsignedness for symbol lookup. 6681 */ 6682 6683 sv = usv = op->d86_value; 6684 6685 /* 6686 * About masks: for immediates that represent 6687 * addresses, the appropriate display size is 6688 * the effective address size of the instruction. 6689 * This includes MODE_OFFSET, MODE_IPREL, and 6690 * MODE_RIPREL. Immediates that are simply 6691 * immediate values should display in the operand's 6692 * size, however, since they don't represent addresses. 6693 */ 6694 6695 /* d86_addr_size is SIZEnn, which is log2(real size) */ 6696 mask = masks[dis->d86_addr_size]; 6697 6698 /* d86_value_size and d86_imm_bytes are in bytes */ 6699 if (op->d86_mode == MODE_SIGNED || 6700 op->d86_mode == MODE_IMPLIED) 6701 mask = masks[log2(op->d86_value_size)]; 6702 6703 switch (op->d86_mode) { 6704 6705 case MODE_NONE: 6706 6707 (void) strlcat(buf, op->d86_opnd, buflen); 6708 break; 6709 6710 case MODE_SIGNED: 6711 case MODE_IMPLIED: 6712 case MODE_OFFSET: 6713 6714 tgt = usv; 6715 6716 if (dis->d86_seg_prefix) 6717 (void) strlcat(buf, dis->d86_seg_prefix, 6718 buflen); 6719 6720 if (op->d86_mode == MODE_SIGNED || 6721 op->d86_mode == MODE_IMPLIED) { 6722 (void) strlcat(buf, "$", buflen); 6723 } 6724 6725 if (print_imm(dis, usv, mask, buf, buflen, 6726 IMM, TRY_NEG) && 6727 (op->d86_mode == MODE_SIGNED || 6728 op->d86_mode == MODE_IMPLIED)) { 6729 6730 /* 6731 * We printed a negative value for an 6732 * immediate that wasn't a 6733 * displacement. Note that fact so we can 6734 * print the positive value as an 6735 * annotation. 6736 */ 6737 6738 save_usv = usv; 6739 save_mask = mask; 6740 } 6741 (void) strlcat(buf, op->d86_opnd, buflen); 6742 break; 6743 6744 case MODE_IPREL: 6745 case MODE_RIPREL: 6746 6747 reltgt = pc + sv; 6748 6749 switch (mode) { 6750 case SIZE16: 6751 reltgt = (uint16_t)reltgt; 6752 break; 6753 case SIZE32: 6754 reltgt = (uint32_t)reltgt; 6755 break; 6756 } 6757 6758 (void) print_imm(dis, usv, mask, buf, buflen, 6759 DISP, TRY_NEG); 6760 6761 if (op->d86_mode == MODE_RIPREL) 6762 (void) strlcat(buf, "(%rip)", buflen); 6763 break; 6764 } 6765 } 6766 6767 /* 6768 * The symbol lookups may result in false positives, 6769 * particularly on object files, where small numbers may match 6770 * the 0-relative non-relocated addresses of symbols. 6771 */ 6772 6773 lookup = dis->d86_sym_lookup; 6774 if (tgt != 0) { 6775 if ((dis->d86_flags & DIS_F_NOIMMSYM) == 0 && 6776 lookup(dis->d86_data, tgt, NULL, 0) == 0) { 6777 (void) strlcat(buf, "\t<", buflen); 6778 curlen = strlen(buf); 6779 lookup(dis->d86_data, tgt, buf + curlen, 6780 buflen - curlen); 6781 (void) strlcat(buf, ">", buflen); 6782 } 6783 6784 /* 6785 * If we printed a negative immediate above, print the 6786 * positive in case our heuristic was unhelpful 6787 */ 6788 if (save_usv) { 6789 (void) strlcat(buf, "\t<", buflen); 6790 (void) print_imm(dis, save_usv, save_mask, buf, buflen, 6791 IMM, POS); 6792 (void) strlcat(buf, ">", buflen); 6793 } 6794 } 6795 6796 if (reltgt != 0) { 6797 /* Print symbol or effective address for reltgt */ 6798 6799 (void) strlcat(buf, "\t<", buflen); 6800 curlen = strlen(buf); 6801 lookup(dis->d86_data, reltgt, buf + curlen, 6802 buflen - curlen); 6803 (void) strlcat(buf, ">", buflen); 6804 } 6805 } 6806 6807 #endif /* DIS_TEXT */ 6808