1 /* 2 * This file and its contents are supplied under the terms of the 3 * Common Development and Distribution License ("CDDL"), version 1.0. 4 * You may only use this file in accordance with the terms of version 5 * 1.0 of the CDDL. 6 * 7 * A full copy of the text of the CDDL should have accompanied this 8 * source. A copy of the CDDL is also available via the Internet at 9 * http://www.illumos.org/license/CDDL. 10 */ 11 12 /* 13 * Copyright 2023 Toomas Soome <tsoome@me.com> 14 */ 15 16 #include <sys/types.h> 17 #include <sys/sysmacros.h> 18 #include "codes.h" 19 20 #if defined(__x86) 21 22 /* vmm_dev.h is expecting to have the types below. */ 23 typedef uint64_t vm_paddr_t; 24 typedef int64_t vm_ooffset_t; 25 #include <sys/vmm_dev.h> 26 27 /* VMM ioctls */ 28 const struct ioc vmmctl_ioc[] = { 29 { (uint_t)VMM_CREATE_VM, "VMM_CREATE_VM", NULL }, 30 { (uint_t)VMM_DESTROY_VM, "VMM_DESTROY_VM", NULL }, 31 { (uint_t)VMM_VM_SUPPORTED, "VMM_VM_SUPPORTED", NULL }, 32 33 { (uint_t)VMM_RESV_QUERY, "VMM_RESV_QUERY", NULL }, 34 { (uint_t)VMM_RESV_SET_TARGET, "VMM_RESV_SET_TARGET", NULL } 35 }; 36 37 const struct ioc vmm_cpu_ioc[] = { 38 { (uint_t)VM_RUN, "VM_RUN", NULL }, 39 { (uint_t)VM_SET_REGISTER, "VM_SET_REGISTER", NULL }, 40 { (uint_t)VM_GET_REGISTER, "VM_GET_REGISTER", NULL }, 41 { (uint_t)VM_SET_SEGMENT_DESCRIPTOR, "VM_SET_SEGMENT_DESCRIPTOR", 42 NULL }, 43 { (uint_t)VM_GET_SEGMENT_DESCRIPTOR, "VM_GET_SEGMENT_DESCRIPTOR", 44 NULL }, 45 { (uint_t)VM_SET_REGISTER_SET, "VM_SET_REGISTER_SET", NULL }, 46 { (uint_t)VM_GET_REGISTER_SET, "VM_GET_REGISTER_SET", NULL }, 47 { (uint_t)VM_INJECT_EXCEPTION, "VM_INJECT_EXCEPTION", NULL }, 48 { (uint_t)VM_SET_CAPABILITY, "VM_SET_CAPABILITY", NULL }, 49 { (uint_t)VM_GET_CAPABILITY, "VM_GET_CAPABILITY", NULL }, 50 { (uint_t)VM_PPTDEV_MSI, "VM_PPTDEV_MSI", NULL }, 51 { (uint_t)VM_PPTDEV_MSIX, "VM_PPTDEV_MSIX", NULL }, 52 { (uint_t)VM_SET_X2APIC_STATE, "VM_SET_X2APIC_STATE", NULL }, 53 { (uint_t)VM_GLA2GPA, "VM_GLA2GPA", NULL }, 54 { (uint_t)VM_GLA2GPA_NOFAULT, "VM_GLA2GPA_NOFAULT", NULL }, 55 { (uint_t)VM_ACTIVATE_CPU, "VM_ACTIVATE_CPU", NULL }, 56 { (uint_t)VM_SET_INTINFO, "VM_SET_INTINFO", NULL }, 57 { (uint_t)VM_GET_INTINFO, "VM_GET_INTINFO", NULL }, 58 { (uint_t)VM_RESTART_INSTRUCTION, "VM_RESTART_INSTRUCTION", 59 NULL }, 60 { (uint_t)VM_SET_KERNEMU_DEV, "VM_SET_KERNEMU_DEV", NULL }, 61 { (uint_t)VM_GET_KERNEMU_DEV, "VM_GET_KERNEMU_DEV", NULL }, 62 { (uint_t)VM_RESET_CPU, "VM_RESET_CPU", NULL }, 63 { (uint_t)VM_GET_RUN_STATE, "VM_GET_RUN_STATE", NULL }, 64 { (uint_t)VM_SET_RUN_STATE, "VM_SET_RUN_STATE", NULL }, 65 { (uint_t)VM_GET_FPU, "VM_GET_FPU", NULL }, 66 { (uint_t)VM_SET_FPU, "VM_SET_FPU", NULL }, 67 { (uint_t)VM_GET_CPUID, "VM_GET_CPUID", NULL }, 68 { (uint_t)VM_SET_CPUID, "VM_SET_CPUID", NULL }, 69 { (uint_t)VM_LEGACY_CPUID, "VM_LEGACY_CPUID", NULL } 70 }; 71 72 const struct ioc vmm_lock_ioc[] = { 73 { (uint_t)VM_REINIT, "VM_REINIT", NULL }, 74 { (uint_t)VM_BIND_PPTDEV, "VM_BIND_PPTDEV", NULL }, 75 { (uint_t)VM_UNBIND_PPTDEV, "VM_UNBIND_PPTDEV", NULL }, 76 { (uint_t)VM_MAP_PPTDEV_MMIO, "VM_MAP_PPTDEV_MMIO", NULL }, 77 { (uint_t)VM_ALLOC_MEMSEG, "VM_ALLOC_MEMSEG", NULL }, 78 { (uint_t)VM_MMAP_MEMSEG, "VM_MMAP_MEMSEG", NULL }, 79 { (uint_t)VM_PMTMR_LOCATE, "VM_PMTMR_LOCATE", NULL }, 80 { (uint_t)VM_MUNMAP_MEMSEG, "VM_MUNMAP_MEMSEG", NULL }, 81 { (uint_t)VM_UNMAP_PPTDEV_MMIO, "VM_UNMAP_PPTDEV_MMIO", NULL }, 82 { (uint_t)VM_PAUSE, "VM_PAUSE", NULL }, 83 { (uint_t)VM_RESUME, "VM_RESUME", NULL }, 84 85 { (uint_t)VM_WRLOCK_CYCLE, "VM_WRLOCK_CYCLE", NULL } 86 }; 87 88 const struct ioc vmm_ioc[] = { 89 { (uint_t)VM_GET_GPA_PMAP, "VM_GET_GPA_PMAP", NULL }, 90 { (uint_t)VM_GET_MEMSEG, "VM_GET_MEMSEG", NULL }, 91 { (uint_t)VM_MMAP_GETNEXT, "VM_MMAP_GETNEXT", NULL }, 92 93 { (uint_t)VM_LAPIC_IRQ, "VM_LAPIC_IRQ", NULL }, 94 { (uint_t)VM_LAPIC_LOCAL_IRQ, "VM_LAPIC_LOCAL_IRQ", NULL }, 95 { (uint_t)VM_LAPIC_MSI, "VM_LAPIC_MSI", NULL }, 96 97 { (uint_t)VM_IOAPIC_ASSERT_IRQ, "VM_IOAPIC_ASSERT_IRQ", NULL }, 98 { (uint_t)VM_IOAPIC_DEASSERT_IRQ, "VM_IOAPIC_DEASSERT_IRQ", 99 NULL }, 100 { (uint_t)VM_IOAPIC_PULSE_IRQ, "VM_IOAPIC_PULSE_IRQ", NULL }, 101 102 { (uint_t)VM_ISA_ASSERT_IRQ, "VM_ISA_ASSERT_IRQ", NULL }, 103 { (uint_t)VM_ISA_DEASSERT_IRQ, "VM_ISA_DEASSERT_IRQ", NULL }, 104 { (uint_t)VM_ISA_PULSE_IRQ, "VM_ISA_PULSE_IRQ", NULL }, 105 { (uint_t)VM_ISA_SET_IRQ_TRIGGER, "VM_ISA_SET_IRQ_TRIGGER", 106 NULL }, 107 108 { (uint_t)VM_RTC_WRITE, "VM_RTC_WRITE", NULL }, 109 { (uint_t)VM_RTC_READ, "VM_RTC_READ", NULL }, 110 { (uint_t)VM_RTC_SETTIME, "VM_RTC_SETTIME", NULL }, 111 { (uint_t)VM_RTC_GETTIME, "VM_RTC_GETTIME", NULL }, 112 113 { (uint_t)VM_SUSPEND, "VM_SUSPEND", NULL }, 114 115 { (uint_t)VM_IOAPIC_PINCOUNT, "VM_IOAPIC_PINCOUNT", NULL }, 116 { (uint_t)VM_GET_PPTDEV_LIMITS, "VM_GET_PPTDEV_LIMITS", NULL }, 117 { (uint_t)VM_GET_HPET_CAPABILITIES, "VM_GET_HPET_CAPABILITIES", 118 NULL }, 119 120 { (uint_t)VM_STATS_IOC, "VM_STATS_IOC", NULL }, 121 { (uint_t)VM_STAT_DESC, "VM_STAT_DESC", NULL }, 122 123 { (uint_t)VM_INJECT_NMI, "VM_INJECT_NMI", NULL }, 124 { (uint_t)VM_GET_X2APIC_STATE, "VM_GET_X2APIC_STATE", NULL }, 125 { (uint_t)VM_SET_TOPOLOGY, "VM_SET_TOPOLOGY", NULL }, 126 { (uint_t)VM_GET_TOPOLOGY, "VM_GET_TOPOLOGY", NULL }, 127 { (uint_t)VM_GET_CPUS, "VM_GET_CPUS", NULL }, 128 { (uint_t)VM_SUSPEND_CPU, "VM_SUSPEND_CPU", NULL }, 129 { (uint_t)VM_RESUME_CPU, "VM_RESUME_CPU", NULL }, 130 131 { (uint_t)VM_PPTDEV_DISABLE_MSIX, "VM_PPTDEV_DISABLE_MSIX", 132 NULL }, 133 134 { (uint_t)VM_TRACK_DIRTY_PAGES, "VM_TRACK_DIRTY_PAGES", NULL }, 135 { (uint_t)VM_DESC_FPU_AREA, "VM_DESC_FPU_AREA", NULL }, 136 137 { (uint_t)VM_DATA_READ, "VM_DATA_READ", NULL }, 138 { (uint_t)VM_DATA_WRITE, "VM_DATA_WRITE", NULL }, 139 140 { (uint_t)VM_SET_AUTODESTRUCT, "VM_SET_AUTODESTRUCT", NULL }, 141 { (uint_t)VM_DESTROY_SELF, "VM_DESTROY_SELF", NULL }, 142 { (uint_t)VM_DESTROY_PENDING, "VM_DESTROY_PENDING", NULL }, 143 144 { (uint_t)VM_VCPU_BARRIER, "VM_VCPU_BARRIER", NULL }, 145 146 { (uint_t)VM_DEVMEM_GETOFFSET, "VM_DEVMEM_GETOFFSET", NULL } 147 }; 148 149 const struct iocs vmm_iocs[] = { 150 { .nitems = ARRAY_SIZE(vmmctl_ioc), .data = vmmctl_ioc }, 151 { .nitems = ARRAY_SIZE(vmm_cpu_ioc), .data = vmm_cpu_ioc }, 152 { .nitems = ARRAY_SIZE(vmm_lock_ioc), .data = vmm_lock_ioc }, 153 { .nitems = ARRAY_SIZE(vmm_ioc), .data = vmm_ioc }, 154 { .nitems = 0, .data = NULL } 155 }; 156 #else 157 const struct iocs vmm_iocs[] = { 158 { .nitems = 0, .data = NULL } 159 }; 160 #endif /* __x86 */ 161