1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma dictionary "INTEL" 28 29/* 30 * Eversholt rules for the intel CPU/Memory 31 */ 32 33/* 34 * Ereports for Simple error codes. 35 */ 36 37#define SMPL_EVENT(leafclass, t) \ 38 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) } 39 40SMPL_EVENT(unknown, 1s); 41SMPL_EVENT(unclassified, 1s); 42SMPL_EVENT(microcode_rom_parity, 1s); 43SMPL_EVENT(external, 1s); 44SMPL_EVENT(frc, 1s); 45SMPL_EVENT(internal_timer, 1s); 46SMPL_EVENT(internal_parity, 1s); 47SMPL_EVENT(internal_unclassified, 1s); 48 49/* 50 * Propogations for all but "external" and "unknown" simple errors. 51 * If the error is uncorrected we produce a fault immediately, otherwise 52 * we diagnose it to an upset and decalre a fault when the SERD engine 53 * trips. 54 */ 55 56engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h; 57event fault.cpu.intel.internal@chip/core/strand, 58 engine=serd.cpu.intel.simple@chip/core/strand; 59 60prop fault.cpu.intel.internal@chip/core/strand 61 { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)-> 62 ereport.cpu.intel.microcode_rom_parity@chip/core/strand, 63 ereport.cpu.intel.internal_timer@chip/core/strand, 64 ereport.cpu.intel.internal_parity@chip/core/strand, 65 ereport.cpu.intel.unclassified@chip/core/strand, 66 ereport.cpu.intel.internal_unclassified@chip/core/strand, 67 ereport.cpu.intel.frc@chip/core/strand; 68 69/* 70 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 71 * for the corrected and uncorrected version of each error type. All are 72 * detected at chip/core/strand. 73 */ 74 75#define CMPND_EVENT(leafclass, t) \ 76 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }; \ 77 event ereport.cpu.intel.leafclass/**/_uc@chip/core/strand { within(t) } 78 79/* 80 * Ereports for Compound error codes - intel errors 81 */ 82CMPND_EVENT(l0cache, 1s); 83CMPND_EVENT(l1cache, 1s); 84CMPND_EVENT(l2cache, 1s); 85CMPND_EVENT(cache, 1s); 86 87/* 88 * Ereports for Compound error codes - TLB errors 89 */ 90CMPND_EVENT(l0dtlb, 1s); 91CMPND_EVENT(l1dtlb, 1s); 92CMPND_EVENT(l2dtlb, 1s); 93CMPND_EVENT(dtlb, 1s); 94 95CMPND_EVENT(l0itlb, 1s); 96CMPND_EVENT(l1itlb, 1s); 97CMPND_EVENT(l2itlb, 1s); 98CMPND_EVENT(itlb, 1s); 99 100CMPND_EVENT(l0tlb, 1s); 101CMPND_EVENT(l1tlb, 1s); 102CMPND_EVENT(l2tlb, 1s); 103CMPND_EVENT(tlb, 1s); 104 105/* 106 * Ereports for Compound error codes - memory hierarchy errors 107 */ 108CMPND_EVENT(l0dcache, 1s); 109CMPND_EVENT(l1dcache, 1s); 110CMPND_EVENT(l2dcache, 1s); 111CMPND_EVENT(dcache, 1s); 112 113CMPND_EVENT(l0icache, 1s); 114CMPND_EVENT(l1icache, 1s); 115CMPND_EVENT(l2icache, 1s); 116CMPND_EVENT(icache, 1s); 117 118/* 119 * Ereports for Compound error codes - bus and interconnect errors 120 */ 121CMPND_EVENT(bus_interconnect, 1s); 122CMPND_EVENT(bus_interconnect_memory, 1s); 123CMPND_EVENT(bus_interconnect_io, 1s); 124 125/* 126 * Compound error propogations. 127 * 128 * We resist the temptation propogate, for example, a single dcache fault 129 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 130 * Instead we will diagnose a distinct fault for each possible cache level, 131 * whether or not current chips have dcaches at all levels. 132 * 133 * Corrected errors are SERDed and produce a fault when the engine fires; 134 * the same fault is diagnosed immediately for a corresponding uncorrected 135 * error. 136 */ 137 138#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 139 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 140 event fault.cpu.intel.fltleaf@chip/core/strand, \ 141 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 142 \ 143 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 144 ereport.cpu.intel.erptleaf@chip/core/strand; \ 145 \ 146 prop fault.cpu.intel.fltleaf@chip/core/strand \ 147 { setserdincrement(n + 1) } (0)-> \ 148 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 149 150#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 151 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 152 event fault.cpu.intel.fltleaf@chip/core/strand, retire=0, response=0,\ 153 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 154 \ 155 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 156 ereport.cpu.intel.erptleaf@chip/core/strand; \ 157 \ 158 prop fault.cpu.intel.fltleaf@chip/core/strand \ 159 { setserdincrement(n + 1) } (0)-> \ 160 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 161 162CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 163CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 164CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 165CMPND_FLT_PROP_1(cache, cache, 12, 72h); 166 167CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 168CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 169CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 170CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 171 172CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 173CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 174CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 175CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 176 177CMPND_FLT_PROP_1(l0tlb, litlb, 3, 72h); 178CMPND_FLT_PROP_1(l1tlb, litlb, 3, 72h); 179CMPND_FLT_PROP_1(l2tlb, litlb, 3, 72h); 180CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 181 182CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 183CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 184CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 185CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 186 187CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 188CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 189CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 190CMPND_FLT_PROP_1(icache, icache, 12, 72h); 191 192CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 193CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 194CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 195 196event upset.discard@chip/core/strand; 197 198prop upset.discard@chip/core/strand (0)-> 199 ereport.cpu.intel.external@chip/core/strand, 200 ereport.cpu.intel.unknown@chip/core/strand; 201 202/* errors detected in northbridge */ 203 204 205/* 206 * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that 207 * we diagnose for page faults, to record the physical address of the faulting 208 * page. 209 */ 210#define SET_ADDR (!payloadprop_defined("physaddr") || \ 211 setpayloadprop("asru-physaddr", payloadprop("physaddr"))) 212 213#define SET_OFFSET (!payloadprop_defined("offset") || \ 214 setpayloadprop("asru-offset", payloadprop("offset"))) 215 216#define EREPORT_BUS_ERROR \ 217 ereport.cpu.intel.bus_interconnect_memory_uc@chip/core/strand, \ 218 ereport.cpu.intel.bus_interconnect_uc@chip/core/strand, \ 219 ereport.cpu.intel.bus_interconnect_memory@chip/core/strand, \ 220 ereport.cpu.intel.bus_interconnect@chip/core/strand, \ 221 ereport.cpu.intel.external@chip/core/strand 222 223engine stat.ce_pgflt@memory-controller/dram-channel/dimm; 224 225event ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller{within(12s)}; 226event ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller{within(12s)}; 227event fault.memory.intel.page_ue@ 228 motherboard/memory-controller/dram-channel/dimm/rank, 229 message=0, response=0; 230event fault.memory.intel.dimm_ue@ 231 motherboard/memory-controller/dram-channel/dimm/rank; 232 233prop fault.memory.intel.page_ue@ 234 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 235 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 236 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 237 SET_ADDR && SET_OFFSET } (1)-> 238 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 239 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 240 241prop fault.memory.intel.dimm_ue@ 242 motherboard/memory-controller/dram-channel<channel_num>/dimm/rank[rank_num] 243 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 244 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 245 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 246 247event upset.memory.intel.discard@motherboard/memory-controller{within(1s)}; 248 249prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 250 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 251 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 252 253prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 254 EREPORT_BUS_ERROR; 255 256#define PAGE_CE_COUNT 2 257#define PAGE_CE_TIME 72h 258#define DIMM_CE_COUNT 10 259#define DIMM_CE_TIME 1week 260 261#define MBDIMM motherboard/memory-controller/dram-channel/dimm 262event ereport.cpu.intel.nb.mem_ce@MBDIMM/rank{within(12s)}; 263 264engine serd.memory.intel.page_ce@MBDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 265event fault.memory.intel.page_ce@MBDIMM/rank, message=0, response=0, 266 count=stat.ce_pgflt@MBDIMM, engine=serd.memory.intel.page_ce@MBDIMM/rank; 267prop fault.memory.intel.page_ce@MBDIMM/rank 268 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 269 SET_ADDR && SET_OFFSET } (0)-> 270 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank; 271 272engine serd.memory.intel.dimm_ce@MBDIMM/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME; 273event fault.memory.intel.dimm_ce@MBDIMM/rank, 274 engine=serd.memory.intel.dimm_ce@MBDIMM/rank; 275prop fault.memory.intel.dimm_ce@MBDIMM/rank 276 { !confprop_defined(MBDIMM, "dimm-size") && 277 count(stat.ce_pgflt@MBDIMM) > 512 } (1)-> 278 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank; 279 280#define DIMM_CE(dimm_size, n, t, fault_rate) \ 281 prop fault.memory.intel.dimm_ce@MBDIMM/rank { \ 282 confprop(MBDIMM, "dimm-size") == dimm_size && \ 283 count(stat.ce_pgflt@MBDIMM) > fault_rate && \ 284 setserdn(n) & setserdt(t) } (1)-> \ 285 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank; 286 287DIMM_CE("8G", 8, 1week, 2000) 288DIMM_CE("4G", 4, 1week, 1500) 289DIMM_CE("2G", 4, 2week, 1000) 290DIMM_CE("1G", 4, 4week, 500) 291DIMM_CE("512M", 4, 8week, 250) 292DIMM_CE("256M", 4, 16week, 125) 293 294event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)}; 295event fault.memory.intel.fbd.alert@rank, retire=0; 296 297prop fault.memory.intel.fbd.alert@rank (1)-> 298 ereport.cpu.intel.nb.fbd.alert@rank; 299 300prop fault.memory.intel.fbd.alert@rank (0)-> 301 EREPORT_BUS_ERROR; 302 303event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)}; 304event fault.memory.intel.fbd.crc@rank, retire=0; 305 306prop fault.memory.intel.fbd.crc@rank (1)-> 307 ereport.cpu.intel.nb.fbd.crc@rank; 308 309prop fault.memory.intel.fbd.crc@rank (0)-> EREPORT_BUS_ERROR; 310 311event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)}; 312event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0; 313 314prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)-> 315 ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller; 316 317prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)-> 318 EREPORT_BUS_ERROR; 319 320event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)}; 321engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month; 322event fault.memory.intel.fbd.ch@dram-channel, retire=0, 323 engine=serd.cpu.intel.nb.fbd.ch@dram-channel; 324 325prop fault.memory.intel.fbd.ch@dram-channel (1)-> 326 ereport.cpu.intel.nb.fbd.ch@dram-channel; 327 328prop fault.memory.intel.fbd.ch@dram-channel (0)-> 329 EREPORT_BUS_ERROR; 330 331event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)}; 332engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week; 333event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0, 334 engine=serd.cpu.intel.nb.fbd_otf@dram-channel; 335 336prop fault.memory.intel.fbd.otf@dram-channel (1)-> 337 ereport.cpu.intel.nb.fbd.otf@dram-channel; 338 339event ereport.cpu.intel.nb.otf@motherboard {within(12s)}; 340event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0; 341 342prop fault.cpu.intel.nb.otf@motherboard (1)-> 343 ereport.cpu.intel.nb.otf@motherboard; 344 345event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)}; 346event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)}; 347event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)}; 348event upset.discard@memory-controller; 349 350prop upset.discard@memory-controller (0)-> 351 ereport.cpu.intel.nb.unknown@memory-controller, 352 ereport.cpu.intel.nb.unknown@memory-controller/dram-channel, 353 ereport.cpu.intel.nb.spd@memory-controller/dram-channel; 354 355event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)}; 356event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank, 357 retire=0; 358 359prop fault.memory.intel.fbd.mem_ds@ 360 memory-controller/dram-channel/dimm/rank[rank_num] 361 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 362 ereport.cpu.intel.nb.mem_ds@memory-controller; 363 364event ereport.cpu.intel.nb.fsb@chip{within(12s)}; 365event fault.cpu.intel.nb.fsb@chip, retire=0; 366 367prop fault.cpu.intel.nb.fsb@chip (1)-> 368 ereport.cpu.intel.nb.fsb@chip; 369 370prop fault.cpu.intel.nb.fsb@chip (0)-> EREPORT_BUS_ERROR; 371 372event ereport.cpu.intel.nb.ie@motherboard{within(12s)}; 373event fault.cpu.intel.nb.ie@motherboard, retire=0; 374event upset.cpu.intel.nb.ie_ce@motherboard{within(12s)}; 375 376prop upset.cpu.intel.nb.ie_ce@motherboard 377 { payloadprop("intel-error-list") == "B6" } (0)-> 378 ereport.cpu.intel.nb.ie@motherboard; 379 380prop fault.cpu.intel.nb.ie@motherboard 381 { payloadprop("intel-error-list") != "B6" } (1)-> 382 ereport.cpu.intel.nb.ie@motherboard; 383 384prop fault.cpu.intel.nb.ie@motherboard (0)-> EREPORT_BUS_ERROR; 385 386event ereport.cpu.intel.nb.dma@motherboard{within(12s)}; 387event fault.cpu.intel.nb.dma@motherboard, retire=0, response=0; 388 389prop fault.cpu.intel.nb.dma@motherboard (1)-> 390 ereport.cpu.intel.nb.dma@motherboard; 391 392prop fault.cpu.intel.nb.dma@motherboard (0)-> EREPORT_BUS_ERROR; 393 394event ereport.cpu.intel.nb.esi@motherboard{within(12s)}; 395event ereport.cpu.intel.nb.pex@hostbridge{within(12s)}; 396event upset.cpu.intel.nb.pex@hostbridge; 397 398prop upset.cpu.intel.nb.pex@hostbridge (1)-> 399 ereport.cpu.intel.nb.esi@motherboard, 400 ereport.cpu.intel.nb.pex@hostbridge; 401 402prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR; 403 404event ereport.cpu.intel.nb.unknown@rank{within(12s)}; 405event upset.discard@rank; 406 407prop upset.discard@rank (1)-> 408 ereport.cpu.intel.nb.unknown@rank; 409 410prop upset.discard@rank (0)-> EREPORT_BUS_ERROR; 411 412/* 413 * CPU integrated memory controller 414 */ 415 416#define CONTAINS_RANK (payloadprop_contains("resource", \ 417 asru(motherboard/chip/memory-controller/dram-channel/dimm/rank)) || \ 418 payloadprop_contains("resource", \ 419 asru(motherboard/chip/memory-controller/dram-channel/dimm))) 420 421#define STAT_CPU_MEM_CE_PGFLTS \ 422 stat.ce_pgflt@motherboard/chip/memory-controller/dram-channel/dimm 423 424#define SET_RES_OFFSET \ 425 (!payloadprop_defined("resource[0].hc-specific.offset") || \ 426 setpayloadprop("asru-offset", \ 427 payloadprop("resource[0].hc-specific.offset"))) 428 429engine STAT_CPU_MEM_CE_PGFLTS; 430 431event ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller 432 {within(12s)}; 433 434event fault.memory.intel.page_ue@ 435 motherboard/chip/memory-controller/dram-channel/dimm/rank, 436 message=0, response=0; /* do not message individual pageflts */ 437 438prop fault.memory.intel.page_ue@ 439 motherboard/chip/memory-controller/dram-channel/dimm/rank 440 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 441 payloadprop_defined("resource[0].hc-specific.offset")) && 442 SET_ADDR && SET_RES_OFFSET } (1)-> 443 ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller; 444 445event fault.memory.intel.dimm_ue@ 446 motherboard/chip/memory-controller/dram-channel/dimm/rank; 447 448prop fault.memory.intel.dimm_ue@ 449 motherboard/chip/memory-controller/dram-channel/dimm/rank 450 { CONTAINS_RANK } (1)-> 451 ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller; 452 453prop fault.memory.intel.dimm_ue@ 454 motherboard/chip/memory-controller/dram-channel/dimm/rank (0)-> 455 EREPORT_BUS_ERROR; 456 457#define CHIPDIMM motherboard/chip/memory-controller/dram-channel/dimm 458event ereport.cpu.intel.quickpath.mem_ce@ 459 motherboard/chip/memory-controller{within(12s)}; 460 461engine serd.memory.intel.page_ce@CHIPDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 462event fault.memory.intel.page_ce@CHIPDIMM/rank, message=0, response=0, 463 count=STAT_CPU_MEM_CE_PGFLTS, 464 engine=serd.memory.intel.page_ce@CHIPDIMM/rank; 465prop fault.memory.intel.page_ce@CHIPDIMM/rank 466 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 467 payloadprop_defined("resource[0].hc-specific.offset")) && 468 SET_ADDR && SET_RES_OFFSET } (1)-> 469 ereport.cpu.intel.quickpath.mem_ce@motherboard/chip/memory-controller; 470 471engine serd.memory.intel.dimm_ce@CHIPDIMM, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 472event fault.memory.intel.dimm_ce@CHIPDIMM, 473 engine=serd.memory.intel.dimm_ce@CHIPDIMM; 474prop fault.memory.intel.dimm_ce@CHIPDIMM 475 { !confprop_defined(CHIPDIMM, "dimm-size") && 476 count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (1)-> 477 ereport.cpu.intel.quickpath.mem_ce@motherboard/chip/memory-controller; 478 479#define CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 480 prop fault.memory.intel.dimm_ce@CHIPDIMM { \ 481 confprop(CHIPDIMM, "dimm-size") == dimm_size && \ 482 count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate && \ 483 setserdn(n) & setserdt(t) } (1)-> \ 484 ereport.cpu.intel.quickpath.mem_ce@ \ 485 motherboard/chip/memory-controller; 486 487CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 488CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 489CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 490CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 491CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 492CPU_MEM_DIMM_CE("512M", 4, 8week, 250) 493 494event ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller {within(12s)}; 495event ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller/dram-channel 496 {within(12s)}; 497event ereport.cpu.intel.quickpath.mem_unknown@ 498 motherboard/chip/memory-controller/dram-channel/dimm/rank{within(12s)}; 499event upset.discard@motherboard/chip/memory-controller; 500event upset.discard@motherboard/chip/memory-controller/dram-channel/dimm/rank; 501 502prop upset.discard@motherboard/chip/memory-controller (0)-> 503 ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller, 504 ereport.cpu.intel.quickpath.mem_unknown@ 505 motherboard/chip/memory-controller/dram-channel; 506 507prop upset.discard@ 508 motherboard/chip/memory-controller/dram-channel/dimm/rank (1)-> 509 ereport.cpu.intel.quickpath.mem_unknown@ 510 motherboard/chip/memory-controller/dram-channel/dimm/rank; 511 512event ereport.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller {within(1s)}; 513event fault.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller; 514 515prop fault.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller (1)-> 516 ereport.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller; 517 518event ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller {within(1s)}; 519event fault.cpu.intel.quickpath.mem_addr_parity@ 520 motherboard/chip/memory-controller/dram-channel/dimm; 521event fault.cpu.intel.quickpath.mem_addr_parity@ 522 motherboard/chip/memory-controller; 523 524prop fault.cpu.intel.quickpath.mem_addr_parity@ 525 motherboard/chip/memory-controller (1)-> 526 ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller; 527 528prop fault.cpu.intel.quickpath.mem_addr_parity@ 529 motherboard/chip/memory-controller/dram-channel/dimm 530 { payloadprop_contains("resource", asru(motherboard/chip/memory-controller/dram-channel/dimm)) } (1)-> 531 ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller; 532 533event ereport.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller {within(1s)}; 534event fault.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller; 535 536prop fault.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller (1)-> 537 ereport.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller; 538 539event ereport.cpu.intel.quickpath.mem_spare@motherboard/chip/memory-controller {within(1s)}; 540event fault.cpu.intel.quickpath.mem_spare@ 541 motherboard/chip/memory-controller/dram-channel/dimm; 542 543prop fault.cpu.intel.quickpath.mem_spare@ 544 motherboard/chip/memory-controller/dram-channel/dimm (1)-> 545 ereport.cpu.intel.quickpath.mem_spare@motherboard/chip/memory-controller; 546 547event ereport.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller {within(1s)}; 548event fault.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller; 549 550prop fault.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller (1)-> 551 ereport.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller; 552 553event ereport.cpu.intel.quickpath.mem_redundant@motherboard/chip/memory-controller {within(1s)}; 554engine serd.cpu.intel.quickpath.mem_redundant@ 555 motherboard/chip/memory-controller/dram-channel/dimm, 556 N=2, T=72h; 557event fault.cpu.intel.quickpath.mem_redundant@ 558 motherboard/chip/memory-controller/dram-channel/dimm, 559 engine=serd.cpu.intel.quickpath.mem_redundant@ 560 motherboard/chip/memory-controller/dram-channel/dimm; 561 562prop fault.cpu.intel.quickpath.mem_redundant@ 563 motherboard/chip/memory-controller/dram-channel/dimm 564 { payloadprop_contains("resource", 565 asru(motherboard/chip/memory-controller/dram-channel/dimm)) } (1)-> 566 ereport.cpu.intel.quickpath.mem_redundant@ 567 motherboard/chip/memory-controller; 568 569event ereport.cpu.intel.quickpath.interconnect@motherboard/chip 570 {within(1s)}; 571event upset.cpu.intel.quickpath.interconnect@motherboard/chip; 572/* Diagnose corrected events to upsets */ 573prop upset.cpu.intel.quickpath.interconnect@motherboard/chip 574 { !STATUS_UC } (1)-> 575 ereport.cpu.intel.quickpath.interconnect@motherboard/chip; 576 577 578engine serd.cpu.intel.quickpath.interconnect@motherboard/chip, 579 N=3, T=72h; 580event fault.cpu.intel.quickpath.interconnect@motherboard/chip, 581 engine=serd.cpu.intel.quickpath.interconnect@motherboard/chip; 582 583/* Diagnose uncorrected events to faults */ 584prop fault.cpu.intel.quickpath.interconnect@motherboard/chip 585 { STATUS_UC } (0)-> 586 ereport.cpu.intel.quickpath.interconnect@motherboard/chip; 587