1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2010 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma dictionary "INTEL" 28 29/* 30 * Eversholt rules for the intel CPU/Memory 31 */ 32 33/* 34 * Ereports for Simple error codes. 35 */ 36 37#define SMPL_EVENT(leafclass, t) \ 38 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) } 39 40SMPL_EVENT(unknown, 1s); 41SMPL_EVENT(unclassified, 1s); 42SMPL_EVENT(microcode_rom_parity, 1s); 43SMPL_EVENT(external, 1s); 44SMPL_EVENT(frc, 1s); 45SMPL_EVENT(internal_timer, 1s); 46SMPL_EVENT(internal_parity, 1s); 47SMPL_EVENT(internal_unclassified, 1s); 48 49/* 50 * Propogations for all but "external" and "unknown" simple errors. 51 * If the error is uncorrected we produce a fault immediately, otherwise 52 * we diagnose it to an upset and decalre a fault when the SERD engine 53 * trips. prop statement for ereport.cpu.intel.internal_unclassified is 54 * moved to the Nehalem EX section to deal with poison case. 55 */ 56 57engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h; 58event fault.cpu.intel.internal@chip/core/strand, 59 engine=serd.cpu.intel.simple@chip/core/strand; 60 61prop fault.cpu.intel.internal@chip/core/strand 62 { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)-> 63 ereport.cpu.intel.microcode_rom_parity@chip/core/strand, 64 ereport.cpu.intel.internal_timer@chip/core/strand, 65 ereport.cpu.intel.internal_parity@chip/core/strand, 66 ereport.cpu.intel.unclassified@chip/core/strand, 67 ereport.cpu.intel.frc@chip/core/strand; 68 69/* 70 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 71 * for the corrected and uncorrected version of each error type. All are 72 * detected at chip/core/strand. 73 */ 74 75#define CMPND_EVENT(leafclass, t) \ 76 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }; \ 77 event ereport.cpu.intel.leafclass/**/_uc@chip/core/strand { within(t) } 78 79/* 80 * Ereports for Compound error codes - intel errors 81 */ 82CMPND_EVENT(l0cache, 1s); 83CMPND_EVENT(l1cache, 1s); 84CMPND_EVENT(l2cache, 1s); 85CMPND_EVENT(cache, 1s); 86 87/* 88 * Ereports for Compound error codes - TLB errors 89 */ 90CMPND_EVENT(l0dtlb, 1s); 91CMPND_EVENT(l1dtlb, 1s); 92CMPND_EVENT(l2dtlb, 1s); 93CMPND_EVENT(dtlb, 1s); 94 95CMPND_EVENT(l0itlb, 1s); 96CMPND_EVENT(l1itlb, 1s); 97CMPND_EVENT(l2itlb, 1s); 98CMPND_EVENT(itlb, 1s); 99 100CMPND_EVENT(l0tlb, 1s); 101CMPND_EVENT(l1tlb, 1s); 102CMPND_EVENT(l2tlb, 1s); 103CMPND_EVENT(tlb, 1s); 104 105/* 106 * Ereports for Compound error codes - memory hierarchy errors 107 */ 108CMPND_EVENT(l0dcache, 1s); 109CMPND_EVENT(l1dcache, 1s); 110CMPND_EVENT(l2dcache, 1s); 111CMPND_EVENT(dcache, 1s); 112 113CMPND_EVENT(l0icache, 1s); 114CMPND_EVENT(l1icache, 1s); 115CMPND_EVENT(l2icache, 1s); 116CMPND_EVENT(icache, 1s); 117 118/* 119 * Ereports for Compound error codes - bus and interconnect errors 120 */ 121CMPND_EVENT(bus_interconnect, 1s); 122CMPND_EVENT(bus_interconnect_memory, 1s); 123CMPND_EVENT(bus_interconnect_io, 1s); 124 125/* 126 * Compound error propogations. 127 * 128 * We resist the temptation propogate, for example, a single dcache fault 129 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 130 * Instead we will diagnose a distinct fault for each possible cache level, 131 * whether or not current chips have dcaches at all levels. 132 * 133 * Corrected errors are SERDed and produce a fault when the engine fires; 134 * the same fault is diagnosed immediately for a corresponding uncorrected 135 * error. 136 */ 137 138#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 139 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 140 event fault.cpu.intel.fltleaf@chip/core/strand, \ 141 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 142 \ 143 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 144 ereport.cpu.intel.erptleaf@chip/core/strand; \ 145 \ 146 prop fault.cpu.intel.fltleaf@chip/core/strand \ 147 { setserdincrement(n + 1) } (0)-> \ 148 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 149 150#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 151 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 152 event fault.cpu.intel.fltleaf@chip/core/strand, retire=0, response=0,\ 153 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 154 \ 155 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 156 ereport.cpu.intel.erptleaf@chip/core/strand; \ 157 \ 158 prop fault.cpu.intel.fltleaf@chip/core/strand \ 159 { setserdincrement(n + 1) } (0)-> \ 160 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 161 162CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 163CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 164CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 165CMPND_FLT_PROP_1(cache, cache, 12, 72h); 166 167CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 168CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 169CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 170CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 171 172CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 173CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 174CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 175CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 176 177CMPND_FLT_PROP_1(l0tlb, l0tlb, 3, 72h); 178CMPND_FLT_PROP_1(l1tlb, l1tlb, 3, 72h); 179CMPND_FLT_PROP_1(l2tlb, l2tlb, 3, 72h); 180CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 181 182CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 183CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 184CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 185CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 186 187CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 188CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 189CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 190CMPND_FLT_PROP_1(icache, icache, 12, 72h); 191 192CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 193CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 194CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 195 196event upset.discard@chip/core/strand; 197 198prop upset.discard@chip/core/strand (0)-> 199 ereport.cpu.intel.external@chip/core/strand, 200 ereport.cpu.intel.unknown@chip/core/strand; 201 202/* errors detected in northbridge */ 203 204 205/* 206 * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that 207 * we diagnose for page faults, to record the physical address of the faulting 208 * page. 209 */ 210#define SET_ADDR (!payloadprop_defined("physaddr") || \ 211 setpayloadprop("asru-physaddr", payloadprop("physaddr"))) 212 213#define SET_OFFSET (!payloadprop_defined("offset") || \ 214 setpayloadprop("asru-offset", payloadprop("offset"))) 215 216#define EREPORT_BUS_ERROR \ 217 ereport.cpu.intel.bus_interconnect_memory_uc@chip/core/strand, \ 218 ereport.cpu.intel.bus_interconnect_uc@chip/core/strand, \ 219 ereport.cpu.intel.bus_interconnect_memory@chip/core/strand, \ 220 ereport.cpu.intel.bus_interconnect@chip/core/strand, \ 221 ereport.cpu.intel.external@chip/core/strand 222 223engine stat.ce_pgflt@memory-controller/dram-channel/dimm; 224 225event ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller{within(12s)}; 226event ereport.cpu.intel.nb.ddr2_mem_ue@ 227 motherboard/memory-controller{within(12s)}; 228event ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller{within(12s)}; 229event fault.memory.intel.page_ue@ 230 motherboard/memory-controller/dram-channel/dimm/rank, 231 message=0, response=0; 232event fault.memory.intel.dimm_ue@ 233 motherboard/memory-controller/dram-channel/dimm/rank; 234 235prop fault.memory.intel.page_ue@ 236 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 237 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 238 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 239 SET_ADDR && SET_OFFSET } (1)-> 240 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 241 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 242 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 243 244prop fault.memory.intel.dimm_ue@ 245 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 246 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 247 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 248 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 249 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 250 251event upset.memory.intel.discard@motherboard/memory-controller{within(1s)}; 252 253prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 254 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 255 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 256 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 257 258prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 259 EREPORT_BUS_ERROR; 260 261#define PAGE_CE_COUNT 2 262#define PAGE_CE_TIME 72h 263#define DIMM_CE_COUNT 10 264#define DIMM_CE_TIME 1week 265 266#define MBDIMM motherboard/memory-controller/dram-channel/dimm 267event ereport.cpu.intel.nb.mem_ce@MBDIMM/rank{within(12s)}; 268event ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank{within(12s)}; 269event ereport.cpu.intel.nb.ddr2_mem_ce@ 270 motherboard/memory-controller{within(12s)}; 271 272engine serd.memory.intel.page_ce@MBDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 273event fault.memory.intel.page_ce@MBDIMM/rank, message=0, response=0, 274 count=stat.ce_pgflt@MBDIMM, engine=serd.memory.intel.page_ce@MBDIMM/rank; 275prop fault.memory.intel.page_ce@MBDIMM/rank 276 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 277 SET_ADDR && SET_OFFSET } (0)-> 278 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, 279 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 280 281engine serd.memory.intel.dimm_ce@MBDIMM/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME; 282event fault.memory.intel.dimm_ce@MBDIMM/rank, 283 engine=serd.memory.intel.dimm_ce@MBDIMM/rank; 284prop fault.memory.intel.dimm_ce@MBDIMM/rank 285 { !confprop_defined(MBDIMM, "dimm-size") && 286 count(stat.ce_pgflt@MBDIMM) > 512 } (1)-> 287 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, 288 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 289#define DIMM_CE(dimm_size, n, t, fault_rate) \ 290 prop fault.memory.intel.dimm_ce@MBDIMM/rank { \ 291 confprop(MBDIMM, "dimm-size") == dimm_size && \ 292 count(stat.ce_pgflt@MBDIMM) > fault_rate && \ 293 setserdn(n) & setserdt(t) } (1)-> \ 294 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, \ 295 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 296 297DIMM_CE("8G", 8, 1week, 2000) 298DIMM_CE("4G", 4, 1week, 1500) 299DIMM_CE("2G", 4, 2week, 1000) 300DIMM_CE("1G", 4, 4week, 500) 301DIMM_CE("512M", 4, 8week, 250) 302DIMM_CE("256M", 4, 16week, 125) 303 304prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 305 ereport.cpu.intel.nb.ddr2_mem_ce@motherboard/memory-controller; 306 307event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)}; 308event fault.memory.intel.fbd.alert@rank, retire=0; 309 310prop fault.memory.intel.fbd.alert@rank (1)-> 311 ereport.cpu.intel.nb.fbd.alert@rank; 312 313prop fault.memory.intel.fbd.alert@rank (0)-> 314 EREPORT_BUS_ERROR; 315 316event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)}; 317event fault.memory.intel.fbd.crc@rank, retire=0; 318 319prop fault.memory.intel.fbd.crc@rank (1)-> 320 ereport.cpu.intel.nb.fbd.crc@rank; 321 322prop fault.memory.intel.fbd.crc@rank (0)-> EREPORT_BUS_ERROR; 323 324event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)}; 325event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0; 326 327prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)-> 328 ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller; 329 330prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)-> 331 EREPORT_BUS_ERROR; 332 333event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)}; 334engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month; 335event fault.memory.intel.fbd.ch@dram-channel, retire=0, 336 engine=serd.cpu.intel.nb.fbd.ch@dram-channel; 337 338prop fault.memory.intel.fbd.ch@dram-channel (1)-> 339 ereport.cpu.intel.nb.fbd.ch@dram-channel; 340 341prop fault.memory.intel.fbd.ch@dram-channel (0)-> 342 EREPORT_BUS_ERROR; 343 344event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)}; 345engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week; 346event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0, 347 engine=serd.cpu.intel.nb.fbd_otf@dram-channel; 348 349prop fault.memory.intel.fbd.otf@dram-channel (1)-> 350 ereport.cpu.intel.nb.fbd.otf@dram-channel; 351 352event ereport.cpu.intel.nb.otf@motherboard {within(12s)}; 353event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0; 354 355prop fault.cpu.intel.nb.otf@motherboard (1)-> 356 ereport.cpu.intel.nb.otf@motherboard; 357 358event ereport.cpu.intel.nb.unknown@motherboard {within(12s)}; 359event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)}; 360event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)}; 361event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)}; 362event ereport.cpu.intel.nb.ddr2_spd@ 363 memory-controller/dram-channel {within(12s)}; 364event upset.discard@memory-controller; 365 366prop upset.discard@memory-controller (0)-> 367 ereport.cpu.intel.nb.unknown@motherboard, 368 ereport.cpu.intel.nb.unknown@memory-controller, 369 ereport.cpu.intel.nb.unknown@memory-controller/dram-channel, 370 ereport.cpu.intel.nb.spd@memory-controller/dram-channel, 371 ereport.cpu.intel.nb.ddr2_spd@memory-controller/dram-channel; 372 373event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)}; 374event ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller{within(30s)}; 375event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank, 376 retire=0; 377 378prop fault.memory.intel.fbd.mem_ds@ 379 memory-controller/dram-channel/dimm/rank[rank_num] 380 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 381 ereport.cpu.intel.nb.mem_ds@memory-controller, 382 ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller; 383 384event ereport.cpu.intel.nb.fsb@chip{within(12s)}; 385event fault.cpu.intel.nb.fsb@chip, retire=0; 386 387prop fault.cpu.intel.nb.fsb@chip (1)-> 388 ereport.cpu.intel.nb.fsb@chip; 389 390prop fault.cpu.intel.nb.fsb@chip (0)-> EREPORT_BUS_ERROR; 391 392event ereport.cpu.intel.nb.ie@motherboard{within(12s)}; 393event fault.cpu.intel.nb.ie@motherboard, retire=0; 394event upset.cpu.intel.nb.ie_ce@motherboard{within(12s)}; 395 396prop upset.cpu.intel.nb.ie_ce@motherboard 397 { payloadprop("intel-error-list") == "B6" } (0)-> 398 ereport.cpu.intel.nb.ie@motherboard; 399 400prop fault.cpu.intel.nb.ie@motherboard 401 { payloadprop("intel-error-list") != "B6" } (1)-> 402 ereport.cpu.intel.nb.ie@motherboard; 403 404prop fault.cpu.intel.nb.ie@motherboard (0)-> EREPORT_BUS_ERROR; 405 406event ereport.cpu.intel.nb.dma@motherboard{within(12s)}; 407event upset.cpu.intel.nb.dma@motherboard; 408 409prop upset.cpu.intel.nb.dma@motherboard (1)-> 410 ereport.cpu.intel.nb.dma@motherboard; 411 412event ereport.cpu.intel.nb.esi@motherboard{within(12s)}; 413event ereport.cpu.intel.nb.pex@hostbridge{within(12s)}; 414event upset.cpu.intel.nb.pex@hostbridge; 415 416prop upset.cpu.intel.nb.pex@hostbridge (1)-> 417 ereport.cpu.intel.nb.esi@motherboard, 418 ereport.cpu.intel.nb.pex@hostbridge; 419 420prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR; 421 422event ereport.cpu.intel.nb.unknown@rank{within(12s)}; 423event upset.discard@rank; 424 425prop upset.discard@rank (1)-> 426 ereport.cpu.intel.nb.unknown@rank; 427 428prop upset.discard@rank (0)-> EREPORT_BUS_ERROR; 429 430/* 431 * CPU integrated memory controller 432 */ 433 434#define CONTAINS_RANK (payloadprop_contains("resource", \ 435 asru(chip/memory-controller/dram-channel/dimm/rank)) || \ 436 payloadprop_contains("resource", \ 437 asru(chip/memory-controller/dram-channel/dimm))) 438 439#define STAT_CPU_MEM_CE_PGFLTS \ 440 stat.ce_pgflt@chip/memory-controller/dram-channel/dimm 441 442#define SET_RES_OFFSET \ 443 (!payloadprop_defined("resource[0].hc-specific.offset") || \ 444 setpayloadprop("asru-offset", \ 445 payloadprop("resource[0].hc-specific.offset"))) 446 447engine STAT_CPU_MEM_CE_PGFLTS; 448 449event ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller 450 {within(12s)}; 451 452event fault.memory.intel.page_ue@ 453 chip/memory-controller/dram-channel/dimm/rank, 454 message=0, response=0; /* do not message individual pageflts */ 455 456prop fault.memory.intel.page_ue@ 457 chip/memory-controller/dram-channel/dimm/rank 458 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 459 payloadprop_defined("resource[0].hc-specific.offset")) && 460 SET_ADDR && SET_RES_OFFSET } (0)-> 461 ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller; 462 463#define CHIPDIMM chip/memory-controller/dram-channel/dimm 464 465event fault.memory.intel.dimm_ue@CHIPDIMM/rank; 466 467event error.memory.intel.dimm_ue_ep@CHIPDIMM/rank; 468event error.memory.intel.dimm_ue_ex@CHIPDIMM/rank; 469 470prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (1)-> 471 error.memory.intel.dimm_ue_ep@CHIPDIMM/rank, 472 error.memory.intel.dimm_ue_ex@CHIPDIMM/rank; 473 474prop error.memory.intel.dimm_ue_ep@CHIPDIMM/rank 475 { CONTAINS_RANK } (1)-> 476 ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller; 477 478prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (0)-> EREPORT_BUS_ERROR; 479 480event ereport.cpu.intel.quickpath.mem_ce@ 481 chip/memory-controller{within(12s)}; 482 483engine serd.memory.intel.page_ce@CHIPDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 484event fault.memory.intel.page_ce@CHIPDIMM/rank, message=0, response=0, 485 count=STAT_CPU_MEM_CE_PGFLTS, 486 engine=serd.memory.intel.page_ce@CHIPDIMM/rank; 487prop fault.memory.intel.page_ce@CHIPDIMM/rank 488 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 489 payloadprop_defined("resource[0].hc-specific.offset")) && 490 SET_ADDR && SET_RES_OFFSET } (0)-> 491 ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller; 492 493engine serd.memory.intel.dimm_ce@CHIPDIMM, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 494event fault.memory.intel.dimm_ce@CHIPDIMM, 495 engine=serd.memory.intel.dimm_ce@CHIPDIMM; 496prop fault.memory.intel.dimm_ce@CHIPDIMM 497 { !confprop_defined(CHIPDIMM, "dimm-size") && 498 count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (0)-> 499 ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller; 500 501#define CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 502 prop fault.memory.intel.dimm_ce@CHIPDIMM { \ 503 confprop(CHIPDIMM, "dimm-size") == dimm_size && \ 504 count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate && \ 505 setserdn(n) & setserdt(t) } (0)-> \ 506 ereport.cpu.intel.quickpath.mem_ce@ \ 507 chip/memory-controller; 508 509CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 510CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 511CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 512CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 513CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 514CPU_MEM_DIMM_CE("512M", 4, 8week, 250) 515 516event ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller {within(12s)}; 517event ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller/dram-channel 518 {within(12s)}; 519event ereport.cpu.intel.quickpath.mem_unknown@ 520 chip/memory-controller/dram-channel/dimm/rank{within(12s)}; 521event upset.discard@chip/memory-controller; 522event upset.discard@chip/memory-controller/dram-channel/dimm/rank; 523 524prop upset.discard@chip/memory-controller (0)-> 525 ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller, 526 ereport.cpu.intel.quickpath.mem_unknown@ 527 chip/memory-controller/dram-channel; 528 529prop upset.discard@ 530 chip/memory-controller/dram-channel/dimm/rank (1)-> 531 ereport.cpu.intel.quickpath.mem_unknown@ 532 chip/memory-controller/dram-channel/dimm/rank; 533 534event ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller {within(1s)}; 535event fault.cpu.intel.quickpath.mem_parity@chip/memory-controller; 536 537prop fault.cpu.intel.quickpath.mem_parity@chip/memory-controller (1)-> 538 ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller; 539 540event ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller {within(1s)}; 541event fault.cpu.intel.quickpath.mem_addr_parity@ 542 chip/memory-controller; 543event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM; 544event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank; 545 546prop fault.cpu.intel.quickpath.mem_addr_parity@ 547 chip/memory-controller (1)-> 548 ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller; 549 550prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM 551 { payloadprop_contains("resource", asru(CHIPDIMM)) } (1)-> 552 ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller; 553 554prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank 555 { payloadprop_contains("resource", asru(CHIPDIMM/rank)) } (1)-> 556 ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller; 557 558event ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller {within(1s)}; 559event fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller; 560 561prop fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller (1)-> 562 ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller; 563 564event ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller {within(1s)}; 565event fault.cpu.intel.quickpath.mem_spare@ 566 chip/memory-controller/dram-channel/dimm; 567 568prop fault.cpu.intel.quickpath.mem_spare@ 569 chip/memory-controller/dram-channel/dimm (1)-> 570 ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller; 571 572event ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller {within(1s)}; 573event fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller; 574 575prop fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller (1)-> 576 ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller; 577 578event ereport.cpu.intel.quickpath.mem_redundant@chip/memory-controller {within(1s)}; 579engine serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM, N=2, T=72h; 580event fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM, 581 engine=serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM; 582 583event error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank; 584 585prop fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM (1)-> 586 error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank<>; 587prop error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank 588 { CONTAINS_RANK } (1)-> 589 ereport.cpu.intel.quickpath.mem_redundant@ 590 chip/memory-controller; 591 592#define STATUS_UC (payloadprop("error_uncorrected") == 1) 593event ereport.cpu.intel.quickpath.interconnect@chip 594 {within(1s)}; 595event upset.cpu.intel.quickpath.interconnect@chip; 596/* Diagnose corrected events to upsets */ 597prop upset.cpu.intel.quickpath.interconnect@chip 598 { !STATUS_UC } (1)-> 599 ereport.cpu.intel.quickpath.interconnect@chip; 600 601engine serd.cpu.intel.quickpath.interconnect@chip, 602 N=3, T=72h; 603event fault.cpu.intel.quickpath.interconnect@chip, 604 engine=serd.cpu.intel.quickpath.interconnect@chip; 605 606/* Diagnose uncorrected events to faults */ 607prop fault.cpu.intel.quickpath.interconnect@chip 608 { STATUS_UC } (0)-> 609 ereport.cpu.intel.quickpath.interconnect@chip; 610 611 612/* 613 * Nehalem EX specific rules 614 */ 615/* MBox errors */ 616#define EX_MEM_EVENT(leafclass, t) \ 617 event ereport.cpu.intel.quickpath.leafclass@ \ 618 chip/memory-controller { within(t) } 619 620EX_MEM_EVENT(mem_lnktrns, 1s); 621EX_MEM_EVENT(mem_lnkpers, 1s); 622EX_MEM_EVENT(mem_sbfbdlinkerr, 1s); 623EX_MEM_EVENT(mem_nbfbdlnkerr, 1s); 624EX_MEM_EVENT(mem_lnkcrcvld, 1s); 625 626engine serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller, 627 N=500, T=1week; 628event fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller, 629 engine=serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller, 630 retire=0, response=0; 631 632prop fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller -> 633 ereport.cpu.intel.quickpath.mem_lnktrns@chip/memory-controller, 634 ereport.cpu.intel.quickpath.mem_lnkpers@chip/memory-controller, 635 ereport.cpu.intel.quickpath.mem_sbfbdlinkerr@chip/memory-controller, 636 ereport.cpu.intel.quickpath.mem_nbfbdlnkerr@chip/memory-controller, 637 ereport.cpu.intel.quickpath.mem_lnkcrcvld@chip/memory-controller; 638 639EX_MEM_EVENT(mem_lnkuncorr_uc, 1s); 640EX_MEM_EVENT(mem_lnkpers_uc, 1s); 641EX_MEM_EVENT(mem_sbfbdlinkerr_uc, 1s); 642EX_MEM_EVENT(mem_nbfbdlnkerr_uc, 1s); 643EX_MEM_EVENT(mem_lnkcrcvld_uc, 1s); 644 645event fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller, 646 retire=0; 647 648prop fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller -> 649 ereport.cpu.intel.quickpath.mem_lnkuncorr_uc@chip/memory-controller, 650 ereport.cpu.intel.quickpath.mem_lnkpers_uc@chip/memory-controller, 651 ereport.cpu.intel.quickpath.mem_sbfbdlinkerr_uc@chip/memory-controller, 652 ereport.cpu.intel.quickpath.mem_nbfbdlnkerr_uc@chip/memory-controller, 653 ereport.cpu.intel.quickpath.mem_lnkcrcvld_uc@chip/memory-controller; 654 655EX_MEM_EVENT(mem_ptrl_fsm_err, 1s); 656EX_MEM_EVENT(mem_errflw_fsm_fail, 1s); 657EX_MEM_EVENT(mem_vberr, 1s); 658 659engine serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller, 660 N=500, T=1week; 661event fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller, 662 engine=serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller, 663 retire=0, response=0; 664 665prop fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller -> 666 ereport.cpu.intel.quickpath.mem_ptrl_fsm_err@chip/memory-controller, 667 ereport.cpu.intel.quickpath.mem_errflw_fsm_fail@chip/memory-controller, 668 ereport.cpu.intel.quickpath.mem_vberr@chip/memory-controller; 669 670EX_MEM_EVENT(mem_ptrl_fsm_err_uc, 1s); 671EX_MEM_EVENT(mem_errflw_fsm_fail_uc, 1s); 672EX_MEM_EVENT(mem_mcpar_fsmerr_uc, 1s); 673EX_MEM_EVENT(mem_vberr_uc, 1s); 674EX_MEM_EVENT(mem_fberr_uc, 1s); 675 676event fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller, 677 retire=0; 678 679prop fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller -> 680 ereport.cpu.intel.quickpath.mem_ptrl_fsm_err_uc@chip/memory-controller, 681 ereport.cpu.intel.quickpath.mem_errflw_fsm_fail_uc@chip/memory-controller, 682 ereport.cpu.intel.quickpath.mem_mcpar_fsmerr_uc@chip/memory-controller, 683 ereport.cpu.intel.quickpath.mem_vberr_uc@chip/memory-controller, 684 ereport.cpu.intel.quickpath.mem_fberr_uc@chip/memory-controller; 685 686EX_MEM_EVENT(mem_scrubbing_uc, 1s); 687event fault.cpu.intel.quickpath.mem_scrubbing@ 688 chip/memory-controller/dram-channel/dimm/rank, 689 response=0; 690 691prop fault.cpu.intel.quickpath.mem_scrubbing@ 692 chip/memory-controller/dram-channel/dimm/rank[rank_num] 693 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 694 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 695 SET_ADDR && SET_OFFSET } (1)-> 696 ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller; 697 698EX_MEM_EVENT(mem_ecc_uc, 12s); 699EX_MEM_EVENT(mem_even_parity_uc, 1s); 700 701EX_MEM_EVENT(mem_ecc, 12s); 702EX_MEM_EVENT(mem_even_parity, 1s); 703 704event error.memory.intel.ex_dimm_ce@ 705 chip/memory-controller/dram-channel/dimm/rank; 706 707prop fault.memory.intel.page_ue@ 708 chip/memory-controller/dram-channel/dimm/rank[rank_num] 709 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 710 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 711 SET_ADDR && SET_OFFSET } (0)-> 712 ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller, 713 ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller; 714 715prop fault.memory.intel.page_ce@ 716 chip/memory-controller/dram-channel/dimm/rank[rank_num] 717 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 718 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 719 SET_ADDR && SET_OFFSET } (0)-> 720 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, 721 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 722 723prop error.memory.intel.dimm_ue_ex@ 724 chip/memory-controller/dram-channel/dimm/rank[rank_num] 725 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 726 ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller, 727 ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller; 728 729prop fault.memory.intel.dimm_ce@ 730 chip/memory-controller/dram-channel/dimm 731 { !confprop_defined(chip/memory-controller/dram-channel/dimm, 732 "dimm-size") && setserdn(10) & setserdt(1week) } (0)-> 733 error.memory.intel.ex_dimm_ce@ 734 chip/memory-controller/dram-channel/dimm/rank; 735prop error.memory.intel.ex_dimm_ce@ 736 chip/memory-controller/dram-channel/dimm/rank[rank_num] 737 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 738 !confprop_defined(chip/memory-controller/dram-channel/dimm, 739 "dimm-size") && 740 count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (1)-> 741 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, 742 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 743 744#define EX_CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 745 prop fault.memory.intel.dimm_ce@ \ 746 chip/memory-controller/dram-channel/dimm { \ 747 confprop(chip/memory-controller/dram-channel/dimm, \ 748 "dimm-size") == dimm_size && \ 749 setserdn(n) & setserdt(t) } (0)-> \ 750 error.memory.intel.ex_dimm_ce@ \ 751 chip/memory-controller/dram-channel/dimm/rank; \ 752 prop error.memory.intel.ex_dimm_ce@ \ 753 chip/memory-controller/dram-channel/dimm/rank[rank_num] { \ 754 payloadprop_defined("rank") && rank_num == payloadprop("rank") && \ 755 confprop(chip/memory-controller/dram-channel/dimm, \ 756 "dimm-size") == dimm_size && \ 757 count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate } (1)-> \ 758 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, \ 759 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 760 761EX_CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 762EX_CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 763EX_CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 764EX_CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 765EX_CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 766 767event upset.memory.intel.discard@chip/memory-controller{within(1s)}; 768 769prop upset.memory.intel.discard@chip/memory-controller (0)-> 770 ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller, 771 ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller, 772 ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller, 773 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, 774 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 775 776EX_MEM_EVENT(mem_failover_mir, 1s); 777event fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller, 778 retire=0; 779 780prop fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller -> 781 ereport.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller; 782 783/* 784 * RBox errors 785 */ 786#define EX_EVENT(leafclass, t) \ 787 event ereport.cpu.intel.quickpath.leafclass@chip { within(t) } 788 789engine serd.cpu.intel.quickpath.bus_interconnect@chip, 790 N=3, T=72h; 791event fault.cpu.intel.quickpath.bus_interconnect@chip, 792 engine=serd.cpu.intel.quickpath.bus_interconnect@chip, 793 retire=0; 794 795EX_EVENT(bus_retry_abort, 1s); 796EX_EVENT(bus_link_init_ce, 1s); 797event upset.cpu.intel.quickpath.discard@chip; 798 799prop upset.cpu.intel.quickpath.discard@chip (0)-> 800 ereport.cpu.intel.quickpath.bus_retry_abort@chip, 801 ereport.cpu.intel.quickpath.bus_link_init_ce@chip; 802 803EX_EVENT(bus_unknown, 1s); 804EX_EVENT(bus_single_ecc, 1s); 805EX_EVENT(bus_crc_flit, 1s); 806 807prop fault.cpu.intel.quickpath.bus_interconnect@chip (0)-> 808 ereport.cpu.intel.quickpath.bus_unknown@chip, 809 ereport.cpu.intel.quickpath.bus_single_ecc@chip, 810 ereport.cpu.intel.quickpath.bus_crc_flit@chip; 811 812EX_EVENT(bus_unknown_external, 1s); 813EX_EVENT(bus_crc_flit_external, 1s); 814prop upset.cpu.intel.quickpath.discard@chip (0)-> 815 ereport.cpu.intel.quickpath.bus_unknown_external@chip, 816 ereport.cpu.intel.quickpath.bus_crc_flit_external@chip; 817 818EX_EVENT(bus_unknown_uc, 1s); 819EX_EVENT(bus_opr_poison_err, 1s); 820EX_EVENT(bus_eot_parity, 1s); 821EX_EVENT(bus_rta_parity, 1s); 822EX_EVENT(bus_bad_sbu_route, 1s); 823EX_EVENT(bus_bad_msg, 1s); 824EX_EVENT(bus_bad_vn_credit, 1s); 825EX_EVENT(bus_hdr_double_ecc, 1s); 826EX_EVENT(bus_link_retry_err, 1s); 827 828prop fault.cpu.intel.quickpath.bus_interconnect@chip 829 { setserdincrement(4) } (0)-> 830 ereport.cpu.intel.quickpath.bus_unknown_uc@chip, 831 ereport.cpu.intel.quickpath.bus_opr_poison_err@chip, 832 ereport.cpu.intel.quickpath.bus_eot_parity@chip, 833 ereport.cpu.intel.quickpath.bus_rta_parity@chip, 834 ereport.cpu.intel.quickpath.bus_bad_sbu_route@chip, 835 ereport.cpu.intel.quickpath.bus_bad_msg@chip, 836 ereport.cpu.intel.quickpath.bus_bad_vn_credit@chip, 837 ereport.cpu.intel.quickpath.bus_hdr_double_ecc@chip, 838 ereport.cpu.intel.quickpath.bus_link_retry_err@chip; 839 840EX_EVENT(bus_unknown_uc_external, 1s); 841EX_EVENT(bus_opr_poison_err_external, 1s); 842EX_EVENT(bus_eot_parity_external, 1s); 843EX_EVENT(bus_rta_parity_external, 1s); 844EX_EVENT(bus_bad_sbu_route_external, 1s); 845EX_EVENT(bus_bad_msg_external, 1s); 846EX_EVENT(bus_bad_vn_credit_external, 1s); 847EX_EVENT(bus_hdr_double_ecc_external, 1s); 848EX_EVENT(bus_link_retry_err_external, 1s); 849 850prop upset.cpu.intel.quickpath.discard@chip (0)-> 851 ereport.cpu.intel.quickpath.bus_unknown_uc_external@chip, 852 ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip, 853 ereport.cpu.intel.quickpath.bus_eot_parity_external@chip, 854 ereport.cpu.intel.quickpath.bus_rta_parity_external@chip, 855 ereport.cpu.intel.quickpath.bus_bad_sbu_route_external@chip, 856 ereport.cpu.intel.quickpath.bus_bad_msg_external@chip, 857 ereport.cpu.intel.quickpath.bus_bad_vn_credit_external@chip, 858 ereport.cpu.intel.quickpath.bus_hdr_double_ecc_external@chip, 859 ereport.cpu.intel.quickpath.bus_link_retry_err_external@chip; 860 861/* 862 * CBox errors 863 */ 864EX_EVENT(llc_ewb_uc, 1s); 865event fault.cpu.intel.quickpath.llc_ewb@chip, 866 retire=0, response=0; 867 868prop fault.cpu.intel.quickpath.llc_ewb@chip 869 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 870 SET_ADDR && SET_OFFSET } (1)-> 871 ereport.cpu.intel.quickpath.llc_ewb_uc@chip; 872 873prop upset.cpu.intel.quickpath.discard@chip (0)-> 874 ereport.cpu.intel.quickpath.llc_ewb_uc@chip; 875 876/* 877 * SBox errors 878 */ 879EX_EVENT(system_cache_uc, 1s); 880event fault.cpu.intel.quickpath.system_cache@chip, 881 retire=0, response=0; 882prop fault.cpu.intel.quickpath.system_cache@chip -> 883 ereport.cpu.intel.quickpath.system_cache_uc@chip; 884 885/* 886 * BBox errors 887 */ 888EX_EVENT(home_agent_uc, 1s); 889event fault.cpu.intel.quickpath.home_agent@chip, 890 retire=0, response=0; 891prop fault.cpu.intel.quickpath.home_agent@chip -> 892 ereport.cpu.intel.quickpath.home_agent_uc@chip; 893 894/* 895 * UBox errors 896 */ 897EX_EVENT(sys_cfg_cfa_ecc, 1s); 898EX_EVENT(sys_cfg_uc, 1s); 899 900engine serd.cpu.intel.quickpath.sys_cfg@chip, 901 N=2, T=72h; 902event fault.cpu.intel.quickpath.sys_cfg@chip, 903 engine=serd.cpu.intel.quickpath.sys_cfg@chip, 904 retire=0, response=0; 905 906prop fault.cpu.intel.quickpath.sys_cfg@chip (0)-> 907 ereport.cpu.intel.quickpath.sys_cfg_cfa_ecc@chip; 908 909prop fault.cpu.intel.quickpath.sys_cfg@chip 910 { setserdincrement(3) } (0)-> 911 ereport.cpu.intel.quickpath.sys_cfg_uc@chip; 912 913/* 914 * Handling poison errors 915 */ 916engine stat.has_poison@motherboard; 917event fault.cpu.intel.has_poison@motherboard, 918 count=stat.has_poison@motherboard[0], 919 message=0, retire=0, response=0; 920engine stat.discard_fatal@motherboard; 921event fault.cpu.intel.discard_fatal@motherboard, 922 count=stat.discard_fatal@motherboard[0], 923 message=0, retire=0, response=0; 924 925prop fault.cpu.intel.has_poison@motherboard 926 { payloadprop_defined("poison") && 1 == payloadprop("poison") } (1)-> 927 ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip<>/memory-controller<>, 928 ereport.cpu.intel.quickpath.llc_ewb_uc@chip<>, 929 ereport.cpu.intel.quickpath.system_cache_uc@chip<>, 930 ereport.cpu.intel.quickpath.bus_opr_poison_err@chip<>, 931 ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip<>; 932 933prop fault.cpu.intel.discard_fatal@motherboard 934 { count(stat.has_poison@motherboard[0]) > count(stat.discard_fatal@motherboard[0]) && 935 payloadprop_defined("bank_number") && 5 == payloadprop("bank_number") && 936 payloadprop_defined("processor_context_corrupt") && 937 1 == payloadprop("processor_context_corrupt") } (0)-> 938 ereport.cpu.intel.internal_unclassified@chip<>/core<>/strand<> {within(10s)}; 939 940prop fault.cpu.intel.internal@chip/core/strand 941 { (count(stat.has_poison@motherboard[0]) <= count(stat.discard_fatal@motherboard[0]) || 942 !payloadprop_defined("bank_number") || 5 != payloadprop("bank_number") || 943 !payloadprop_defined("processor_context_corrupt") || 944 0 == payloadprop("processor_context_corrupt")) && 945 (payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1) } (0)-> 946 ereport.cpu.intel.internal_unclassified@chip/core/strand; 947