1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma dictionary "INTEL" 28 29/* 30 * Eversholt rules for the intel CPU/Memory 31 */ 32 33/* 34 * Ereports for Simple error codes. 35 */ 36 37#define SMPL_EVENT(leafclass, t) \ 38 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) } 39 40SMPL_EVENT(unknown, 1s); 41SMPL_EVENT(unclassified, 1s); 42SMPL_EVENT(microcode_rom_parity, 1s); 43SMPL_EVENT(external, 1s); 44SMPL_EVENT(frc, 1s); 45SMPL_EVENT(internal_timer, 1s); 46SMPL_EVENT(internal_parity, 1s); 47SMPL_EVENT(internal_unclassified, 1s); 48 49/* 50 * Propogations for all but "external" and "unknown" simple errors. 51 * If the error is uncorrected we produce a fault immediately, otherwise 52 * we diagnose it to an upset and decalre a fault when the SERD engine 53 * trips. prop statement for ereport.cpu.intel.internal_unclassified is 54 * moved to the Nehalem EX section to deal with poison case. 55 */ 56 57engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h; 58event fault.cpu.intel.internal@chip/core/strand, 59 engine=serd.cpu.intel.simple@chip/core/strand; 60 61prop fault.cpu.intel.internal@chip/core/strand 62 { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)-> 63 ereport.cpu.intel.microcode_rom_parity@chip/core/strand, 64 ereport.cpu.intel.internal_timer@chip/core/strand, 65 ereport.cpu.intel.internal_parity@chip/core/strand, 66 ereport.cpu.intel.unclassified@chip/core/strand, 67 ereport.cpu.intel.frc@chip/core/strand; 68 69/* 70 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 71 * for the corrected and uncorrected version of each error type. All are 72 * detected at chip/core/strand. 73 */ 74 75#define CMPND_EVENT(leafclass, t) \ 76 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }; \ 77 event ereport.cpu.intel.leafclass/**/_uc@chip/core/strand { within(t) } 78 79/* 80 * Ereports for Compound error codes - intel errors 81 */ 82CMPND_EVENT(l0cache, 1s); 83CMPND_EVENT(l1cache, 1s); 84CMPND_EVENT(l2cache, 1s); 85CMPND_EVENT(cache, 1s); 86 87/* 88 * Ereports for Compound error codes - TLB errors 89 */ 90CMPND_EVENT(l0dtlb, 1s); 91CMPND_EVENT(l1dtlb, 1s); 92CMPND_EVENT(l2dtlb, 1s); 93CMPND_EVENT(dtlb, 1s); 94 95CMPND_EVENT(l0itlb, 1s); 96CMPND_EVENT(l1itlb, 1s); 97CMPND_EVENT(l2itlb, 1s); 98CMPND_EVENT(itlb, 1s); 99 100CMPND_EVENT(l0tlb, 1s); 101CMPND_EVENT(l1tlb, 1s); 102CMPND_EVENT(l2tlb, 1s); 103CMPND_EVENT(tlb, 1s); 104 105/* 106 * Ereports for Compound error codes - memory hierarchy errors 107 */ 108CMPND_EVENT(l0dcache, 1s); 109CMPND_EVENT(l1dcache, 1s); 110CMPND_EVENT(l2dcache, 1s); 111CMPND_EVENT(dcache, 1s); 112 113CMPND_EVENT(l0icache, 1s); 114CMPND_EVENT(l1icache, 1s); 115CMPND_EVENT(l2icache, 1s); 116CMPND_EVENT(icache, 1s); 117 118/* 119 * Ereports for Compound error codes - bus and interconnect errors 120 */ 121CMPND_EVENT(bus_interconnect, 1s); 122CMPND_EVENT(bus_interconnect_memory, 1s); 123CMPND_EVENT(bus_interconnect_io, 1s); 124 125/* 126 * Compound error propogations. 127 * 128 * We resist the temptation propogate, for example, a single dcache fault 129 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 130 * Instead we will diagnose a distinct fault for each possible cache level, 131 * whether or not current chips have dcaches at all levels. 132 * 133 * Corrected errors are SERDed and produce a fault when the engine fires; 134 * the same fault is diagnosed immediately for a corresponding uncorrected 135 * error. 136 */ 137 138#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 139 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 140 event fault.cpu.intel.fltleaf@chip/core/strand, \ 141 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 142 \ 143 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 144 ereport.cpu.intel.erptleaf@chip/core/strand; \ 145 \ 146 prop fault.cpu.intel.fltleaf@chip/core/strand \ 147 { setserdincrement(n + 1) } (0)-> \ 148 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 149 150#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 151 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 152 event fault.cpu.intel.fltleaf@chip/core/strand, retire=0, response=0,\ 153 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 154 \ 155 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 156 ereport.cpu.intel.erptleaf@chip/core/strand; \ 157 \ 158 prop fault.cpu.intel.fltleaf@chip/core/strand \ 159 { setserdincrement(n + 1) } (0)-> \ 160 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 161 162CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 163CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 164CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 165CMPND_FLT_PROP_1(cache, cache, 12, 72h); 166 167CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 168CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 169CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 170CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 171 172CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 173CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 174CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 175CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 176 177CMPND_FLT_PROP_1(l0tlb, l0tlb, 3, 72h); 178CMPND_FLT_PROP_1(l1tlb, l1tlb, 3, 72h); 179CMPND_FLT_PROP_1(l2tlb, l2tlb, 3, 72h); 180CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 181 182CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 183CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 184CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 185CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 186 187CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 188CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 189CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 190CMPND_FLT_PROP_1(icache, icache, 12, 72h); 191 192CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 193CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 194CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 195 196event upset.discard@chip/core/strand; 197 198prop upset.discard@chip/core/strand (0)-> 199 ereport.cpu.intel.external@chip/core/strand, 200 ereport.cpu.intel.unknown@chip/core/strand; 201 202/* errors detected in northbridge */ 203 204 205/* 206 * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that 207 * we diagnose for page faults, to record the physical address of the faulting 208 * page. 209 */ 210#define SET_ADDR (!payloadprop_defined("physaddr") || \ 211 setpayloadprop("asru-physaddr", payloadprop("physaddr"))) 212 213#define SET_OFFSET (!payloadprop_defined("offset") || \ 214 setpayloadprop("asru-offset", payloadprop("offset"))) 215 216#define EREPORT_BUS_ERROR \ 217 ereport.cpu.intel.bus_interconnect_memory_uc@chip/core/strand, \ 218 ereport.cpu.intel.bus_interconnect_uc@chip/core/strand, \ 219 ereport.cpu.intel.bus_interconnect_memory@chip/core/strand, \ 220 ereport.cpu.intel.bus_interconnect@chip/core/strand, \ 221 ereport.cpu.intel.external@chip/core/strand 222 223engine stat.ce_pgflt@memory-controller/dram-channel/dimm; 224 225event ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller{within(12s)}; 226event ereport.cpu.intel.nb.ddr2_mem_ue@ 227 motherboard/memory-controller{within(12s)}; 228event ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller{within(12s)}; 229event fault.memory.intel.page_ue@ 230 motherboard/memory-controller/dram-channel/dimm/rank, 231 message=0, response=0; 232event fault.memory.intel.dimm_ue@ 233 motherboard/memory-controller/dram-channel/dimm/rank; 234 235prop fault.memory.intel.page_ue@ 236 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 237 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 238 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 239 SET_ADDR && SET_OFFSET } (1)-> 240 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 241 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 242 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 243 244prop fault.memory.intel.dimm_ue@ 245 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 246 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 247 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 248 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 249 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 250 251event upset.memory.intel.discard@motherboard/memory-controller{within(1s)}; 252 253prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 254 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 255 ereport.cpu.intel.nb.ddr2_mem_ue@motherboard/memory-controller, 256 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 257 258prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 259 EREPORT_BUS_ERROR; 260 261#define PAGE_CE_COUNT 2 262#define PAGE_CE_TIME 72h 263#define DIMM_CE_COUNT 10 264#define DIMM_CE_TIME 1week 265 266#define MBDIMM motherboard/memory-controller/dram-channel/dimm 267event ereport.cpu.intel.nb.mem_ce@MBDIMM/rank{within(12s)}; 268event ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank{within(12s)}; 269event ereport.cpu.intel.nb.ddr2_mem_ce@ 270 motherboard/memory-controller{within(12s)}; 271 272engine serd.memory.intel.page_ce@MBDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 273event fault.memory.intel.page_ce@MBDIMM/rank, message=0, response=0, 274 count=stat.ce_pgflt@MBDIMM, engine=serd.memory.intel.page_ce@MBDIMM/rank; 275prop fault.memory.intel.page_ce@MBDIMM/rank 276 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 277 SET_ADDR && SET_OFFSET } (0)-> 278 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, 279 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 280 281engine serd.memory.intel.dimm_ce@MBDIMM/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME; 282event fault.memory.intel.dimm_ce@MBDIMM/rank, 283 engine=serd.memory.intel.dimm_ce@MBDIMM/rank; 284prop fault.memory.intel.dimm_ce@MBDIMM/rank 285 { !confprop_defined(MBDIMM, "dimm-size") && 286 count(stat.ce_pgflt@MBDIMM) > 512 } (1)-> 287 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, 288 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 289#define DIMM_CE(dimm_size, n, t, fault_rate) \ 290 prop fault.memory.intel.dimm_ce@MBDIMM/rank { \ 291 confprop(MBDIMM, "dimm-size") == dimm_size && \ 292 count(stat.ce_pgflt@MBDIMM) > fault_rate && \ 293 setserdn(n) & setserdt(t) } (1)-> \ 294 ereport.cpu.intel.nb.mem_ce@MBDIMM/rank, \ 295 ereport.cpu.intel.nb.ddr2_mem_ce@MBDIMM/rank; 296 297DIMM_CE("8G", 8, 1week, 2000) 298DIMM_CE("4G", 4, 1week, 1500) 299DIMM_CE("2G", 4, 2week, 1000) 300DIMM_CE("1G", 4, 4week, 500) 301DIMM_CE("512M", 4, 8week, 250) 302DIMM_CE("256M", 4, 16week, 125) 303 304prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 305 ereport.cpu.intel.nb.ddr2_mem_ce@motherboard/memory-controller; 306 307event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)}; 308event fault.memory.intel.fbd.alert@rank, retire=0; 309 310prop fault.memory.intel.fbd.alert@rank (1)-> 311 ereport.cpu.intel.nb.fbd.alert@rank; 312 313prop fault.memory.intel.fbd.alert@rank (0)-> 314 EREPORT_BUS_ERROR; 315 316event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)}; 317event fault.memory.intel.fbd.crc@rank, retire=0; 318 319prop fault.memory.intel.fbd.crc@rank (1)-> 320 ereport.cpu.intel.nb.fbd.crc@rank; 321 322prop fault.memory.intel.fbd.crc@rank (0)-> EREPORT_BUS_ERROR; 323 324event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)}; 325event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0; 326 327prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)-> 328 ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller; 329 330prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)-> 331 EREPORT_BUS_ERROR; 332 333event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)}; 334engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month; 335event fault.memory.intel.fbd.ch@dram-channel, retire=0, 336 engine=serd.cpu.intel.nb.fbd.ch@dram-channel; 337 338prop fault.memory.intel.fbd.ch@dram-channel (1)-> 339 ereport.cpu.intel.nb.fbd.ch@dram-channel; 340 341prop fault.memory.intel.fbd.ch@dram-channel (0)-> 342 EREPORT_BUS_ERROR; 343 344event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)}; 345engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week; 346event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0, 347 engine=serd.cpu.intel.nb.fbd_otf@dram-channel; 348 349prop fault.memory.intel.fbd.otf@dram-channel (1)-> 350 ereport.cpu.intel.nb.fbd.otf@dram-channel; 351 352event ereport.cpu.intel.nb.otf@motherboard {within(12s)}; 353event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0; 354 355prop fault.cpu.intel.nb.otf@motherboard (1)-> 356 ereport.cpu.intel.nb.otf@motherboard; 357 358event ereport.cpu.intel.nb.unknown@motherboard {within(12s)}; 359event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)}; 360event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)}; 361event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)}; 362event ereport.cpu.intel.nb.ddr2_spd@ 363 memory-controller/dram-channel {within(12s)}; 364event upset.discard@memory-controller; 365 366prop upset.discard@memory-controller (0)-> 367 ereport.cpu.intel.nb.unknown@motherboard, 368 ereport.cpu.intel.nb.unknown@memory-controller, 369 ereport.cpu.intel.nb.unknown@memory-controller/dram-channel, 370 ereport.cpu.intel.nb.spd@memory-controller/dram-channel, 371 ereport.cpu.intel.nb.ddr2_spd@memory-controller/dram-channel; 372 373event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)}; 374event ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller{within(30s)}; 375event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank, 376 retire=0; 377 378prop fault.memory.intel.fbd.mem_ds@ 379 memory-controller/dram-channel/dimm/rank[rank_num] 380 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 381 ereport.cpu.intel.nb.mem_ds@memory-controller, 382 ereport.cpu.intel.nb.ddr2_mem_ds@memory-controller; 383 384event ereport.cpu.intel.nb.fsb@chip{within(12s)}; 385event fault.cpu.intel.nb.fsb@chip, retire=0; 386 387prop fault.cpu.intel.nb.fsb@chip (1)-> 388 ereport.cpu.intel.nb.fsb@chip; 389 390prop fault.cpu.intel.nb.fsb@chip (0)-> EREPORT_BUS_ERROR; 391 392event ereport.cpu.intel.nb.ie@motherboard{within(12s)}; 393event fault.cpu.intel.nb.ie@motherboard, retire=0; 394event upset.cpu.intel.nb.ie_ce@motherboard{within(12s)}; 395 396prop upset.cpu.intel.nb.ie_ce@motherboard 397 { payloadprop("intel-error-list") == "B6" } (0)-> 398 ereport.cpu.intel.nb.ie@motherboard; 399 400prop fault.cpu.intel.nb.ie@motherboard 401 { payloadprop("intel-error-list") != "B6" } (1)-> 402 ereport.cpu.intel.nb.ie@motherboard; 403 404prop fault.cpu.intel.nb.ie@motherboard (0)-> EREPORT_BUS_ERROR; 405 406event ereport.cpu.intel.nb.dma@motherboard{within(12s)}; 407event fault.cpu.intel.nb.dma@motherboard, retire=0, response=0; 408 409prop fault.cpu.intel.nb.dma@motherboard (1)-> 410 ereport.cpu.intel.nb.dma@motherboard; 411 412prop fault.cpu.intel.nb.dma@motherboard (0)-> EREPORT_BUS_ERROR; 413 414event ereport.cpu.intel.nb.esi@motherboard{within(12s)}; 415event ereport.cpu.intel.nb.pex@hostbridge{within(12s)}; 416event upset.cpu.intel.nb.pex@hostbridge; 417 418prop upset.cpu.intel.nb.pex@hostbridge (1)-> 419 ereport.cpu.intel.nb.esi@motherboard, 420 ereport.cpu.intel.nb.pex@hostbridge; 421 422prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR; 423 424event ereport.cpu.intel.nb.unknown@rank{within(12s)}; 425event upset.discard@rank; 426 427prop upset.discard@rank (1)-> 428 ereport.cpu.intel.nb.unknown@rank; 429 430prop upset.discard@rank (0)-> EREPORT_BUS_ERROR; 431 432/* 433 * CPU integrated memory controller 434 */ 435 436#define CONTAINS_RANK (payloadprop_contains("resource", \ 437 asru(chip/memory-controller/dram-channel/dimm/rank)) || \ 438 payloadprop_contains("resource", \ 439 asru(chip/memory-controller/dram-channel/dimm))) 440 441#define STAT_CPU_MEM_CE_PGFLTS \ 442 stat.ce_pgflt@chip/memory-controller/dram-channel/dimm 443 444#define SET_RES_OFFSET \ 445 (!payloadprop_defined("resource[0].hc-specific.offset") || \ 446 setpayloadprop("asru-offset", \ 447 payloadprop("resource[0].hc-specific.offset"))) 448 449engine STAT_CPU_MEM_CE_PGFLTS; 450 451event ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller 452 {within(12s)}; 453 454event fault.memory.intel.page_ue@ 455 chip/memory-controller/dram-channel/dimm/rank, 456 message=0, response=0; /* do not message individual pageflts */ 457 458prop fault.memory.intel.page_ue@ 459 chip/memory-controller/dram-channel/dimm/rank 460 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 461 payloadprop_defined("resource[0].hc-specific.offset")) && 462 SET_ADDR && SET_RES_OFFSET } (0)-> 463 ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller; 464 465#define CHIPDIMM chip/memory-controller/dram-channel/dimm 466 467event fault.memory.intel.dimm_ue@CHIPDIMM/rank; 468 469event error.memory.intel.dimm_ue_ep@CHIPDIMM/rank; 470event error.memory.intel.dimm_ue_ex@CHIPDIMM/rank; 471 472prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (1)-> 473 error.memory.intel.dimm_ue_ep@CHIPDIMM/rank, 474 error.memory.intel.dimm_ue_ex@CHIPDIMM/rank; 475 476prop error.memory.intel.dimm_ue_ep@CHIPDIMM/rank 477 { CONTAINS_RANK } (1)-> 478 ereport.cpu.intel.quickpath.mem_ue@chip/memory-controller; 479 480prop fault.memory.intel.dimm_ue@CHIPDIMM/rank (0)-> EREPORT_BUS_ERROR; 481 482event ereport.cpu.intel.quickpath.mem_ce@ 483 chip/memory-controller{within(12s)}; 484 485engine serd.memory.intel.page_ce@CHIPDIMM/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 486event fault.memory.intel.page_ce@CHIPDIMM/rank, message=0, response=0, 487 count=STAT_CPU_MEM_CE_PGFLTS, 488 engine=serd.memory.intel.page_ce@CHIPDIMM/rank; 489prop fault.memory.intel.page_ce@CHIPDIMM/rank 490 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 491 payloadprop_defined("resource[0].hc-specific.offset")) && 492 SET_ADDR && SET_RES_OFFSET } (0)-> 493 ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller; 494 495engine serd.memory.intel.dimm_ce@CHIPDIMM, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 496event fault.memory.intel.dimm_ce@CHIPDIMM, 497 engine=serd.memory.intel.dimm_ce@CHIPDIMM; 498prop fault.memory.intel.dimm_ce@CHIPDIMM 499 { !confprop_defined(CHIPDIMM, "dimm-size") && 500 count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (0)-> 501 ereport.cpu.intel.quickpath.mem_ce@chip/memory-controller; 502 503#define CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 504 prop fault.memory.intel.dimm_ce@CHIPDIMM { \ 505 confprop(CHIPDIMM, "dimm-size") == dimm_size && \ 506 count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate && \ 507 setserdn(n) & setserdt(t) } (0)-> \ 508 ereport.cpu.intel.quickpath.mem_ce@ \ 509 chip/memory-controller; 510 511CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 512CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 513CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 514CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 515CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 516CPU_MEM_DIMM_CE("512M", 4, 8week, 250) 517 518event ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller {within(12s)}; 519event ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller/dram-channel 520 {within(12s)}; 521event ereport.cpu.intel.quickpath.mem_unknown@ 522 chip/memory-controller/dram-channel/dimm/rank{within(12s)}; 523event upset.discard@chip/memory-controller; 524event upset.discard@chip/memory-controller/dram-channel/dimm/rank; 525 526prop upset.discard@chip/memory-controller (0)-> 527 ereport.cpu.intel.quickpath.mem_unknown@chip/memory-controller, 528 ereport.cpu.intel.quickpath.mem_unknown@ 529 chip/memory-controller/dram-channel; 530 531prop upset.discard@ 532 chip/memory-controller/dram-channel/dimm/rank (1)-> 533 ereport.cpu.intel.quickpath.mem_unknown@ 534 chip/memory-controller/dram-channel/dimm/rank; 535 536event ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller {within(1s)}; 537event fault.cpu.intel.quickpath.mem_parity@chip/memory-controller; 538 539prop fault.cpu.intel.quickpath.mem_parity@chip/memory-controller (1)-> 540 ereport.cpu.intel.quickpath.mem_parity@chip/memory-controller; 541 542event ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller {within(1s)}; 543event fault.cpu.intel.quickpath.mem_addr_parity@ 544 chip/memory-controller; 545event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM; 546event fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank; 547 548prop fault.cpu.intel.quickpath.mem_addr_parity@ 549 chip/memory-controller (1)-> 550 ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller; 551 552prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM 553 { payloadprop_contains("resource", asru(CHIPDIMM)) } (1)-> 554 ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller; 555 556prop fault.cpu.intel.quickpath.mem_addr_parity@CHIPDIMM/rank 557 { payloadprop_contains("resource", asru(CHIPDIMM/rank)) } (1)-> 558 ereport.cpu.intel.quickpath.mem_addr_parity@chip/memory-controller; 559 560event ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller {within(1s)}; 561event fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller; 562 563prop fault.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller (1)-> 564 ereport.cpu.intel.quickpath.mem_bad_addr@chip/memory-controller; 565 566event ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller {within(1s)}; 567event fault.cpu.intel.quickpath.mem_spare@ 568 chip/memory-controller/dram-channel/dimm; 569 570prop fault.cpu.intel.quickpath.mem_spare@ 571 chip/memory-controller/dram-channel/dimm (1)-> 572 ereport.cpu.intel.quickpath.mem_spare@chip/memory-controller; 573 574event ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller {within(1s)}; 575event fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller; 576 577prop fault.cpu.intel.quickpath.mem_bad_id@chip/memory-controller (1)-> 578 ereport.cpu.intel.quickpath.mem_bad_id@chip/memory-controller; 579 580event ereport.cpu.intel.quickpath.mem_redundant@chip/memory-controller {within(1s)}; 581engine serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM, N=2, T=72h; 582event fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM, 583 engine=serd.cpu.intel.quickpath.mem_redundant@CHIPDIMM; 584 585event error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank; 586 587prop fault.cpu.intel.quickpath.mem_redundant@CHIPDIMM (1)-> 588 error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank 589 { is_under(CHIPDIMM, CHIPDIMM/rank) }; 590prop error.cpu.intel.quickpath.mem_redundant@CHIPDIMM/rank 591 { CONTAINS_RANK } (1)-> 592 ereport.cpu.intel.quickpath.mem_redundant@ 593 chip/memory-controller; 594 595#define STATUS_UC (payloadprop("error_uncorrected") == 1) 596event ereport.cpu.intel.quickpath.interconnect@chip 597 {within(1s)}; 598event upset.cpu.intel.quickpath.interconnect@chip; 599/* Diagnose corrected events to upsets */ 600prop upset.cpu.intel.quickpath.interconnect@chip 601 { !STATUS_UC } (1)-> 602 ereport.cpu.intel.quickpath.interconnect@chip; 603 604engine serd.cpu.intel.quickpath.interconnect@chip, 605 N=3, T=72h; 606event fault.cpu.intel.quickpath.interconnect@chip, 607 engine=serd.cpu.intel.quickpath.interconnect@chip; 608 609/* Diagnose uncorrected events to faults */ 610prop fault.cpu.intel.quickpath.interconnect@chip 611 { STATUS_UC } (0)-> 612 ereport.cpu.intel.quickpath.interconnect@chip; 613 614 615/* 616 * Nehalem EX specific rules 617 */ 618/* MBox errors */ 619#define EX_MEM_EVENT(leafclass, t) \ 620 event ereport.cpu.intel.quickpath.leafclass@ \ 621 chip/memory-controller { within(t) } 622 623EX_MEM_EVENT(mem_lnktrns, 1s); 624EX_MEM_EVENT(mem_lnkpers, 1s); 625EX_MEM_EVENT(mem_sbfbdlinkerr, 1s); 626EX_MEM_EVENT(mem_nbfbdlnkerr, 1s); 627EX_MEM_EVENT(mem_lnkcrcvld, 1s); 628 629engine serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller, 630 N=500, T=1week; 631event fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller, 632 engine=serd.cpu.intel.quickpath.mem_link_ce@chip/memory-controller, 633 retire=0, response=0; 634 635prop fault.cpu.intel.quickpath.mem_link_ce@chip/memory-controller -> 636 ereport.cpu.intel.quickpath.mem_lnktrns@chip/memory-controller, 637 ereport.cpu.intel.quickpath.mem_lnkpers@chip/memory-controller, 638 ereport.cpu.intel.quickpath.mem_sbfbdlinkerr@chip/memory-controller, 639 ereport.cpu.intel.quickpath.mem_nbfbdlnkerr@chip/memory-controller, 640 ereport.cpu.intel.quickpath.mem_lnkcrcvld@chip/memory-controller; 641 642EX_MEM_EVENT(mem_lnkuncorr_uc, 1s); 643EX_MEM_EVENT(mem_lnkpers_uc, 1s); 644EX_MEM_EVENT(mem_sbfbdlinkerr_uc, 1s); 645EX_MEM_EVENT(mem_nbfbdlnkerr_uc, 1s); 646EX_MEM_EVENT(mem_lnkcrcvld_uc, 1s); 647 648event fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller, 649 retire=0; 650 651prop fault.cpu.intel.quickpath.mem_link_ue@chip/memory-controller -> 652 ereport.cpu.intel.quickpath.mem_lnkuncorr_uc@chip/memory-controller, 653 ereport.cpu.intel.quickpath.mem_lnkpers_uc@chip/memory-controller, 654 ereport.cpu.intel.quickpath.mem_sbfbdlinkerr_uc@chip/memory-controller, 655 ereport.cpu.intel.quickpath.mem_nbfbdlnkerr_uc@chip/memory-controller, 656 ereport.cpu.intel.quickpath.mem_lnkcrcvld_uc@chip/memory-controller; 657 658EX_MEM_EVENT(mem_ptrl_fsm_err, 1s); 659EX_MEM_EVENT(mem_errflw_fsm_fail, 1s); 660EX_MEM_EVENT(mem_vberr, 1s); 661 662engine serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller, 663 N=500, T=1week; 664event fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller, 665 engine=serd.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller, 666 retire=0, response=0; 667 668prop fault.cpu.intel.quickpath.mem_controller_ce@chip/memory-controller -> 669 ereport.cpu.intel.quickpath.mem_ptrl_fsm_err@chip/memory-controller, 670 ereport.cpu.intel.quickpath.mem_errflw_fsm_fail@chip/memory-controller, 671 ereport.cpu.intel.quickpath.mem_vberr@chip/memory-controller; 672 673EX_MEM_EVENT(mem_ptrl_fsm_err_uc, 1s); 674EX_MEM_EVENT(mem_errflw_fsm_fail_uc, 1s); 675EX_MEM_EVENT(mem_mcpar_fsmerr_uc, 1s); 676EX_MEM_EVENT(mem_vberr_uc, 1s); 677EX_MEM_EVENT(mem_fberr_uc, 1s); 678 679event fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller, 680 retire=0; 681 682prop fault.cpu.intel.quickpath.mem_controller_ue@chip/memory-controller -> 683 ereport.cpu.intel.quickpath.mem_ptrl_fsm_err_uc@chip/memory-controller, 684 ereport.cpu.intel.quickpath.mem_errflw_fsm_fail_uc@chip/memory-controller, 685 ereport.cpu.intel.quickpath.mem_mcpar_fsmerr_uc@chip/memory-controller, 686 ereport.cpu.intel.quickpath.mem_vberr_uc@chip/memory-controller, 687 ereport.cpu.intel.quickpath.mem_fberr_uc@chip/memory-controller; 688 689EX_MEM_EVENT(mem_scrubbing_uc, 1s); 690event fault.cpu.intel.quickpath.mem_scrubbing@ 691 chip/memory-controller/dram-channel/dimm/rank, 692 response=0; 693 694prop fault.cpu.intel.quickpath.mem_scrubbing@ 695 chip/memory-controller/dram-channel/dimm/rank[rank_num] 696 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 697 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 698 SET_ADDR && SET_OFFSET } (1)-> 699 ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller; 700 701EX_MEM_EVENT(mem_ecc_uc, 12s); 702EX_MEM_EVENT(mem_even_parity_uc, 1s); 703 704EX_MEM_EVENT(mem_ecc, 12s); 705EX_MEM_EVENT(mem_even_parity, 1s); 706 707event error.memory.intel.ex_dimm_ce@ 708 chip/memory-controller/dram-channel/dimm/rank; 709 710prop fault.memory.intel.page_ue@ 711 chip/memory-controller/dram-channel/dimm/rank[rank_num] 712 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 713 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 714 SET_ADDR && SET_OFFSET } (0)-> 715 ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller, 716 ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller; 717 718prop fault.memory.intel.page_ce@ 719 chip/memory-controller/dram-channel/dimm/rank[rank_num] 720 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 721 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 722 SET_ADDR && SET_OFFSET } (0)-> 723 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, 724 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 725 726prop error.memory.intel.dimm_ue_ex@ 727 chip/memory-controller/dram-channel/dimm/rank[rank_num] 728 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 729 ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller, 730 ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller; 731 732prop fault.memory.intel.dimm_ce@ 733 chip/memory-controller/dram-channel/dimm 734 { !confprop_defined(chip/memory-controller/dram-channel/dimm, 735 "dimm-size") && setserdn(10) & setserdt(1week) } (0)-> 736 error.memory.intel.ex_dimm_ce@ 737 chip/memory-controller/dram-channel/dimm/rank; 738prop error.memory.intel.ex_dimm_ce@ 739 chip/memory-controller/dram-channel/dimm/rank[rank_num] 740 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 741 !confprop_defined(chip/memory-controller/dram-channel/dimm, 742 "dimm-size") && 743 count(STAT_CPU_MEM_CE_PGFLTS) > 512 } (1)-> 744 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, 745 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 746 747#define EX_CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 748 prop fault.memory.intel.dimm_ce@ \ 749 chip/memory-controller/dram-channel/dimm { \ 750 confprop(chip/memory-controller/dram-channel/dimm, \ 751 "dimm-size") == dimm_size && \ 752 setserdn(n) & setserdt(t) } (0)-> \ 753 error.memory.intel.ex_dimm_ce@ \ 754 chip/memory-controller/dram-channel/dimm/rank; \ 755 prop error.memory.intel.ex_dimm_ce@ \ 756 chip/memory-controller/dram-channel/dimm/rank[rank_num] { \ 757 payloadprop_defined("rank") && rank_num == payloadprop("rank") && \ 758 confprop(chip/memory-controller/dram-channel/dimm, \ 759 "dimm-size") == dimm_size && \ 760 count(STAT_CPU_MEM_CE_PGFLTS) > fault_rate } (1)-> \ 761 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, \ 762 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 763 764EX_CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 765EX_CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 766EX_CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 767EX_CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 768EX_CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 769 770event upset.memory.intel.discard@chip/memory-controller{within(1s)}; 771 772prop upset.memory.intel.discard@chip/memory-controller (0)-> 773 ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip/memory-controller, 774 ereport.cpu.intel.quickpath.mem_ecc_uc@chip/memory-controller, 775 ereport.cpu.intel.quickpath.mem_even_parity_uc@chip/memory-controller, 776 ereport.cpu.intel.quickpath.mem_ecc@chip/memory-controller, 777 ereport.cpu.intel.quickpath.mem_even_parity@chip/memory-controller; 778 779EX_MEM_EVENT(mem_failover_mir, 1s); 780event fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller, 781 retire=0; 782 783prop fault.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller -> 784 ereport.cpu.intel.quickpath.mem_failover_mir@chip/memory-controller; 785 786/* 787 * RBox errors 788 */ 789#define EX_EVENT(leafclass, t) \ 790 event ereport.cpu.intel.quickpath.leafclass@chip { within(t) } 791 792engine serd.cpu.intel.quickpath.bus_interconnect@chip, 793 N=3, T=72h; 794event fault.cpu.intel.quickpath.bus_interconnect@chip, 795 engine=serd.cpu.intel.quickpath.bus_interconnect@chip, 796 retire=0; 797 798EX_EVENT(bus_retry_abort, 1s); 799EX_EVENT(bus_link_init_ce, 1s); 800event upset.cpu.intel.quickpath.discard@chip; 801 802prop upset.cpu.intel.quickpath.discard@chip (0)-> 803 ereport.cpu.intel.quickpath.bus_retry_abort@chip, 804 ereport.cpu.intel.quickpath.bus_link_init_ce@chip; 805 806EX_EVENT(bus_unknown, 1s); 807EX_EVENT(bus_single_ecc, 1s); 808EX_EVENT(bus_crc_flit, 1s); 809 810prop fault.cpu.intel.quickpath.bus_interconnect@chip (0)-> 811 ereport.cpu.intel.quickpath.bus_unknown@chip, 812 ereport.cpu.intel.quickpath.bus_single_ecc@chip, 813 ereport.cpu.intel.quickpath.bus_crc_flit@chip; 814 815EX_EVENT(bus_unknown_external, 1s); 816EX_EVENT(bus_crc_flit_external, 1s); 817prop upset.cpu.intel.quickpath.discard@chip (0)-> 818 ereport.cpu.intel.quickpath.bus_unknown_external@chip, 819 ereport.cpu.intel.quickpath.bus_crc_flit_external@chip; 820 821EX_EVENT(bus_unknown_uc, 1s); 822EX_EVENT(bus_opr_poison_err, 1s); 823EX_EVENT(bus_eot_parity, 1s); 824EX_EVENT(bus_rta_parity, 1s); 825EX_EVENT(bus_bad_sbu_route, 1s); 826EX_EVENT(bus_bad_msg, 1s); 827EX_EVENT(bus_bad_vn_credit, 1s); 828EX_EVENT(bus_hdr_double_ecc, 1s); 829EX_EVENT(bus_link_retry_err, 1s); 830 831prop fault.cpu.intel.quickpath.bus_interconnect@chip 832 { setserdincrement(4) } (0)-> 833 ereport.cpu.intel.quickpath.bus_unknown_uc@chip, 834 ereport.cpu.intel.quickpath.bus_opr_poison_err@chip, 835 ereport.cpu.intel.quickpath.bus_eot_parity@chip, 836 ereport.cpu.intel.quickpath.bus_rta_parity@chip, 837 ereport.cpu.intel.quickpath.bus_bad_sbu_route@chip, 838 ereport.cpu.intel.quickpath.bus_bad_msg@chip, 839 ereport.cpu.intel.quickpath.bus_bad_vn_credit@chip, 840 ereport.cpu.intel.quickpath.bus_hdr_double_ecc@chip, 841 ereport.cpu.intel.quickpath.bus_link_retry_err@chip; 842 843EX_EVENT(bus_unknown_uc_external, 1s); 844EX_EVENT(bus_opr_poison_err_external, 1s); 845EX_EVENT(bus_eot_parity_external, 1s); 846EX_EVENT(bus_rta_parity_external, 1s); 847EX_EVENT(bus_bad_sbu_route_external, 1s); 848EX_EVENT(bus_bad_msg_external, 1s); 849EX_EVENT(bus_bad_vn_credit_external, 1s); 850EX_EVENT(bus_hdr_double_ecc_external, 1s); 851EX_EVENT(bus_link_retry_err_external, 1s); 852 853prop upset.cpu.intel.quickpath.discard@chip (0)-> 854 ereport.cpu.intel.quickpath.bus_unknown_uc_external@chip, 855 ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip, 856 ereport.cpu.intel.quickpath.bus_eot_parity_external@chip, 857 ereport.cpu.intel.quickpath.bus_rta_parity_external@chip, 858 ereport.cpu.intel.quickpath.bus_bad_sbu_route_external@chip, 859 ereport.cpu.intel.quickpath.bus_bad_msg_external@chip, 860 ereport.cpu.intel.quickpath.bus_bad_vn_credit_external@chip, 861 ereport.cpu.intel.quickpath.bus_hdr_double_ecc_external@chip, 862 ereport.cpu.intel.quickpath.bus_link_retry_err_external@chip; 863 864/* 865 * CBox errors 866 */ 867EX_EVENT(llc_ewb_uc, 1s); 868event fault.cpu.intel.quickpath.llc_ewb@chip, 869 retire=0, response=0; 870 871prop fault.cpu.intel.quickpath.llc_ewb@chip 872 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 873 SET_ADDR && SET_OFFSET } (1)-> 874 ereport.cpu.intel.quickpath.llc_ewb_uc@chip; 875 876prop upset.cpu.intel.quickpath.discard@chip (0)-> 877 ereport.cpu.intel.quickpath.llc_ewb_uc@chip; 878 879/* 880 * SBox errors 881 */ 882EX_EVENT(system_cache_uc, 1s); 883event fault.cpu.intel.quickpath.system_cache@chip, 884 retire=0, response=0; 885prop fault.cpu.intel.quickpath.system_cache@chip -> 886 ereport.cpu.intel.quickpath.system_cache_uc@chip; 887 888/* 889 * BBox errors 890 */ 891EX_EVENT(home_agent_uc, 1s); 892event fault.cpu.intel.quickpath.home_agent@chip, 893 retire=0, response=0; 894prop fault.cpu.intel.quickpath.home_agent@chip -> 895 ereport.cpu.intel.quickpath.home_agent_uc@chip; 896 897/* 898 * UBox errors 899 */ 900EX_EVENT(sys_cfg_cfa_ecc, 1s); 901EX_EVENT(sys_cfg_uc, 1s); 902 903engine serd.cpu.intel.quickpath.sys_cfg@chip, 904 N=2, T=72h; 905event fault.cpu.intel.quickpath.sys_cfg@chip, 906 engine=serd.cpu.intel.quickpath.sys_cfg@chip, 907 retire=0, response=0; 908 909prop fault.cpu.intel.quickpath.sys_cfg@chip (0)-> 910 ereport.cpu.intel.quickpath.sys_cfg_cfa_ecc@chip; 911 912prop fault.cpu.intel.quickpath.sys_cfg@chip 913 { setserdincrement(3) } (0)-> 914 ereport.cpu.intel.quickpath.sys_cfg_uc@chip; 915 916/* 917 * Handling poison errors 918 */ 919engine stat.has_poison@motherboard; 920event fault.cpu.intel.has_poison@motherboard, 921 count=stat.has_poison@motherboard[0], 922 message=0, retire=0, response=0; 923engine stat.discard_fatal@motherboard; 924event fault.cpu.intel.discard_fatal@motherboard, 925 count=stat.discard_fatal@motherboard[0], 926 message=0, retire=0, response=0; 927 928prop fault.cpu.intel.has_poison@motherboard 929 { payloadprop_defined("poison") && 1 == payloadprop("poison") } (1)-> 930 ereport.cpu.intel.quickpath.mem_scrubbing_uc@chip<>/memory-controller<>, 931 ereport.cpu.intel.quickpath.llc_ewb_uc@chip<>, 932 ereport.cpu.intel.quickpath.system_cache_uc@chip<>, 933 ereport.cpu.intel.quickpath.bus_opr_poison_err@chip<>, 934 ereport.cpu.intel.quickpath.bus_opr_poison_err_external@chip<>; 935 936prop fault.cpu.intel.discard_fatal@motherboard 937 { count(stat.has_poison@motherboard[0]) > count(stat.discard_fatal@motherboard[0]) && 938 payloadprop_defined("bank_number") && 5 == payloadprop("bank_number") && 939 payloadprop_defined("processor_context_corrupt") && 940 1 == payloadprop("processor_context_corrupt") } (0)-> 941 ereport.cpu.intel.internal_unclassified@chip<>/core<>/strand<>; 942 943prop fault.cpu.intel.internal@chip/core/strand 944 { (count(stat.has_poison@motherboard[0]) <= count(stat.discard_fatal@motherboard[0]) || 945 !payloadprop_defined("bank_number") || 5 != payloadprop("bank_number") || 946 !payloadprop_defined("processor_context_corrupt") || 947 0 == payloadprop("processor_context_corrupt")) && 948 (payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1) } (0)-> 949 ereport.cpu.intel.internal_unclassified@chip/core/strand; 950