1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29#pragma dictionary "INTEL" 30 31/* 32 * Eversholt rules for the intel CPU/Memory 33 */ 34 35/* 36 * Ereports for Simple error codes. 37 */ 38 39#define SMPL_EVENT(leafclass, t) \ 40 event ereport.cpu.intel.leafclass@chip/cpu { within(t) } 41 42SMPL_EVENT(unknown, 1s); 43SMPL_EVENT(unclassified, 1s); 44SMPL_EVENT(microcode_rom_parity, 1s); 45SMPL_EVENT(external, 1s); 46SMPL_EVENT(frc, 1s); 47SMPL_EVENT(internal_timer, 1s); 48SMPL_EVENT(internal_unclassified, 1s); 49 50/* 51 * Propogations for all but "external" and "unknown" simple errors. 52 * If the error is uncorrected we produce a fault immediately, otherwise 53 * we diagnose it to an upset and decalre a fault when the SERD engine 54 * trips. 55 */ 56 57engine serd.cpu.intel.simple@chip/cpu, N=3, T=72h; 58event fault.cpu.intel.internal@chip/cpu, engine=serd.cpu.intel.simple@chip/cpu; 59 60prop fault.cpu.intel.internal@chip/cpu 61 { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)-> 62 ereport.cpu.intel.microcode_rom_parity@chip/cpu, 63 ereport.cpu.intel.internal_timer@chip/cpu, 64 ereport.cpu.intel.unclassified@chip/cpu, 65 ereport.cpu.intel.internal_unclassified@chip/cpu, 66 ereport.cpu.intel.frc@chip/cpu; 67 68/* 69 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 70 * for the corrected and uncorrected version of each error type. All are 71 * detected at chip/cpu. 72 */ 73 74#define CMPND_EVENT(leafclass, t) \ 75 event ereport.cpu.intel.leafclass@chip/cpu { within(t) }; \ 76 event ereport.cpu.intel.leafclass/**/_uc@chip/cpu { within(t) } 77 78/* 79 * Ereports for Compound error codes - intel errors 80 */ 81CMPND_EVENT(l0cache, 1s); 82CMPND_EVENT(l1cache, 1s); 83CMPND_EVENT(l2cache, 1s); 84CMPND_EVENT(cache, 1s); 85 86/* 87 * Ereports for Compound error codes - TLB errors 88 */ 89CMPND_EVENT(l0dtlb, 1s); 90CMPND_EVENT(l1dtlb, 1s); 91CMPND_EVENT(l2dtlb, 1s); 92CMPND_EVENT(dtlb, 1s); 93 94CMPND_EVENT(l0itlb, 1s); 95CMPND_EVENT(l1itlb, 1s); 96CMPND_EVENT(l2itlb, 1s); 97CMPND_EVENT(itlb, 1s); 98 99CMPND_EVENT(l0tlb, 1s); 100CMPND_EVENT(l1tlb, 1s); 101CMPND_EVENT(l2tlb, 1s); 102CMPND_EVENT(tlb, 1s); 103 104/* 105 * Ereports for Compound error codes - memory hierarchy errors 106 */ 107CMPND_EVENT(l0dcache, 1s); 108CMPND_EVENT(l1dcache, 1s); 109CMPND_EVENT(l2dcache, 1s); 110CMPND_EVENT(dcache, 1s); 111 112CMPND_EVENT(l0icache, 1s); 113CMPND_EVENT(l1icache, 1s); 114CMPND_EVENT(l2icache, 1s); 115CMPND_EVENT(icache, 1s); 116 117/* 118 * Ereports for Compound error codes - bus and interconnect errors 119 */ 120CMPND_EVENT(bus_interconnect, 1s); 121CMPND_EVENT(bus_interconnect_memory, 1s); 122CMPND_EVENT(bus_interconnect_io, 1s); 123 124/* 125 * Compound error propogations. 126 * 127 * We resist the temptation propogate, for example, a single dcache fault 128 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 129 * Instead we will diagnose a distinct fault for each possible cache level, 130 * whether or not current chips have dcaches at all levels. 131 * 132 * Corrected errors are SERDed and produce a fault when the engine fires; 133 * the same fault is diagnosed immediately for a corresponding uncorrected 134 * error. 135 */ 136 137#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 138 engine serd.cpu.intel.fltleaf@chip/cpu, N=n, T=t; \ 139 event fault.cpu.intel.fltleaf@chip/cpu, \ 140 engine=serd.cpu.intel.fltleaf@chip/cpu; \ 141 \ 142 prop fault.cpu.intel.fltleaf@chip/cpu (0)-> \ 143 ereport.cpu.intel.erptleaf@chip/cpu; \ 144 \ 145 prop fault.cpu.intel.fltleaf@chip/cpu \ 146 { setserdincrement(n + 1) } (0)-> \ 147 ereport.cpu.intel.erptleaf/**/_uc@chip/cpu 148 149#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 150 engine serd.cpu.intel.fltleaf@chip/cpu, N=n, T=t; \ 151 event fault.cpu.intel.fltleaf@chip/cpu, retire=0, response=0, \ 152 engine=serd.cpu.intel.fltleaf@chip/cpu; \ 153 \ 154 prop fault.cpu.intel.fltleaf@chip/cpu (0)-> \ 155 ereport.cpu.intel.erptleaf@chip/cpu; \ 156 \ 157 prop fault.cpu.intel.fltleaf@chip/cpu \ 158 { setserdincrement(n + 1) } (0)-> \ 159 ereport.cpu.intel.erptleaf/**/_uc@chip/cpu 160 161CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 162CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 163CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 164CMPND_FLT_PROP_1(cache, cache, 12, 72h); 165 166CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 167CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 168CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 169CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 170 171CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 172CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 173CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 174CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 175 176CMPND_FLT_PROP_1(l0tlb, litlb, 3, 72h); 177CMPND_FLT_PROP_1(l1tlb, litlb, 3, 72h); 178CMPND_FLT_PROP_1(l2tlb, litlb, 3, 72h); 179CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 180 181CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 182CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 183CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 184CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 185 186CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 187CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 188CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 189CMPND_FLT_PROP_1(icache, icache, 12, 72h); 190 191CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 192CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 193CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 194 195event upset.discard@chip/cpu; 196 197prop upset.discard@chip/cpu (0)-> 198 ereport.cpu.intel.external@chip/cpu, 199 ereport.cpu.intel.unknown@chip/cpu; 200 201/* errors detected in northbridge */ 202 203 204/* 205 * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that 206 * we diagnose for page faults, to record the physical address of the faulting 207 * page. 208 */ 209#define SET_ADDR (!payloadprop_defined("physaddr") || \ 210 setpayloadprop("asru-physaddr", payloadprop("physaddr"))) 211 212#define SET_OFFSET (!payloadprop_defined("offset") || \ 213 setpayloadprop("asru-offset", payloadprop("offset"))) 214 215engine stat.ce_pgflt@memory-controller/dram-channel/dimm; 216 217event ereport.cpu.intel.nb.mem_ue@memory-controller{within(12s)}; 218event ereport.cpu.intel.nb.fbd.ma@memory-controller{within(12s)}; 219event fault.memory.intel.page_ue@memory-controller/dram-channel/dimm/rank, 220 message=0, response=0; 221event fault.memory.intel.dimm_ue@memory-controller/dram-channel/dimm/rank; 222 223prop fault.memory.intel.page_ue@ 224 memory-controller/dram-channel/dimm/rank[rank_num] 225 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 226 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 227 SET_ADDR && SET_OFFSET } (1)-> 228 ereport.cpu.intel.nb.mem_ue@memory-controller, 229 ereport.cpu.intel.nb.fbd.ma@memory-controller; 230 231prop fault.memory.intel.page_ue@memory-controller/dram-channel/dimm/rank (1)-> 232 ereport.cpu.intel.nb.mem_ue@memory-controller, 233 ereport.cpu.intel.nb.fbd.ma@memory-controller; 234 235prop fault.memory.intel.page_ue@memory-controller/dram-channel/dimm/rank (0)-> 236 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 237 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 238 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 239 ereport.cpu.intel.bus_interconnect@chip/cpu, 240 ereport.cpu.intel.external@chip/cpu; 241 242prop fault.memory.intel.dimm_ue@ 243 memory-controller/dram-channel<channel_num>/dimm/rank[rank_num] 244 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 245 ereport.cpu.intel.nb.mem_ue@memory-controller, 246 ereport.cpu.intel.nb.fbd.ma@memory-controller; 247 248prop fault.memory.intel.dimm_ue@memory-controller/dram-channel/dimm/rank (1)-> 249 ereport.cpu.intel.nb.mem_ue@memory-controller, 250 ereport.cpu.intel.nb.fbd.ma@memory-controller; 251 252prop fault.memory.intel.dimm_ue@memory-controller/dram-channel/dimm/rank (0)-> 253 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 254 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 255 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 256 ereport.cpu.intel.bus_interconnect@chip/cpu, 257 ereport.cpu.intel.external@chip/cpu; 258 259event upset.memory.intel.discard@memory-controller{within(1s)}; 260 261prop upset.memory.intel.discard@memory-controller 262 { !payloadprop_defined("rank") } (1)-> 263 ereport.cpu.intel.nb.mem_ue@memory-controller, 264 ereport.cpu.intel.nb.fbd.ma@memory-controller; 265 266prop upset.memory.intel.discard@memory-controller (0)-> 267 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 268 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 269 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 270 ereport.cpu.intel.bus_interconnect@chip/cpu, 271 ereport.cpu.intel.external@chip/cpu; 272 273#define PAGE_CE_COUNT 2 274#define PAGE_CE_TIME 72h 275#define DIMM_CE_COUNT 10 276#define DIMM_CE_TIME 1week 277 278event ereport.cpu.intel.nb.mem_ce@dimm/rank{within(12s)}; 279 280engine serd.memory.intel.page_ce@dimm/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 281event fault.memory.intel.page_ce@dimm/rank, message=0, response=0, 282 count=stat.ce_pgflt@dimm, engine=serd.memory.intel.page_ce@dimm/rank; 283prop fault.memory.intel.page_ce@dimm/rank 284 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 285 SET_ADDR && SET_OFFSET } (0)-> 286 ereport.cpu.intel.nb.mem_ce@dimm/rank; 287 288engine serd.memory.intel.dimm_ce@dimm/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME; 289event fault.memory.intel.dimm_ce@dimm/rank, 290 engine=serd.memory.intel.dimm_ce@dimm/rank; 291event error.memory.intel.dimm_ce@dimm; 292prop fault.memory.intel.dimm_ce@dimm/rank (1)-> 293 ereport.cpu.intel.nb.mem_ce@dimm/rank; 294prop fault.memory.intel.dimm_ce@dimm/rank 295 { !confprop_defined(dimm, "dimm-size") } (1)-> 296 error.memory.intel.dimm_ce@dimm; 297prop error.memory.intel.dimm_ce@dimm 298 { !confprop_defined(dimm, "dimm-size") && 299 count(stat.ce_pgflt@dimm) > 512 } (1)-> 300 ereport.cpu.intel.nb.mem_ce@dimm/rank; 301 302#define DIMM_CE(dimm_size, n, t, fault_rate) \ 303 prop fault.memory.intel.dimm_ce@dimm/rank { \ 304 confprop(dimm, "dimm-size") == dimm_size && \ 305 setserdn(n) & setserdt(t) } (1)-> \ 306 error.memory.intel.dimm_ce@dimm; \ 307 prop error.memory.intel.dimm_ce@dimm { \ 308 confprop(dimm, "dimm-size") == dimm_size && \ 309 count(stat.ce_pgflt@dimm) > fault_rate } (1)-> \ 310 ereport.cpu.intel.nb.mem_ce@dimm/rank; 311 312DIMM_CE("8G", 8, 1week, 2000) 313DIMM_CE("4G", 4, 1week, 1500) 314DIMM_CE("2G", 4, 2week, 1000) 315DIMM_CE("1G", 4, 4week, 500) 316DIMM_CE("512M", 4, 8week, 250) 317DIMM_CE("256M", 4, 16week, 125) 318 319event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)}; 320event fault.memory.intel.fbd.alert@rank, retire=0; 321 322prop fault.memory.intel.fbd.alert@rank (1)-> 323 ereport.cpu.intel.nb.fbd.alert@rank; 324 325prop fault.memory.intel.fbd.alert@rank (0)-> 326 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 327 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 328 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 329 ereport.cpu.intel.bus_interconnect@chip/cpu, 330 ereport.cpu.intel.external@chip/cpu; 331 332event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)}; 333event fault.memory.intel.fbd.crc@rank, retire=0; 334 335prop fault.memory.intel.fbd.crc@rank (1)-> 336 ereport.cpu.intel.nb.fbd.crc@rank; 337 338prop fault.memory.intel.fbd.crc@rank (0)-> 339 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 340 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 341 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 342 ereport.cpu.intel.bus_interconnect@chip/cpu, 343 ereport.cpu.intel.external@chip/cpu; 344 345event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)}; 346event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0; 347 348prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)-> 349 ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller; 350 351prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)-> 352 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 353 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 354 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 355 ereport.cpu.intel.bus_interconnect@chip/cpu, 356 ereport.cpu.intel.external@chip/cpu; 357 358event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)}; 359engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month; 360event fault.memory.intel.fbd.ch@dram-channel, retire=0, 361 engine=serd.cpu.intel.nb.fbd.ch@dram-channel; 362 363prop fault.memory.intel.fbd.ch@dram-channel (1)-> 364 ereport.cpu.intel.nb.fbd.ch@dram-channel; 365 366prop fault.memory.intel.fbd.ch@dram-channel (0)-> 367 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 368 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 369 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 370 ereport.cpu.intel.bus_interconnect@chip/cpu, 371 ereport.cpu.intel.external@chip/cpu; 372 373event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)}; 374engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week; 375event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0, 376 engine=serd.cpu.intel.nb.fbd_otf@dram-channel; 377 378prop fault.memory.intel.fbd.otf@dram-channel (1)-> 379 ereport.cpu.intel.nb.fbd.otf@dram-channel; 380 381event ereport.cpu.intel.nb.otf@motherboard {within(12s)}; 382event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0; 383 384prop fault.cpu.intel.nb.otf@motherboard (1)-> 385 ereport.cpu.intel.nb.otf@motherboard; 386 387event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)}; 388event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)}; 389event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)}; 390event upset.discard@memory-controller; 391 392prop upset.discard@memory-controller (0)-> 393 ereport.cpu.intel.nb.unknown@memory-controller, 394 ereport.cpu.intel.nb.unknown@memory-controller/dram-channel, 395 ereport.cpu.intel.nb.spd@memory-controller/dram-channel; 396 397event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)}; 398event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank, 399 retire=0; 400 401prop fault.memory.intel.fbd.mem_ds@ 402 memory-controller/dram-channel/dimm/rank[rank_num] 403 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 404 ereport.cpu.intel.nb.mem_ds@memory-controller; 405 406event ereport.cpu.intel.nb.fsb@chip{within(12s)}; 407event fault.cpu.intel.nb.fsb@chip, retire=0; 408 409prop fault.cpu.intel.nb.fsb@chip (1)-> 410 ereport.cpu.intel.nb.fsb@chip; 411 412prop fault.cpu.intel.nb.fsb@chip (0)-> 413 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 414 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 415 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 416 ereport.cpu.intel.bus_interconnect@chip/cpu, 417 ereport.cpu.intel.external@chip/cpu; 418 419event ereport.cpu.intel.nb.ie@motherboard{within(12s)}; 420event fault.cpu.intel.nb.ie@motherboard, retire=0; 421 422prop fault.cpu.intel.nb.ie@motherboard (1)-> 423 ereport.cpu.intel.nb.ie@motherboard; 424 425prop fault.cpu.intel.nb.ie@motherboard (0)-> 426 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 427 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 428 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 429 ereport.cpu.intel.bus_interconnect@chip/cpu, 430 ereport.cpu.intel.external@chip/cpu; 431 432event ereport.cpu.intel.nb.dma@motherboard{within(12s)}; 433event fault.cpu.intel.nb.dma@motherboard, retire=0, response=0; 434 435prop fault.cpu.intel.nb.dma@motherboard (1)-> 436 ereport.cpu.intel.nb.dma@motherboard; 437 438prop fault.cpu.intel.nb.dma@motherboard (0)-> 439 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 440 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 441 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 442 ereport.cpu.intel.bus_interconnect@chip/cpu, 443 ereport.cpu.intel.external@chip/cpu; 444 445event ereport.cpu.intel.nb.esi@motherboard{within(12s)}; 446event ereport.cpu.intel.nb.pex@hostbridge{within(12s)}; 447event upset.cpu.intel.nb.pex@hostbridge; 448 449prop upset.cpu.intel.nb.pex@hostbridge (1)-> 450 ereport.cpu.intel.nb.esi@motherboard, 451 ereport.cpu.intel.nb.pex@hostbridge; 452 453prop upset.cpu.intel.nb.pex@hostbridge (0)-> 454 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 455 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 456 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 457 ereport.cpu.intel.bus_interconnect@chip/cpu, 458 ereport.cpu.intel.external@chip/cpu; 459 460event ereport.cpu.intel.nb.unknown@rank{within(12s)}; 461event upset.discard@rank; 462 463prop upset.discard@rank (1)-> 464 ereport.cpu.intel.nb.unknown@rank; 465 466prop upset.discard@rank (0)-> 467 ereport.cpu.intel.bus_interconnect_memory_uc@chip/cpu, 468 ereport.cpu.intel.bus_interconnect_uc@chip/cpu, 469 ereport.cpu.intel.bus_interconnect_memory@chip/cpu, 470 ereport.cpu.intel.bus_interconnect@chip/cpu, 471 ereport.cpu.intel.external@chip/cpu; 472