1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma dictionary "INTEL" 28 29/* 30 * Eversholt rules for the intel CPU/Memory 31 */ 32 33/* 34 * Ereports for Simple error codes. 35 */ 36 37#define SMPL_EVENT(leafclass, t) \ 38 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) } 39 40SMPL_EVENT(unknown, 1s); 41SMPL_EVENT(unclassified, 1s); 42SMPL_EVENT(microcode_rom_parity, 1s); 43SMPL_EVENT(external, 1s); 44SMPL_EVENT(frc, 1s); 45SMPL_EVENT(internal_timer, 1s); 46SMPL_EVENT(internal_parity, 1s); 47SMPL_EVENT(internal_unclassified, 1s); 48 49/* 50 * Propogations for all but "external" and "unknown" simple errors. 51 * If the error is uncorrected we produce a fault immediately, otherwise 52 * we diagnose it to an upset and decalre a fault when the SERD engine 53 * trips. 54 */ 55 56engine serd.cpu.intel.simple@chip/core/strand, N=3, T=72h; 57event fault.cpu.intel.internal@chip/core/strand, 58 engine=serd.cpu.intel.simple@chip/core/strand; 59 60prop fault.cpu.intel.internal@chip/core/strand 61 { payloadprop("error_uncorrected") == 1 ? setserdincrement(4) : 1} (0)-> 62 ereport.cpu.intel.microcode_rom_parity@chip/core/strand, 63 ereport.cpu.intel.internal_timer@chip/core/strand, 64 ereport.cpu.intel.internal_parity@chip/core/strand, 65 ereport.cpu.intel.unclassified@chip/core/strand, 66 ereport.cpu.intel.internal_unclassified@chip/core/strand, 67 ereport.cpu.intel.frc@chip/core/strand; 68 69/* 70 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 71 * for the corrected and uncorrected version of each error type. All are 72 * detected at chip/core/strand. 73 */ 74 75#define CMPND_EVENT(leafclass, t) \ 76 event ereport.cpu.intel.leafclass@chip/core/strand { within(t) }; \ 77 event ereport.cpu.intel.leafclass/**/_uc@chip/core/strand { within(t) } 78 79/* 80 * Ereports for Compound error codes - intel errors 81 */ 82CMPND_EVENT(l0cache, 1s); 83CMPND_EVENT(l1cache, 1s); 84CMPND_EVENT(l2cache, 1s); 85CMPND_EVENT(cache, 1s); 86 87/* 88 * Ereports for Compound error codes - TLB errors 89 */ 90CMPND_EVENT(l0dtlb, 1s); 91CMPND_EVENT(l1dtlb, 1s); 92CMPND_EVENT(l2dtlb, 1s); 93CMPND_EVENT(dtlb, 1s); 94 95CMPND_EVENT(l0itlb, 1s); 96CMPND_EVENT(l1itlb, 1s); 97CMPND_EVENT(l2itlb, 1s); 98CMPND_EVENT(itlb, 1s); 99 100CMPND_EVENT(l0tlb, 1s); 101CMPND_EVENT(l1tlb, 1s); 102CMPND_EVENT(l2tlb, 1s); 103CMPND_EVENT(tlb, 1s); 104 105/* 106 * Ereports for Compound error codes - memory hierarchy errors 107 */ 108CMPND_EVENT(l0dcache, 1s); 109CMPND_EVENT(l1dcache, 1s); 110CMPND_EVENT(l2dcache, 1s); 111CMPND_EVENT(dcache, 1s); 112 113CMPND_EVENT(l0icache, 1s); 114CMPND_EVENT(l1icache, 1s); 115CMPND_EVENT(l2icache, 1s); 116CMPND_EVENT(icache, 1s); 117 118/* 119 * Ereports for Compound error codes - bus and interconnect errors 120 */ 121CMPND_EVENT(bus_interconnect, 1s); 122CMPND_EVENT(bus_interconnect_memory, 1s); 123CMPND_EVENT(bus_interconnect_io, 1s); 124 125/* 126 * Compound error propogations. 127 * 128 * We resist the temptation propogate, for example, a single dcache fault 129 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 130 * Instead we will diagnose a distinct fault for each possible cache level, 131 * whether or not current chips have dcaches at all levels. 132 * 133 * Corrected errors are SERDed and produce a fault when the engine fires; 134 * the same fault is diagnosed immediately for a corresponding uncorrected 135 * error. 136 */ 137 138#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 139 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 140 event fault.cpu.intel.fltleaf@chip/core/strand, \ 141 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 142 \ 143 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 144 ereport.cpu.intel.erptleaf@chip/core/strand; \ 145 \ 146 prop fault.cpu.intel.fltleaf@chip/core/strand \ 147 { setserdincrement(n + 1) } (0)-> \ 148 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 149 150#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 151 engine serd.cpu.intel.fltleaf@chip/core/strand, N=n, T=t; \ 152 event fault.cpu.intel.fltleaf@chip/core/strand, retire=0, response=0,\ 153 engine=serd.cpu.intel.fltleaf@chip/core/strand; \ 154 \ 155 prop fault.cpu.intel.fltleaf@chip/core/strand (0)-> \ 156 ereport.cpu.intel.erptleaf@chip/core/strand; \ 157 \ 158 prop fault.cpu.intel.fltleaf@chip/core/strand \ 159 { setserdincrement(n + 1) } (0)-> \ 160 ereport.cpu.intel.erptleaf/**/_uc@chip/core/strand 161 162CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 163CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 164CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 165CMPND_FLT_PROP_1(cache, cache, 12, 72h); 166 167CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 168CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 169CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 170CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 171 172CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 173CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 174CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 175CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 176 177CMPND_FLT_PROP_1(l0tlb, litlb, 3, 72h); 178CMPND_FLT_PROP_1(l1tlb, litlb, 3, 72h); 179CMPND_FLT_PROP_1(l2tlb, litlb, 3, 72h); 180CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 181 182CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 183CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 184CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 185CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 186 187CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 188CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 189CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 190CMPND_FLT_PROP_1(icache, icache, 12, 72h); 191 192CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 193CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 194CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 195 196event upset.discard@chip/core/strand; 197 198prop upset.discard@chip/core/strand (0)-> 199 ereport.cpu.intel.external@chip/core/strand, 200 ereport.cpu.intel.unknown@chip/core/strand; 201 202/* errors detected in northbridge */ 203 204 205/* 206 * SET_ADDR and SET_OFFSET are used to set a payload value in the fault that 207 * we diagnose for page faults, to record the physical address of the faulting 208 * page. 209 */ 210#define SET_ADDR (!payloadprop_defined("physaddr") || \ 211 setpayloadprop("asru-physaddr", payloadprop("physaddr"))) 212 213#define SET_OFFSET (!payloadprop_defined("offset") || \ 214 setpayloadprop("asru-offset", payloadprop("offset"))) 215 216#define EREPORT_BUS_ERROR \ 217 ereport.cpu.intel.bus_interconnect_memory_uc@chip/core/strand, \ 218 ereport.cpu.intel.bus_interconnect_uc@chip/core/strand, \ 219 ereport.cpu.intel.bus_interconnect_memory@chip/core/strand, \ 220 ereport.cpu.intel.bus_interconnect@chip/core/strand, \ 221 ereport.cpu.intel.external@chip/core/strand 222 223engine stat.ce_pgflt@memory-controller/dram-channel/dimm; 224 225event ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller{within(12s)}; 226event ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller{within(12s)}; 227event fault.memory.intel.page_ue@ 228 motherboard/memory-controller/dram-channel/dimm/rank, 229 message=0, response=0; 230event fault.memory.intel.dimm_ue@ 231 motherboard/memory-controller/dram-channel/dimm/rank; 232 233prop fault.memory.intel.page_ue@ 234 motherboard/memory-controller/dram-channel/dimm/rank[rank_num] 235 { payloadprop_defined("rank") && rank_num == payloadprop("rank") && 236 (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 237 SET_ADDR && SET_OFFSET } (1)-> 238 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 239 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 240 241prop fault.memory.intel.dimm_ue@ 242 motherboard/memory-controller/dram-channel<channel_num>/dimm/rank[rank_num] 243 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 244 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 245 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 246 247event upset.memory.intel.discard@motherboard/memory-controller{within(1s)}; 248 249prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 250 ereport.cpu.intel.nb.mem_ue@motherboard/memory-controller, 251 ereport.cpu.intel.nb.fbd.ma@motherboard/memory-controller; 252 253prop upset.memory.intel.discard@motherboard/memory-controller (0)-> 254 EREPORT_BUS_ERROR; 255 256#define PAGE_CE_COUNT 2 257#define PAGE_CE_TIME 72h 258#define DIMM_CE_COUNT 10 259#define DIMM_CE_TIME 1week 260 261event ereport.cpu.intel.nb.mem_ce@dimm/rank{within(12s)}; 262 263engine serd.memory.intel.page_ce@dimm/rank, N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 264event fault.memory.intel.page_ce@dimm/rank, message=0, response=0, 265 count=stat.ce_pgflt@dimm, engine=serd.memory.intel.page_ce@dimm/rank; 266prop fault.memory.intel.page_ce@dimm/rank 267 { (payloadprop_defined("physaddr") || payloadprop_defined("offset")) && 268 SET_ADDR && SET_OFFSET } (0)-> 269 ereport.cpu.intel.nb.mem_ce@dimm/rank; 270 271engine serd.memory.intel.dimm_ce@dimm/rank, N=DIMM_CE_COUNT, T=DIMM_CE_TIME; 272event fault.memory.intel.dimm_ce@dimm/rank, 273 engine=serd.memory.intel.dimm_ce@dimm/rank; 274event error.memory.intel.dimm_ce@dimm; 275prop fault.memory.intel.dimm_ce@dimm/rank (1)-> 276 ereport.cpu.intel.nb.mem_ce@dimm/rank; 277prop fault.memory.intel.dimm_ce@dimm/rank 278 { !confprop_defined(dimm, "dimm-size") } (1)-> 279 error.memory.intel.dimm_ce@dimm; 280prop error.memory.intel.dimm_ce@dimm 281 { !confprop_defined(dimm, "dimm-size") && 282 count(stat.ce_pgflt@dimm) > 512 } (1)-> 283 ereport.cpu.intel.nb.mem_ce@dimm/rank; 284 285#define DIMM_CE(dimm_size, n, t, fault_rate) \ 286 prop fault.memory.intel.dimm_ce@dimm/rank { \ 287 confprop(dimm, "dimm-size") == dimm_size && \ 288 setserdn(n) & setserdt(t) } (1)-> \ 289 error.memory.intel.dimm_ce@dimm; \ 290 prop error.memory.intel.dimm_ce@dimm { \ 291 confprop(dimm, "dimm-size") == dimm_size && \ 292 count(stat.ce_pgflt@dimm) > fault_rate } (1)-> \ 293 ereport.cpu.intel.nb.mem_ce@dimm/rank; 294 295DIMM_CE("8G", 8, 1week, 2000) 296DIMM_CE("4G", 4, 1week, 1500) 297DIMM_CE("2G", 4, 2week, 1000) 298DIMM_CE("1G", 4, 4week, 500) 299DIMM_CE("512M", 4, 8week, 250) 300DIMM_CE("256M", 4, 16week, 125) 301 302event ereport.cpu.intel.nb.fbd.alert@rank{within(12s)}; 303event fault.memory.intel.fbd.alert@rank, retire=0; 304 305prop fault.memory.intel.fbd.alert@rank (1)-> 306 ereport.cpu.intel.nb.fbd.alert@rank; 307 308prop fault.memory.intel.fbd.alert@rank (0)-> 309 EREPORT_BUS_ERROR; 310 311event ereport.cpu.intel.nb.fbd.crc@rank{within(12s)}; 312event fault.memory.intel.fbd.crc@rank, retire=0; 313 314prop fault.memory.intel.fbd.crc@rank (1)-> 315 ereport.cpu.intel.nb.fbd.crc@rank; 316 317prop fault.memory.intel.fbd.crc@rank (0)-> EREPORT_BUS_ERROR; 318 319event ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller {within(12s)}; 320event fault.memory.intel.fbd.reset_timeout@memory-controller, retire=0; 321 322prop fault.memory.intel.fbd.reset_timeout@memory-controller (1)-> 323 ereport.cpu.intel.nb.fbd.reset_timeout@memory-controller; 324 325prop fault.memory.intel.fbd.reset_timeout@memory-controller (0)-> 326 EREPORT_BUS_ERROR; 327 328event ereport.cpu.intel.nb.fbd.ch@dram-channel {within(12s)}; 329engine serd.cpu.intel.nb.fbd.ch@dram-channel, N=2, T=1month; 330event fault.memory.intel.fbd.ch@dram-channel, retire=0, 331 engine=serd.cpu.intel.nb.fbd.ch@dram-channel; 332 333prop fault.memory.intel.fbd.ch@dram-channel (1)-> 334 ereport.cpu.intel.nb.fbd.ch@dram-channel; 335 336prop fault.memory.intel.fbd.ch@dram-channel (0)-> 337 EREPORT_BUS_ERROR; 338 339event ereport.cpu.intel.nb.fbd.otf@dram-channel {within(12s)}; 340engine serd.cpu.intel.nb.fbd_otf@dram-channel, N=2, T=1week; 341event fault.memory.intel.fbd.otf@dram-channel, retire=0, response=0, 342 engine=serd.cpu.intel.nb.fbd_otf@dram-channel; 343 344prop fault.memory.intel.fbd.otf@dram-channel (1)-> 345 ereport.cpu.intel.nb.fbd.otf@dram-channel; 346 347event ereport.cpu.intel.nb.otf@motherboard {within(12s)}; 348event fault.cpu.intel.nb.otf@motherboard, retire=0, response=0; 349 350prop fault.cpu.intel.nb.otf@motherboard (1)-> 351 ereport.cpu.intel.nb.otf@motherboard; 352 353event ereport.cpu.intel.nb.unknown@memory-controller {within(12s)}; 354event ereport.cpu.intel.nb.unknown@memory-controller/dram-channel {within(12s)}; 355event ereport.cpu.intel.nb.spd@memory-controller/dram-channel {within(12s)}; 356event upset.discard@memory-controller; 357 358prop upset.discard@memory-controller (0)-> 359 ereport.cpu.intel.nb.unknown@memory-controller, 360 ereport.cpu.intel.nb.unknown@memory-controller/dram-channel, 361 ereport.cpu.intel.nb.spd@memory-controller/dram-channel; 362 363event ereport.cpu.intel.nb.mem_ds@memory-controller{within(30s)}; 364event fault.memory.intel.fbd.mem_ds@memory-controller/dram-channel/dimm/rank, 365 retire=0; 366 367prop fault.memory.intel.fbd.mem_ds@ 368 memory-controller/dram-channel/dimm/rank[rank_num] 369 { payloadprop_defined("rank") && rank_num == payloadprop("rank") } (1)-> 370 ereport.cpu.intel.nb.mem_ds@memory-controller; 371 372event ereport.cpu.intel.nb.fsb@chip{within(12s)}; 373event fault.cpu.intel.nb.fsb@chip, retire=0; 374 375prop fault.cpu.intel.nb.fsb@chip (1)-> 376 ereport.cpu.intel.nb.fsb@chip; 377 378prop fault.cpu.intel.nb.fsb@chip (0)-> EREPORT_BUS_ERROR; 379 380event ereport.cpu.intel.nb.ie@motherboard{within(12s)}; 381event fault.cpu.intel.nb.ie@motherboard, retire=0; 382 383prop fault.cpu.intel.nb.ie@motherboard (1)-> 384 ereport.cpu.intel.nb.ie@motherboard; 385 386prop fault.cpu.intel.nb.ie@motherboard (0)-> EREPORT_BUS_ERROR; 387 388event ereport.cpu.intel.nb.dma@motherboard{within(12s)}; 389event fault.cpu.intel.nb.dma@motherboard, retire=0, response=0; 390 391prop fault.cpu.intel.nb.dma@motherboard (1)-> 392 ereport.cpu.intel.nb.dma@motherboard; 393 394prop fault.cpu.intel.nb.dma@motherboard (0)-> EREPORT_BUS_ERROR; 395 396event ereport.cpu.intel.nb.esi@motherboard{within(12s)}; 397event ereport.cpu.intel.nb.pex@hostbridge{within(12s)}; 398event upset.cpu.intel.nb.pex@hostbridge; 399 400prop upset.cpu.intel.nb.pex@hostbridge (1)-> 401 ereport.cpu.intel.nb.esi@motherboard, 402 ereport.cpu.intel.nb.pex@hostbridge; 403 404prop upset.cpu.intel.nb.pex@hostbridge (0)-> EREPORT_BUS_ERROR; 405 406event ereport.cpu.intel.nb.unknown@rank{within(12s)}; 407event upset.discard@rank; 408 409prop upset.discard@rank (1)-> 410 ereport.cpu.intel.nb.unknown@rank; 411 412prop upset.discard@rank (0)-> EREPORT_BUS_ERROR; 413 414/* 415 * CPU integrated memory controller 416 */ 417 418#define CONTAINS_RANK (payloadprop_contains("resource", \ 419 asru(motherboard/chip/memory-controller/dram-channel/dimm/rank)) || \ 420 payloadprop_contains("resource", \ 421 asru(motherboard/chip/memory-controller/dram-channel/dimm))) 422 423#define CPU_MEM_CE_PGFLTS \ 424 (count(stat.ce_pgflt@motherboard/chip/memory-controller/dram-channel/dimm)) 425 426#define SET_RES_OFFSET \ 427 (!payloadprop_defined("resource[0].hc-specific.offset") || \ 428 setpayloadprop("asru-offset", \ 429 payloadprop("resource[0].hc-specific.offset"))) 430 431engine stat.ce_pgflt@motherboard/chip/memory-controller/dram-channel/dimm; 432 433event ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller 434 {within(12s)}; 435 436event fault.memory.intel.page_ue@ 437 motherboard/chip/memory-controller/dram-channel/dimm/rank, 438 message=0, response=0; /* do not message individual pageflts */ 439 440prop fault.memory.intel.page_ue@ 441 motherboard/chip/memory-controller/dram-channel/dimm/rank 442 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 443 payloadprop_defined("resource[0].hc-specific.offset")) && 444 SET_ADDR && SET_RES_OFFSET } (1)-> 445 ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller; 446 447event fault.memory.intel.dimm_ue@ 448 motherboard/chip/memory-controller/dram-channel/dimm/rank; 449 450prop fault.memory.intel.dimm_ue@ 451 motherboard/chip/memory-controller/dram-channel/dimm/rank 452 { CONTAINS_RANK } (1)-> 453 ereport.cpu.intel.quickpath.mem_ue@motherboard/chip/memory-controller; 454 455prop fault.memory.intel.dimm_ue@ 456 motherboard/chip/memory-controller/dram-channel/dimm/rank (0)-> 457 EREPORT_BUS_ERROR; 458 459event ereport.cpu.intel.quickpath.mem_ce@ 460 motherboard/chip/memory-controller{within(12s)}; 461 462engine serd.memory.intel.page_ce@ 463 motherboard/chip/memory-controller/dram-channel/dimm/rank, 464 N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 465 466event fault.memory.intel.page_ce@ 467 motherboard/chip/memory-controller/dram-channel/dimm/rank, 468 message=0, response=0, 469 count=stat.ce_pgflt@motherboard/chip/memory-controller/dram-channel/dimm, 470 engine=serd.memory.intel.page_ce@ 471 motherboard/chip/memory-controller/dram-channel/dimm/rank; 472 473prop fault.memory.intel.page_ce@ 474 motherboard/chip/memory-controller/dram-channel/dimm/rank 475 { CONTAINS_RANK && (payloadprop_defined("physaddr") || 476 payloadprop_defined("resource[0].hc-specific.offset")) && 477 SET_ADDR && SET_RES_OFFSET } (1)-> 478 ereport.cpu.intel.quickpath.mem_ce@motherboard/chip/memory-controller; 479 480engine serd.memory.intel.dimm_ce@ 481 motherboard/chip/memory-controller/dram-channel/dimm, 482 N=PAGE_CE_COUNT, T=PAGE_CE_TIME; 483event fault.memory.intel.dimm_ce@ 484 motherboard/chip/memory-controller/dram-channel/dimm, 485 engine=serd.memory.intel.dimm_ce@ 486 motherboard/chip/memory-controller/dram-channel/dimm; 487event error.memory.intel.dimm_ce@ 488 motherboard/chip/memory-controller/dram-channel/dimm; 489prop fault.memory.intel.dimm_ce@ 490 motherboard/chip/memory-controller/dram-channel/dimm 491 { !confprop_defined(dimm, "dimm-size") } (1)-> 492 error.memory.intel.dimm_ce@ 493 motherboard/chip/memory-controller/dram-channel/dimm; 494prop error.memory.intel.dimm_ce@ 495 motherboard/chip/memory-controller/dram-channel/dimm 496 { !confprop_defined(dimm, "dimm-size") && 497 count(stat.ce_pgflt@dimm) > 512 } (1)-> 498 ereport.cpu.intel.quickpath.mem_ce@motherboard/chip/memory-controller; 499 500#define CPU_MEM_DIMM_CE(dimm_size, n, t, fault_rate) \ 501 prop fault.memory.intel.dimm_ce@ \ 502 motherboard/chip/memory-controller/dram-channel/dimm { \ 503 confprop(dimm, "dimm-size") == dimm_size && \ 504 setserdn(n) & setserdt(t) } (1)-> \ 505 error.memory.intel.dimm_ce@ \ 506 motherboard/chip/memory-controller/dram-channel/dimm; \ 507 prop error.memory.intel.dimm_ce@ \ 508 motherboard/chip/memory-controller/dram-channel/dimm { \ 509 confprop(dimm, "dimm-size") == dimm_size && \ 510 count(stat.ce_pgflt@dimm) > fault_rate } (1)-> \ 511 ereport.cpu.intel.quickpath.mem_ce@ \ 512 motherboard/chip/memory-controller; 513 514CPU_MEM_DIMM_CE("16G", 16, 1week, 2000) 515CPU_MEM_DIMM_CE("8G", 8, 1week, 2000) 516CPU_MEM_DIMM_CE("4G", 4, 1week, 1500) 517CPU_MEM_DIMM_CE("2G", 4, 2week, 1000) 518CPU_MEM_DIMM_CE("1G", 4, 4week, 500) 519CPU_MEM_DIMM_CE("512M", 4, 8week, 250) 520 521event ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller {within(12s)}; 522event ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller/dram-channel 523 {within(12s)}; 524event ereport.cpu.intel.quickpath.mem_unknown@ 525 motherboard/chip/memory-controller/dram-channel/dimm/rank{within(12s)}; 526event upset.discard@motherboard/chip/memory-controller; 527event upset.discard@motherboard/chip/memory-controller/dram-channel/dimm/rank; 528 529prop upset.discard@motherboard/chip/memory-controller (0)-> 530 ereport.cpu.intel.quickpath.mem_unknown@motherboard/chip/memory-controller, 531 ereport.cpu.intel.quickpath.mem_unknown@ 532 motherboard/chip/memory-controller/dram-channel; 533 534prop upset.discard@ 535 motherboard/chip/memory-controller/dram-channel/dimm/rank (1)-> 536 ereport.cpu.intel.quickpath.mem_unknown@ 537 motherboard/chip/memory-controller/dram-channel/dimm/rank; 538 539event ereport.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller {within(1s)}; 540event fault.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller; 541 542prop fault.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller (1)-> 543 ereport.cpu.intel.quickpath.mem_parity@motherboard/chip/memory-controller; 544 545event ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller {within(1s)}; 546event fault.cpu.intel.quickpath.mem_addr_parity@ 547 motherboard/chip/memory-controller/dram-channel/dimm; 548event fault.cpu.intel.quickpath.mem_addr_parity@ 549 motherboard/chip/memory-controller; 550 551prop fault.cpu.intel.quickpath.mem_addr_parity@ 552 motherboard/chip/memory-controller (1)-> 553 ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller; 554 555prop fault.cpu.intel.quickpath.mem_addr_parity@ 556 motherboard/chip/memory-controller/dram-channel/dimm 557 { payloadprop_contains("resource", asru(motherboard/chip/memory-controller/dram-channel/dimm)) } (1)-> 558 ereport.cpu.intel.quickpath.mem_addr_parity@motherboard/chip/memory-controller; 559 560event ereport.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller {within(1s)}; 561event fault.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller; 562 563prop fault.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller (1)-> 564 ereport.cpu.intel.quickpath.mem_bad_addr@motherboard/chip/memory-controller; 565 566event ereport.cpu.intel.quickpath.mem_spare@motherboard/chip/memory-controller {within(1s)}; 567event fault.cpu.intel.quickpath.mem_spare@ 568 motherboard/chip/memory-controller/dram-channel/dimm; 569 570prop fault.cpu.intel.quickpath.mem_spare@ 571 motherboard/chip/memory-controller/dram-channel/dimm (1)-> 572 ereport.cpu.intel.quickpath.mem_spare@motherboard/chip/memory-controller; 573 574event ereport.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller {within(1s)}; 575event fault.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller; 576 577prop fault.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller (1)-> 578 ereport.cpu.intel.quickpath.mem_bad_id@motherboard/chip/memory-controller; 579 580event ereport.cpu.intel.quickpath.mem_redundant@motherboard/chip/memory-controller {within(1s)}; 581engine serd.cpu.intel.quickpath.mem_redundant@motherboard/chip/memory-controller, 582 N=2, T=72h; 583event fault.cpu.intel.quickpath.mem_redundant@ 584 motherboard/chip/memory-controller/dram-channel/dimm, 585 engine=serd.cpu.intel.quickpath.mem_redundant@ 586 motherboard/chip/memory-controller; 587 588prop fault.cpu.intel.quickpath.mem_redundant@ 589 motherboard/chip/memory-controller/dram-channel/dimm (1)-> 590 ereport.cpu.intel.quickpath.mem_redundant@ 591 motherboard/chip/memory-controller; 592 593event ereport.cpu.intel.quickpath.interconnect@motherboard/chip 594 {within(1s)}; 595event upset.cpu.intel.quickpath.interconnect@motherboard/chip; 596/* Diagnose corrected events to upsets */ 597prop upset.cpu.intel.quickpath.interconnect@motherboard/chip 598 { !STATUS_UC } (1)-> 599 ereport.cpu.intel.quickpath.interconnect@motherboard/chip; 600 601 602engine serd.cpu.intel.quickpath.interconnect@motherboard/chip, 603 N=3, T=72h; 604event fault.cpu.intel.quickpath.interconnect@motherboard/chip, 605 engine=serd.cpu.intel.quickpath.interconnect@motherboard/chip; 606 607/* Diagnose uncorrected events to faults */ 608prop fault.cpu.intel.quickpath.interconnect@motherboard/chip 609 { STATUS_UC } (0)-> 610 ereport.cpu.intel.quickpath.interconnect@motherboard/chip; 611