1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * eversholt rules for generic x86 MCA 29 * 30 * Most propogations are generated by preprocessor macros. The event 31 * declarations are deliberately not part of the propogation macros 32 * so that we know we have full coverage - propogations defined without 33 * events, or events not used in propogations, will produce compiler 34 * whinges. 35 */ 36 37#pragma dictionary "GMCA" 38 39/* 40 * Ereports for Simple error codes. 41 */ 42 43#define SMPL_EVENT(leafclass) \ 44 event ereport.cpu.generic-x86.leafclass@chip/core/strand { within(1s) } 45 46SMPL_EVENT(unknown); 47SMPL_EVENT(unclassified); 48SMPL_EVENT(microcode_rom_parity); 49SMPL_EVENT(external); 50SMPL_EVENT(frc); 51SMPL_EVENT(internal_timer); 52SMPL_EVENT(internal_parity); 53SMPL_EVENT(internal_unclassified); 54 55/* 56 * Propogations for all but "external" and "unknown" simple errors. 57 * If the error is uncorrected we produce a fault immediately by incrementing 58 * by N+1, otherwise we declare a fault when the SERD engine trips. 59 */ 60 61#define SMPL_N 3 62 63engine serd.cpu.generic-x86.simple@chip/core/strand, N=SMPL_N, T=72h; 64event fault.cpu.generic-x86.internal@chip/core/strand, 65 engine=serd.cpu.generic-x86.simple@chip/core/strand; 66 67prop fault.cpu.generic-x86.internal@chip/core/strand 68 { payloadprop("error_uncorrected") == 1 ? 69 setserdincrement(SMPL_N + 1) : 1 } (1)-> 70 ereport.cpu.generic-x86.microcode_rom_parity@chip/core/strand, 71 ereport.cpu.generic-x86.internal_timer@chip/core/strand, 72 ereport.cpu.generic-x86.internal_parity@chip/core/strand, 73 ereport.cpu.generic-x86.unclassified@chip/core/strand, 74 ereport.cpu.generic-x86.internal_unclassified@chip/core/strand, 75 ereport.cpu.generic-x86.frc@chip/core/strand; 76 77/* 78 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 79 * for the corrected and uncorrected version of each error type. All are 80 * detected at chip/core[/strand]. 81 */ 82 83#define CMPND_EVENT(leafclass) \ 84 event ereport.cpu.generic-x86.leafclass@chip/core/strand \ 85 { within(1s) }; \ 86 event ereport.cpu.generic-x86.leafclass/**/_uc@chip/core/strand \ 87 { within(1s) } 88 89/* 90 * Ereports for Compound error codes - generic memory hierarchy errors 91 */ 92CMPND_EVENT(l0cache); 93CMPND_EVENT(l1cache); 94CMPND_EVENT(l2cache); 95CMPND_EVENT(cache); 96 97/* 98 * Ereports for Compound error codes - TLB errors 99 */ 100CMPND_EVENT(l0dtlb); 101CMPND_EVENT(l1dtlb); 102CMPND_EVENT(l2dtlb); 103CMPND_EVENT(dtlb); 104 105CMPND_EVENT(l0itlb); 106CMPND_EVENT(l1itlb); 107CMPND_EVENT(l2itlb); 108CMPND_EVENT(itlb); 109 110CMPND_EVENT(l0tlb); 111CMPND_EVENT(l1tlb); 112CMPND_EVENT(l2tlb); 113CMPND_EVENT(tlb); 114 115/* 116 * Ereports for Compound error codes - memory hierarchy errors 117 */ 118CMPND_EVENT(l0dcache); 119CMPND_EVENT(l1dcache); 120CMPND_EVENT(l2dcache); 121CMPND_EVENT(dcache); 122 123CMPND_EVENT(l0icache); 124CMPND_EVENT(l1icache); 125CMPND_EVENT(l2icache); 126CMPND_EVENT(icache); 127 128/* 129 * Ereports for Compound error codes - bus and interconnect errors 130 */ 131CMPND_EVENT(bus_interconnect); 132CMPND_EVENT(bus_interconnect_memory); 133CMPND_EVENT(bus_interconnect_io); 134CMPND_EVENT(mc); 135 136/* 137 * Compound error propogations 138 * 139 * We resist the temptation propogate, for example, a single dcache fault 140 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 141 * Instead we will diagnose a distinct fault for each possible cache level, 142 * whether or not current chips have dcaches at all levels. 143 * 144 * Corrected errors are SERDed and produce a fault when the engine fires; 145 * the same fault is diagnosed immediately for a corresponding uncorrected 146 * error by incrementing the serd engine by n + 1. 147 */ 148 149#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 150 engine serd.cpu.generic-x86.fltleaf@chip/core/strand, N=n, T=t; \ 151 event fault.cpu.generic-x86.fltleaf@chip/core/strand, \ 152 engine=serd.cpu.generic-x86.fltleaf@chip/core/strand; \ 153 \ 154 prop fault.cpu.generic-x86.fltleaf@chip/core/strand (0)-> \ 155 ereport.cpu.generic-x86.erptleaf@chip/core/strand; \ 156 prop fault.cpu.generic-x86.fltleaf@chip/core/strand \ 157 { setserdincrement(n + 1) } (0)-> \ 158 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/core/strand 159 160#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 161 engine serd.cpu.generic-x86.fltleaf@chip/core/strand, N=n, T=t; \ 162 event fault.cpu.generic-x86.fltleaf@chip/core/strand, retire=0, \ 163 response=0, engine=serd.cpu.generic-x86.fltleaf@chip/core/strand;\ 164 \ 165 prop fault.cpu.generic-x86.fltleaf@chip/core/strand (0)-> \ 166 ereport.cpu.generic-x86.erptleaf@chip/core/strand; \ 167 prop fault.cpu.generic-x86.fltleaf@chip/core/strand \ 168 { setserdincrement(n + 1) } (0)-> \ 169 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/core/strand 170 171CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 172CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 173CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 174CMPND_FLT_PROP_1(cache, cache, 12, 72h); 175 176CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 177CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 178CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 179CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 180 181CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 182CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 183CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 184CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 185 186CMPND_FLT_PROP_1(l0tlb, l0tlb, 3, 72h); 187CMPND_FLT_PROP_1(l1tlb, l1tlb, 3, 72h); 188CMPND_FLT_PROP_1(l2tlb, l2tlb, 3, 72h); 189CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 190 191CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 192CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 193CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 194CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 195 196CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 197CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 198CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 199CMPND_FLT_PROP_1(icache, icache, 12, 72h); 200 201CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 202CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 203CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 204 205CMPND_FLT_PROP_2(mc, mc, 10, 72h); 206 207/* 208 * Discards - not enough info to diagnose. 209 */ 210event upset.discard@chip/core/strand; 211 212prop upset.discard@chip/core/strand (0)-> 213 ereport.cpu.generic-x86.external@chip/core/strand, 214 ereport.cpu.generic-x86.unknown@chip/core/strand; 215