1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * eversholt rules for generic x86 MCA 31 * 32 * Most propogations are generated by preprocessor macros. The event 33 * declarations are deliberately not part of the propogation macros 34 * so that we know we have full coverage - propogations defined without 35 * events, or events not used in propogations, will produce compiler 36 * whinges. 37 */ 38 39#pragma dictionary "GMCA" 40 41fru motherboard/chip; 42 43asru motherboard/chip/cpu; 44 45/* 46 * Ereports for Simple error codes. 47 */ 48 49#define SMPL_EVENT(leafclass) \ 50 event ereport.cpu.generic-x86.leafclass@chip/cpu { within(1s) } 51 52SMPL_EVENT(unknown); 53SMPL_EVENT(unclassified); 54SMPL_EVENT(microcode_rom_parity); 55SMPL_EVENT(external); 56SMPL_EVENT(frc); 57SMPL_EVENT(internal_timer); 58SMPL_EVENT(internal_unclassified); 59 60/* 61 * Propogations for all but "external" and "unknown" simple errors. 62 * If the error is uncorrected we produce a fault immediately, otherwise 63 * we diagnose it to an upset and decalre a fault when the SERD engine 64 * trips. 65 */ 66 67/* Simple fault event */ 68event fault.cpu.generic-x86.internal@chip/cpu, 69 ASRU=motherboard/chip/cpu, FRU=motherboard/chip, 70 FITrate=1000; 71 72/* Produced when the correctable engine trips */ 73event ereport.cpu.generic-x86.simple_trip@chip/cpu { within(1s) }; 74 75/* Upset to diagnose corrected events to */ 76event upset.cpu.generic-x86.simple@chip/cpu 77 engine=serd.cpu.generic-x86.simple@chip/cpu; 78 79/* SERD engine for corrected simple errors */ 80engine serd.cpu.generic-x86.simple@chip/cpu, 81 N=3, T=72h, method=persistent, 82 trip=ereport.cpu.generic-x86.simple_trip@chip/cpu; 83 84#define STATUS_UC \ 85 (payloadprop("error_uncorrected") + 0 == 1) 86 87/* Diagnose corrected events to upsets */ 88prop upset.cpu.generic-x86.simple@chip/cpu 89 { !STATUS_UC } (1)-> 90 ereport.cpu.generic-x86.microcode_rom_parity@chip/cpu, 91 ereport.cpu.generic-x86.internal_timer@chip/cpu, 92 ereport.cpu.generic-x86.unclassified@chip/cpu, 93 ereport.cpu.generic-x86.internal_unclassified@chip/cpu, 94 ereport.cpu.generic-x86.frc@chip/cpu; 95 96/* When the correctable engine trips, diagnose a fault */ 97prop fault.cpu.generic-x86.internal@chip/cpu (0)-> 98 ereport.cpu.generic-x86.simple_trip@chip/cpu; 99 100/* Diagnose uncorrected events to faults */ 101prop fault.cpu.generic-x86.internal@chip/cpu 102 { STATUS_UC } (0)-> 103 ereport.cpu.generic-x86.microcode_rom_parity@chip/cpu, 104 ereport.cpu.generic-x86.internal_timer@chip/cpu, 105 ereport.cpu.generic-x86.unclassified@chip/cpu, 106 ereport.cpu.generic-x86.internal_unclassified@chip/cpu, 107 ereport.cpu.generic-x86.frc@chip/cpu; 108 109/* 110 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 111 * for the corrected and uncorrected version of each error type. All are 112 * detected at chip/cpu. 113 */ 114 115#define CMPND_EVENT(leafclass) \ 116 event ereport.cpu.generic-x86.leafclass@chip/cpu { within(1s) }; \ 117 event ereport.cpu.generic-x86.leafclass/**/_uc@chip/cpu { within(1s) } 118 119/* 120 * Ereports for Compound error codes - generic memory hierarchy errors 121 */ 122CMPND_EVENT(l0cache); 123CMPND_EVENT(l1cache); 124CMPND_EVENT(l2cache); 125CMPND_EVENT(cache); 126 127/* 128 * Ereports for Compound error codes - TLB errors 129 */ 130CMPND_EVENT(l0dtlb); 131CMPND_EVENT(l1dtlb); 132CMPND_EVENT(l2dtlb); 133CMPND_EVENT(dtlb); 134 135CMPND_EVENT(l0itlb); 136CMPND_EVENT(l1itlb); 137CMPND_EVENT(l2itlb); 138CMPND_EVENT(itlb); 139 140CMPND_EVENT(l0tlb); 141CMPND_EVENT(l1tlb); 142CMPND_EVENT(l2tlb); 143CMPND_EVENT(tlb); 144 145/* 146 * Ereports for Compound error codes - memory hierarchy errors 147 */ 148CMPND_EVENT(l0dcache); 149CMPND_EVENT(l1dcache); 150CMPND_EVENT(l2dcache); 151CMPND_EVENT(dcache); 152 153CMPND_EVENT(l0icache); 154CMPND_EVENT(l1icache); 155CMPND_EVENT(l2icache); 156CMPND_EVENT(icache); 157 158/* 159 * Ereports for Compound error codes - bus and interconnect errors 160 */ 161CMPND_EVENT(bus_interconnect); 162CMPND_EVENT(bus_interconnect_memory); 163CMPND_EVENT(bus_interconnect_io); 164 165/* 166 * Compound error propogations for all but bus_interconnect*. 167 * 168 * We resist the temptation propogate, for example, a single dcache fault 169 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 170 * Instead we will diagnose a distinct fault for each possible cache level, 171 * whether or not current chips have dcaches at all levels. 172 * 173 * Corrected errors are SERDed and produce a fault when the engine fires; 174 * the same fault is diagnosed immediately for a corresponding uncorrected 175 * error. 176 */ 177 178#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 179 /* Declare the fault that we can diagnose here */ \ 180 event fault.cpu.generic-x86.fltleaf@chip/cpu, \ 181 FITrate=1000, \ 182 FRU=motherboard/chip, \ 183 ASRU=motherboard/chip/cpu; \ 184 \ 185 /* Produced when the correctable engine trips */ \ 186 event ereport.cpu.generic-x86.fltleaf/**/_error@chip/cpu \ 187 { within(1s) }; \ 188 \ 189 /* Upset to diagnose corrected events to */ \ 190 event upset.cpu.generic-x86.fltleaf@chip/cpu, \ 191 engine=serd.cpu.generic-x86.fltleaf@chip/cpu; \ 192 \ 193 /* SERD engine for corrected events */ \ 194 engine serd.cpu.generic-x86.fltleaf@chip/cpu, \ 195 N=n, T=t, method=persistent, \ 196 trip=ereport.cpu.generic-x86.fltleaf/**/_error@chip/cpu; \ 197 \ 198 /* Diagnose corrected events to the corresponding upset */ \ 199 prop upset.cpu.generic-x86.fltleaf@chip/cpu (1)-> \ 200 ereport.cpu.generic-x86.erptleaf@chip/cpu; \ 201 \ 202 /* When the engine trips, diagnose a fault */ \ 203 prop fault.cpu.generic-x86.fltleaf@chip/cpu (0)-> \ 204 ereport.cpu.generic-x86.fltleaf/**/_error@chip/cpu; \ 205 \ 206 /* Produce immediate faults for uncorrected errors */ \ 207 prop fault.cpu.generic-x86.fltleaf@chip/cpu (0)-> \ 208 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/cpu 209 210 211CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 212CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 213CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 214CMPND_FLT_PROP_1(cache, cache, 12, 72h); 215 216CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 217CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 218CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 219CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 220 221CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 222CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 223CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 224CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 225 226CMPND_FLT_PROP_1(l0tlb, l0tlb, 3, 72h); 227CMPND_FLT_PROP_1(l1tlb, l1tlb, 3, 72h); 228CMPND_FLT_PROP_1(l2tlb, l2tlb, 3, 72h); 229CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 230 231CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 232CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 233CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 234CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 235 236CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 237CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 238CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 239CMPND_FLT_PROP_1(icache, icache, 12, 72h); 240 241/* 242 * Compound error propogations for bus_interconnect* - as above but 243 * with no FRU. 244 */ 245 246#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 247 /* Declare the fault that we can diagnose here */ \ 248 event fault.cpu.generic-x86.fltleaf@chip/cpu, \ 249 FITrate=1000, \ 250 ASRU=motherboard/chip/cpu; \ 251 \ 252 /* Produced when the correctable engine trips */ \ 253 event ereport.cpu.generic-x86.fltleaf/**/_error@chip/cpu \ 254 { within(1s) }; \ 255 \ 256 /* Upset to diagnose corrected events to */ \ 257 event upset.cpu.generic-x86.fltleaf@chip/cpu, \ 258 engine=serd.cpu.generic-x86.fltleaf@chip/cpu; \ 259 \ 260 /* SERD engine for corrected events */ \ 261 engine serd.cpu.generic-x86.fltleaf@chip/cpu, \ 262 N=n, T=t, method=persistent, \ 263 trip=ereport.cpu.generic-x86.fltleaf/**/_error@chip/cpu; \ 264 \ 265 /* Diagnose corrected events to the corresponding upset */ \ 266 prop upset.cpu.generic-x86.fltleaf@chip/cpu (1)-> \ 267 ereport.cpu.generic-x86.erptleaf@chip/cpu; \ 268 \ 269 /* When the engine trips, diagnose a fault */ \ 270 prop fault.cpu.generic-x86.fltleaf@chip/cpu (0)-> \ 271 ereport.cpu.generic-x86.fltleaf/**/_error@chip/cpu; \ 272 \ 273 /* Produce immediate faults for uncorrected errors */ \ 274 prop fault.cpu.generic-x86.fltleaf@chip/cpu (0)-> \ 275 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/cpu 276 277 278CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 279CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 280CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 281 282/* 283 * Discards - not enough info to diagnose. 284 */ 285event upset.discard@chip/cpu; 286 287prop upset.discard@chip/cpu (0)-> 288 ereport.cpu.generic-x86.external@chip/cpu, 289 ereport.cpu.generic-x86.unknown@chip/cpu; 290 291