1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * eversholt rules for generic x86 MCA 29 * 30 * Most propogations are generated by preprocessor macros. The event 31 * declarations are deliberately not part of the propogation macros 32 * so that we know we have full coverage - propogations defined without 33 * events, or events not used in propogations, will produce compiler 34 * whinges. 35 */ 36 37#pragma dictionary "GMCA" 38 39/* 40 * Ereports for Simple error codes. 41 */ 42 43#define SMPL_EVENT(leafclass) \ 44 event ereport.cpu.generic-x86.leafclass@chip/cpu { within(1s) }; \ 45 event ereport.cpu.generic-x86.leafclass@chip/core/strand { within(1s) } 46 47SMPL_EVENT(unknown); 48SMPL_EVENT(unclassified); 49SMPL_EVENT(microcode_rom_parity); 50SMPL_EVENT(external); 51SMPL_EVENT(frc); 52SMPL_EVENT(internal_timer); 53SMPL_EVENT(internal_parity); 54SMPL_EVENT(internal_unclassified); 55 56/* 57 * Propogations for all but "external" and "unknown" simple errors. 58 * If the error is uncorrected we produce a fault immediately by incrementing 59 * by N+1, otherwise we declare a fault when the SERD engine trips. 60 */ 61 62#define SMPL_N 3 63 64engine serd.cpu.generic-x86.simple@chip/cpu, N=SMPL_N, T=72h; 65event fault.cpu.generic-x86.internal@chip/cpu, 66 engine=serd.cpu.generic-x86.simple@chip/cpu; 67engine serd.cpu.generic-x86.simple@chip/core/strand, N=SMPL_N, T=72h; 68event fault.cpu.generic-x86.internal@chip/core/strand, 69 engine=serd.cpu.generic-x86.simple@chip/core/strand; 70 71prop fault.cpu.generic-x86.internal@chip/cpu 72 { payloadprop("error_uncorrected") == 1 ? 73 setserdincrement(SMPL_N + 1) : 1 } (1)-> 74 ereport.cpu.generic-x86.microcode_rom_parity@chip/cpu, 75 ereport.cpu.generic-x86.internal_timer@chip/cpu, 76 ereport.cpu.generic-x86.internal_parity@chip/cpu, 77 ereport.cpu.generic-x86.unclassified@chip/cpu, 78 ereport.cpu.generic-x86.internal_unclassified@chip/cpu, 79 ereport.cpu.generic-x86.frc@chip/cpu; 80prop fault.cpu.generic-x86.internal@chip/core/strand 81 { payloadprop("error_uncorrected") == 1 ? 82 setserdincrement(SMPL_N + 1) : 1 } (1)-> 83 ereport.cpu.generic-x86.microcode_rom_parity@chip/core/strand, 84 ereport.cpu.generic-x86.internal_timer@chip/core/strand, 85 ereport.cpu.generic-x86.internal_parity@chip/core/strand, 86 ereport.cpu.generic-x86.unclassified@chip/core/strand, 87 ereport.cpu.generic-x86.internal_unclassified@chip/core/strand, 88 ereport.cpu.generic-x86.frc@chip/core/strand; 89 90/* 91 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 92 * for the corrected and uncorrected version of each error type. All are 93 * detected at chip/cpu and chip/core/strand. 94 */ 95 96#define CMPND_EVENT(leafclass) \ 97 event ereport.cpu.generic-x86.leafclass@chip/cpu { within(1s) }; \ 98 event ereport.cpu.generic-x86.leafclass/**/_uc@chip/cpu { within(1s) };\ 99 event ereport.cpu.generic-x86.leafclass@chip/core/strand \ 100 { within(1s) }; \ 101 event ereport.cpu.generic-x86.leafclass/**/_uc@chip/core/strand \ 102 { within(1s) } 103 104/* 105 * Ereports for Compound error codes - generic memory hierarchy errors 106 */ 107CMPND_EVENT(l0cache); 108CMPND_EVENT(l1cache); 109CMPND_EVENT(l2cache); 110CMPND_EVENT(cache); 111 112/* 113 * Ereports for Compound error codes - TLB errors 114 */ 115CMPND_EVENT(l0dtlb); 116CMPND_EVENT(l1dtlb); 117CMPND_EVENT(l2dtlb); 118CMPND_EVENT(dtlb); 119 120CMPND_EVENT(l0itlb); 121CMPND_EVENT(l1itlb); 122CMPND_EVENT(l2itlb); 123CMPND_EVENT(itlb); 124 125CMPND_EVENT(l0tlb); 126CMPND_EVENT(l1tlb); 127CMPND_EVENT(l2tlb); 128CMPND_EVENT(tlb); 129 130/* 131 * Ereports for Compound error codes - memory hierarchy errors 132 */ 133CMPND_EVENT(l0dcache); 134CMPND_EVENT(l1dcache); 135CMPND_EVENT(l2dcache); 136CMPND_EVENT(dcache); 137 138CMPND_EVENT(l0icache); 139CMPND_EVENT(l1icache); 140CMPND_EVENT(l2icache); 141CMPND_EVENT(icache); 142 143/* 144 * Ereports for Compound error codes - bus and interconnect errors 145 */ 146CMPND_EVENT(bus_interconnect); 147CMPND_EVENT(bus_interconnect_memory); 148CMPND_EVENT(bus_interconnect_io); 149CMPND_EVENT(mc); 150 151/* 152 * Compound error propogations 153 * 154 * We resist the temptation propogate, for example, a single dcache fault 155 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 156 * Instead we will diagnose a distinct fault for each possible cache level, 157 * whether or not current chips have dcaches at all levels. 158 * 159 * Corrected errors are SERDed and produce a fault when the engine fires; 160 * the same fault is diagnosed immediately for a corresponding uncorrected 161 * error by incrementing the serd engine by n + 1. 162 */ 163 164#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 165 engine serd.cpu.generic-x86.fltleaf@chip/cpu, N=n, T=t; \ 166 event fault.cpu.generic-x86.fltleaf@chip/cpu, \ 167 engine=serd.cpu.generic-x86.fltleaf@chip/cpu; \ 168 engine serd.cpu.generic-x86.fltleaf@chip/core/strand, N=n, T=t; \ 169 event fault.cpu.generic-x86.fltleaf@chip/core/strand, \ 170 engine=serd.cpu.generic-x86.fltleaf@chip/core/strand; \ 171 \ 172 prop fault.cpu.generic-x86.fltleaf@chip/cpu (0)-> \ 173 ereport.cpu.generic-x86.erptleaf@chip/cpu; \ 174 prop fault.cpu.generic-x86.fltleaf@chip/cpu \ 175 { setserdincrement(n + 1) } (0)-> \ 176 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/cpu; \ 177 prop fault.cpu.generic-x86.fltleaf@chip/core/strand (0)-> \ 178 ereport.cpu.generic-x86.erptleaf@chip/core/strand; \ 179 prop fault.cpu.generic-x86.fltleaf@chip/core/strand \ 180 { setserdincrement(n + 1) } (0)-> \ 181 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/core/strand 182 183#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 184 engine serd.cpu.generic-x86.fltleaf@chip/cpu, N=n, T=t; \ 185 event fault.cpu.generic-x86.fltleaf@chip/cpu, retire=0, \ 186 response=0, engine=serd.cpu.generic-x86.fltleaf@chip/cpu; \ 187 engine serd.cpu.generic-x86.fltleaf@chip/core/strand, N=n, T=t; \ 188 event fault.cpu.generic-x86.fltleaf@chip/core/strand, retire=0, \ 189 response=0, engine=serd.cpu.generic-x86.fltleaf@chip/core/strand;\ 190 \ 191 prop fault.cpu.generic-x86.fltleaf@chip/cpu (0)-> \ 192 ereport.cpu.generic-x86.erptleaf@chip/cpu; \ 193 prop fault.cpu.generic-x86.fltleaf@chip/cpu \ 194 { setserdincrement(n + 1) } (0)-> \ 195 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/cpu; \ 196 prop fault.cpu.generic-x86.fltleaf@chip/core/strand (0)-> \ 197 ereport.cpu.generic-x86.erptleaf@chip/core/strand; \ 198 prop fault.cpu.generic-x86.fltleaf@chip/core/strand \ 199 { setserdincrement(n + 1) } (0)-> \ 200 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/core/strand 201 202CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 203CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 204CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 205CMPND_FLT_PROP_1(cache, cache, 12, 72h); 206 207CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 208CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 209CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 210CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 211 212CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 213CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 214CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 215CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 216 217CMPND_FLT_PROP_1(l0tlb, l0tlb, 3, 72h); 218CMPND_FLT_PROP_1(l1tlb, l1tlb, 3, 72h); 219CMPND_FLT_PROP_1(l2tlb, l2tlb, 3, 72h); 220CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 221 222CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 223CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 224CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 225CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 226 227CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 228CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 229CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 230CMPND_FLT_PROP_1(icache, icache, 12, 72h); 231 232CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 233CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 234CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 235 236CMPND_FLT_PROP_2(mc, mc, 10, 72h); 237 238/* 239 * Discards - not enough info to diagnose. 240 */ 241event upset.discard@chip/cpu; 242 243prop upset.discard@chip/cpu (0)-> 244 ereport.cpu.generic-x86.external@chip/cpu, 245 ereport.cpu.generic-x86.unknown@chip/cpu; 246 247event upset.discard@chip/core/strand; 248 249prop upset.discard@chip/core/strand (0)-> 250 ereport.cpu.generic-x86.external@chip/core/strand, 251 ereport.cpu.generic-x86.unknown@chip/core/strand; 252