1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/* 30 * eversholt rules for generic x86 MCA 31 * 32 * Most propogations are generated by preprocessor macros. The event 33 * declarations are deliberately not part of the propogation macros 34 * so that we know we have full coverage - propogations defined without 35 * events, or events not used in propogations, will produce compiler 36 * whinges. 37 */ 38 39#pragma dictionary "GMCA" 40 41/* 42 * Ereports for Simple error codes. 43 */ 44 45#define SMPL_EVENT(leafclass) \ 46 event ereport.cpu.generic-x86.leafclass@chip/cpu { within(1s) } 47 48SMPL_EVENT(unknown); 49SMPL_EVENT(unclassified); 50SMPL_EVENT(microcode_rom_parity); 51SMPL_EVENT(external); 52SMPL_EVENT(frc); 53SMPL_EVENT(internal_timer); 54SMPL_EVENT(internal_unclassified); 55 56/* 57 * Propogations for all but "external" and "unknown" simple errors. 58 * If the error is uncorrected we produce a fault immediately by incrementing 59 * by N+1, otherwise we declare a fault when the SERD engine trips. 60 */ 61 62#define SMPL_N 3 63 64engine serd.cpu.generic-x86.simple@chip/cpu, N=SMPL_N, T=72h; 65event fault.cpu.generic-x86.internal@chip/cpu, 66 engine=serd.cpu.generic-x86.simple@chip/cpu; 67 68prop fault.cpu.generic-x86.internal@chip/cpu 69 { payloadprop("error_uncorrected") == 1 ? 70 setserdincrement(SMPL_N + 1) : 1 } (1)-> 71 ereport.cpu.generic-x86.microcode_rom_parity@chip/cpu, 72 ereport.cpu.generic-x86.internal_timer@chip/cpu, 73 ereport.cpu.generic-x86.unclassified@chip/cpu, 74 ereport.cpu.generic-x86.internal_unclassified@chip/cpu, 75 ereport.cpu.generic-x86.frc@chip/cpu; 76 77/* 78 * Ereports for Compound error codes. These are in pairs "foo" and "foo_uc" 79 * for the corrected and uncorrected version of each error type. All are 80 * detected at chip/cpu. 81 */ 82 83#define CMPND_EVENT(leafclass) \ 84 event ereport.cpu.generic-x86.leafclass@chip/cpu { within(1s) }; \ 85 event ereport.cpu.generic-x86.leafclass/**/_uc@chip/cpu { within(1s) } 86 87/* 88 * Ereports for Compound error codes - generic memory hierarchy errors 89 */ 90CMPND_EVENT(l0cache); 91CMPND_EVENT(l1cache); 92CMPND_EVENT(l2cache); 93CMPND_EVENT(cache); 94 95/* 96 * Ereports for Compound error codes - TLB errors 97 */ 98CMPND_EVENT(l0dtlb); 99CMPND_EVENT(l1dtlb); 100CMPND_EVENT(l2dtlb); 101CMPND_EVENT(dtlb); 102 103CMPND_EVENT(l0itlb); 104CMPND_EVENT(l1itlb); 105CMPND_EVENT(l2itlb); 106CMPND_EVENT(itlb); 107 108CMPND_EVENT(l0tlb); 109CMPND_EVENT(l1tlb); 110CMPND_EVENT(l2tlb); 111CMPND_EVENT(tlb); 112 113/* 114 * Ereports for Compound error codes - memory hierarchy errors 115 */ 116CMPND_EVENT(l0dcache); 117CMPND_EVENT(l1dcache); 118CMPND_EVENT(l2dcache); 119CMPND_EVENT(dcache); 120 121CMPND_EVENT(l0icache); 122CMPND_EVENT(l1icache); 123CMPND_EVENT(l2icache); 124CMPND_EVENT(icache); 125 126/* 127 * Ereports for Compound error codes - bus and interconnect errors 128 */ 129CMPND_EVENT(bus_interconnect); 130CMPND_EVENT(bus_interconnect_memory); 131CMPND_EVENT(bus_interconnect_io); 132 133/* 134 * Compound error propogations 135 * 136 * We resist the temptation propogate, for example, a single dcache fault 137 * to all ereports mentioning dcache (l0dcache, l1dcache, l2dcache, dcache). 138 * Instead we will diagnose a distinct fault for each possible cache level, 139 * whether or not current chips have dcaches at all levels. 140 * 141 * Corrected errors are SERDed and produce a fault when the engine fires; 142 * the same fault is diagnosed immediately for a corresponding uncorrected 143 * error by incrementing the serd engine by n + 1. 144 */ 145 146#define CMPND_FLT_PROP_1(erptleaf, fltleaf, n, t) \ 147 engine serd.cpu.generic-x86.fltleaf@chip/cpu, N=n, T=t; \ 148 event fault.cpu.generic-x86.fltleaf@chip/cpu, \ 149 engine=serd.cpu.generic-x86.fltleaf@chip/cpu; \ 150 \ 151 prop fault.cpu.generic-x86.fltleaf@chip/cpu (0)-> \ 152 ereport.cpu.generic-x86.erptleaf@chip/cpu; \ 153 prop fault.cpu.generic-x86.fltleaf@chip/cpu \ 154 { setserdincrement(n + 1) } (0)-> \ 155 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/cpu 156 157#define CMPND_FLT_PROP_2(erptleaf, fltleaf, n, t) \ 158 engine serd.cpu.generic-x86.fltleaf@chip/cpu, N=n, T=t; \ 159 event fault.cpu.generic-x86.fltleaf@chip/cpu, retire=0, \ 160 response=0, engine=serd.cpu.generic-x86.fltleaf@chip/cpu; \ 161 \ 162 prop fault.cpu.generic-x86.fltleaf@chip/cpu (0)-> \ 163 ereport.cpu.generic-x86.erptleaf@chip/cpu; \ 164 prop fault.cpu.generic-x86.fltleaf@chip/cpu \ 165 { setserdincrement(n + 1) } (0)-> \ 166 ereport.cpu.generic-x86.erptleaf/**/_uc@chip/cpu 167 168CMPND_FLT_PROP_1(l0cache, l0cache, 3, 72h); 169CMPND_FLT_PROP_1(l1cache, l1cache, 3, 72h); 170CMPND_FLT_PROP_1(l2cache, l2cache, 3, 72h); 171CMPND_FLT_PROP_1(cache, cache, 12, 72h); 172 173CMPND_FLT_PROP_1(l0dtlb, l0dtlb, 3, 72h); 174CMPND_FLT_PROP_1(l1dtlb, l1dtlb, 3, 72h); 175CMPND_FLT_PROP_1(l2dtlb, l2dtlb, 3, 72h); 176CMPND_FLT_PROP_1(dtlb, dtlb, 12, 72h); 177 178CMPND_FLT_PROP_1(l0itlb, l0itlb, 3, 72h); 179CMPND_FLT_PROP_1(l1itlb, l1itlb, 3, 72h); 180CMPND_FLT_PROP_1(l2itlb, l2itlb, 3, 72h); 181CMPND_FLT_PROP_1(itlb, itlb, 12, 72h); 182 183CMPND_FLT_PROP_1(l0tlb, l0tlb, 3, 72h); 184CMPND_FLT_PROP_1(l1tlb, l1tlb, 3, 72h); 185CMPND_FLT_PROP_1(l2tlb, l2tlb, 3, 72h); 186CMPND_FLT_PROP_1(tlb, tlb, 12, 72h); 187 188CMPND_FLT_PROP_1(l0dcache, l0dcache, 3, 72h); 189CMPND_FLT_PROP_1(l1dcache, l1dcache, 3, 72h); 190CMPND_FLT_PROP_1(l2dcache, l2dcache, 3, 72h); 191CMPND_FLT_PROP_1(dcache, dcache, 12, 72h); 192 193CMPND_FLT_PROP_1(l0icache, l0icache, 3, 72h); 194CMPND_FLT_PROP_1(l1icache, l1icache, 3, 72h); 195CMPND_FLT_PROP_1(l2icache, l2icache, 3, 72h); 196CMPND_FLT_PROP_1(icache, icache, 12, 72h); 197 198CMPND_FLT_PROP_2(bus_interconnect, bus_interconnect, 10, 72h); 199CMPND_FLT_PROP_2(bus_interconnect_memory, bus_interconnect_memory, 10, 72h); 200CMPND_FLT_PROP_2(bus_interconnect_io, bus_interconnect_io, 10, 72h); 201 202/* 203 * Discards - not enough info to diagnose. 204 */ 205event upset.discard@chip/cpu; 206 207prop upset.discard@chip/cpu (0)-> 208 ereport.cpu.generic-x86.external@chip/cpu, 209 ereport.cpu.generic-x86.unknown@chip/cpu; 210 211