xref: /illumos-gate/usr/src/cmd/devfsadm/cfg_link.h (revision 7b34a9a5df26271af0da06974fc361c468cd48d3)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 /*
26  * Copyright 2019, Joyent, Inc.
27  */
28 
29 /* private devlink info interfaces */
30 
31 #ifndef	_CFG_LINK_H
32 #define	_CFG_LINK_H
33 
34 #include <devfsadm.h>
35 
36 #ifdef	__cplusplus
37 extern "C" {
38 #endif
39 
40 #define	SCSI_CFG_LINK_RE	"^cfg/c[0-9]+$"
41 #define	SBD_CFG_LINK_RE		"^cfg/((((N[0-9]+[.])?(SB|IB))?[0-9]+)|[abcd])$"
42 #define	USB_CFG_LINK_RE		"^cfg/((usb[0-9]+)/([0-9]+)([.]([0-9])+)*)$"
43 #define	PCI_CFG_LINK_RE		"^cfg/[:alnum:]$"
44 #define	IB_CFG_LINK_RE		"^cfg/(hca[0-9A-F]+)$"
45 #define	SATA_CFG_LINK_RE	"^cfg/((sata[0-9]+)/([0-9]+)([.]([0-9])+)*)$"
46 #define	SDCARD_CFG_LINK_RE	"^cfg/sdcard[0-9]+/[0-9]+$"
47 #define	PCI_CFG_PATH_LINK_RE	\
48 	"^cfg/(.*(pci[0-9]|pcie[0-9]|Slot[0-9]|\\<pci\\>|\\<pcie\\>).*)$"
49 #define	CCID_CFG_LINK_RE	"^cfg/ccid[0-9]+/slot[0-9]+$"
50 
51 #define	CFG_DIRNAME		"cfg"
52 
53 #define	PROPVAL_PCIEX		"pciex"
54 #define	DEVTYPE_PCIE		"pcie"
55 #define	IOB_PRE			"iob"
56 #define	AP_PATH_SEP		":"
57 #define	AP_PATH_IOB_SEP		"."
58 #define	IEEE_SUN_ID		0x080020
59 #define	APNODE_DEFNAME		0x1
60 #define	PCIDEV_NIL		((minor_t)-1)
61 
62 /* converts size in bits to a mask covering those bit positions */
63 #define	SIZE2MASK(s)		((1 << (s)) - 1)
64 #define	SIZE2MASK64(s)		((1LL << (s)) - 1LL)
65 
66 /*
67  * macros for the ieee1275 "reg" property
68  * naming format and semantics:
69  *
70  * REG_<cell>_SIZE_<field> = bit size of <field> in <cell>
71  * REG_<cell>_OFF_<field> = starting bit position of <field> in <cell>
72  *
73  * REG_<cell>_<field>(r) = returns the value of <field> in <cell> using:
74  *	(((r) >> REG_<cell>_OFF_<field>) & SIZE2MASK(REG_<cell>_SIZE_<field>))
75  */
76 #define	REG_PHYSHI_SIZE_PCIDEV	5
77 #define	REG_PHYSHI_OFF_PCIDEV	11
78 #define	REG_PHYSHI_PCIDEV(r)	\
79 	(((r) >> REG_PHYSHI_OFF_PCIDEV) & SIZE2MASK(REG_PHYSHI_SIZE_PCIDEV))
80 
81 /* rp = ptr to 5-tuple int array */
82 #define	REG_PHYSHI_INDEX	0
83 #define	REG_PHYSHI(rp)		((rp)[REG_PHYSHI_INDEX])
84 
85 #define	REG_PCIDEV(rp)		(REG_PHYSHI_PCIDEV(REG_PHYSHI(rp)))
86 
87 
88 #define	DEV "/dev"
89 #define	DEV_LEN 4
90 #define	DEVICES "/devices"
91 #define	DEVICES_LEN 8
92 
93 #ifdef	__cplusplus
94 }
95 #endif
96 
97 #endif /* _CFG_LINK_H */
98