1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2014 Leon Dang <ldang@nahannisys.com> 5 * Copyright 2018 Joyent, Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 /* 30 XHCI options: 31 -s <n>,xhci,{devices} 32 33 devices: 34 tablet USB tablet mouse 35 */ 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/uio.h> 41 #include <sys/types.h> 42 #include <sys/queue.h> 43 44 #include <stdio.h> 45 #include <stdlib.h> 46 #include <stdint.h> 47 #include <string.h> 48 #include <errno.h> 49 #include <pthread.h> 50 #include <unistd.h> 51 52 #include <dev/usb/usbdi.h> 53 #include <dev/usb/usb.h> 54 #include <dev/usb/usb_freebsd.h> 55 #include <xhcireg.h> 56 57 #include "bhyverun.h" 58 #include "config.h" 59 #include "debug.h" 60 #include "pci_emul.h" 61 #include "pci_xhci.h" 62 #include "usb_emul.h" 63 64 65 static int xhci_debug = 0; 66 #define DPRINTF(params) if (xhci_debug) PRINTLN params 67 #define WPRINTF(params) PRINTLN params 68 69 70 #define XHCI_NAME "xhci" 71 #define XHCI_MAX_DEVS 8 /* 4 USB3 + 4 USB2 devs */ 72 73 #define XHCI_MAX_SLOTS 64 /* min allowed by Windows drivers */ 74 75 /* 76 * XHCI data structures can be up to 64k, but limit paddr_guest2host mapping 77 * to 4k to avoid going over the guest physical memory barrier. 78 */ 79 #define XHCI_PADDR_SZ 4096 /* paddr_guest2host max size */ 80 81 #define XHCI_ERST_MAX 0 /* max 2^entries event ring seg tbl */ 82 83 #define XHCI_CAPLEN (4*8) /* offset of op register space */ 84 #define XHCI_HCCPRAMS2 0x1C /* offset of HCCPARAMS2 register */ 85 #define XHCI_PORTREGS_START 0x400 86 #define XHCI_DOORBELL_MAX 256 87 88 #define XHCI_STREAMS_MAX 1 /* 4-15 in XHCI spec */ 89 90 /* caplength and hci-version registers */ 91 #define XHCI_SET_CAPLEN(x) ((x) & 0xFF) 92 #define XHCI_SET_HCIVERSION(x) (((x) & 0xFFFF) << 16) 93 #define XHCI_GET_HCIVERSION(x) (((x) >> 16) & 0xFFFF) 94 95 /* hcsparams1 register */ 96 #define XHCI_SET_HCSP1_MAXSLOTS(x) ((x) & 0xFF) 97 #define XHCI_SET_HCSP1_MAXINTR(x) (((x) & 0x7FF) << 8) 98 #define XHCI_SET_HCSP1_MAXPORTS(x) (((x) & 0xFF) << 24) 99 100 /* hcsparams2 register */ 101 #define XHCI_SET_HCSP2_IST(x) ((x) & 0x0F) 102 #define XHCI_SET_HCSP2_ERSTMAX(x) (((x) & 0x0F) << 4) 103 #define XHCI_SET_HCSP2_MAXSCRATCH_HI(x) (((x) & 0x1F) << 21) 104 #define XHCI_SET_HCSP2_MAXSCRATCH_LO(x) (((x) & 0x1F) << 27) 105 106 /* hcsparams3 register */ 107 #define XHCI_SET_HCSP3_U1EXITLATENCY(x) ((x) & 0xFF) 108 #define XHCI_SET_HCSP3_U2EXITLATENCY(x) (((x) & 0xFFFF) << 16) 109 110 /* hccparams1 register */ 111 #define XHCI_SET_HCCP1_AC64(x) ((x) & 0x01) 112 #define XHCI_SET_HCCP1_BNC(x) (((x) & 0x01) << 1) 113 #define XHCI_SET_HCCP1_CSZ(x) (((x) & 0x01) << 2) 114 #define XHCI_SET_HCCP1_PPC(x) (((x) & 0x01) << 3) 115 #define XHCI_SET_HCCP1_PIND(x) (((x) & 0x01) << 4) 116 #define XHCI_SET_HCCP1_LHRC(x) (((x) & 0x01) << 5) 117 #define XHCI_SET_HCCP1_LTC(x) (((x) & 0x01) << 6) 118 #define XHCI_SET_HCCP1_NSS(x) (((x) & 0x01) << 7) 119 #define XHCI_SET_HCCP1_PAE(x) (((x) & 0x01) << 8) 120 #define XHCI_SET_HCCP1_SPC(x) (((x) & 0x01) << 9) 121 #define XHCI_SET_HCCP1_SEC(x) (((x) & 0x01) << 10) 122 #define XHCI_SET_HCCP1_CFC(x) (((x) & 0x01) << 11) 123 #define XHCI_SET_HCCP1_MAXPSA(x) (((x) & 0x0F) << 12) 124 #define XHCI_SET_HCCP1_XECP(x) (((x) & 0xFFFF) << 16) 125 126 /* hccparams2 register */ 127 #define XHCI_SET_HCCP2_U3C(x) ((x) & 0x01) 128 #define XHCI_SET_HCCP2_CMC(x) (((x) & 0x01) << 1) 129 #define XHCI_SET_HCCP2_FSC(x) (((x) & 0x01) << 2) 130 #define XHCI_SET_HCCP2_CTC(x) (((x) & 0x01) << 3) 131 #define XHCI_SET_HCCP2_LEC(x) (((x) & 0x01) << 4) 132 #define XHCI_SET_HCCP2_CIC(x) (((x) & 0x01) << 5) 133 134 /* other registers */ 135 #define XHCI_SET_DOORBELL(x) ((x) & ~0x03) 136 #define XHCI_SET_RTSOFFSET(x) ((x) & ~0x0F) 137 138 /* register masks */ 139 #define XHCI_PS_PLS_MASK (0xF << 5) /* port link state */ 140 #define XHCI_PS_SPEED_MASK (0xF << 10) /* port speed */ 141 #define XHCI_PS_PIC_MASK (0x3 << 14) /* port indicator */ 142 143 /* port register set */ 144 #define XHCI_PORTREGS_BASE 0x400 /* base offset */ 145 #define XHCI_PORTREGS_PORT0 0x3F0 146 #define XHCI_PORTREGS_SETSZ 0x10 /* size of a set */ 147 148 #define MASK_64_HI(x) ((x) & ~0xFFFFFFFFULL) 149 #define MASK_64_LO(x) ((x) & 0xFFFFFFFFULL) 150 151 #define FIELD_REPLACE(a,b,m,s) (((a) & ~((m) << (s))) | \ 152 (((b) & (m)) << (s))) 153 #define FIELD_COPY(a,b,m,s) (((a) & ~((m) << (s))) | \ 154 (((b) & ((m) << (s))))) 155 156 struct pci_xhci_trb_ring { 157 uint64_t ringaddr; /* current dequeue guest address */ 158 uint32_t ccs; /* consumer cycle state */ 159 }; 160 161 /* device endpoint transfer/stream rings */ 162 struct pci_xhci_dev_ep { 163 union { 164 struct xhci_trb *_epu_tr; 165 struct xhci_stream_ctx *_epu_sctx; 166 } _ep_trbsctx; 167 #define ep_tr _ep_trbsctx._epu_tr 168 #define ep_sctx _ep_trbsctx._epu_sctx 169 170 /* 171 * Caches the value of MaxPStreams from the endpoint context 172 * when an endpoint is initialized and is used to validate the 173 * use of ep_ringaddr vs ep_sctx_trbs[] as well as the length 174 * of ep_sctx_trbs[]. 175 */ 176 uint32_t ep_MaxPStreams; 177 union { 178 struct pci_xhci_trb_ring _epu_trb; 179 struct pci_xhci_trb_ring *_epu_sctx_trbs; 180 } _ep_trb_rings; 181 #define ep_ringaddr _ep_trb_rings._epu_trb.ringaddr 182 #define ep_ccs _ep_trb_rings._epu_trb.ccs 183 #define ep_sctx_trbs _ep_trb_rings._epu_sctx_trbs 184 185 struct usb_data_xfer *ep_xfer; /* transfer chain */ 186 }; 187 188 /* device context base address array: maps slot->device context */ 189 struct xhci_dcbaa { 190 uint64_t dcba[USB_MAX_DEVICES+1]; /* xhci_dev_ctx ptrs */ 191 }; 192 193 /* port status registers */ 194 struct pci_xhci_portregs { 195 uint32_t portsc; /* port status and control */ 196 uint32_t portpmsc; /* port pwr mgmt status & control */ 197 uint32_t portli; /* port link info */ 198 uint32_t porthlpmc; /* port hardware LPM control */ 199 } __packed; 200 #define XHCI_PS_SPEED_SET(x) (((x) & 0xF) << 10) 201 202 /* xHC operational registers */ 203 struct pci_xhci_opregs { 204 uint32_t usbcmd; /* usb command */ 205 uint32_t usbsts; /* usb status */ 206 uint32_t pgsz; /* page size */ 207 uint32_t dnctrl; /* device notification control */ 208 uint64_t crcr; /* command ring control */ 209 uint64_t dcbaap; /* device ctx base addr array ptr */ 210 uint32_t config; /* configure */ 211 212 /* guest mapped addresses: */ 213 struct xhci_trb *cr_p; /* crcr dequeue */ 214 struct xhci_dcbaa *dcbaa_p; /* dev ctx array ptr */ 215 }; 216 217 /* xHC runtime registers */ 218 struct pci_xhci_rtsregs { 219 uint32_t mfindex; /* microframe index */ 220 struct { /* interrupter register set */ 221 uint32_t iman; /* interrupter management */ 222 uint32_t imod; /* interrupter moderation */ 223 uint32_t erstsz; /* event ring segment table size */ 224 uint32_t rsvd; 225 uint64_t erstba; /* event ring seg-tbl base addr */ 226 uint64_t erdp; /* event ring dequeue ptr */ 227 } intrreg __packed; 228 229 /* guest mapped addresses */ 230 struct xhci_event_ring_seg *erstba_p; 231 struct xhci_trb *erst_p; /* event ring segment tbl */ 232 int er_deq_seg; /* event ring dequeue segment */ 233 int er_enq_idx; /* event ring enqueue index - xHCI */ 234 int er_enq_seg; /* event ring enqueue segment */ 235 uint32_t er_events_cnt; /* number of events in ER */ 236 uint32_t event_pcs; /* producer cycle state flag */ 237 }; 238 239 240 struct pci_xhci_softc; 241 242 243 /* 244 * USB device emulation container. 245 * This is referenced from usb_hci->hci_sc; 1 pci_xhci_dev_emu for each 246 * emulated device instance. 247 */ 248 struct pci_xhci_dev_emu { 249 struct pci_xhci_softc *xsc; 250 251 /* XHCI contexts */ 252 struct xhci_dev_ctx *dev_ctx; 253 struct pci_xhci_dev_ep eps[XHCI_MAX_ENDPOINTS]; 254 int dev_slotstate; 255 256 struct usb_devemu *dev_ue; /* USB emulated dev */ 257 void *dev_sc; /* device's softc */ 258 259 struct usb_hci hci; 260 }; 261 262 struct pci_xhci_softc { 263 struct pci_devinst *xsc_pi; 264 265 pthread_mutex_t mtx; 266 267 uint32_t caplength; /* caplen & hciversion */ 268 uint32_t hcsparams1; /* structural parameters 1 */ 269 uint32_t hcsparams2; /* structural parameters 2 */ 270 uint32_t hcsparams3; /* structural parameters 3 */ 271 uint32_t hccparams1; /* capability parameters 1 */ 272 uint32_t dboff; /* doorbell offset */ 273 uint32_t rtsoff; /* runtime register space offset */ 274 uint32_t hccparams2; /* capability parameters 2 */ 275 276 uint32_t regsend; /* end of configuration registers */ 277 278 struct pci_xhci_opregs opregs; 279 struct pci_xhci_rtsregs rtsregs; 280 281 struct pci_xhci_portregs *portregs; 282 struct pci_xhci_dev_emu **devices; /* XHCI[port] = device */ 283 struct pci_xhci_dev_emu **slots; /* slots assigned from 1 */ 284 285 int usb2_port_start; 286 int usb3_port_start; 287 }; 288 289 290 /* portregs and devices arrays are set up to start from idx=1 */ 291 #define XHCI_PORTREG_PTR(x,n) &(x)->portregs[(n)] 292 #define XHCI_DEVINST_PTR(x,n) (x)->devices[(n)] 293 #define XHCI_SLOTDEV_PTR(x,n) (x)->slots[(n)] 294 295 #define XHCI_HALTED(sc) ((sc)->opregs.usbsts & XHCI_STS_HCH) 296 297 #define XHCI_GADDR(sc,a) paddr_guest2host((sc)->xsc_pi->pi_vmctx, \ 298 (a), \ 299 XHCI_PADDR_SZ - ((a) & (XHCI_PADDR_SZ-1))) 300 301 static int xhci_in_use; 302 303 /* map USB errors to XHCI */ 304 static const int xhci_usb_errors[USB_ERR_MAX] = { 305 [USB_ERR_NORMAL_COMPLETION] = XHCI_TRB_ERROR_SUCCESS, 306 [USB_ERR_PENDING_REQUESTS] = XHCI_TRB_ERROR_RESOURCE, 307 [USB_ERR_NOT_STARTED] = XHCI_TRB_ERROR_ENDP_NOT_ON, 308 [USB_ERR_INVAL] = XHCI_TRB_ERROR_INVALID, 309 [USB_ERR_NOMEM] = XHCI_TRB_ERROR_RESOURCE, 310 [USB_ERR_CANCELLED] = XHCI_TRB_ERROR_STOPPED, 311 [USB_ERR_BAD_ADDRESS] = XHCI_TRB_ERROR_PARAMETER, 312 [USB_ERR_BAD_BUFSIZE] = XHCI_TRB_ERROR_PARAMETER, 313 [USB_ERR_BAD_FLAG] = XHCI_TRB_ERROR_PARAMETER, 314 [USB_ERR_NO_CALLBACK] = XHCI_TRB_ERROR_STALL, 315 [USB_ERR_IN_USE] = XHCI_TRB_ERROR_RESOURCE, 316 [USB_ERR_NO_ADDR] = XHCI_TRB_ERROR_RESOURCE, 317 [USB_ERR_NO_PIPE] = XHCI_TRB_ERROR_RESOURCE, 318 [USB_ERR_ZERO_NFRAMES] = XHCI_TRB_ERROR_UNDEFINED, 319 [USB_ERR_ZERO_MAXP] = XHCI_TRB_ERROR_UNDEFINED, 320 [USB_ERR_SET_ADDR_FAILED] = XHCI_TRB_ERROR_RESOURCE, 321 [USB_ERR_NO_POWER] = XHCI_TRB_ERROR_ENDP_NOT_ON, 322 [USB_ERR_TOO_DEEP] = XHCI_TRB_ERROR_RESOURCE, 323 [USB_ERR_IOERROR] = XHCI_TRB_ERROR_TRB, 324 [USB_ERR_NOT_CONFIGURED] = XHCI_TRB_ERROR_ENDP_NOT_ON, 325 [USB_ERR_TIMEOUT] = XHCI_TRB_ERROR_CMD_ABORTED, 326 [USB_ERR_SHORT_XFER] = XHCI_TRB_ERROR_SHORT_PKT, 327 [USB_ERR_STALLED] = XHCI_TRB_ERROR_STALL, 328 [USB_ERR_INTERRUPTED] = XHCI_TRB_ERROR_CMD_ABORTED, 329 [USB_ERR_DMA_LOAD_FAILED] = XHCI_TRB_ERROR_DATA_BUF, 330 [USB_ERR_BAD_CONTEXT] = XHCI_TRB_ERROR_TRB, 331 [USB_ERR_NO_ROOT_HUB] = XHCI_TRB_ERROR_UNDEFINED, 332 [USB_ERR_NO_INTR_THREAD] = XHCI_TRB_ERROR_UNDEFINED, 333 [USB_ERR_NOT_LOCKED] = XHCI_TRB_ERROR_UNDEFINED, 334 }; 335 #define USB_TO_XHCI_ERR(e) ((e) < USB_ERR_MAX ? xhci_usb_errors[(e)] : \ 336 XHCI_TRB_ERROR_INVALID) 337 338 static int pci_xhci_insert_event(struct pci_xhci_softc *sc, 339 struct xhci_trb *evtrb, int do_intr); 340 static void pci_xhci_dump_trb(struct xhci_trb *trb); 341 static void pci_xhci_assert_interrupt(struct pci_xhci_softc *sc); 342 static void pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot); 343 static void pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm); 344 static void pci_xhci_update_ep_ring(struct pci_xhci_softc *sc, 345 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, 346 struct xhci_endp_ctx *ep_ctx, uint32_t streamid, 347 uint64_t ringaddr, int ccs); 348 349 static void 350 pci_xhci_set_evtrb(struct xhci_trb *evtrb, uint64_t port, uint32_t errcode, 351 uint32_t evtype) 352 { 353 evtrb->qwTrb0 = port << 24; 354 evtrb->dwTrb2 = XHCI_TRB_2_ERROR_SET(errcode); 355 evtrb->dwTrb3 = XHCI_TRB_3_TYPE_SET(evtype); 356 } 357 358 359 /* controller reset */ 360 static void 361 pci_xhci_reset(struct pci_xhci_softc *sc) 362 { 363 int i; 364 365 sc->rtsregs.er_enq_idx = 0; 366 sc->rtsregs.er_events_cnt = 0; 367 sc->rtsregs.event_pcs = 1; 368 369 for (i = 1; i <= XHCI_MAX_SLOTS; i++) { 370 pci_xhci_reset_slot(sc, i); 371 } 372 } 373 374 static uint32_t 375 pci_xhci_usbcmd_write(struct pci_xhci_softc *sc, uint32_t cmd) 376 { 377 int do_intr = 0; 378 int i; 379 380 if (cmd & XHCI_CMD_RS) { 381 do_intr = (sc->opregs.usbcmd & XHCI_CMD_RS) == 0; 382 383 sc->opregs.usbcmd |= XHCI_CMD_RS; 384 sc->opregs.usbsts &= ~XHCI_STS_HCH; 385 sc->opregs.usbsts |= XHCI_STS_PCD; 386 387 /* Queue port change event on controller run from stop */ 388 if (do_intr) 389 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 390 struct pci_xhci_dev_emu *dev; 391 struct pci_xhci_portregs *port; 392 struct xhci_trb evtrb; 393 394 if ((dev = XHCI_DEVINST_PTR(sc, i)) == NULL) 395 continue; 396 397 port = XHCI_PORTREG_PTR(sc, i); 398 port->portsc |= XHCI_PS_CSC | XHCI_PS_CCS; 399 port->portsc &= ~XHCI_PS_PLS_MASK; 400 401 /* 402 * XHCI 4.19.3 USB2 RxDetect->Polling, 403 * USB3 Polling->U0 404 */ 405 if (dev->dev_ue->ue_usbver == 2) 406 port->portsc |= 407 XHCI_PS_PLS_SET(UPS_PORT_LS_POLL); 408 else 409 port->portsc |= 410 XHCI_PS_PLS_SET(UPS_PORT_LS_U0); 411 412 pci_xhci_set_evtrb(&evtrb, i, 413 XHCI_TRB_ERROR_SUCCESS, 414 XHCI_TRB_EVENT_PORT_STS_CHANGE); 415 416 if (pci_xhci_insert_event(sc, &evtrb, 0) != 417 XHCI_TRB_ERROR_SUCCESS) 418 break; 419 } 420 } else { 421 sc->opregs.usbcmd &= ~XHCI_CMD_RS; 422 sc->opregs.usbsts |= XHCI_STS_HCH; 423 sc->opregs.usbsts &= ~XHCI_STS_PCD; 424 } 425 426 /* start execution of schedule; stop when set to 0 */ 427 cmd |= sc->opregs.usbcmd & XHCI_CMD_RS; 428 429 if (cmd & XHCI_CMD_HCRST) { 430 /* reset controller */ 431 pci_xhci_reset(sc); 432 cmd &= ~XHCI_CMD_HCRST; 433 } 434 435 cmd &= ~(XHCI_CMD_CSS | XHCI_CMD_CRS); 436 437 if (do_intr) 438 pci_xhci_assert_interrupt(sc); 439 440 return (cmd); 441 } 442 443 static void 444 pci_xhci_portregs_write(struct pci_xhci_softc *sc, uint64_t offset, 445 uint64_t value) 446 { 447 struct xhci_trb evtrb; 448 struct pci_xhci_portregs *p; 449 int port; 450 uint32_t oldpls, newpls; 451 452 if (sc->portregs == NULL) 453 return; 454 455 port = (offset - XHCI_PORTREGS_PORT0) / XHCI_PORTREGS_SETSZ; 456 offset = (offset - XHCI_PORTREGS_PORT0) % XHCI_PORTREGS_SETSZ; 457 458 DPRINTF(("pci_xhci: portregs wr offset 0x%lx, port %u: 0x%lx", 459 offset, port, value)); 460 461 assert(port >= 0); 462 463 if (port > XHCI_MAX_DEVS) { 464 DPRINTF(("pci_xhci: portregs_write port %d > ndevices", 465 port)); 466 return; 467 } 468 469 if (XHCI_DEVINST_PTR(sc, port) == NULL) { 470 DPRINTF(("pci_xhci: portregs_write to unattached port %d", 471 port)); 472 } 473 474 p = XHCI_PORTREG_PTR(sc, port); 475 switch (offset) { 476 case 0: 477 /* port reset or warm reset */ 478 if (value & (XHCI_PS_PR | XHCI_PS_WPR)) { 479 pci_xhci_reset_port(sc, port, value & XHCI_PS_WPR); 480 break; 481 } 482 483 if ((p->portsc & XHCI_PS_PP) == 0) { 484 WPRINTF(("pci_xhci: portregs_write to unpowered " 485 "port %d", port)); 486 break; 487 } 488 489 /* Port status and control register */ 490 oldpls = XHCI_PS_PLS_GET(p->portsc); 491 newpls = XHCI_PS_PLS_GET(value); 492 493 #ifndef __FreeBSD__ 494 p->portsc &= XHCI_PS_PED | XHCI_PS_PP | XHCI_PS_PLS_MASK | 495 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK; 496 #else 497 p->portsc &= XHCI_PS_PED | XHCI_PS_PLS_MASK | 498 XHCI_PS_SPEED_MASK | XHCI_PS_PIC_MASK; 499 #endif 500 501 if (XHCI_DEVINST_PTR(sc, port)) 502 p->portsc |= XHCI_PS_CCS; 503 504 p->portsc |= (value & 505 ~(XHCI_PS_OCA | 506 XHCI_PS_PR | 507 XHCI_PS_PED | 508 XHCI_PS_PLS_MASK | /* link state */ 509 XHCI_PS_SPEED_MASK | 510 XHCI_PS_PIC_MASK | /* port indicator */ 511 XHCI_PS_LWS | XHCI_PS_DR | XHCI_PS_WPR)); 512 513 /* clear control bits */ 514 p->portsc &= ~(value & 515 (XHCI_PS_CSC | 516 XHCI_PS_PEC | 517 XHCI_PS_WRC | 518 XHCI_PS_OCC | 519 XHCI_PS_PRC | 520 XHCI_PS_PLC | 521 XHCI_PS_CEC | 522 XHCI_PS_CAS)); 523 524 /* port disable request; for USB3, don't care */ 525 if (value & XHCI_PS_PED) 526 DPRINTF(("Disable port %d request", port)); 527 528 if (!(value & XHCI_PS_LWS)) 529 break; 530 531 DPRINTF(("Port new PLS: %d", newpls)); 532 switch (newpls) { 533 case 0: /* U0 */ 534 case 3: /* U3 */ 535 if (oldpls != newpls) { 536 p->portsc &= ~XHCI_PS_PLS_MASK; 537 p->portsc |= XHCI_PS_PLS_SET(newpls) | 538 XHCI_PS_PLC; 539 540 if (oldpls != 0 && newpls == 0) { 541 pci_xhci_set_evtrb(&evtrb, port, 542 XHCI_TRB_ERROR_SUCCESS, 543 XHCI_TRB_EVENT_PORT_STS_CHANGE); 544 545 pci_xhci_insert_event(sc, &evtrb, 1); 546 } 547 } 548 break; 549 550 default: 551 DPRINTF(("Unhandled change port %d PLS %u", 552 port, newpls)); 553 break; 554 } 555 break; 556 case 4: 557 /* Port power management status and control register */ 558 p->portpmsc = value; 559 break; 560 case 8: 561 /* Port link information register */ 562 DPRINTF(("pci_xhci attempted write to PORTLI, port %d", 563 port)); 564 break; 565 case 12: 566 /* 567 * Port hardware LPM control register. 568 * For USB3, this register is reserved. 569 */ 570 p->porthlpmc = value; 571 break; 572 } 573 } 574 575 static struct xhci_dev_ctx * 576 pci_xhci_get_dev_ctx(struct pci_xhci_softc *sc, uint32_t slot) 577 { 578 uint64_t devctx_addr; 579 struct xhci_dev_ctx *devctx; 580 581 assert(slot > 0 && slot <= XHCI_MAX_DEVS); 582 assert(XHCI_SLOTDEV_PTR(sc, slot) != NULL); 583 assert(sc->opregs.dcbaa_p != NULL); 584 585 devctx_addr = sc->opregs.dcbaa_p->dcba[slot]; 586 587 if (devctx_addr == 0) { 588 DPRINTF(("get_dev_ctx devctx_addr == 0")); 589 return (NULL); 590 } 591 592 DPRINTF(("pci_xhci: get dev ctx, slot %u devctx addr %016lx", 593 slot, devctx_addr)); 594 devctx = XHCI_GADDR(sc, devctx_addr & ~0x3FUL); 595 596 return (devctx); 597 } 598 599 static struct xhci_trb * 600 pci_xhci_trb_next(struct pci_xhci_softc *sc, struct xhci_trb *curtrb, 601 uint64_t *guestaddr) 602 { 603 struct xhci_trb *next; 604 605 assert(curtrb != NULL); 606 607 if (XHCI_TRB_3_TYPE_GET(curtrb->dwTrb3) == XHCI_TRB_TYPE_LINK) { 608 if (guestaddr) 609 *guestaddr = curtrb->qwTrb0 & ~0xFUL; 610 611 next = XHCI_GADDR(sc, curtrb->qwTrb0 & ~0xFUL); 612 } else { 613 if (guestaddr) 614 *guestaddr += sizeof(struct xhci_trb) & ~0xFUL; 615 616 next = curtrb + 1; 617 } 618 619 return (next); 620 } 621 622 static void 623 pci_xhci_assert_interrupt(struct pci_xhci_softc *sc) 624 { 625 626 sc->rtsregs.intrreg.erdp |= XHCI_ERDP_LO_BUSY; 627 sc->rtsregs.intrreg.iman |= XHCI_IMAN_INTR_PEND; 628 sc->opregs.usbsts |= XHCI_STS_EINT; 629 630 /* only trigger interrupt if permitted */ 631 if ((sc->opregs.usbcmd & XHCI_CMD_INTE) && 632 (sc->rtsregs.intrreg.iman & XHCI_IMAN_INTR_ENA)) { 633 if (pci_msi_enabled(sc->xsc_pi)) 634 pci_generate_msi(sc->xsc_pi, 0); 635 else 636 pci_lintr_assert(sc->xsc_pi); 637 } 638 } 639 640 static void 641 pci_xhci_deassert_interrupt(struct pci_xhci_softc *sc) 642 { 643 644 if (!pci_msi_enabled(sc->xsc_pi)) 645 pci_lintr_assert(sc->xsc_pi); 646 } 647 648 static void 649 pci_xhci_init_ep(struct pci_xhci_dev_emu *dev, int epid) 650 { 651 struct xhci_dev_ctx *dev_ctx; 652 struct pci_xhci_dev_ep *devep; 653 struct xhci_endp_ctx *ep_ctx; 654 uint32_t pstreams; 655 int i; 656 657 dev_ctx = dev->dev_ctx; 658 ep_ctx = &dev_ctx->ctx_ep[epid]; 659 devep = &dev->eps[epid]; 660 pstreams = XHCI_EPCTX_0_MAXP_STREAMS_GET(ep_ctx->dwEpCtx0); 661 if (pstreams > 0) { 662 DPRINTF(("init_ep %d with pstreams %d", epid, pstreams)); 663 assert(devep->ep_sctx_trbs == NULL); 664 665 devep->ep_sctx = XHCI_GADDR(dev->xsc, ep_ctx->qwEpCtx2 & 666 XHCI_EPCTX_2_TR_DQ_PTR_MASK); 667 devep->ep_sctx_trbs = calloc(pstreams, 668 sizeof(struct pci_xhci_trb_ring)); 669 for (i = 0; i < pstreams; i++) { 670 devep->ep_sctx_trbs[i].ringaddr = 671 devep->ep_sctx[i].qwSctx0 & 672 XHCI_SCTX_0_TR_DQ_PTR_MASK; 673 devep->ep_sctx_trbs[i].ccs = 674 XHCI_SCTX_0_DCS_GET(devep->ep_sctx[i].qwSctx0); 675 } 676 } else { 677 DPRINTF(("init_ep %d with no pstreams", epid)); 678 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & 679 XHCI_EPCTX_2_TR_DQ_PTR_MASK; 680 devep->ep_ccs = XHCI_EPCTX_2_DCS_GET(ep_ctx->qwEpCtx2); 681 devep->ep_tr = XHCI_GADDR(dev->xsc, devep->ep_ringaddr); 682 DPRINTF(("init_ep tr DCS %x", devep->ep_ccs)); 683 } 684 devep->ep_MaxPStreams = pstreams; 685 686 if (devep->ep_xfer == NULL) { 687 devep->ep_xfer = malloc(sizeof(struct usb_data_xfer)); 688 USB_DATA_XFER_INIT(devep->ep_xfer); 689 } 690 } 691 692 static void 693 pci_xhci_disable_ep(struct pci_xhci_dev_emu *dev, int epid) 694 { 695 struct xhci_dev_ctx *dev_ctx; 696 struct pci_xhci_dev_ep *devep; 697 struct xhci_endp_ctx *ep_ctx; 698 699 DPRINTF(("pci_xhci disable_ep %d", epid)); 700 701 dev_ctx = dev->dev_ctx; 702 ep_ctx = &dev_ctx->ctx_ep[epid]; 703 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_DISABLED; 704 705 devep = &dev->eps[epid]; 706 if (devep->ep_MaxPStreams > 0) 707 free(devep->ep_sctx_trbs); 708 709 if (devep->ep_xfer != NULL) { 710 free(devep->ep_xfer); 711 devep->ep_xfer = NULL; 712 } 713 714 memset(devep, 0, sizeof(struct pci_xhci_dev_ep)); 715 } 716 717 718 /* reset device at slot and data structures related to it */ 719 static void 720 pci_xhci_reset_slot(struct pci_xhci_softc *sc, int slot) 721 { 722 struct pci_xhci_dev_emu *dev; 723 724 dev = XHCI_SLOTDEV_PTR(sc, slot); 725 726 if (!dev) { 727 DPRINTF(("xhci reset unassigned slot (%d)?", slot)); 728 } else { 729 dev->dev_slotstate = XHCI_ST_DISABLED; 730 } 731 732 /* TODO: reset ring buffer pointers */ 733 } 734 735 static int 736 pci_xhci_insert_event(struct pci_xhci_softc *sc, struct xhci_trb *evtrb, 737 int do_intr) 738 { 739 struct pci_xhci_rtsregs *rts; 740 uint64_t erdp; 741 int erdp_idx; 742 int err; 743 struct xhci_trb *evtrbptr; 744 745 err = XHCI_TRB_ERROR_SUCCESS; 746 747 rts = &sc->rtsregs; 748 749 erdp = rts->intrreg.erdp & ~0xF; 750 erdp_idx = (erdp - rts->erstba_p[rts->er_deq_seg].qwEvrsTablePtr) / 751 sizeof(struct xhci_trb); 752 753 DPRINTF(("pci_xhci: insert event 0[%lx] 2[%x] 3[%x]", 754 evtrb->qwTrb0, evtrb->dwTrb2, evtrb->dwTrb3)); 755 DPRINTF(("\terdp idx %d/seg %d, enq idx %d/seg %d, pcs %u", 756 erdp_idx, rts->er_deq_seg, rts->er_enq_idx, 757 rts->er_enq_seg, rts->event_pcs)); 758 DPRINTF(("\t(erdp=0x%lx, erst=0x%lx, tblsz=%u, do_intr %d)", 759 erdp, rts->erstba_p->qwEvrsTablePtr, 760 rts->erstba_p->dwEvrsTableSize, do_intr)); 761 762 evtrbptr = &rts->erst_p[rts->er_enq_idx]; 763 764 /* TODO: multi-segment table */ 765 if (rts->er_events_cnt >= rts->erstba_p->dwEvrsTableSize) { 766 DPRINTF(("pci_xhci[%d] cannot insert event; ring full", 767 __LINE__)); 768 err = XHCI_TRB_ERROR_EV_RING_FULL; 769 goto done; 770 } 771 772 if (rts->er_events_cnt == rts->erstba_p->dwEvrsTableSize - 1) { 773 struct xhci_trb errev; 774 775 if ((evtrbptr->dwTrb3 & 0x1) == (rts->event_pcs & 0x1)) { 776 777 DPRINTF(("pci_xhci[%d] insert evt err: ring full", 778 __LINE__)); 779 780 errev.qwTrb0 = 0; 781 errev.dwTrb2 = XHCI_TRB_2_ERROR_SET( 782 XHCI_TRB_ERROR_EV_RING_FULL); 783 errev.dwTrb3 = XHCI_TRB_3_TYPE_SET( 784 XHCI_TRB_EVENT_HOST_CTRL) | 785 rts->event_pcs; 786 rts->er_events_cnt++; 787 memcpy(&rts->erst_p[rts->er_enq_idx], &errev, 788 sizeof(struct xhci_trb)); 789 rts->er_enq_idx = (rts->er_enq_idx + 1) % 790 rts->erstba_p->dwEvrsTableSize; 791 err = XHCI_TRB_ERROR_EV_RING_FULL; 792 do_intr = 1; 793 794 goto done; 795 } 796 } else { 797 rts->er_events_cnt++; 798 } 799 800 evtrb->dwTrb3 &= ~XHCI_TRB_3_CYCLE_BIT; 801 evtrb->dwTrb3 |= rts->event_pcs; 802 803 memcpy(&rts->erst_p[rts->er_enq_idx], evtrb, sizeof(struct xhci_trb)); 804 rts->er_enq_idx = (rts->er_enq_idx + 1) % 805 rts->erstba_p->dwEvrsTableSize; 806 807 if (rts->er_enq_idx == 0) 808 rts->event_pcs ^= 1; 809 810 done: 811 if (do_intr) 812 pci_xhci_assert_interrupt(sc); 813 814 return (err); 815 } 816 817 static uint32_t 818 pci_xhci_cmd_enable_slot(struct pci_xhci_softc *sc, uint32_t *slot) 819 { 820 struct pci_xhci_dev_emu *dev; 821 uint32_t cmderr; 822 int i; 823 824 cmderr = XHCI_TRB_ERROR_NO_SLOTS; 825 if (sc->portregs != NULL) 826 for (i = 1; i <= XHCI_MAX_SLOTS; i++) { 827 dev = XHCI_SLOTDEV_PTR(sc, i); 828 if (dev && dev->dev_slotstate == XHCI_ST_DISABLED) { 829 *slot = i; 830 dev->dev_slotstate = XHCI_ST_ENABLED; 831 cmderr = XHCI_TRB_ERROR_SUCCESS; 832 dev->hci.hci_address = i; 833 break; 834 } 835 } 836 837 DPRINTF(("pci_xhci enable slot (error=%d) slot %u", 838 cmderr != XHCI_TRB_ERROR_SUCCESS, *slot)); 839 840 return (cmderr); 841 } 842 843 static uint32_t 844 pci_xhci_cmd_disable_slot(struct pci_xhci_softc *sc, uint32_t slot) 845 { 846 struct pci_xhci_dev_emu *dev; 847 uint32_t cmderr; 848 849 DPRINTF(("pci_xhci disable slot %u", slot)); 850 851 cmderr = XHCI_TRB_ERROR_NO_SLOTS; 852 if (sc->portregs == NULL) 853 goto done; 854 855 if (slot > XHCI_MAX_SLOTS) { 856 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 857 goto done; 858 } 859 860 dev = XHCI_SLOTDEV_PTR(sc, slot); 861 if (dev) { 862 if (dev->dev_slotstate == XHCI_ST_DISABLED) { 863 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 864 } else { 865 dev->dev_slotstate = XHCI_ST_DISABLED; 866 cmderr = XHCI_TRB_ERROR_SUCCESS; 867 /* TODO: reset events and endpoints */ 868 } 869 } else 870 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 871 872 done: 873 return (cmderr); 874 } 875 876 static uint32_t 877 pci_xhci_cmd_reset_device(struct pci_xhci_softc *sc, uint32_t slot) 878 { 879 struct pci_xhci_dev_emu *dev; 880 struct xhci_dev_ctx *dev_ctx; 881 struct xhci_endp_ctx *ep_ctx; 882 uint32_t cmderr; 883 int i; 884 885 cmderr = XHCI_TRB_ERROR_NO_SLOTS; 886 if (sc->portregs == NULL) 887 goto done; 888 889 DPRINTF(("pci_xhci reset device slot %u", slot)); 890 891 dev = XHCI_SLOTDEV_PTR(sc, slot); 892 if (!dev || dev->dev_slotstate == XHCI_ST_DISABLED) 893 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 894 else { 895 dev->dev_slotstate = XHCI_ST_DEFAULT; 896 897 dev->hci.hci_address = 0; 898 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 899 900 /* slot state */ 901 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( 902 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_DEFAULT, 903 0x1F, 27); 904 905 /* number of contexts */ 906 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE( 907 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27); 908 909 /* reset all eps other than ep-0 */ 910 for (i = 2; i <= 31; i++) { 911 ep_ctx = &dev_ctx->ctx_ep[i]; 912 ep_ctx->dwEpCtx0 = FIELD_REPLACE( ep_ctx->dwEpCtx0, 913 XHCI_ST_EPCTX_DISABLED, 0x7, 0); 914 } 915 916 cmderr = XHCI_TRB_ERROR_SUCCESS; 917 } 918 919 pci_xhci_reset_slot(sc, slot); 920 921 done: 922 return (cmderr); 923 } 924 925 static uint32_t 926 pci_xhci_cmd_address_device(struct pci_xhci_softc *sc, uint32_t slot, 927 struct xhci_trb *trb) 928 { 929 struct pci_xhci_dev_emu *dev; 930 struct xhci_input_dev_ctx *input_ctx; 931 struct xhci_slot_ctx *islot_ctx; 932 struct xhci_dev_ctx *dev_ctx; 933 struct xhci_endp_ctx *ep0_ctx; 934 uint32_t cmderr; 935 936 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); 937 islot_ctx = &input_ctx->ctx_slot; 938 ep0_ctx = &input_ctx->ctx_ep[1]; 939 940 cmderr = XHCI_TRB_ERROR_SUCCESS; 941 942 DPRINTF(("pci_xhci: address device, input ctl: D 0x%08x A 0x%08x,", 943 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1)); 944 DPRINTF((" slot %08x %08x %08x %08x", 945 islot_ctx->dwSctx0, islot_ctx->dwSctx1, 946 islot_ctx->dwSctx2, islot_ctx->dwSctx3)); 947 DPRINTF((" ep0 %08x %08x %016lx %08x", 948 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 949 ep0_ctx->dwEpCtx4)); 950 951 /* when setting address: drop-ctx=0, add-ctx=slot+ep0 */ 952 if ((input_ctx->ctx_input.dwInCtx0 != 0) || 953 (input_ctx->ctx_input.dwInCtx1 & 0x03) != 0x03) { 954 DPRINTF(("pci_xhci: address device, input ctl invalid")); 955 cmderr = XHCI_TRB_ERROR_TRB; 956 goto done; 957 } 958 959 /* assign address to slot */ 960 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 961 962 DPRINTF(("pci_xhci: address device, dev ctx")); 963 DPRINTF((" slot %08x %08x %08x %08x", 964 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 965 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 966 967 dev = XHCI_SLOTDEV_PTR(sc, slot); 968 assert(dev != NULL); 969 970 dev->hci.hci_address = slot; 971 dev->dev_ctx = dev_ctx; 972 973 if (dev->dev_ue->ue_reset == NULL || 974 dev->dev_ue->ue_reset(dev->dev_sc) < 0) { 975 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON; 976 goto done; 977 } 978 979 memcpy(&dev_ctx->ctx_slot, islot_ctx, sizeof(struct xhci_slot_ctx)); 980 981 dev_ctx->ctx_slot.dwSctx3 = 982 XHCI_SCTX_3_SLOT_STATE_SET(XHCI_ST_SLCTX_ADDRESSED) | 983 XHCI_SCTX_3_DEV_ADDR_SET(slot); 984 985 memcpy(&dev_ctx->ctx_ep[1], ep0_ctx, sizeof(struct xhci_endp_ctx)); 986 ep0_ctx = &dev_ctx->ctx_ep[1]; 987 ep0_ctx->dwEpCtx0 = (ep0_ctx->dwEpCtx0 & ~0x7) | 988 XHCI_EPCTX_0_EPSTATE_SET(XHCI_ST_EPCTX_RUNNING); 989 990 pci_xhci_init_ep(dev, 1); 991 992 dev->dev_slotstate = XHCI_ST_ADDRESSED; 993 994 DPRINTF(("pci_xhci: address device, output ctx")); 995 DPRINTF((" slot %08x %08x %08x %08x", 996 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 997 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 998 DPRINTF((" ep0 %08x %08x %016lx %08x", 999 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 1000 ep0_ctx->dwEpCtx4)); 1001 1002 done: 1003 return (cmderr); 1004 } 1005 1006 static uint32_t 1007 pci_xhci_cmd_config_ep(struct pci_xhci_softc *sc, uint32_t slot, 1008 struct xhci_trb *trb) 1009 { 1010 struct xhci_input_dev_ctx *input_ctx; 1011 struct pci_xhci_dev_emu *dev; 1012 struct xhci_dev_ctx *dev_ctx; 1013 struct xhci_endp_ctx *ep_ctx, *iep_ctx; 1014 uint32_t cmderr; 1015 int i; 1016 1017 cmderr = XHCI_TRB_ERROR_SUCCESS; 1018 1019 DPRINTF(("pci_xhci config_ep slot %u", slot)); 1020 1021 dev = XHCI_SLOTDEV_PTR(sc, slot); 1022 assert(dev != NULL); 1023 1024 if ((trb->dwTrb3 & XHCI_TRB_3_DCEP_BIT) != 0) { 1025 DPRINTF(("pci_xhci config_ep - deconfigure ep slot %u", 1026 slot)); 1027 if (dev->dev_ue->ue_stop != NULL) 1028 dev->dev_ue->ue_stop(dev->dev_sc); 1029 1030 dev->dev_slotstate = XHCI_ST_ADDRESSED; 1031 1032 dev->hci.hci_address = 0; 1033 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1034 1035 /* number of contexts */ 1036 dev_ctx->ctx_slot.dwSctx0 = FIELD_REPLACE( 1037 dev_ctx->ctx_slot.dwSctx0, 1, 0x1F, 27); 1038 1039 /* slot state */ 1040 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( 1041 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_ADDRESSED, 1042 0x1F, 27); 1043 1044 /* disable endpoints */ 1045 for (i = 2; i < 32; i++) 1046 pci_xhci_disable_ep(dev, i); 1047 1048 cmderr = XHCI_TRB_ERROR_SUCCESS; 1049 1050 goto done; 1051 } 1052 1053 if (dev->dev_slotstate < XHCI_ST_ADDRESSED) { 1054 DPRINTF(("pci_xhci: config_ep slotstate x%x != addressed", 1055 dev->dev_slotstate)); 1056 cmderr = XHCI_TRB_ERROR_SLOT_NOT_ON; 1057 goto done; 1058 } 1059 1060 /* In addressed/configured state; 1061 * for each drop endpoint ctx flag: 1062 * ep->state = DISABLED 1063 * for each add endpoint ctx flag: 1064 * cp(ep-in, ep-out) 1065 * ep->state = RUNNING 1066 * for each drop+add endpoint flag: 1067 * reset ep resources 1068 * cp(ep-in, ep-out) 1069 * ep->state = RUNNING 1070 * if input->DisabledCtx[2-31] < 30: (at least 1 ep not disabled) 1071 * slot->state = configured 1072 */ 1073 1074 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); 1075 dev_ctx = dev->dev_ctx; 1076 DPRINTF(("pci_xhci: config_ep inputctx: D:x%08x A:x%08x 7:x%08x", 1077 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1, 1078 input_ctx->ctx_input.dwInCtx7)); 1079 1080 for (i = 2; i <= 31; i++) { 1081 ep_ctx = &dev_ctx->ctx_ep[i]; 1082 1083 if (input_ctx->ctx_input.dwInCtx0 & 1084 XHCI_INCTX_0_DROP_MASK(i)) { 1085 DPRINTF((" config ep - dropping ep %d", i)); 1086 pci_xhci_disable_ep(dev, i); 1087 } 1088 1089 if (input_ctx->ctx_input.dwInCtx1 & 1090 XHCI_INCTX_1_ADD_MASK(i)) { 1091 iep_ctx = &input_ctx->ctx_ep[i]; 1092 1093 DPRINTF((" enable ep[%d] %08x %08x %016lx %08x", 1094 i, iep_ctx->dwEpCtx0, iep_ctx->dwEpCtx1, 1095 iep_ctx->qwEpCtx2, iep_ctx->dwEpCtx4)); 1096 1097 memcpy(ep_ctx, iep_ctx, sizeof(struct xhci_endp_ctx)); 1098 1099 pci_xhci_init_ep(dev, i); 1100 1101 /* ep state */ 1102 ep_ctx->dwEpCtx0 = FIELD_REPLACE( 1103 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0); 1104 } 1105 } 1106 1107 /* slot state to configured */ 1108 dev_ctx->ctx_slot.dwSctx3 = FIELD_REPLACE( 1109 dev_ctx->ctx_slot.dwSctx3, XHCI_ST_SLCTX_CONFIGURED, 0x1F, 27); 1110 dev_ctx->ctx_slot.dwSctx0 = FIELD_COPY( 1111 dev_ctx->ctx_slot.dwSctx0, input_ctx->ctx_slot.dwSctx0, 0x1F, 27); 1112 dev->dev_slotstate = XHCI_ST_CONFIGURED; 1113 1114 DPRINTF(("EP configured; slot %u [0]=0x%08x [1]=0x%08x [2]=0x%08x " 1115 "[3]=0x%08x", 1116 slot, dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1117 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1118 1119 done: 1120 return (cmderr); 1121 } 1122 1123 static uint32_t 1124 pci_xhci_cmd_reset_ep(struct pci_xhci_softc *sc, uint32_t slot, 1125 struct xhci_trb *trb) 1126 { 1127 struct pci_xhci_dev_emu *dev; 1128 struct pci_xhci_dev_ep *devep; 1129 struct xhci_dev_ctx *dev_ctx; 1130 struct xhci_endp_ctx *ep_ctx; 1131 uint32_t cmderr, epid; 1132 uint32_t type; 1133 1134 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3); 1135 1136 DPRINTF(("pci_xhci: reset ep %u: slot %u", epid, slot)); 1137 1138 cmderr = XHCI_TRB_ERROR_SUCCESS; 1139 1140 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); 1141 1142 dev = XHCI_SLOTDEV_PTR(sc, slot); 1143 assert(dev != NULL); 1144 1145 if (type == XHCI_TRB_TYPE_STOP_EP && 1146 (trb->dwTrb3 & XHCI_TRB_3_SUSP_EP_BIT) != 0) { 1147 /* XXX suspend endpoint for 10ms */ 1148 } 1149 1150 if (epid < 1 || epid > 31) { 1151 DPRINTF(("pci_xhci: reset ep: invalid epid %u", epid)); 1152 cmderr = XHCI_TRB_ERROR_TRB; 1153 goto done; 1154 } 1155 1156 devep = &dev->eps[epid]; 1157 if (devep->ep_xfer != NULL) 1158 USB_DATA_XFER_RESET(devep->ep_xfer); 1159 1160 dev_ctx = dev->dev_ctx; 1161 assert(dev_ctx != NULL); 1162 1163 ep_ctx = &dev_ctx->ctx_ep[epid]; 1164 1165 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED; 1166 1167 if (devep->ep_MaxPStreams == 0) 1168 ep_ctx->qwEpCtx2 = devep->ep_ringaddr | devep->ep_ccs; 1169 1170 DPRINTF(("pci_xhci: reset ep[%u] %08x %08x %016lx %08x", 1171 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2, 1172 ep_ctx->dwEpCtx4)); 1173 1174 if (type == XHCI_TRB_TYPE_RESET_EP && 1175 (dev->dev_ue->ue_reset == NULL || 1176 dev->dev_ue->ue_reset(dev->dev_sc) < 0)) { 1177 cmderr = XHCI_TRB_ERROR_ENDP_NOT_ON; 1178 goto done; 1179 } 1180 1181 done: 1182 return (cmderr); 1183 } 1184 1185 1186 static uint32_t 1187 pci_xhci_find_stream(struct pci_xhci_softc *sc, struct xhci_endp_ctx *ep, 1188 struct pci_xhci_dev_ep *devep, uint32_t streamid, 1189 struct xhci_stream_ctx **osctx) 1190 { 1191 struct xhci_stream_ctx *sctx; 1192 1193 if (devep->ep_MaxPStreams == 0) 1194 return (XHCI_TRB_ERROR_TRB); 1195 1196 if (devep->ep_MaxPStreams > XHCI_STREAMS_MAX) 1197 return (XHCI_TRB_ERROR_INVALID_SID); 1198 1199 if (XHCI_EPCTX_0_LSA_GET(ep->dwEpCtx0) == 0) { 1200 DPRINTF(("pci_xhci: find_stream; LSA bit not set")); 1201 return (XHCI_TRB_ERROR_INVALID_SID); 1202 } 1203 1204 /* only support primary stream */ 1205 if (streamid > devep->ep_MaxPStreams) 1206 return (XHCI_TRB_ERROR_STREAM_TYPE); 1207 1208 sctx = XHCI_GADDR(sc, ep->qwEpCtx2 & ~0xFUL) + streamid; 1209 if (!XHCI_SCTX_0_SCT_GET(sctx->qwSctx0)) 1210 return (XHCI_TRB_ERROR_STREAM_TYPE); 1211 1212 *osctx = sctx; 1213 1214 return (XHCI_TRB_ERROR_SUCCESS); 1215 } 1216 1217 1218 static uint32_t 1219 pci_xhci_cmd_set_tr(struct pci_xhci_softc *sc, uint32_t slot, 1220 struct xhci_trb *trb) 1221 { 1222 struct pci_xhci_dev_emu *dev; 1223 struct pci_xhci_dev_ep *devep; 1224 struct xhci_dev_ctx *dev_ctx; 1225 struct xhci_endp_ctx *ep_ctx; 1226 uint32_t cmderr, epid; 1227 uint32_t streamid; 1228 1229 cmderr = XHCI_TRB_ERROR_SUCCESS; 1230 1231 dev = XHCI_SLOTDEV_PTR(sc, slot); 1232 assert(dev != NULL); 1233 1234 DPRINTF(("pci_xhci set_tr: new-tr x%016lx, SCT %u DCS %u", 1235 (trb->qwTrb0 & ~0xF), (uint32_t)((trb->qwTrb0 >> 1) & 0x7), 1236 (uint32_t)(trb->qwTrb0 & 0x1))); 1237 DPRINTF((" stream-id %u, slot %u, epid %u, C %u", 1238 (trb->dwTrb2 >> 16) & 0xFFFF, 1239 XHCI_TRB_3_SLOT_GET(trb->dwTrb3), 1240 XHCI_TRB_3_EP_GET(trb->dwTrb3), trb->dwTrb3 & 0x1)); 1241 1242 epid = XHCI_TRB_3_EP_GET(trb->dwTrb3); 1243 if (epid < 1 || epid > 31) { 1244 DPRINTF(("pci_xhci: set_tr_deq: invalid epid %u", epid)); 1245 cmderr = XHCI_TRB_ERROR_TRB; 1246 goto done; 1247 } 1248 1249 dev_ctx = dev->dev_ctx; 1250 assert(dev_ctx != NULL); 1251 1252 ep_ctx = &dev_ctx->ctx_ep[epid]; 1253 devep = &dev->eps[epid]; 1254 1255 switch (XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0)) { 1256 case XHCI_ST_EPCTX_STOPPED: 1257 case XHCI_ST_EPCTX_ERROR: 1258 break; 1259 default: 1260 DPRINTF(("pci_xhci cmd set_tr invalid state %x", 1261 XHCI_EPCTX_0_EPSTATE_GET(ep_ctx->dwEpCtx0))); 1262 cmderr = XHCI_TRB_ERROR_CONTEXT_STATE; 1263 goto done; 1264 } 1265 1266 streamid = XHCI_TRB_2_STREAM_GET(trb->dwTrb2); 1267 if (devep->ep_MaxPStreams > 0) { 1268 struct xhci_stream_ctx *sctx; 1269 1270 sctx = NULL; 1271 cmderr = pci_xhci_find_stream(sc, ep_ctx, devep, streamid, 1272 &sctx); 1273 if (sctx != NULL) { 1274 assert(devep->ep_sctx != NULL); 1275 1276 devep->ep_sctx[streamid].qwSctx0 = trb->qwTrb0; 1277 devep->ep_sctx_trbs[streamid].ringaddr = 1278 trb->qwTrb0 & ~0xF; 1279 devep->ep_sctx_trbs[streamid].ccs = 1280 XHCI_EPCTX_2_DCS_GET(trb->qwTrb0); 1281 } 1282 } else { 1283 if (streamid != 0) { 1284 DPRINTF(("pci_xhci cmd set_tr streamid %x != 0", 1285 streamid)); 1286 } 1287 ep_ctx->qwEpCtx2 = trb->qwTrb0 & ~0xFUL; 1288 devep->ep_ringaddr = ep_ctx->qwEpCtx2 & ~0xFUL; 1289 devep->ep_ccs = trb->qwTrb0 & 0x1; 1290 devep->ep_tr = XHCI_GADDR(sc, devep->ep_ringaddr); 1291 1292 DPRINTF(("pci_xhci set_tr first TRB:")); 1293 pci_xhci_dump_trb(devep->ep_tr); 1294 } 1295 ep_ctx->dwEpCtx0 = (ep_ctx->dwEpCtx0 & ~0x7) | XHCI_ST_EPCTX_STOPPED; 1296 1297 done: 1298 return (cmderr); 1299 } 1300 1301 static uint32_t 1302 pci_xhci_cmd_eval_ctx(struct pci_xhci_softc *sc, uint32_t slot, 1303 struct xhci_trb *trb) 1304 { 1305 struct xhci_input_dev_ctx *input_ctx; 1306 struct xhci_slot_ctx *islot_ctx; 1307 struct xhci_dev_ctx *dev_ctx; 1308 struct xhci_endp_ctx *ep0_ctx; 1309 uint32_t cmderr; 1310 1311 input_ctx = XHCI_GADDR(sc, trb->qwTrb0 & ~0xFUL); 1312 islot_ctx = &input_ctx->ctx_slot; 1313 ep0_ctx = &input_ctx->ctx_ep[1]; 1314 1315 cmderr = XHCI_TRB_ERROR_SUCCESS; 1316 DPRINTF(("pci_xhci: eval ctx, input ctl: D 0x%08x A 0x%08x,", 1317 input_ctx->ctx_input.dwInCtx0, input_ctx->ctx_input.dwInCtx1)); 1318 DPRINTF((" slot %08x %08x %08x %08x", 1319 islot_ctx->dwSctx0, islot_ctx->dwSctx1, 1320 islot_ctx->dwSctx2, islot_ctx->dwSctx3)); 1321 DPRINTF((" ep0 %08x %08x %016lx %08x", 1322 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 1323 ep0_ctx->dwEpCtx4)); 1324 1325 /* this command expects drop-ctx=0 & add-ctx=slot+ep0 */ 1326 if ((input_ctx->ctx_input.dwInCtx0 != 0) || 1327 (input_ctx->ctx_input.dwInCtx1 & 0x03) == 0) { 1328 DPRINTF(("pci_xhci: eval ctx, input ctl invalid")); 1329 cmderr = XHCI_TRB_ERROR_TRB; 1330 goto done; 1331 } 1332 1333 /* assign address to slot; in this emulation, slot_id = address */ 1334 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1335 1336 DPRINTF(("pci_xhci: eval ctx, dev ctx")); 1337 DPRINTF((" slot %08x %08x %08x %08x", 1338 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1339 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1340 1341 if (input_ctx->ctx_input.dwInCtx1 & 0x01) { /* slot ctx */ 1342 /* set max exit latency */ 1343 dev_ctx->ctx_slot.dwSctx1 = FIELD_COPY( 1344 dev_ctx->ctx_slot.dwSctx1, input_ctx->ctx_slot.dwSctx1, 1345 0xFFFF, 0); 1346 1347 /* set interrupter target */ 1348 dev_ctx->ctx_slot.dwSctx2 = FIELD_COPY( 1349 dev_ctx->ctx_slot.dwSctx2, input_ctx->ctx_slot.dwSctx2, 1350 0x3FF, 22); 1351 } 1352 if (input_ctx->ctx_input.dwInCtx1 & 0x02) { /* control ctx */ 1353 /* set max packet size */ 1354 dev_ctx->ctx_ep[1].dwEpCtx1 = FIELD_COPY( 1355 dev_ctx->ctx_ep[1].dwEpCtx1, ep0_ctx->dwEpCtx1, 1356 0xFFFF, 16); 1357 1358 ep0_ctx = &dev_ctx->ctx_ep[1]; 1359 } 1360 1361 DPRINTF(("pci_xhci: eval ctx, output ctx")); 1362 DPRINTF((" slot %08x %08x %08x %08x", 1363 dev_ctx->ctx_slot.dwSctx0, dev_ctx->ctx_slot.dwSctx1, 1364 dev_ctx->ctx_slot.dwSctx2, dev_ctx->ctx_slot.dwSctx3)); 1365 DPRINTF((" ep0 %08x %08x %016lx %08x", 1366 ep0_ctx->dwEpCtx0, ep0_ctx->dwEpCtx1, ep0_ctx->qwEpCtx2, 1367 ep0_ctx->dwEpCtx4)); 1368 1369 done: 1370 return (cmderr); 1371 } 1372 1373 static int 1374 pci_xhci_complete_commands(struct pci_xhci_softc *sc) 1375 { 1376 struct xhci_trb evtrb; 1377 struct xhci_trb *trb; 1378 uint64_t crcr; 1379 uint32_t ccs; /* cycle state (XHCI 4.9.2) */ 1380 uint32_t type; 1381 uint32_t slot; 1382 uint32_t cmderr; 1383 int error; 1384 1385 error = 0; 1386 sc->opregs.crcr |= XHCI_CRCR_LO_CRR; 1387 1388 trb = sc->opregs.cr_p; 1389 ccs = sc->opregs.crcr & XHCI_CRCR_LO_RCS; 1390 crcr = sc->opregs.crcr & ~0xF; 1391 1392 while (1) { 1393 sc->opregs.cr_p = trb; 1394 1395 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); 1396 1397 if ((trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT) != 1398 (ccs & XHCI_TRB_3_CYCLE_BIT)) 1399 break; 1400 1401 DPRINTF(("pci_xhci: cmd type 0x%x, Trb0 x%016lx dwTrb2 x%08x" 1402 " dwTrb3 x%08x, TRB_CYCLE %u/ccs %u", 1403 type, trb->qwTrb0, trb->dwTrb2, trb->dwTrb3, 1404 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT, ccs)); 1405 1406 cmderr = XHCI_TRB_ERROR_SUCCESS; 1407 evtrb.dwTrb2 = 0; 1408 evtrb.dwTrb3 = (ccs & XHCI_TRB_3_CYCLE_BIT) | 1409 XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_CMD_COMPLETE); 1410 slot = 0; 1411 1412 switch (type) { 1413 case XHCI_TRB_TYPE_LINK: /* 0x06 */ 1414 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT) 1415 ccs ^= XHCI_CRCR_LO_RCS; 1416 break; 1417 1418 case XHCI_TRB_TYPE_ENABLE_SLOT: /* 0x09 */ 1419 cmderr = pci_xhci_cmd_enable_slot(sc, &slot); 1420 break; 1421 1422 case XHCI_TRB_TYPE_DISABLE_SLOT: /* 0x0A */ 1423 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1424 cmderr = pci_xhci_cmd_disable_slot(sc, slot); 1425 break; 1426 1427 case XHCI_TRB_TYPE_ADDRESS_DEVICE: /* 0x0B */ 1428 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1429 cmderr = pci_xhci_cmd_address_device(sc, slot, trb); 1430 break; 1431 1432 case XHCI_TRB_TYPE_CONFIGURE_EP: /* 0x0C */ 1433 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1434 cmderr = pci_xhci_cmd_config_ep(sc, slot, trb); 1435 break; 1436 1437 case XHCI_TRB_TYPE_EVALUATE_CTX: /* 0x0D */ 1438 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1439 cmderr = pci_xhci_cmd_eval_ctx(sc, slot, trb); 1440 break; 1441 1442 case XHCI_TRB_TYPE_RESET_EP: /* 0x0E */ 1443 DPRINTF(("Reset Endpoint on slot %d", slot)); 1444 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1445 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb); 1446 break; 1447 1448 case XHCI_TRB_TYPE_STOP_EP: /* 0x0F */ 1449 DPRINTF(("Stop Endpoint on slot %d", slot)); 1450 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1451 cmderr = pci_xhci_cmd_reset_ep(sc, slot, trb); 1452 break; 1453 1454 case XHCI_TRB_TYPE_SET_TR_DEQUEUE: /* 0x10 */ 1455 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1456 cmderr = pci_xhci_cmd_set_tr(sc, slot, trb); 1457 break; 1458 1459 case XHCI_TRB_TYPE_RESET_DEVICE: /* 0x11 */ 1460 slot = XHCI_TRB_3_SLOT_GET(trb->dwTrb3); 1461 cmderr = pci_xhci_cmd_reset_device(sc, slot); 1462 break; 1463 1464 case XHCI_TRB_TYPE_FORCE_EVENT: /* 0x12 */ 1465 /* TODO: */ 1466 break; 1467 1468 case XHCI_TRB_TYPE_NEGOTIATE_BW: /* 0x13 */ 1469 break; 1470 1471 case XHCI_TRB_TYPE_SET_LATENCY_TOL: /* 0x14 */ 1472 break; 1473 1474 case XHCI_TRB_TYPE_GET_PORT_BW: /* 0x15 */ 1475 break; 1476 1477 case XHCI_TRB_TYPE_FORCE_HEADER: /* 0x16 */ 1478 break; 1479 1480 case XHCI_TRB_TYPE_NOOP_CMD: /* 0x17 */ 1481 break; 1482 1483 default: 1484 DPRINTF(("pci_xhci: unsupported cmd %x", type)); 1485 break; 1486 } 1487 1488 if (type != XHCI_TRB_TYPE_LINK) { 1489 /* 1490 * insert command completion event and assert intr 1491 */ 1492 evtrb.qwTrb0 = crcr; 1493 evtrb.dwTrb2 |= XHCI_TRB_2_ERROR_SET(cmderr); 1494 evtrb.dwTrb3 |= XHCI_TRB_3_SLOT_SET(slot); 1495 DPRINTF(("pci_xhci: command 0x%x result: 0x%x", 1496 type, cmderr)); 1497 pci_xhci_insert_event(sc, &evtrb, 1); 1498 } 1499 1500 trb = pci_xhci_trb_next(sc, trb, &crcr); 1501 } 1502 1503 sc->opregs.crcr = crcr | (sc->opregs.crcr & XHCI_CRCR_LO_CA) | ccs; 1504 sc->opregs.crcr &= ~XHCI_CRCR_LO_CRR; 1505 return (error); 1506 } 1507 1508 static void 1509 pci_xhci_dump_trb(struct xhci_trb *trb) 1510 { 1511 static const char *trbtypes[] = { 1512 "RESERVED", 1513 "NORMAL", 1514 "SETUP_STAGE", 1515 "DATA_STAGE", 1516 "STATUS_STAGE", 1517 "ISOCH", 1518 "LINK", 1519 "EVENT_DATA", 1520 "NOOP", 1521 "ENABLE_SLOT", 1522 "DISABLE_SLOT", 1523 "ADDRESS_DEVICE", 1524 "CONFIGURE_EP", 1525 "EVALUATE_CTX", 1526 "RESET_EP", 1527 "STOP_EP", 1528 "SET_TR_DEQUEUE", 1529 "RESET_DEVICE", 1530 "FORCE_EVENT", 1531 "NEGOTIATE_BW", 1532 "SET_LATENCY_TOL", 1533 "GET_PORT_BW", 1534 "FORCE_HEADER", 1535 "NOOP_CMD" 1536 }; 1537 uint32_t type; 1538 1539 type = XHCI_TRB_3_TYPE_GET(trb->dwTrb3); 1540 DPRINTF(("pci_xhci: trb[@%p] type x%02x %s 0:x%016lx 2:x%08x 3:x%08x", 1541 trb, type, 1542 type <= XHCI_TRB_TYPE_NOOP_CMD ? trbtypes[type] : "INVALID", 1543 trb->qwTrb0, trb->dwTrb2, trb->dwTrb3)); 1544 } 1545 1546 static int 1547 pci_xhci_xfer_complete(struct pci_xhci_softc *sc, struct usb_data_xfer *xfer, 1548 uint32_t slot, uint32_t epid, int *do_intr) 1549 { 1550 struct pci_xhci_dev_emu *dev; 1551 struct pci_xhci_dev_ep *devep; 1552 struct xhci_dev_ctx *dev_ctx; 1553 struct xhci_endp_ctx *ep_ctx; 1554 struct xhci_trb *trb; 1555 struct xhci_trb evtrb; 1556 uint32_t trbflags; 1557 uint32_t edtla; 1558 int i, err; 1559 1560 dev = XHCI_SLOTDEV_PTR(sc, slot); 1561 devep = &dev->eps[epid]; 1562 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1563 1564 assert(dev_ctx != NULL); 1565 1566 ep_ctx = &dev_ctx->ctx_ep[epid]; 1567 1568 err = XHCI_TRB_ERROR_SUCCESS; 1569 *do_intr = 0; 1570 edtla = 0; 1571 1572 /* go through list of TRBs and insert event(s) */ 1573 for (i = xfer->head; xfer->ndata > 0; ) { 1574 evtrb.qwTrb0 = (uint64_t)xfer->data[i].hci_data; 1575 trb = XHCI_GADDR(sc, evtrb.qwTrb0); 1576 trbflags = trb->dwTrb3; 1577 1578 DPRINTF(("pci_xhci: xfer[%d] done?%u:%d trb %x %016lx %x " 1579 "(err %d) IOC?%d", 1580 i, xfer->data[i].processed, xfer->data[i].blen, 1581 XHCI_TRB_3_TYPE_GET(trbflags), evtrb.qwTrb0, 1582 trbflags, err, 1583 trb->dwTrb3 & XHCI_TRB_3_IOC_BIT ? 1 : 0)); 1584 1585 if (!xfer->data[i].processed) { 1586 xfer->head = i; 1587 break; 1588 } 1589 1590 xfer->ndata--; 1591 edtla += xfer->data[i].bdone; 1592 1593 trb->dwTrb3 = (trb->dwTrb3 & ~0x1) | (xfer->data[i].ccs); 1594 1595 pci_xhci_update_ep_ring(sc, dev, devep, ep_ctx, 1596 xfer->data[i].streamid, xfer->data[i].trbnext, 1597 xfer->data[i].ccs); 1598 1599 /* Only interrupt if IOC or short packet */ 1600 if (!(trb->dwTrb3 & XHCI_TRB_3_IOC_BIT) && 1601 !((err == XHCI_TRB_ERROR_SHORT_PKT) && 1602 (trb->dwTrb3 & XHCI_TRB_3_ISP_BIT))) { 1603 1604 i = (i + 1) % USB_MAX_XFER_BLOCKS; 1605 continue; 1606 } 1607 1608 evtrb.dwTrb2 = XHCI_TRB_2_ERROR_SET(err) | 1609 XHCI_TRB_2_REM_SET(xfer->data[i].blen); 1610 1611 evtrb.dwTrb3 = XHCI_TRB_3_TYPE_SET(XHCI_TRB_EVENT_TRANSFER) | 1612 XHCI_TRB_3_SLOT_SET(slot) | XHCI_TRB_3_EP_SET(epid); 1613 1614 if (XHCI_TRB_3_TYPE_GET(trbflags) == XHCI_TRB_TYPE_EVENT_DATA) { 1615 DPRINTF(("pci_xhci EVENT_DATA edtla %u", edtla)); 1616 evtrb.qwTrb0 = trb->qwTrb0; 1617 evtrb.dwTrb2 = (edtla & 0xFFFFF) | 1618 XHCI_TRB_2_ERROR_SET(err); 1619 evtrb.dwTrb3 |= XHCI_TRB_3_ED_BIT; 1620 edtla = 0; 1621 } 1622 1623 *do_intr = 1; 1624 1625 err = pci_xhci_insert_event(sc, &evtrb, 0); 1626 if (err != XHCI_TRB_ERROR_SUCCESS) { 1627 break; 1628 } 1629 1630 i = (i + 1) % USB_MAX_XFER_BLOCKS; 1631 } 1632 1633 return (err); 1634 } 1635 1636 static void 1637 pci_xhci_update_ep_ring(struct pci_xhci_softc *sc, struct pci_xhci_dev_emu *dev, 1638 struct pci_xhci_dev_ep *devep, struct xhci_endp_ctx *ep_ctx, 1639 uint32_t streamid, uint64_t ringaddr, int ccs) 1640 { 1641 1642 if (devep->ep_MaxPStreams != 0) { 1643 devep->ep_sctx[streamid].qwSctx0 = (ringaddr & ~0xFUL) | 1644 (ccs & 0x1); 1645 1646 devep->ep_sctx_trbs[streamid].ringaddr = ringaddr & ~0xFUL; 1647 devep->ep_sctx_trbs[streamid].ccs = ccs & 0x1; 1648 ep_ctx->qwEpCtx2 = (ep_ctx->qwEpCtx2 & ~0x1) | (ccs & 0x1); 1649 1650 DPRINTF(("xhci update ep-ring stream %d, addr %lx", 1651 streamid, devep->ep_sctx[streamid].qwSctx0)); 1652 } else { 1653 devep->ep_ringaddr = ringaddr & ~0xFUL; 1654 devep->ep_ccs = ccs & 0x1; 1655 devep->ep_tr = XHCI_GADDR(sc, ringaddr & ~0xFUL); 1656 ep_ctx->qwEpCtx2 = (ringaddr & ~0xFUL) | (ccs & 0x1); 1657 1658 DPRINTF(("xhci update ep-ring, addr %lx", 1659 (devep->ep_ringaddr | devep->ep_ccs))); 1660 } 1661 } 1662 1663 /* 1664 * Outstanding transfer still in progress (device NAK'd earlier) so retry 1665 * the transfer again to see if it succeeds. 1666 */ 1667 static int 1668 pci_xhci_try_usb_xfer(struct pci_xhci_softc *sc, 1669 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, 1670 struct xhci_endp_ctx *ep_ctx, uint32_t slot, uint32_t epid) 1671 { 1672 struct usb_data_xfer *xfer; 1673 int err; 1674 int do_intr; 1675 1676 ep_ctx->dwEpCtx0 = FIELD_REPLACE( 1677 ep_ctx->dwEpCtx0, XHCI_ST_EPCTX_RUNNING, 0x7, 0); 1678 1679 err = 0; 1680 do_intr = 0; 1681 1682 xfer = devep->ep_xfer; 1683 #ifdef __FreeBSD__ 1684 USB_DATA_XFER_LOCK(xfer); 1685 #else 1686 /* 1687 * At least one caller needs to hold this lock across the call to this 1688 * function and other code. To avoid deadlock from a recursive mutex 1689 * enter, we ensure that all callers hold this lock. 1690 */ 1691 assert(USB_DATA_XFER_LOCK_HELD(xfer)); 1692 #endif 1693 1694 /* outstanding requests queued up */ 1695 if (dev->dev_ue->ue_data != NULL) { 1696 err = dev->dev_ue->ue_data(dev->dev_sc, xfer, 1697 epid & 0x1 ? USB_XFER_IN : USB_XFER_OUT, epid/2); 1698 if (err == USB_ERR_CANCELLED) { 1699 if (USB_DATA_GET_ERRCODE(&xfer->data[xfer->head]) == 1700 USB_NAK) 1701 err = XHCI_TRB_ERROR_SUCCESS; 1702 } else { 1703 err = pci_xhci_xfer_complete(sc, xfer, slot, epid, 1704 &do_intr); 1705 if (err == XHCI_TRB_ERROR_SUCCESS && do_intr) { 1706 pci_xhci_assert_interrupt(sc); 1707 } 1708 1709 1710 /* XXX should not do it if error? */ 1711 USB_DATA_XFER_RESET(xfer); 1712 } 1713 } 1714 1715 #ifdef __FreeBSD__ 1716 USB_DATA_XFER_UNLOCK(xfer); 1717 #endif 1718 1719 return (err); 1720 } 1721 1722 1723 static int 1724 pci_xhci_handle_transfer(struct pci_xhci_softc *sc, 1725 struct pci_xhci_dev_emu *dev, struct pci_xhci_dev_ep *devep, 1726 struct xhci_endp_ctx *ep_ctx, struct xhci_trb *trb, uint32_t slot, 1727 uint32_t epid, uint64_t addr, uint32_t ccs, uint32_t streamid) 1728 { 1729 struct xhci_trb *setup_trb; 1730 struct usb_data_xfer *xfer; 1731 struct usb_data_xfer_block *xfer_block; 1732 uint64_t val; 1733 uint32_t trbflags; 1734 int do_intr, err; 1735 int do_retry; 1736 1737 ep_ctx->dwEpCtx0 = FIELD_REPLACE(ep_ctx->dwEpCtx0, 1738 XHCI_ST_EPCTX_RUNNING, 0x7, 0); 1739 1740 xfer = devep->ep_xfer; 1741 USB_DATA_XFER_LOCK(xfer); 1742 1743 DPRINTF(("pci_xhci handle_transfer slot %u", slot)); 1744 1745 retry: 1746 err = 0; 1747 do_retry = 0; 1748 do_intr = 0; 1749 setup_trb = NULL; 1750 1751 while (1) { 1752 pci_xhci_dump_trb(trb); 1753 1754 trbflags = trb->dwTrb3; 1755 1756 if (XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK && 1757 (trbflags & XHCI_TRB_3_CYCLE_BIT) != 1758 (ccs & XHCI_TRB_3_CYCLE_BIT)) { 1759 DPRINTF(("Cycle-bit changed trbflags %x, ccs %x", 1760 trbflags & XHCI_TRB_3_CYCLE_BIT, ccs)); 1761 break; 1762 } 1763 1764 xfer_block = NULL; 1765 1766 switch (XHCI_TRB_3_TYPE_GET(trbflags)) { 1767 case XHCI_TRB_TYPE_LINK: 1768 if (trb->dwTrb3 & XHCI_TRB_3_TC_BIT) 1769 ccs ^= 0x1; 1770 1771 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1772 (void *)addr, ccs); 1773 xfer_block->processed = 1; 1774 break; 1775 1776 case XHCI_TRB_TYPE_SETUP_STAGE: 1777 if ((trbflags & XHCI_TRB_3_IDT_BIT) == 0 || 1778 XHCI_TRB_2_BYTES_GET(trb->dwTrb2) != 8) { 1779 DPRINTF(("pci_xhci: invalid setup trb")); 1780 err = XHCI_TRB_ERROR_TRB; 1781 goto errout; 1782 } 1783 setup_trb = trb; 1784 1785 val = trb->qwTrb0; 1786 if (!xfer->ureq) 1787 xfer->ureq = malloc( 1788 sizeof(struct usb_device_request)); 1789 memcpy(xfer->ureq, &val, 1790 sizeof(struct usb_device_request)); 1791 1792 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1793 (void *)addr, ccs); 1794 xfer_block->processed = 1; 1795 break; 1796 1797 case XHCI_TRB_TYPE_NORMAL: 1798 case XHCI_TRB_TYPE_ISOCH: 1799 if (setup_trb != NULL) { 1800 DPRINTF(("pci_xhci: trb not supposed to be in " 1801 "ctl scope")); 1802 err = XHCI_TRB_ERROR_TRB; 1803 goto errout; 1804 } 1805 /* fall through */ 1806 1807 case XHCI_TRB_TYPE_DATA_STAGE: 1808 xfer_block = usb_data_xfer_append(xfer, 1809 (void *)(trbflags & XHCI_TRB_3_IDT_BIT ? 1810 &trb->qwTrb0 : XHCI_GADDR(sc, trb->qwTrb0)), 1811 trb->dwTrb2 & 0x1FFFF, (void *)addr, ccs); 1812 break; 1813 1814 case XHCI_TRB_TYPE_STATUS_STAGE: 1815 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1816 (void *)addr, ccs); 1817 break; 1818 1819 case XHCI_TRB_TYPE_NOOP: 1820 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1821 (void *)addr, ccs); 1822 xfer_block->processed = 1; 1823 break; 1824 1825 case XHCI_TRB_TYPE_EVENT_DATA: 1826 xfer_block = usb_data_xfer_append(xfer, NULL, 0, 1827 (void *)addr, ccs); 1828 if ((epid > 1) && (trbflags & XHCI_TRB_3_IOC_BIT)) { 1829 xfer_block->processed = 1; 1830 } 1831 break; 1832 1833 default: 1834 DPRINTF(("pci_xhci: handle xfer unexpected trb type " 1835 "0x%x", 1836 XHCI_TRB_3_TYPE_GET(trbflags))); 1837 err = XHCI_TRB_ERROR_TRB; 1838 goto errout; 1839 } 1840 1841 trb = pci_xhci_trb_next(sc, trb, &addr); 1842 1843 DPRINTF(("pci_xhci: next trb: 0x%lx", (uint64_t)trb)); 1844 1845 if (xfer_block) { 1846 xfer_block->trbnext = addr; 1847 xfer_block->streamid = streamid; 1848 } 1849 1850 if (!setup_trb && !(trbflags & XHCI_TRB_3_CHAIN_BIT) && 1851 XHCI_TRB_3_TYPE_GET(trbflags) != XHCI_TRB_TYPE_LINK) { 1852 break; 1853 } 1854 1855 /* handle current batch that requires interrupt on complete */ 1856 if (trbflags & XHCI_TRB_3_IOC_BIT) { 1857 DPRINTF(("pci_xhci: trb IOC bit set")); 1858 if (epid == 1) 1859 do_retry = 1; 1860 break; 1861 } 1862 } 1863 1864 DPRINTF(("pci_xhci[%d]: xfer->ndata %u", __LINE__, xfer->ndata)); 1865 1866 if (xfer->ndata <= 0) 1867 goto errout; 1868 1869 if (epid == 1) { 1870 err = USB_ERR_NOT_STARTED; 1871 if (dev->dev_ue->ue_request != NULL) 1872 err = dev->dev_ue->ue_request(dev->dev_sc, xfer); 1873 setup_trb = NULL; 1874 } else { 1875 /* handle data transfer */ 1876 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid); 1877 err = XHCI_TRB_ERROR_SUCCESS; 1878 goto errout; 1879 } 1880 1881 err = USB_TO_XHCI_ERR(err); 1882 if ((err == XHCI_TRB_ERROR_SUCCESS) || 1883 (err == XHCI_TRB_ERROR_STALL) || 1884 (err == XHCI_TRB_ERROR_SHORT_PKT)) { 1885 err = pci_xhci_xfer_complete(sc, xfer, slot, epid, &do_intr); 1886 if (err != XHCI_TRB_ERROR_SUCCESS) 1887 do_retry = 0; 1888 } 1889 1890 errout: 1891 if (err == XHCI_TRB_ERROR_EV_RING_FULL) 1892 DPRINTF(("pci_xhci[%d]: event ring full", __LINE__)); 1893 1894 if (!do_retry) 1895 USB_DATA_XFER_UNLOCK(xfer); 1896 1897 if (do_intr) 1898 pci_xhci_assert_interrupt(sc); 1899 1900 if (do_retry) { 1901 USB_DATA_XFER_RESET(xfer); 1902 DPRINTF(("pci_xhci[%d]: retry:continuing with next TRBs", 1903 __LINE__)); 1904 goto retry; 1905 } 1906 1907 if (epid == 1) 1908 USB_DATA_XFER_RESET(xfer); 1909 1910 return (err); 1911 } 1912 1913 static void 1914 pci_xhci_device_doorbell(struct pci_xhci_softc *sc, uint32_t slot, 1915 uint32_t epid, uint32_t streamid) 1916 { 1917 struct pci_xhci_dev_emu *dev; 1918 struct pci_xhci_dev_ep *devep; 1919 struct xhci_dev_ctx *dev_ctx; 1920 struct xhci_endp_ctx *ep_ctx; 1921 struct pci_xhci_trb_ring *sctx_tr; 1922 struct xhci_trb *trb; 1923 uint64_t ringaddr; 1924 uint32_t ccs; 1925 1926 DPRINTF(("pci_xhci doorbell slot %u epid %u stream %u", 1927 slot, epid, streamid)); 1928 1929 if (slot == 0 || slot > XHCI_MAX_SLOTS) { 1930 DPRINTF(("pci_xhci: invalid doorbell slot %u", slot)); 1931 return; 1932 } 1933 1934 if (epid == 0 || epid >= XHCI_MAX_ENDPOINTS) { 1935 DPRINTF(("pci_xhci: invalid endpoint %u", epid)); 1936 return; 1937 } 1938 1939 dev = XHCI_SLOTDEV_PTR(sc, slot); 1940 devep = &dev->eps[epid]; 1941 dev_ctx = pci_xhci_get_dev_ctx(sc, slot); 1942 if (!dev_ctx) { 1943 return; 1944 } 1945 ep_ctx = &dev_ctx->ctx_ep[epid]; 1946 1947 sctx_tr = NULL; 1948 1949 DPRINTF(("pci_xhci: device doorbell ep[%u] %08x %08x %016lx %08x", 1950 epid, ep_ctx->dwEpCtx0, ep_ctx->dwEpCtx1, ep_ctx->qwEpCtx2, 1951 ep_ctx->dwEpCtx4)); 1952 1953 if (ep_ctx->qwEpCtx2 == 0) 1954 return; 1955 1956 /* handle pending transfers */ 1957 if (devep->ep_xfer->ndata > 0) { 1958 #ifndef __FreeBSD__ 1959 USB_DATA_XFER_LOCK(devep->ep_xfer); 1960 #endif 1961 pci_xhci_try_usb_xfer(sc, dev, devep, ep_ctx, slot, epid); 1962 #ifndef __FreeBSD__ 1963 USB_DATA_XFER_UNLOCK(devep->ep_xfer); 1964 #endif 1965 return; 1966 } 1967 1968 /* get next trb work item */ 1969 if (devep->ep_MaxPStreams != 0) { 1970 struct xhci_stream_ctx *sctx; 1971 1972 /* 1973 * Stream IDs of 0, 65535 (any stream), and 65534 1974 * (prime) are invalid. 1975 */ 1976 if (streamid == 0 || streamid == 65534 || streamid == 65535) { 1977 DPRINTF(("pci_xhci: invalid stream %u", streamid)); 1978 return; 1979 } 1980 1981 sctx = NULL; 1982 pci_xhci_find_stream(sc, ep_ctx, devep, streamid, &sctx); 1983 if (sctx == NULL) { 1984 DPRINTF(("pci_xhci: invalid stream %u", streamid)); 1985 return; 1986 } 1987 sctx_tr = &devep->ep_sctx_trbs[streamid]; 1988 ringaddr = sctx_tr->ringaddr; 1989 ccs = sctx_tr->ccs; 1990 trb = XHCI_GADDR(sc, sctx_tr->ringaddr & ~0xFUL); 1991 DPRINTF(("doorbell, stream %u, ccs %lx, trb ccs %x", 1992 streamid, ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT, 1993 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT)); 1994 } else { 1995 if (streamid != 0) { 1996 DPRINTF(("pci_xhci: invalid stream %u", streamid)); 1997 return; 1998 } 1999 ringaddr = devep->ep_ringaddr; 2000 ccs = devep->ep_ccs; 2001 trb = devep->ep_tr; 2002 DPRINTF(("doorbell, ccs %lx, trb ccs %x", 2003 ep_ctx->qwEpCtx2 & XHCI_TRB_3_CYCLE_BIT, 2004 trb->dwTrb3 & XHCI_TRB_3_CYCLE_BIT)); 2005 } 2006 2007 if (XHCI_TRB_3_TYPE_GET(trb->dwTrb3) == 0) { 2008 DPRINTF(("pci_xhci: ring %lx trb[%lx] EP %u is RESERVED?", 2009 ep_ctx->qwEpCtx2, devep->ep_ringaddr, epid)); 2010 return; 2011 } 2012 2013 pci_xhci_handle_transfer(sc, dev, devep, ep_ctx, trb, slot, epid, 2014 ringaddr, ccs, streamid); 2015 } 2016 2017 static void 2018 pci_xhci_dbregs_write(struct pci_xhci_softc *sc, uint64_t offset, 2019 uint64_t value) 2020 { 2021 2022 offset = (offset - sc->dboff) / sizeof(uint32_t); 2023 2024 DPRINTF(("pci_xhci: doorbell write offset 0x%lx: 0x%lx", 2025 offset, value)); 2026 2027 if (XHCI_HALTED(sc)) { 2028 DPRINTF(("pci_xhci: controller halted")); 2029 return; 2030 } 2031 2032 if (offset == 0) 2033 pci_xhci_complete_commands(sc); 2034 else if (sc->portregs != NULL) 2035 pci_xhci_device_doorbell(sc, offset, 2036 XHCI_DB_TARGET_GET(value), XHCI_DB_SID_GET(value)); 2037 } 2038 2039 static void 2040 pci_xhci_rtsregs_write(struct pci_xhci_softc *sc, uint64_t offset, 2041 uint64_t value) 2042 { 2043 struct pci_xhci_rtsregs *rts; 2044 2045 offset -= sc->rtsoff; 2046 2047 if (offset == 0) { 2048 DPRINTF(("pci_xhci attempted write to MFINDEX")); 2049 return; 2050 } 2051 2052 DPRINTF(("pci_xhci: runtime regs write offset 0x%lx: 0x%lx", 2053 offset, value)); 2054 2055 offset -= 0x20; /* start of intrreg */ 2056 2057 rts = &sc->rtsregs; 2058 2059 switch (offset) { 2060 case 0x00: 2061 if (value & XHCI_IMAN_INTR_PEND) 2062 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND; 2063 rts->intrreg.iman = (value & XHCI_IMAN_INTR_ENA) | 2064 (rts->intrreg.iman & XHCI_IMAN_INTR_PEND); 2065 2066 if (!(value & XHCI_IMAN_INTR_ENA)) 2067 pci_xhci_deassert_interrupt(sc); 2068 2069 break; 2070 2071 case 0x04: 2072 rts->intrreg.imod = value; 2073 break; 2074 2075 case 0x08: 2076 rts->intrreg.erstsz = value & 0xFFFF; 2077 break; 2078 2079 case 0x10: 2080 /* ERSTBA low bits */ 2081 rts->intrreg.erstba = MASK_64_HI(sc->rtsregs.intrreg.erstba) | 2082 (value & ~0x3F); 2083 break; 2084 2085 case 0x14: 2086 /* ERSTBA high bits */ 2087 rts->intrreg.erstba = (value << 32) | 2088 MASK_64_LO(sc->rtsregs.intrreg.erstba); 2089 2090 rts->erstba_p = XHCI_GADDR(sc, 2091 sc->rtsregs.intrreg.erstba & ~0x3FUL); 2092 2093 rts->erst_p = XHCI_GADDR(sc, 2094 sc->rtsregs.erstba_p->qwEvrsTablePtr & ~0x3FUL); 2095 2096 rts->er_enq_idx = 0; 2097 rts->er_events_cnt = 0; 2098 2099 DPRINTF(("pci_xhci: wr erstba erst (%p) ptr 0x%lx, sz %u", 2100 rts->erstba_p, 2101 rts->erstba_p->qwEvrsTablePtr, 2102 rts->erstba_p->dwEvrsTableSize)); 2103 break; 2104 2105 case 0x18: 2106 /* ERDP low bits */ 2107 rts->intrreg.erdp = 2108 MASK_64_HI(sc->rtsregs.intrreg.erdp) | 2109 (rts->intrreg.erdp & XHCI_ERDP_LO_BUSY) | 2110 (value & ~0xF); 2111 if (value & XHCI_ERDP_LO_BUSY) { 2112 rts->intrreg.erdp &= ~XHCI_ERDP_LO_BUSY; 2113 rts->intrreg.iman &= ~XHCI_IMAN_INTR_PEND; 2114 } 2115 2116 rts->er_deq_seg = XHCI_ERDP_LO_SINDEX(value); 2117 2118 break; 2119 2120 case 0x1C: 2121 /* ERDP high bits */ 2122 rts->intrreg.erdp = (value << 32) | 2123 MASK_64_LO(sc->rtsregs.intrreg.erdp); 2124 2125 if (rts->er_events_cnt > 0) { 2126 uint64_t erdp; 2127 uint32_t erdp_i; 2128 2129 erdp = rts->intrreg.erdp & ~0xF; 2130 erdp_i = (erdp - rts->erstba_p->qwEvrsTablePtr) / 2131 sizeof(struct xhci_trb); 2132 2133 if (erdp_i <= rts->er_enq_idx) 2134 rts->er_events_cnt = rts->er_enq_idx - erdp_i; 2135 else 2136 rts->er_events_cnt = 2137 rts->erstba_p->dwEvrsTableSize - 2138 (erdp_i - rts->er_enq_idx); 2139 2140 DPRINTF(("pci_xhci: erdp 0x%lx, events cnt %u", 2141 erdp, rts->er_events_cnt)); 2142 } 2143 2144 break; 2145 2146 default: 2147 DPRINTF(("pci_xhci attempted write to RTS offset 0x%lx", 2148 offset)); 2149 break; 2150 } 2151 } 2152 2153 static uint64_t 2154 pci_xhci_portregs_read(struct pci_xhci_softc *sc, uint64_t offset) 2155 { 2156 int port; 2157 uint32_t *p; 2158 2159 if (sc->portregs == NULL) 2160 return (0); 2161 2162 port = (offset - 0x3F0) / 0x10; 2163 2164 if (port > XHCI_MAX_DEVS) { 2165 DPRINTF(("pci_xhci: portregs_read port %d >= XHCI_MAX_DEVS", 2166 port)); 2167 2168 /* return default value for unused port */ 2169 return (XHCI_PS_SPEED_SET(3)); 2170 } 2171 2172 offset = (offset - 0x3F0) % 0x10; 2173 2174 p = &sc->portregs[port].portsc; 2175 p += offset / sizeof(uint32_t); 2176 2177 DPRINTF(("pci_xhci: portregs read offset 0x%lx port %u -> 0x%x", 2178 offset, port, *p)); 2179 2180 return (*p); 2181 } 2182 2183 static void 2184 pci_xhci_hostop_write(struct pci_xhci_softc *sc, uint64_t offset, 2185 uint64_t value) 2186 { 2187 offset -= XHCI_CAPLEN; 2188 2189 if (offset < 0x400) 2190 DPRINTF(("pci_xhci: hostop write offset 0x%lx: 0x%lx", 2191 offset, value)); 2192 2193 switch (offset) { 2194 case XHCI_USBCMD: 2195 sc->opregs.usbcmd = pci_xhci_usbcmd_write(sc, value & 0x3F0F); 2196 break; 2197 2198 case XHCI_USBSTS: 2199 /* clear bits on write */ 2200 sc->opregs.usbsts &= ~(value & 2201 (XHCI_STS_HSE|XHCI_STS_EINT|XHCI_STS_PCD|XHCI_STS_SSS| 2202 XHCI_STS_RSS|XHCI_STS_SRE|XHCI_STS_CNR)); 2203 break; 2204 2205 case XHCI_PAGESIZE: 2206 /* read only */ 2207 break; 2208 2209 case XHCI_DNCTRL: 2210 sc->opregs.dnctrl = value & 0xFFFF; 2211 break; 2212 2213 case XHCI_CRCR_LO: 2214 if (sc->opregs.crcr & XHCI_CRCR_LO_CRR) { 2215 sc->opregs.crcr &= ~(XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA); 2216 sc->opregs.crcr |= value & 2217 (XHCI_CRCR_LO_CS|XHCI_CRCR_LO_CA); 2218 } else { 2219 sc->opregs.crcr = MASK_64_HI(sc->opregs.crcr) | 2220 (value & (0xFFFFFFC0 | XHCI_CRCR_LO_RCS)); 2221 } 2222 break; 2223 2224 case XHCI_CRCR_HI: 2225 if (!(sc->opregs.crcr & XHCI_CRCR_LO_CRR)) { 2226 sc->opregs.crcr = MASK_64_LO(sc->opregs.crcr) | 2227 (value << 32); 2228 2229 sc->opregs.cr_p = XHCI_GADDR(sc, 2230 sc->opregs.crcr & ~0xF); 2231 } 2232 2233 if (sc->opregs.crcr & XHCI_CRCR_LO_CS) { 2234 /* Stop operation of Command Ring */ 2235 } 2236 2237 if (sc->opregs.crcr & XHCI_CRCR_LO_CA) { 2238 /* Abort command */ 2239 } 2240 2241 break; 2242 2243 case XHCI_DCBAAP_LO: 2244 sc->opregs.dcbaap = MASK_64_HI(sc->opregs.dcbaap) | 2245 (value & 0xFFFFFFC0); 2246 break; 2247 2248 case XHCI_DCBAAP_HI: 2249 sc->opregs.dcbaap = MASK_64_LO(sc->opregs.dcbaap) | 2250 (value << 32); 2251 sc->opregs.dcbaa_p = XHCI_GADDR(sc, sc->opregs.dcbaap & ~0x3FUL); 2252 2253 DPRINTF(("pci_xhci: opregs dcbaap = 0x%lx (vaddr 0x%lx)", 2254 sc->opregs.dcbaap, (uint64_t)sc->opregs.dcbaa_p)); 2255 break; 2256 2257 case XHCI_CONFIG: 2258 sc->opregs.config = value & 0x03FF; 2259 break; 2260 2261 default: 2262 if (offset >= 0x400) 2263 pci_xhci_portregs_write(sc, offset, value); 2264 2265 break; 2266 } 2267 } 2268 2269 2270 static void 2271 pci_xhci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, 2272 int baridx, uint64_t offset, int size, uint64_t value) 2273 { 2274 struct pci_xhci_softc *sc; 2275 2276 sc = pi->pi_arg; 2277 2278 assert(baridx == 0); 2279 2280 2281 pthread_mutex_lock(&sc->mtx); 2282 if (offset < XHCI_CAPLEN) /* read only registers */ 2283 WPRINTF(("pci_xhci: write RO-CAPs offset %ld", offset)); 2284 else if (offset < sc->dboff) 2285 pci_xhci_hostop_write(sc, offset, value); 2286 else if (offset < sc->rtsoff) 2287 pci_xhci_dbregs_write(sc, offset, value); 2288 else if (offset < sc->regsend) 2289 pci_xhci_rtsregs_write(sc, offset, value); 2290 else 2291 WPRINTF(("pci_xhci: write invalid offset %ld", offset)); 2292 2293 pthread_mutex_unlock(&sc->mtx); 2294 } 2295 2296 static uint64_t 2297 pci_xhci_hostcap_read(struct pci_xhci_softc *sc, uint64_t offset) 2298 { 2299 uint64_t value; 2300 2301 switch (offset) { 2302 case XHCI_CAPLENGTH: /* 0x00 */ 2303 value = sc->caplength; 2304 break; 2305 2306 case XHCI_HCSPARAMS1: /* 0x04 */ 2307 value = sc->hcsparams1; 2308 break; 2309 2310 case XHCI_HCSPARAMS2: /* 0x08 */ 2311 value = sc->hcsparams2; 2312 break; 2313 2314 case XHCI_HCSPARAMS3: /* 0x0C */ 2315 value = sc->hcsparams3; 2316 break; 2317 2318 case XHCI_HCSPARAMS0: /* 0x10 */ 2319 value = sc->hccparams1; 2320 break; 2321 2322 case XHCI_DBOFF: /* 0x14 */ 2323 value = sc->dboff; 2324 break; 2325 2326 case XHCI_RTSOFF: /* 0x18 */ 2327 value = sc->rtsoff; 2328 break; 2329 2330 case XHCI_HCCPRAMS2: /* 0x1C */ 2331 value = sc->hccparams2; 2332 break; 2333 2334 default: 2335 value = 0; 2336 break; 2337 } 2338 2339 DPRINTF(("pci_xhci: hostcap read offset 0x%lx -> 0x%lx", 2340 offset, value)); 2341 2342 return (value); 2343 } 2344 2345 static uint64_t 2346 pci_xhci_hostop_read(struct pci_xhci_softc *sc, uint64_t offset) 2347 { 2348 uint64_t value; 2349 2350 offset = (offset - XHCI_CAPLEN); 2351 2352 switch (offset) { 2353 case XHCI_USBCMD: /* 0x00 */ 2354 value = sc->opregs.usbcmd; 2355 break; 2356 2357 case XHCI_USBSTS: /* 0x04 */ 2358 value = sc->opregs.usbsts; 2359 break; 2360 2361 case XHCI_PAGESIZE: /* 0x08 */ 2362 value = sc->opregs.pgsz; 2363 break; 2364 2365 case XHCI_DNCTRL: /* 0x14 */ 2366 value = sc->opregs.dnctrl; 2367 break; 2368 2369 case XHCI_CRCR_LO: /* 0x18 */ 2370 value = sc->opregs.crcr & XHCI_CRCR_LO_CRR; 2371 break; 2372 2373 case XHCI_CRCR_HI: /* 0x1C */ 2374 value = 0; 2375 break; 2376 2377 case XHCI_DCBAAP_LO: /* 0x30 */ 2378 value = sc->opregs.dcbaap & 0xFFFFFFFF; 2379 break; 2380 2381 case XHCI_DCBAAP_HI: /* 0x34 */ 2382 value = (sc->opregs.dcbaap >> 32) & 0xFFFFFFFF; 2383 break; 2384 2385 case XHCI_CONFIG: /* 0x38 */ 2386 value = sc->opregs.config; 2387 break; 2388 2389 default: 2390 if (offset >= 0x400) 2391 value = pci_xhci_portregs_read(sc, offset); 2392 else 2393 value = 0; 2394 2395 break; 2396 } 2397 2398 if (offset < 0x400) 2399 DPRINTF(("pci_xhci: hostop read offset 0x%lx -> 0x%lx", 2400 offset, value)); 2401 2402 return (value); 2403 } 2404 2405 static uint64_t 2406 pci_xhci_dbregs_read(struct pci_xhci_softc *sc, uint64_t offset) 2407 { 2408 2409 /* read doorbell always returns 0 */ 2410 return (0); 2411 } 2412 2413 static uint64_t 2414 pci_xhci_rtsregs_read(struct pci_xhci_softc *sc, uint64_t offset) 2415 { 2416 uint32_t value; 2417 2418 offset -= sc->rtsoff; 2419 value = 0; 2420 2421 if (offset == XHCI_MFINDEX) { 2422 value = sc->rtsregs.mfindex; 2423 } else if (offset >= 0x20) { 2424 int item; 2425 uint32_t *p; 2426 2427 offset -= 0x20; 2428 item = offset % 32; 2429 2430 assert(offset < sizeof(sc->rtsregs.intrreg)); 2431 2432 p = &sc->rtsregs.intrreg.iman; 2433 p += item / sizeof(uint32_t); 2434 value = *p; 2435 } 2436 2437 DPRINTF(("pci_xhci: rtsregs read offset 0x%lx -> 0x%x", 2438 offset, value)); 2439 2440 return (value); 2441 } 2442 2443 static uint64_t 2444 pci_xhci_xecp_read(struct pci_xhci_softc *sc, uint64_t offset) 2445 { 2446 uint32_t value; 2447 2448 offset -= sc->regsend; 2449 value = 0; 2450 2451 switch (offset) { 2452 case 0: 2453 /* rev major | rev minor | next-cap | cap-id */ 2454 value = (0x02 << 24) | (4 << 8) | XHCI_ID_PROTOCOLS; 2455 break; 2456 case 4: 2457 /* name string = "USB" */ 2458 value = 0x20425355; 2459 break; 2460 case 8: 2461 /* psic | proto-defined | compat # | compat offset */ 2462 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb2_port_start; 2463 break; 2464 case 12: 2465 break; 2466 case 16: 2467 /* rev major | rev minor | next-cap | cap-id */ 2468 value = (0x03 << 24) | XHCI_ID_PROTOCOLS; 2469 break; 2470 case 20: 2471 /* name string = "USB" */ 2472 value = 0x20425355; 2473 break; 2474 case 24: 2475 /* psic | proto-defined | compat # | compat offset */ 2476 value = ((XHCI_MAX_DEVS/2) << 8) | sc->usb3_port_start; 2477 break; 2478 case 28: 2479 break; 2480 default: 2481 DPRINTF(("pci_xhci: xecp invalid offset 0x%lx", offset)); 2482 break; 2483 } 2484 2485 DPRINTF(("pci_xhci: xecp read offset 0x%lx -> 0x%x", 2486 offset, value)); 2487 2488 return (value); 2489 } 2490 2491 2492 static uint64_t 2493 pci_xhci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2494 uint64_t offset, int size) 2495 { 2496 struct pci_xhci_softc *sc; 2497 uint32_t value; 2498 2499 sc = pi->pi_arg; 2500 2501 assert(baridx == 0); 2502 2503 pthread_mutex_lock(&sc->mtx); 2504 if (offset < XHCI_CAPLEN) 2505 value = pci_xhci_hostcap_read(sc, offset); 2506 else if (offset < sc->dboff) 2507 value = pci_xhci_hostop_read(sc, offset); 2508 else if (offset < sc->rtsoff) 2509 value = pci_xhci_dbregs_read(sc, offset); 2510 else if (offset < sc->regsend) 2511 value = pci_xhci_rtsregs_read(sc, offset); 2512 else if (offset < (sc->regsend + 4*32)) 2513 value = pci_xhci_xecp_read(sc, offset); 2514 else { 2515 value = 0; 2516 WPRINTF(("pci_xhci: read invalid offset %ld", offset)); 2517 } 2518 2519 pthread_mutex_unlock(&sc->mtx); 2520 2521 switch (size) { 2522 case 1: 2523 value &= 0xFF; 2524 break; 2525 case 2: 2526 value &= 0xFFFF; 2527 break; 2528 case 4: 2529 value &= 0xFFFFFFFF; 2530 break; 2531 } 2532 2533 return (value); 2534 } 2535 2536 static void 2537 pci_xhci_reset_port(struct pci_xhci_softc *sc, int portn, int warm) 2538 { 2539 struct pci_xhci_portregs *port; 2540 struct pci_xhci_dev_emu *dev; 2541 struct xhci_trb evtrb; 2542 int error; 2543 2544 assert(portn <= XHCI_MAX_DEVS); 2545 2546 DPRINTF(("xhci reset port %d", portn)); 2547 2548 port = XHCI_PORTREG_PTR(sc, portn); 2549 dev = XHCI_DEVINST_PTR(sc, portn); 2550 if (dev) { 2551 port->portsc &= ~(XHCI_PS_PLS_MASK | XHCI_PS_PR | XHCI_PS_PRC); 2552 port->portsc |= XHCI_PS_PED | 2553 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); 2554 2555 if (warm && dev->dev_ue->ue_usbver == 3) { 2556 port->portsc |= XHCI_PS_WRC; 2557 } 2558 2559 if ((port->portsc & XHCI_PS_PRC) == 0) { 2560 port->portsc |= XHCI_PS_PRC; 2561 2562 pci_xhci_set_evtrb(&evtrb, portn, 2563 XHCI_TRB_ERROR_SUCCESS, 2564 XHCI_TRB_EVENT_PORT_STS_CHANGE); 2565 error = pci_xhci_insert_event(sc, &evtrb, 1); 2566 if (error != XHCI_TRB_ERROR_SUCCESS) 2567 DPRINTF(("xhci reset port insert event " 2568 "failed")); 2569 } 2570 } 2571 } 2572 2573 static void 2574 pci_xhci_init_port(struct pci_xhci_softc *sc, int portn) 2575 { 2576 struct pci_xhci_portregs *port; 2577 struct pci_xhci_dev_emu *dev; 2578 2579 port = XHCI_PORTREG_PTR(sc, portn); 2580 dev = XHCI_DEVINST_PTR(sc, portn); 2581 if (dev) { 2582 port->portsc = XHCI_PS_CCS | /* connected */ 2583 XHCI_PS_PP; /* port power */ 2584 2585 if (dev->dev_ue->ue_usbver == 2) { 2586 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_POLL) | 2587 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); 2588 } else { 2589 port->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_U0) | 2590 XHCI_PS_PED | /* enabled */ 2591 XHCI_PS_SPEED_SET(dev->dev_ue->ue_usbspeed); 2592 } 2593 2594 DPRINTF(("Init port %d 0x%x", portn, port->portsc)); 2595 } else { 2596 port->portsc = XHCI_PS_PLS_SET(UPS_PORT_LS_RX_DET) | XHCI_PS_PP; 2597 DPRINTF(("Init empty port %d 0x%x", portn, port->portsc)); 2598 } 2599 } 2600 2601 static int 2602 pci_xhci_dev_intr(struct usb_hci *hci, int epctx) 2603 { 2604 struct pci_xhci_dev_emu *dev; 2605 struct xhci_dev_ctx *dev_ctx; 2606 struct xhci_trb evtrb; 2607 struct pci_xhci_softc *sc; 2608 struct pci_xhci_portregs *p; 2609 struct xhci_endp_ctx *ep_ctx; 2610 int error = 0; 2611 int dir_in; 2612 int epid; 2613 2614 dir_in = epctx & 0x80; 2615 epid = epctx & ~0x80; 2616 2617 /* HW endpoint contexts are 0-15; convert to epid based on dir */ 2618 epid = (epid * 2) + (dir_in ? 1 : 0); 2619 2620 assert(epid >= 1 && epid <= 31); 2621 2622 dev = hci->hci_sc; 2623 sc = dev->xsc; 2624 2625 /* check if device is ready; OS has to initialise it */ 2626 if (sc->rtsregs.erstba_p == NULL || 2627 (sc->opregs.usbcmd & XHCI_CMD_RS) == 0 || 2628 dev->dev_ctx == NULL) 2629 return (0); 2630 2631 p = XHCI_PORTREG_PTR(sc, hci->hci_port); 2632 2633 /* raise event if link U3 (suspended) state */ 2634 if (XHCI_PS_PLS_GET(p->portsc) == 3) { 2635 p->portsc &= ~XHCI_PS_PLS_MASK; 2636 p->portsc |= XHCI_PS_PLS_SET(UPS_PORT_LS_RESUME); 2637 if ((p->portsc & XHCI_PS_PLC) != 0) 2638 return (0); 2639 2640 p->portsc |= XHCI_PS_PLC; 2641 2642 pci_xhci_set_evtrb(&evtrb, hci->hci_port, 2643 XHCI_TRB_ERROR_SUCCESS, XHCI_TRB_EVENT_PORT_STS_CHANGE); 2644 error = pci_xhci_insert_event(sc, &evtrb, 0); 2645 if (error != XHCI_TRB_ERROR_SUCCESS) 2646 goto done; 2647 } 2648 2649 dev_ctx = dev->dev_ctx; 2650 ep_ctx = &dev_ctx->ctx_ep[epid]; 2651 if ((ep_ctx->dwEpCtx0 & 0x7) == XHCI_ST_EPCTX_DISABLED) { 2652 DPRINTF(("xhci device interrupt on disabled endpoint %d", 2653 epid)); 2654 return (0); 2655 } 2656 2657 DPRINTF(("xhci device interrupt on endpoint %d", epid)); 2658 2659 pci_xhci_device_doorbell(sc, hci->hci_port, epid, 0); 2660 2661 done: 2662 return (error); 2663 } 2664 2665 static int 2666 pci_xhci_dev_event(struct usb_hci *hci, enum hci_usbev evid, void *param) 2667 { 2668 2669 DPRINTF(("xhci device event port %d", hci->hci_port)); 2670 return (0); 2671 } 2672 2673 /* 2674 * Each controller contains a "slot" node which contains a list of 2675 * child nodes each of which is a device. Each slot node's name 2676 * corresponds to a specific controller slot. These nodes 2677 * contain a "device" variable identifying the device model of the 2678 * USB device. For example: 2679 * 2680 * pci.0.1.0 2681 * .device="xhci" 2682 * .slot 2683 * .1 2684 * .device="tablet" 2685 */ 2686 static int 2687 pci_xhci_legacy_config(nvlist_t *nvl, const char *opts) 2688 { 2689 char node_name[16]; 2690 nvlist_t *slots_nvl, *slot_nvl; 2691 char *cp, *opt, *str, *tofree; 2692 int slot; 2693 2694 if (opts == NULL) 2695 return (0); 2696 2697 slots_nvl = create_relative_config_node(nvl, "slot"); 2698 slot = 1; 2699 tofree = str = strdup(opts); 2700 while ((opt = strsep(&str, ",")) != NULL) { 2701 /* device[=<config>] */ 2702 cp = strchr(opt, '='); 2703 if (cp != NULL) { 2704 *cp = '\0'; 2705 cp++; 2706 } 2707 2708 snprintf(node_name, sizeof(node_name), "%d", slot); 2709 slot++; 2710 slot_nvl = create_relative_config_node(slots_nvl, node_name); 2711 set_config_value_node(slot_nvl, "device", opt); 2712 2713 /* 2714 * NB: Given that we split on commas above, the legacy 2715 * format only supports a single option. 2716 */ 2717 if (cp != NULL && *cp != '\0') 2718 pci_parse_legacy_config(slot_nvl, cp); 2719 } 2720 free(tofree); 2721 return (0); 2722 } 2723 2724 static int 2725 pci_xhci_parse_devices(struct pci_xhci_softc *sc, nvlist_t *nvl) 2726 { 2727 struct pci_xhci_dev_emu *dev; 2728 struct usb_devemu *ue; 2729 const nvlist_t *slots_nvl, *slot_nvl; 2730 const char *name, *device; 2731 char *cp; 2732 void *devsc, *cookie; 2733 long slot; 2734 int type, usb3_port, usb2_port, i, ndevices; 2735 2736 usb3_port = sc->usb3_port_start; 2737 usb2_port = sc->usb2_port_start; 2738 2739 sc->devices = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_dev_emu *)); 2740 sc->slots = calloc(XHCI_MAX_SLOTS, sizeof(struct pci_xhci_dev_emu *)); 2741 2742 /* port and slot numbering start from 1 */ 2743 sc->devices--; 2744 sc->slots--; 2745 2746 ndevices = 0; 2747 2748 slots_nvl = find_relative_config_node(nvl, "slot"); 2749 if (slots_nvl == NULL) 2750 goto portsfinal; 2751 2752 cookie = NULL; 2753 while ((name = nvlist_next(slots_nvl, &type, &cookie)) != NULL) { 2754 if (usb2_port == ((sc->usb2_port_start) + XHCI_MAX_DEVS/2) || 2755 usb3_port == ((sc->usb3_port_start) + XHCI_MAX_DEVS/2)) { 2756 WPRINTF(("pci_xhci max number of USB 2 or 3 " 2757 "devices reached, max %d", XHCI_MAX_DEVS/2)); 2758 goto bad; 2759 } 2760 2761 if (type != NV_TYPE_NVLIST) { 2762 EPRINTLN( 2763 "pci_xhci: config variable '%s' under slot node", 2764 name); 2765 goto bad; 2766 } 2767 2768 slot = strtol(name, &cp, 0); 2769 if (*cp != '\0' || slot <= 0 || slot > XHCI_MAX_SLOTS) { 2770 EPRINTLN("pci_xhci: invalid slot '%s'", name); 2771 goto bad; 2772 } 2773 2774 if (XHCI_SLOTDEV_PTR(sc, slot) != NULL) { 2775 EPRINTLN("pci_xhci: duplicate slot '%s'", name); 2776 goto bad; 2777 } 2778 2779 slot_nvl = nvlist_get_nvlist(slots_nvl, name); 2780 device = get_config_value_node(slot_nvl, "device"); 2781 if (device == NULL) { 2782 EPRINTLN( 2783 "pci_xhci: missing \"device\" value for slot '%s'", 2784 name); 2785 goto bad; 2786 } 2787 2788 ue = usb_emu_finddev(device); 2789 if (ue == NULL) { 2790 EPRINTLN("pci_xhci: unknown device model \"%s\"", 2791 device); 2792 goto bad; 2793 } 2794 2795 DPRINTF(("pci_xhci adding device %s", device)); 2796 2797 dev = calloc(1, sizeof(struct pci_xhci_dev_emu)); 2798 dev->xsc = sc; 2799 dev->hci.hci_sc = dev; 2800 dev->hci.hci_intr = pci_xhci_dev_intr; 2801 dev->hci.hci_event = pci_xhci_dev_event; 2802 2803 if (ue->ue_usbver == 2) { 2804 if (usb2_port == sc->usb2_port_start + 2805 XHCI_MAX_DEVS / 2) { 2806 WPRINTF(("pci_xhci max number of USB 2 devices " 2807 "reached, max %d", XHCI_MAX_DEVS / 2)); 2808 goto bad; 2809 } 2810 dev->hci.hci_port = usb2_port; 2811 usb2_port++; 2812 } else { 2813 if (usb3_port == sc->usb3_port_start + 2814 XHCI_MAX_DEVS / 2) { 2815 WPRINTF(("pci_xhci max number of USB 3 devices " 2816 "reached, max %d", XHCI_MAX_DEVS / 2)); 2817 goto bad; 2818 } 2819 dev->hci.hci_port = usb3_port; 2820 usb3_port++; 2821 } 2822 XHCI_DEVINST_PTR(sc, dev->hci.hci_port) = dev; 2823 2824 dev->hci.hci_address = 0; 2825 devsc = ue->ue_init(&dev->hci, nvl); 2826 if (devsc == NULL) { 2827 goto bad; 2828 } 2829 2830 dev->dev_ue = ue; 2831 dev->dev_sc = devsc; 2832 2833 XHCI_SLOTDEV_PTR(sc, slot) = dev; 2834 ndevices++; 2835 } 2836 2837 portsfinal: 2838 sc->portregs = calloc(XHCI_MAX_DEVS, sizeof(struct pci_xhci_portregs)); 2839 sc->portregs--; 2840 2841 if (ndevices > 0) { 2842 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 2843 pci_xhci_init_port(sc, i); 2844 } 2845 } else { 2846 WPRINTF(("pci_xhci no USB devices configured")); 2847 } 2848 return (0); 2849 2850 bad: 2851 for (i = 1; i <= XHCI_MAX_DEVS; i++) { 2852 free(XHCI_DEVINST_PTR(sc, i)); 2853 } 2854 2855 free(sc->devices + 1); 2856 free(sc->slots + 1); 2857 2858 return (-1); 2859 } 2860 2861 static int 2862 pci_xhci_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl) 2863 { 2864 struct pci_xhci_softc *sc; 2865 int error; 2866 2867 #ifndef __FreeBSD__ 2868 if (get_config_bool_default("xhci.debug", false)) 2869 xhci_debug = 1; 2870 #endif 2871 2872 if (xhci_in_use) { 2873 WPRINTF(("pci_xhci controller already defined")); 2874 return (-1); 2875 } 2876 xhci_in_use = 1; 2877 2878 sc = calloc(1, sizeof(struct pci_xhci_softc)); 2879 pi->pi_arg = sc; 2880 sc->xsc_pi = pi; 2881 2882 sc->usb2_port_start = (XHCI_MAX_DEVS/2) + 1; 2883 sc->usb3_port_start = 1; 2884 2885 /* discover devices */ 2886 error = pci_xhci_parse_devices(sc, nvl); 2887 if (error < 0) 2888 goto done; 2889 else 2890 error = 0; 2891 2892 sc->caplength = XHCI_SET_CAPLEN(XHCI_CAPLEN) | 2893 XHCI_SET_HCIVERSION(0x0100); 2894 sc->hcsparams1 = XHCI_SET_HCSP1_MAXPORTS(XHCI_MAX_DEVS) | 2895 XHCI_SET_HCSP1_MAXINTR(1) | /* interrupters */ 2896 XHCI_SET_HCSP1_MAXSLOTS(XHCI_MAX_SLOTS); 2897 sc->hcsparams2 = XHCI_SET_HCSP2_ERSTMAX(XHCI_ERST_MAX) | 2898 XHCI_SET_HCSP2_IST(0x04); 2899 sc->hcsparams3 = 0; /* no latency */ 2900 sc->hccparams1 = XHCI_SET_HCCP1_AC64(1) | /* 64-bit addrs */ 2901 XHCI_SET_HCCP1_NSS(1) | /* no 2nd-streams */ 2902 XHCI_SET_HCCP1_SPC(1) | /* short packet */ 2903 XHCI_SET_HCCP1_MAXPSA(XHCI_STREAMS_MAX); 2904 sc->hccparams2 = XHCI_SET_HCCP2_LEC(1) | 2905 XHCI_SET_HCCP2_U3C(1); 2906 sc->dboff = XHCI_SET_DOORBELL(XHCI_CAPLEN + XHCI_PORTREGS_START + 2907 XHCI_MAX_DEVS * sizeof(struct pci_xhci_portregs)); 2908 2909 /* dboff must be 32-bit aligned */ 2910 if (sc->dboff & 0x3) 2911 sc->dboff = (sc->dboff + 0x3) & ~0x3; 2912 2913 /* rtsoff must be 32-bytes aligned */ 2914 sc->rtsoff = XHCI_SET_RTSOFFSET(sc->dboff + (XHCI_MAX_SLOTS+1) * 32); 2915 if (sc->rtsoff & 0x1F) 2916 sc->rtsoff = (sc->rtsoff + 0x1F) & ~0x1F; 2917 2918 DPRINTF(("pci_xhci dboff: 0x%x, rtsoff: 0x%x", sc->dboff, 2919 sc->rtsoff)); 2920 2921 sc->opregs.usbsts = XHCI_STS_HCH; 2922 sc->opregs.pgsz = XHCI_PAGESIZE_4K; 2923 2924 pci_xhci_reset(sc); 2925 2926 sc->regsend = sc->rtsoff + 0x20 + 32; /* only 1 intrpter */ 2927 2928 /* 2929 * Set extended capabilities pointer to be after regsend; 2930 * value of xecp field is 32-bit offset. 2931 */ 2932 sc->hccparams1 |= XHCI_SET_HCCP1_XECP(sc->regsend/4); 2933 2934 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x1E31); 2935 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2936 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_SERIALBUS); 2937 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_SERIALBUS_USB); 2938 pci_set_cfgdata8(pi, PCIR_PROGIF,PCIP_SERIALBUS_USB_XHCI); 2939 pci_set_cfgdata8(pi, PCI_USBREV, PCI_USB_REV_3_0); 2940 2941 pci_emul_add_msicap(pi, 1); 2942 2943 /* regsend + xecp registers */ 2944 pci_emul_alloc_bar(pi, 0, PCIBAR_MEM32, sc->regsend + 4*32); 2945 DPRINTF(("pci_xhci pci_emu_alloc: %d", sc->regsend + 4*32)); 2946 2947 2948 pci_lintr_request(pi); 2949 2950 pthread_mutex_init(&sc->mtx, NULL); 2951 2952 done: 2953 if (error) { 2954 free(sc); 2955 } 2956 2957 return (error); 2958 } 2959 2960 static const struct pci_devemu pci_de_xhci = { 2961 .pe_emu = "xhci", 2962 .pe_init = pci_xhci_init, 2963 .pe_legacy_config = pci_xhci_legacy_config, 2964 .pe_barwrite = pci_xhci_write, 2965 .pe_barread = pci_xhci_read 2966 }; 2967 PCI_EMUL_SET(pci_de_xhci); 2968