1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * Copyright 2018 Joyent, Inc. 32 */ 33 34 #ifndef _PCI_EMUL_H_ 35 #define _PCI_EMUL_H_ 36 37 #include <sys/types.h> 38 #include <sys/queue.h> 39 #include <sys/kernel.h> 40 #include <sys/nv.h> 41 #include <sys/_pthreadtypes.h> 42 43 #include <dev/pci/pcireg.h> 44 45 #include <assert.h> 46 47 #define PCI_BARMAX PCIR_MAX_BAR_0 /* BAR registers in a Type 0 header */ 48 49 struct vmctx; 50 struct pci_devinst; 51 struct memory_region; 52 53 struct pci_devemu { 54 char *pe_emu; /* Name of device emulation */ 55 56 /* instance creation */ 57 int (*pe_init)(struct vmctx *, struct pci_devinst *, 58 nvlist_t *); 59 int (*pe_legacy_config)(nvlist_t *, const char *); 60 const char *pe_alias; 61 62 /* ACPI DSDT enumeration */ 63 void (*pe_write_dsdt)(struct pci_devinst *); 64 65 /* config space read/write callbacks */ 66 int (*pe_cfgwrite)(struct vmctx *ctx, int vcpu, 67 struct pci_devinst *pi, int offset, 68 int bytes, uint32_t val); 69 int (*pe_cfgread)(struct vmctx *ctx, int vcpu, 70 struct pci_devinst *pi, int offset, 71 int bytes, uint32_t *retval); 72 73 /* BAR read/write callbacks */ 74 void (*pe_barwrite)(struct vmctx *ctx, int vcpu, 75 struct pci_devinst *pi, int baridx, 76 uint64_t offset, int size, uint64_t value); 77 uint64_t (*pe_barread)(struct vmctx *ctx, int vcpu, 78 struct pci_devinst *pi, int baridx, 79 uint64_t offset, int size); 80 81 void (*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi, 82 int baridx, int enabled, uint64_t address); 83 #ifndef __FreeBSD__ 84 void (*pe_lintrupdate)(struct pci_devinst *pi); 85 #endif /* __FreeBSD__ */ 86 }; 87 88 #define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x); 89 90 enum pcibar_type { 91 PCIBAR_NONE, 92 PCIBAR_IO, 93 PCIBAR_MEM32, 94 PCIBAR_MEM64, 95 PCIBAR_MEMHI64 96 }; 97 98 struct pcibar { 99 enum pcibar_type type; /* io or memory */ 100 uint64_t size; 101 uint64_t addr; 102 uint8_t lobits; 103 }; 104 105 #define PI_NAMESZ 40 106 107 struct msix_table_entry { 108 uint64_t addr; 109 uint32_t msg_data; 110 uint32_t vector_control; 111 } __packed; 112 113 /* 114 * In case the structure is modified to hold extra information, use a define 115 * for the size that should be emulated. 116 */ 117 #define MSIX_TABLE_ENTRY_SIZE 16 118 #define MAX_MSIX_TABLE_ENTRIES 2048 119 #define PBA_SIZE(msgnum) (roundup2((msgnum), 64) / 8) 120 121 enum lintr_stat { 122 IDLE, 123 ASSERTED, 124 PENDING 125 }; 126 127 struct pci_devinst { 128 struct pci_devemu *pi_d; 129 struct vmctx *pi_vmctx; 130 uint8_t pi_bus, pi_slot, pi_func; 131 char pi_name[PI_NAMESZ]; 132 int pi_bar_getsize; 133 int pi_prevcap; 134 int pi_capend; 135 136 struct { 137 int8_t pin; 138 enum lintr_stat state; 139 int pirq_pin; 140 int ioapic_irq; 141 pthread_mutex_t lock; 142 } pi_lintr; 143 144 struct { 145 int enabled; 146 uint64_t addr; 147 uint64_t msg_data; 148 int maxmsgnum; 149 } pi_msi; 150 151 struct { 152 int enabled; 153 int table_bar; 154 int pba_bar; 155 uint32_t table_offset; 156 int table_count; 157 uint32_t pba_offset; 158 int pba_size; 159 int function_mask; 160 struct msix_table_entry *table; /* allocated at runtime */ 161 void *pba_page; 162 int pba_page_offset; 163 uint8_t *mapped_addr; 164 size_t mapped_size; 165 } pi_msix; 166 167 void *pi_arg; /* devemu-private data */ 168 169 u_char pi_cfgdata[PCI_REGMAX + 1]; 170 struct pcibar pi_bar[PCI_BARMAX + 1]; 171 }; 172 173 struct msicap { 174 uint8_t capid; 175 uint8_t nextptr; 176 uint16_t msgctrl; 177 uint32_t addrlo; 178 uint32_t addrhi; 179 uint16_t msgdata; 180 } __packed; 181 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed"); 182 183 struct msixcap { 184 uint8_t capid; 185 uint8_t nextptr; 186 uint16_t msgctrl; 187 uint32_t table_info; /* bar index and offset within it */ 188 uint32_t pba_info; /* bar index and offset within it */ 189 } __packed; 190 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed"); 191 192 struct pciecap { 193 uint8_t capid; 194 uint8_t nextptr; 195 uint16_t pcie_capabilities; 196 197 uint32_t dev_capabilities; /* all devices */ 198 uint16_t dev_control; 199 uint16_t dev_status; 200 201 uint32_t link_capabilities; /* devices with links */ 202 uint16_t link_control; 203 uint16_t link_status; 204 205 uint32_t slot_capabilities; /* ports with slots */ 206 uint16_t slot_control; 207 uint16_t slot_status; 208 209 uint16_t root_control; /* root ports */ 210 uint16_t root_capabilities; 211 uint32_t root_status; 212 213 uint32_t dev_capabilities2; /* all devices */ 214 uint16_t dev_control2; 215 uint16_t dev_status2; 216 217 uint32_t link_capabilities2; /* devices with links */ 218 uint16_t link_control2; 219 uint16_t link_status2; 220 221 uint32_t slot_capabilities2; /* ports with slots */ 222 uint16_t slot_control2; 223 uint16_t slot_status2; 224 } __packed; 225 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed"); 226 227 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin, 228 int ioapic_irq, void *arg); 229 230 int init_pci(struct vmctx *ctx); 231 void pci_callback(void); 232 int pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, 233 enum pcibar_type type, uint64_t size); 234 int pci_emul_add_msicap(struct pci_devinst *pi, int msgnum); 235 int pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type); 236 void pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, 237 uint32_t val, uint8_t capoff, int capid); 238 void pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old); 239 void pci_generate_msi(struct pci_devinst *pi, int msgnum); 240 void pci_generate_msix(struct pci_devinst *pi, int msgnum); 241 void pci_lintr_assert(struct pci_devinst *pi); 242 void pci_lintr_deassert(struct pci_devinst *pi); 243 void pci_lintr_request(struct pci_devinst *pi); 244 int pci_msi_enabled(struct pci_devinst *pi); 245 int pci_msix_enabled(struct pci_devinst *pi); 246 int pci_msix_table_bar(struct pci_devinst *pi); 247 int pci_msix_pba_bar(struct pci_devinst *pi); 248 int pci_msi_maxmsgnum(struct pci_devinst *pi); 249 int pci_parse_legacy_config(nvlist_t *nvl, const char *opt); 250 int pci_parse_slot(char *opt); 251 void pci_print_supported_devices(); 252 void pci_populate_msicap(struct msicap *cap, int msgs, int nextptr); 253 int pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum); 254 int pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 255 uint64_t value); 256 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size); 257 int pci_count_lintr(int bus); 258 void pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg); 259 void pci_write_dsdt(void); 260 uint64_t pci_ecfg_base(void); 261 int pci_bus_configured(int bus); 262 263 static __inline void 264 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val) 265 { 266 assert(offset <= PCI_REGMAX); 267 *(uint8_t *)(pi->pi_cfgdata + offset) = val; 268 } 269 270 static __inline void 271 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val) 272 { 273 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 274 *(uint16_t *)(pi->pi_cfgdata + offset) = val; 275 } 276 277 static __inline void 278 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val) 279 { 280 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 281 *(uint32_t *)(pi->pi_cfgdata + offset) = val; 282 } 283 284 static __inline uint8_t 285 pci_get_cfgdata8(struct pci_devinst *pi, int offset) 286 { 287 assert(offset <= PCI_REGMAX); 288 return (*(uint8_t *)(pi->pi_cfgdata + offset)); 289 } 290 291 static __inline uint16_t 292 pci_get_cfgdata16(struct pci_devinst *pi, int offset) 293 { 294 assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0); 295 return (*(uint16_t *)(pi->pi_cfgdata + offset)); 296 } 297 298 static __inline uint32_t 299 pci_get_cfgdata32(struct pci_devinst *pi, int offset) 300 { 301 assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0); 302 return (*(uint32_t *)(pi->pi_cfgdata + offset)); 303 } 304 305 #endif /* _PCI_EMUL_H_ */ 306