1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 /* 31 * This file and its contents are supplied under the terms of the 32 * Common Development and Distribution License ("CDDL"), version 1.0. 33 * You may only use this file in accordance with the terms of version 34 * 1.0 of the CDDL. 35 * 36 * A full copy of the text of the CDDL should have accompanied this 37 * source. A copy of the CDDL is also available via the Internet at 38 * http://www.illumos.org/license/CDDL. 39 * 40 * Copyright 2014 Pluribus Networks Inc. 41 * Copyright 2018 Joyent, Inc. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD$"); 46 47 #include <sys/param.h> 48 #include <sys/linker_set.h> 49 50 #include <ctype.h> 51 #include <errno.h> 52 #include <pthread.h> 53 #include <stdio.h> 54 #include <stdlib.h> 55 #include <string.h> 56 #include <strings.h> 57 #include <assert.h> 58 #include <stdbool.h> 59 60 #include <machine/vmm.h> 61 #include <vmmapi.h> 62 63 #include "acpi.h" 64 #include "bhyverun.h" 65 #include "inout.h" 66 #include "ioapic.h" 67 #include "mem.h" 68 #include "pci_emul.h" 69 #include "pci_irq.h" 70 #include "pci_lpc.h" 71 72 #define CONF1_ADDR_PORT 0x0cf8 73 #define CONF1_DATA_PORT 0x0cfc 74 75 #define CONF1_ENABLE 0x80000000ul 76 77 #define MAXBUSES (PCI_BUSMAX + 1) 78 #define MAXSLOTS (PCI_SLOTMAX + 1) 79 #define MAXFUNCS (PCI_FUNCMAX + 1) 80 81 struct funcinfo { 82 char *fi_name; 83 char *fi_param; 84 struct pci_devinst *fi_devi; 85 }; 86 87 struct intxinfo { 88 int ii_count; 89 int ii_pirq_pin; 90 int ii_ioapic_irq; 91 }; 92 93 struct slotinfo { 94 struct intxinfo si_intpins[4]; 95 struct funcinfo si_funcs[MAXFUNCS]; 96 }; 97 98 struct businfo { 99 uint16_t iobase, iolimit; /* I/O window */ 100 uint32_t membase32, memlimit32; /* mmio window below 4GB */ 101 uint64_t membase64, memlimit64; /* mmio window above 4GB */ 102 struct slotinfo slotinfo[MAXSLOTS]; 103 }; 104 105 static struct businfo *pci_businfo[MAXBUSES]; 106 107 SET_DECLARE(pci_devemu_set, struct pci_devemu); 108 109 static uint64_t pci_emul_iobase; 110 static uint64_t pci_emul_membase32; 111 static uint64_t pci_emul_membase64; 112 113 #define PCI_EMUL_IOBASE 0x2000 114 #define PCI_EMUL_IOLIMIT 0x10000 115 116 #define PCI_EMUL_ECFG_BASE 0xE0000000 /* 3.5GB */ 117 #define PCI_EMUL_ECFG_SIZE (MAXBUSES * 1024 * 1024) /* 1MB per bus */ 118 SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE); 119 120 #define PCI_EMUL_MEMLIMIT32 PCI_EMUL_ECFG_BASE 121 122 #define PCI_EMUL_MEMBASE64 0xD000000000UL 123 #define PCI_EMUL_MEMLIMIT64 0xFD00000000UL 124 125 static struct pci_devemu *pci_emul_finddev(char *name); 126 static void pci_lintr_route(struct pci_devinst *pi); 127 static void pci_lintr_update(struct pci_devinst *pi); 128 static void pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, 129 int func, int coff, int bytes, uint32_t *val); 130 131 static __inline void 132 CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes) 133 { 134 135 if (bytes == 1) 136 pci_set_cfgdata8(pi, coff, val); 137 else if (bytes == 2) 138 pci_set_cfgdata16(pi, coff, val); 139 else 140 pci_set_cfgdata32(pi, coff, val); 141 } 142 143 static __inline uint32_t 144 CFGREAD(struct pci_devinst *pi, int coff, int bytes) 145 { 146 147 if (bytes == 1) 148 return (pci_get_cfgdata8(pi, coff)); 149 else if (bytes == 2) 150 return (pci_get_cfgdata16(pi, coff)); 151 else 152 return (pci_get_cfgdata32(pi, coff)); 153 } 154 155 /* 156 * I/O access 157 */ 158 159 /* 160 * Slot options are in the form: 161 * 162 * <bus>:<slot>:<func>,<emul>[,<config>] 163 * <slot>[:<func>],<emul>[,<config>] 164 * 165 * slot is 0..31 166 * func is 0..7 167 * emul is a string describing the type of PCI device e.g. virtio-net 168 * config is an optional string, depending on the device, that can be 169 * used for configuration. 170 * Examples are: 171 * 1,virtio-net,tap0 172 * 3:0,dummy 173 */ 174 static void 175 pci_parse_slot_usage(char *aopt) 176 { 177 178 fprintf(stderr, "Invalid PCI slot info field \"%s\"\n", aopt); 179 } 180 181 int 182 pci_parse_slot(char *opt) 183 { 184 struct businfo *bi; 185 struct slotinfo *si; 186 char *emul, *config, *str, *cp; 187 int error, bnum, snum, fnum; 188 189 error = -1; 190 str = strdup(opt); 191 192 emul = config = NULL; 193 if ((cp = strchr(str, ',')) != NULL) { 194 *cp = '\0'; 195 emul = cp + 1; 196 if ((cp = strchr(emul, ',')) != NULL) { 197 *cp = '\0'; 198 config = cp + 1; 199 } 200 } else { 201 pci_parse_slot_usage(opt); 202 goto done; 203 } 204 205 /* <bus>:<slot>:<func> */ 206 if (sscanf(str, "%d:%d:%d", &bnum, &snum, &fnum) != 3) { 207 bnum = 0; 208 /* <slot>:<func> */ 209 if (sscanf(str, "%d:%d", &snum, &fnum) != 2) { 210 fnum = 0; 211 /* <slot> */ 212 if (sscanf(str, "%d", &snum) != 1) { 213 snum = -1; 214 } 215 } 216 } 217 218 if (bnum < 0 || bnum >= MAXBUSES || snum < 0 || snum >= MAXSLOTS || 219 fnum < 0 || fnum >= MAXFUNCS) { 220 pci_parse_slot_usage(opt); 221 goto done; 222 } 223 224 if (pci_businfo[bnum] == NULL) 225 pci_businfo[bnum] = calloc(1, sizeof(struct businfo)); 226 227 bi = pci_businfo[bnum]; 228 si = &bi->slotinfo[snum]; 229 230 if (si->si_funcs[fnum].fi_name != NULL) { 231 fprintf(stderr, "pci slot %d:%d already occupied!\n", 232 snum, fnum); 233 goto done; 234 } 235 236 if (pci_emul_finddev(emul) == NULL) { 237 fprintf(stderr, "pci slot %d:%d: unknown device \"%s\"\n", 238 snum, fnum, emul); 239 goto done; 240 } 241 242 error = 0; 243 si->si_funcs[fnum].fi_name = emul; 244 si->si_funcs[fnum].fi_param = config; 245 246 done: 247 if (error) 248 free(str); 249 250 return (error); 251 } 252 253 void 254 pci_print_supported_devices() 255 { 256 struct pci_devemu **pdpp, *pdp; 257 258 SET_FOREACH(pdpp, pci_devemu_set) { 259 pdp = *pdpp; 260 printf("%s\n", pdp->pe_emu); 261 } 262 } 263 264 static int 265 pci_valid_pba_offset(struct pci_devinst *pi, uint64_t offset) 266 { 267 268 if (offset < pi->pi_msix.pba_offset) 269 return (0); 270 271 if (offset >= pi->pi_msix.pba_offset + pi->pi_msix.pba_size) { 272 return (0); 273 } 274 275 return (1); 276 } 277 278 int 279 pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size, 280 uint64_t value) 281 { 282 int msix_entry_offset; 283 int tab_index; 284 char *dest; 285 286 /* support only 4 or 8 byte writes */ 287 if (size != 4 && size != 8) 288 return (-1); 289 290 /* 291 * Return if table index is beyond what device supports 292 */ 293 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 294 if (tab_index >= pi->pi_msix.table_count) 295 return (-1); 296 297 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 298 299 /* support only aligned writes */ 300 if ((msix_entry_offset % size) != 0) 301 return (-1); 302 303 dest = (char *)(pi->pi_msix.table + tab_index); 304 dest += msix_entry_offset; 305 306 if (size == 4) 307 *((uint32_t *)dest) = value; 308 else 309 *((uint64_t *)dest) = value; 310 311 return (0); 312 } 313 314 uint64_t 315 pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size) 316 { 317 char *dest; 318 int msix_entry_offset; 319 int tab_index; 320 uint64_t retval = ~0; 321 322 /* 323 * The PCI standard only allows 4 and 8 byte accesses to the MSI-X 324 * table but we also allow 1 byte access to accommodate reads from 325 * ddb. 326 */ 327 if (size != 1 && size != 4 && size != 8) 328 return (retval); 329 330 msix_entry_offset = offset % MSIX_TABLE_ENTRY_SIZE; 331 332 /* support only aligned reads */ 333 if ((msix_entry_offset % size) != 0) { 334 return (retval); 335 } 336 337 tab_index = offset / MSIX_TABLE_ENTRY_SIZE; 338 339 if (tab_index < pi->pi_msix.table_count) { 340 /* valid MSI-X Table access */ 341 dest = (char *)(pi->pi_msix.table + tab_index); 342 dest += msix_entry_offset; 343 344 if (size == 1) 345 retval = *((uint8_t *)dest); 346 else if (size == 4) 347 retval = *((uint32_t *)dest); 348 else 349 retval = *((uint64_t *)dest); 350 } else if (pci_valid_pba_offset(pi, offset)) { 351 /* return 0 for PBA access */ 352 retval = 0; 353 } 354 355 return (retval); 356 } 357 358 int 359 pci_msix_table_bar(struct pci_devinst *pi) 360 { 361 362 if (pi->pi_msix.table != NULL) 363 return (pi->pi_msix.table_bar); 364 else 365 return (-1); 366 } 367 368 int 369 pci_msix_pba_bar(struct pci_devinst *pi) 370 { 371 372 if (pi->pi_msix.table != NULL) 373 return (pi->pi_msix.pba_bar); 374 else 375 return (-1); 376 } 377 378 static int 379 pci_emul_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 380 uint32_t *eax, void *arg) 381 { 382 struct pci_devinst *pdi = arg; 383 struct pci_devemu *pe = pdi->pi_d; 384 uint64_t offset; 385 int i; 386 387 for (i = 0; i <= PCI_BARMAX; i++) { 388 if (pdi->pi_bar[i].type == PCIBAR_IO && 389 port >= pdi->pi_bar[i].addr && 390 port + bytes <= pdi->pi_bar[i].addr + pdi->pi_bar[i].size) { 391 offset = port - pdi->pi_bar[i].addr; 392 if (in) 393 *eax = (*pe->pe_barread)(ctx, vcpu, pdi, i, 394 offset, bytes); 395 else 396 (*pe->pe_barwrite)(ctx, vcpu, pdi, i, offset, 397 bytes, *eax); 398 return (0); 399 } 400 } 401 return (-1); 402 } 403 404 static int 405 pci_emul_mem_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 406 int size, uint64_t *val, void *arg1, long arg2) 407 { 408 struct pci_devinst *pdi = arg1; 409 struct pci_devemu *pe = pdi->pi_d; 410 uint64_t offset; 411 int bidx = (int) arg2; 412 413 assert(bidx <= PCI_BARMAX); 414 assert(pdi->pi_bar[bidx].type == PCIBAR_MEM32 || 415 pdi->pi_bar[bidx].type == PCIBAR_MEM64); 416 assert(addr >= pdi->pi_bar[bidx].addr && 417 addr + size <= pdi->pi_bar[bidx].addr + pdi->pi_bar[bidx].size); 418 419 offset = addr - pdi->pi_bar[bidx].addr; 420 421 if (dir == MEM_F_WRITE) { 422 if (size == 8) { 423 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 424 4, *val & 0xffffffff); 425 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset + 4, 426 4, *val >> 32); 427 } else { 428 (*pe->pe_barwrite)(ctx, vcpu, pdi, bidx, offset, 429 size, *val); 430 } 431 } else { 432 if (size == 8) { 433 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 434 offset, 4); 435 *val |= (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 436 offset + 4, 4) << 32; 437 } else { 438 *val = (*pe->pe_barread)(ctx, vcpu, pdi, bidx, 439 offset, size); 440 } 441 } 442 443 return (0); 444 } 445 446 447 static int 448 pci_emul_alloc_resource(uint64_t *baseptr, uint64_t limit, uint64_t size, 449 uint64_t *addr) 450 { 451 uint64_t base; 452 453 assert((size & (size - 1)) == 0); /* must be a power of 2 */ 454 455 base = roundup2(*baseptr, size); 456 457 if (base + size <= limit) { 458 *addr = base; 459 *baseptr = base + size; 460 return (0); 461 } else 462 return (-1); 463 } 464 465 int 466 pci_emul_alloc_bar(struct pci_devinst *pdi, int idx, enum pcibar_type type, 467 uint64_t size) 468 { 469 470 return (pci_emul_alloc_pbar(pdi, idx, 0, type, size)); 471 } 472 473 /* 474 * Register (or unregister) the MMIO or I/O region associated with the BAR 475 * register 'idx' of an emulated pci device. 476 */ 477 static void 478 modify_bar_registration(struct pci_devinst *pi, int idx, int registration) 479 { 480 int error; 481 struct inout_port iop; 482 struct mem_range mr; 483 484 switch (pi->pi_bar[idx].type) { 485 case PCIBAR_IO: 486 bzero(&iop, sizeof(struct inout_port)); 487 iop.name = pi->pi_name; 488 iop.port = pi->pi_bar[idx].addr; 489 iop.size = pi->pi_bar[idx].size; 490 if (registration) { 491 iop.flags = IOPORT_F_INOUT; 492 iop.handler = pci_emul_io_handler; 493 iop.arg = pi; 494 error = register_inout(&iop); 495 } else 496 error = unregister_inout(&iop); 497 break; 498 case PCIBAR_MEM32: 499 case PCIBAR_MEM64: 500 bzero(&mr, sizeof(struct mem_range)); 501 mr.name = pi->pi_name; 502 mr.base = pi->pi_bar[idx].addr; 503 mr.size = pi->pi_bar[idx].size; 504 if (registration) { 505 mr.flags = MEM_F_RW; 506 mr.handler = pci_emul_mem_handler; 507 mr.arg1 = pi; 508 mr.arg2 = idx; 509 error = register_mem(&mr); 510 } else 511 error = unregister_mem(&mr); 512 break; 513 default: 514 error = EINVAL; 515 break; 516 } 517 assert(error == 0); 518 } 519 520 static void 521 unregister_bar(struct pci_devinst *pi, int idx) 522 { 523 524 modify_bar_registration(pi, idx, 0); 525 } 526 527 static void 528 register_bar(struct pci_devinst *pi, int idx) 529 { 530 531 modify_bar_registration(pi, idx, 1); 532 } 533 534 /* Are we decoding i/o port accesses for the emulated pci device? */ 535 static int 536 porten(struct pci_devinst *pi) 537 { 538 uint16_t cmd; 539 540 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 541 542 return (cmd & PCIM_CMD_PORTEN); 543 } 544 545 /* Are we decoding memory accesses for the emulated pci device? */ 546 static int 547 memen(struct pci_devinst *pi) 548 { 549 uint16_t cmd; 550 551 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 552 553 return (cmd & PCIM_CMD_MEMEN); 554 } 555 556 /* 557 * Update the MMIO or I/O address that is decoded by the BAR register. 558 * 559 * If the pci device has enabled the address space decoding then intercept 560 * the address range decoded by the BAR register. 561 */ 562 static void 563 update_bar_address(struct pci_devinst *pi, uint64_t addr, int idx, int type) 564 { 565 int decode; 566 567 if (pi->pi_bar[idx].type == PCIBAR_IO) 568 decode = porten(pi); 569 else 570 decode = memen(pi); 571 572 if (decode) 573 unregister_bar(pi, idx); 574 575 switch (type) { 576 case PCIBAR_IO: 577 case PCIBAR_MEM32: 578 pi->pi_bar[idx].addr = addr; 579 break; 580 case PCIBAR_MEM64: 581 pi->pi_bar[idx].addr &= ~0xffffffffUL; 582 pi->pi_bar[idx].addr |= addr; 583 break; 584 case PCIBAR_MEMHI64: 585 pi->pi_bar[idx].addr &= 0xffffffff; 586 pi->pi_bar[idx].addr |= addr; 587 break; 588 default: 589 assert(0); 590 } 591 592 if (decode) 593 register_bar(pi, idx); 594 } 595 596 int 597 pci_emul_alloc_pbar(struct pci_devinst *pdi, int idx, uint64_t hostbase, 598 enum pcibar_type type, uint64_t size) 599 { 600 uint64_t *baseptr = NULL; 601 uint64_t limit = 0, lobits = 0; 602 uint64_t addr, mask, bar; 603 int error; 604 605 assert(idx >= 0 && idx <= PCI_BARMAX); 606 607 if ((size & (size - 1)) != 0) 608 size = 1UL << flsl(size); /* round up to a power of 2 */ 609 610 /* Enforce minimum BAR sizes required by the PCI standard */ 611 if (type == PCIBAR_IO) { 612 if (size < 4) 613 size = 4; 614 } else { 615 if (size < 16) 616 size = 16; 617 } 618 619 switch (type) { 620 case PCIBAR_NONE: 621 baseptr = NULL; 622 addr = mask = lobits = 0; 623 break; 624 case PCIBAR_IO: 625 baseptr = &pci_emul_iobase; 626 limit = PCI_EMUL_IOLIMIT; 627 mask = PCIM_BAR_IO_BASE; 628 lobits = PCIM_BAR_IO_SPACE; 629 break; 630 case PCIBAR_MEM64: 631 /* 632 * XXX 633 * Some drivers do not work well if the 64-bit BAR is allocated 634 * above 4GB. Allow for this by allocating small requests under 635 * 4GB unless then allocation size is larger than some arbitrary 636 * number (32MB currently). 637 */ 638 if (size > 32 * 1024 * 1024) { 639 /* 640 * XXX special case for device requiring peer-peer DMA 641 */ 642 if (size == 0x100000000UL) 643 baseptr = &hostbase; 644 else 645 baseptr = &pci_emul_membase64; 646 limit = PCI_EMUL_MEMLIMIT64; 647 mask = PCIM_BAR_MEM_BASE; 648 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 649 PCIM_BAR_MEM_PREFETCH; 650 break; 651 } else { 652 baseptr = &pci_emul_membase32; 653 limit = PCI_EMUL_MEMLIMIT32; 654 mask = PCIM_BAR_MEM_BASE; 655 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64; 656 } 657 break; 658 case PCIBAR_MEM32: 659 baseptr = &pci_emul_membase32; 660 limit = PCI_EMUL_MEMLIMIT32; 661 mask = PCIM_BAR_MEM_BASE; 662 lobits = PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 663 break; 664 default: 665 printf("pci_emul_alloc_base: invalid bar type %d\n", type); 666 #ifdef FreeBSD 667 assert(0); 668 #else 669 abort(); 670 #endif 671 } 672 673 if (baseptr != NULL) { 674 error = pci_emul_alloc_resource(baseptr, limit, size, &addr); 675 if (error != 0) 676 return (error); 677 } 678 679 pdi->pi_bar[idx].type = type; 680 pdi->pi_bar[idx].addr = addr; 681 pdi->pi_bar[idx].size = size; 682 683 /* Initialize the BAR register in config space */ 684 bar = (addr & mask) | lobits; 685 pci_set_cfgdata32(pdi, PCIR_BAR(idx), bar); 686 687 if (type == PCIBAR_MEM64) { 688 assert(idx + 1 <= PCI_BARMAX); 689 pdi->pi_bar[idx + 1].type = PCIBAR_MEMHI64; 690 pci_set_cfgdata32(pdi, PCIR_BAR(idx + 1), bar >> 32); 691 } 692 693 register_bar(pdi, idx); 694 695 return (0); 696 } 697 698 #define CAP_START_OFFSET 0x40 699 static int 700 pci_emul_add_capability(struct pci_devinst *pi, u_char *capdata, int caplen) 701 { 702 int i, capoff, reallen; 703 uint16_t sts; 704 705 assert(caplen > 0); 706 707 reallen = roundup2(caplen, 4); /* dword aligned */ 708 709 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 710 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) 711 capoff = CAP_START_OFFSET; 712 else 713 capoff = pi->pi_capend + 1; 714 715 /* Check if we have enough space */ 716 if (capoff + reallen > PCI_REGMAX + 1) 717 return (-1); 718 719 /* Set the previous capability pointer */ 720 if ((sts & PCIM_STATUS_CAPPRESENT) == 0) { 721 pci_set_cfgdata8(pi, PCIR_CAP_PTR, capoff); 722 pci_set_cfgdata16(pi, PCIR_STATUS, sts|PCIM_STATUS_CAPPRESENT); 723 } else 724 pci_set_cfgdata8(pi, pi->pi_prevcap + 1, capoff); 725 726 /* Copy the capability */ 727 for (i = 0; i < caplen; i++) 728 pci_set_cfgdata8(pi, capoff + i, capdata[i]); 729 730 /* Set the next capability pointer */ 731 pci_set_cfgdata8(pi, capoff + 1, 0); 732 733 pi->pi_prevcap = capoff; 734 pi->pi_capend = capoff + reallen - 1; 735 return (0); 736 } 737 738 static struct pci_devemu * 739 pci_emul_finddev(char *name) 740 { 741 struct pci_devemu **pdpp, *pdp; 742 743 SET_FOREACH(pdpp, pci_devemu_set) { 744 pdp = *pdpp; 745 if (!strcmp(pdp->pe_emu, name)) { 746 return (pdp); 747 } 748 } 749 750 return (NULL); 751 } 752 753 static int 754 pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot, 755 int func, struct funcinfo *fi) 756 { 757 struct pci_devinst *pdi; 758 int err; 759 760 pdi = calloc(1, sizeof(struct pci_devinst)); 761 762 pdi->pi_vmctx = ctx; 763 pdi->pi_bus = bus; 764 pdi->pi_slot = slot; 765 pdi->pi_func = func; 766 pthread_mutex_init(&pdi->pi_lintr.lock, NULL); 767 pdi->pi_lintr.pin = 0; 768 pdi->pi_lintr.state = IDLE; 769 pdi->pi_lintr.pirq_pin = 0; 770 pdi->pi_lintr.ioapic_irq = 0; 771 pdi->pi_d = pde; 772 snprintf(pdi->pi_name, PI_NAMESZ, "%s-pci-%d", pde->pe_emu, slot); 773 774 /* Disable legacy interrupts */ 775 pci_set_cfgdata8(pdi, PCIR_INTLINE, 255); 776 pci_set_cfgdata8(pdi, PCIR_INTPIN, 0); 777 778 pci_set_cfgdata8(pdi, PCIR_COMMAND, 779 PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 780 781 err = (*pde->pe_init)(ctx, pdi, fi->fi_param); 782 if (err == 0) 783 fi->fi_devi = pdi; 784 else 785 free(pdi); 786 787 return (err); 788 } 789 790 void 791 pci_populate_msicap(struct msicap *msicap, int msgnum, int nextptr) 792 { 793 int mmc; 794 795 /* Number of msi messages must be a power of 2 between 1 and 32 */ 796 assert((msgnum & (msgnum - 1)) == 0 && msgnum >= 1 && msgnum <= 32); 797 mmc = ffs(msgnum) - 1; 798 799 bzero(msicap, sizeof(struct msicap)); 800 msicap->capid = PCIY_MSI; 801 msicap->nextptr = nextptr; 802 msicap->msgctrl = PCIM_MSICTRL_64BIT | (mmc << 1); 803 } 804 805 int 806 pci_emul_add_msicap(struct pci_devinst *pi, int msgnum) 807 { 808 struct msicap msicap; 809 810 pci_populate_msicap(&msicap, msgnum, 0); 811 812 return (pci_emul_add_capability(pi, (u_char *)&msicap, sizeof(msicap))); 813 } 814 815 static void 816 pci_populate_msixcap(struct msixcap *msixcap, int msgnum, int barnum, 817 uint32_t msix_tab_size) 818 { 819 820 assert(msix_tab_size % 4096 == 0); 821 822 bzero(msixcap, sizeof(struct msixcap)); 823 msixcap->capid = PCIY_MSIX; 824 825 /* 826 * Message Control Register, all fields set to 827 * zero except for the Table Size. 828 * Note: Table size N is encoded as N-1 829 */ 830 msixcap->msgctrl = msgnum - 1; 831 832 /* 833 * MSI-X BAR setup: 834 * - MSI-X table start at offset 0 835 * - PBA table starts at a 4K aligned offset after the MSI-X table 836 */ 837 msixcap->table_info = barnum & PCIM_MSIX_BIR_MASK; 838 msixcap->pba_info = msix_tab_size | (barnum & PCIM_MSIX_BIR_MASK); 839 } 840 841 static void 842 pci_msix_table_init(struct pci_devinst *pi, int table_entries) 843 { 844 int i, table_size; 845 846 assert(table_entries > 0); 847 assert(table_entries <= MAX_MSIX_TABLE_ENTRIES); 848 849 table_size = table_entries * MSIX_TABLE_ENTRY_SIZE; 850 pi->pi_msix.table = calloc(1, table_size); 851 852 /* set mask bit of vector control register */ 853 for (i = 0; i < table_entries; i++) 854 pi->pi_msix.table[i].vector_control |= PCIM_MSIX_VCTRL_MASK; 855 } 856 857 int 858 pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum) 859 { 860 uint32_t tab_size; 861 struct msixcap msixcap; 862 863 assert(msgnum >= 1 && msgnum <= MAX_MSIX_TABLE_ENTRIES); 864 assert(barnum >= 0 && barnum <= PCIR_MAX_BAR_0); 865 866 tab_size = msgnum * MSIX_TABLE_ENTRY_SIZE; 867 868 /* Align table size to nearest 4K */ 869 tab_size = roundup2(tab_size, 4096); 870 871 pi->pi_msix.table_bar = barnum; 872 pi->pi_msix.pba_bar = barnum; 873 pi->pi_msix.table_offset = 0; 874 pi->pi_msix.table_count = msgnum; 875 pi->pi_msix.pba_offset = tab_size; 876 pi->pi_msix.pba_size = PBA_SIZE(msgnum); 877 878 pci_msix_table_init(pi, msgnum); 879 880 pci_populate_msixcap(&msixcap, msgnum, barnum, tab_size); 881 882 /* allocate memory for MSI-X Table and PBA */ 883 pci_emul_alloc_bar(pi, barnum, PCIBAR_MEM32, 884 tab_size + pi->pi_msix.pba_size); 885 886 return (pci_emul_add_capability(pi, (u_char *)&msixcap, 887 sizeof(msixcap))); 888 } 889 890 void 891 msixcap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 892 int bytes, uint32_t val) 893 { 894 uint16_t msgctrl, rwmask; 895 int off; 896 897 off = offset - capoff; 898 /* Message Control Register */ 899 if (off == 2 && bytes == 2) { 900 rwmask = PCIM_MSIXCTRL_MSIX_ENABLE | PCIM_MSIXCTRL_FUNCTION_MASK; 901 msgctrl = pci_get_cfgdata16(pi, offset); 902 msgctrl &= ~rwmask; 903 msgctrl |= val & rwmask; 904 val = msgctrl; 905 906 pi->pi_msix.enabled = val & PCIM_MSIXCTRL_MSIX_ENABLE; 907 pi->pi_msix.function_mask = val & PCIM_MSIXCTRL_FUNCTION_MASK; 908 pci_lintr_update(pi); 909 } 910 911 CFGWRITE(pi, offset, val, bytes); 912 } 913 914 void 915 msicap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 916 int bytes, uint32_t val) 917 { 918 uint16_t msgctrl, rwmask, msgdata, mme; 919 uint32_t addrlo; 920 921 /* 922 * If guest is writing to the message control register make sure 923 * we do not overwrite read-only fields. 924 */ 925 if ((offset - capoff) == 2 && bytes == 2) { 926 rwmask = PCIM_MSICTRL_MME_MASK | PCIM_MSICTRL_MSI_ENABLE; 927 msgctrl = pci_get_cfgdata16(pi, offset); 928 msgctrl &= ~rwmask; 929 msgctrl |= val & rwmask; 930 val = msgctrl; 931 932 addrlo = pci_get_cfgdata32(pi, capoff + 4); 933 if (msgctrl & PCIM_MSICTRL_64BIT) 934 msgdata = pci_get_cfgdata16(pi, capoff + 12); 935 else 936 msgdata = pci_get_cfgdata16(pi, capoff + 8); 937 938 mme = msgctrl & PCIM_MSICTRL_MME_MASK; 939 pi->pi_msi.enabled = msgctrl & PCIM_MSICTRL_MSI_ENABLE ? 1 : 0; 940 if (pi->pi_msi.enabled) { 941 pi->pi_msi.addr = addrlo; 942 pi->pi_msi.msg_data = msgdata; 943 pi->pi_msi.maxmsgnum = 1 << (mme >> 4); 944 } else { 945 pi->pi_msi.maxmsgnum = 0; 946 } 947 pci_lintr_update(pi); 948 } 949 950 CFGWRITE(pi, offset, val, bytes); 951 } 952 953 void 954 pciecap_cfgwrite(struct pci_devinst *pi, int capoff, int offset, 955 int bytes, uint32_t val) 956 { 957 958 /* XXX don't write to the readonly parts */ 959 CFGWRITE(pi, offset, val, bytes); 960 } 961 962 #define PCIECAP_VERSION 0x2 963 int 964 pci_emul_add_pciecap(struct pci_devinst *pi, int type) 965 { 966 int err; 967 struct pciecap pciecap; 968 969 if (type != PCIEM_TYPE_ROOT_PORT) 970 return (-1); 971 972 bzero(&pciecap, sizeof(pciecap)); 973 974 pciecap.capid = PCIY_EXPRESS; 975 pciecap.pcie_capabilities = PCIECAP_VERSION | PCIEM_TYPE_ROOT_PORT; 976 pciecap.link_capabilities = 0x411; /* gen1, x1 */ 977 pciecap.link_status = 0x11; /* gen1, x1 */ 978 979 err = pci_emul_add_capability(pi, (u_char *)&pciecap, sizeof(pciecap)); 980 return (err); 981 } 982 983 /* 984 * This function assumes that 'coff' is in the capabilities region of the 985 * config space. 986 */ 987 static void 988 pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes, uint32_t val) 989 { 990 int capid; 991 uint8_t capoff, nextoff; 992 993 /* Do not allow un-aligned writes */ 994 if ((offset & (bytes - 1)) != 0) 995 return; 996 997 /* Find the capability that we want to update */ 998 capoff = CAP_START_OFFSET; 999 while (1) { 1000 nextoff = pci_get_cfgdata8(pi, capoff + 1); 1001 if (nextoff == 0) 1002 break; 1003 if (offset >= capoff && offset < nextoff) 1004 break; 1005 1006 capoff = nextoff; 1007 } 1008 assert(offset >= capoff); 1009 1010 /* 1011 * Capability ID and Next Capability Pointer are readonly. 1012 * However, some o/s's do 4-byte writes that include these. 1013 * For this case, trim the write back to 2 bytes and adjust 1014 * the data. 1015 */ 1016 if (offset == capoff || offset == capoff + 1) { 1017 if (offset == capoff && bytes == 4) { 1018 bytes = 2; 1019 offset += 2; 1020 val >>= 16; 1021 } else 1022 return; 1023 } 1024 1025 capid = pci_get_cfgdata8(pi, capoff); 1026 switch (capid) { 1027 case PCIY_MSI: 1028 msicap_cfgwrite(pi, capoff, offset, bytes, val); 1029 break; 1030 case PCIY_MSIX: 1031 msixcap_cfgwrite(pi, capoff, offset, bytes, val); 1032 break; 1033 case PCIY_EXPRESS: 1034 pciecap_cfgwrite(pi, capoff, offset, bytes, val); 1035 break; 1036 default: 1037 break; 1038 } 1039 } 1040 1041 static int 1042 pci_emul_iscap(struct pci_devinst *pi, int offset) 1043 { 1044 uint16_t sts; 1045 1046 sts = pci_get_cfgdata16(pi, PCIR_STATUS); 1047 if ((sts & PCIM_STATUS_CAPPRESENT) != 0) { 1048 if (offset >= CAP_START_OFFSET && offset <= pi->pi_capend) 1049 return (1); 1050 } 1051 return (0); 1052 } 1053 1054 static int 1055 pci_emul_fallback_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1056 int size, uint64_t *val, void *arg1, long arg2) 1057 { 1058 /* 1059 * Ignore writes; return 0xff's for reads. The mem read code 1060 * will take care of truncating to the correct size. 1061 */ 1062 if (dir == MEM_F_READ) { 1063 *val = 0xffffffffffffffff; 1064 } 1065 1066 return (0); 1067 } 1068 1069 static int 1070 pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu, int dir, uint64_t addr, 1071 int bytes, uint64_t *val, void *arg1, long arg2) 1072 { 1073 int bus, slot, func, coff, in; 1074 1075 coff = addr & 0xfff; 1076 func = (addr >> 12) & 0x7; 1077 slot = (addr >> 15) & 0x1f; 1078 bus = (addr >> 20) & 0xff; 1079 in = (dir == MEM_F_READ); 1080 if (in) 1081 *val = ~0UL; 1082 pci_cfgrw(ctx, vcpu, in, bus, slot, func, coff, bytes, (uint32_t *)val); 1083 return (0); 1084 } 1085 1086 uint64_t 1087 pci_ecfg_base(void) 1088 { 1089 1090 return (PCI_EMUL_ECFG_BASE); 1091 } 1092 1093 #define BUSIO_ROUNDUP 32 1094 #define BUSMEM_ROUNDUP (1024 * 1024) 1095 1096 int 1097 init_pci(struct vmctx *ctx) 1098 { 1099 struct mem_range mr; 1100 struct pci_devemu *pde; 1101 struct businfo *bi; 1102 struct slotinfo *si; 1103 struct funcinfo *fi; 1104 size_t lowmem; 1105 int bus, slot, func; 1106 int error; 1107 1108 pci_emul_iobase = PCI_EMUL_IOBASE; 1109 pci_emul_membase32 = vm_get_lowmem_limit(ctx); 1110 pci_emul_membase64 = PCI_EMUL_MEMBASE64; 1111 1112 for (bus = 0; bus < MAXBUSES; bus++) { 1113 if ((bi = pci_businfo[bus]) == NULL) 1114 continue; 1115 /* 1116 * Keep track of the i/o and memory resources allocated to 1117 * this bus. 1118 */ 1119 bi->iobase = pci_emul_iobase; 1120 bi->membase32 = pci_emul_membase32; 1121 bi->membase64 = pci_emul_membase64; 1122 1123 for (slot = 0; slot < MAXSLOTS; slot++) { 1124 si = &bi->slotinfo[slot]; 1125 for (func = 0; func < MAXFUNCS; func++) { 1126 fi = &si->si_funcs[func]; 1127 if (fi->fi_name == NULL) 1128 continue; 1129 pde = pci_emul_finddev(fi->fi_name); 1130 assert(pde != NULL); 1131 error = pci_emul_init(ctx, pde, bus, slot, 1132 func, fi); 1133 if (error) 1134 return (error); 1135 } 1136 } 1137 1138 /* 1139 * Add some slop to the I/O and memory resources decoded by 1140 * this bus to give a guest some flexibility if it wants to 1141 * reprogram the BARs. 1142 */ 1143 pci_emul_iobase += BUSIO_ROUNDUP; 1144 pci_emul_iobase = roundup2(pci_emul_iobase, BUSIO_ROUNDUP); 1145 bi->iolimit = pci_emul_iobase; 1146 1147 pci_emul_membase32 += BUSMEM_ROUNDUP; 1148 pci_emul_membase32 = roundup2(pci_emul_membase32, 1149 BUSMEM_ROUNDUP); 1150 bi->memlimit32 = pci_emul_membase32; 1151 1152 pci_emul_membase64 += BUSMEM_ROUNDUP; 1153 pci_emul_membase64 = roundup2(pci_emul_membase64, 1154 BUSMEM_ROUNDUP); 1155 bi->memlimit64 = pci_emul_membase64; 1156 } 1157 1158 /* 1159 * PCI backends are initialized before routing INTx interrupts 1160 * so that LPC devices are able to reserve ISA IRQs before 1161 * routing PIRQ pins. 1162 */ 1163 for (bus = 0; bus < MAXBUSES; bus++) { 1164 if ((bi = pci_businfo[bus]) == NULL) 1165 continue; 1166 1167 for (slot = 0; slot < MAXSLOTS; slot++) { 1168 si = &bi->slotinfo[slot]; 1169 for (func = 0; func < MAXFUNCS; func++) { 1170 fi = &si->si_funcs[func]; 1171 if (fi->fi_devi == NULL) 1172 continue; 1173 pci_lintr_route(fi->fi_devi); 1174 } 1175 } 1176 } 1177 lpc_pirq_routed(); 1178 1179 /* 1180 * The guest physical memory map looks like the following: 1181 * [0, lowmem) guest system memory 1182 * [lowmem, lowmem_limit) memory hole (may be absent) 1183 * [lowmem_limit, 0xE0000000) PCI hole (32-bit BAR allocation) 1184 * [0xE0000000, 0xF0000000) PCI extended config window 1185 * [0xF0000000, 4GB) LAPIC, IOAPIC, HPET, firmware 1186 * [4GB, 4GB + highmem) 1187 */ 1188 1189 /* 1190 * Accesses to memory addresses that are not allocated to system 1191 * memory or PCI devices return 0xff's. 1192 */ 1193 lowmem = vm_get_lowmem_size(ctx); 1194 bzero(&mr, sizeof(struct mem_range)); 1195 mr.name = "PCI hole"; 1196 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1197 mr.base = lowmem; 1198 mr.size = (4ULL * 1024 * 1024 * 1024) - lowmem; 1199 mr.handler = pci_emul_fallback_handler; 1200 error = register_mem_fallback(&mr); 1201 assert(error == 0); 1202 1203 /* PCI extended config space */ 1204 bzero(&mr, sizeof(struct mem_range)); 1205 mr.name = "PCI ECFG"; 1206 mr.flags = MEM_F_RW | MEM_F_IMMUTABLE; 1207 mr.base = PCI_EMUL_ECFG_BASE; 1208 mr.size = PCI_EMUL_ECFG_SIZE; 1209 mr.handler = pci_emul_ecfg_handler; 1210 error = register_mem(&mr); 1211 assert(error == 0); 1212 1213 return (0); 1214 } 1215 1216 static void 1217 pci_apic_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1218 void *arg) 1219 { 1220 1221 dsdt_line(" Package ()"); 1222 dsdt_line(" {"); 1223 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1224 dsdt_line(" 0x%02X,", pin - 1); 1225 dsdt_line(" Zero,"); 1226 dsdt_line(" 0x%X", ioapic_irq); 1227 dsdt_line(" },"); 1228 } 1229 1230 static void 1231 pci_pirq_prt_entry(int bus, int slot, int pin, int pirq_pin, int ioapic_irq, 1232 void *arg) 1233 { 1234 char *name; 1235 1236 name = lpc_pirq_name(pirq_pin); 1237 if (name == NULL) 1238 return; 1239 dsdt_line(" Package ()"); 1240 dsdt_line(" {"); 1241 dsdt_line(" 0x%X,", slot << 16 | 0xffff); 1242 dsdt_line(" 0x%02X,", pin - 1); 1243 dsdt_line(" %s,", name); 1244 dsdt_line(" 0x00"); 1245 dsdt_line(" },"); 1246 free(name); 1247 } 1248 1249 /* 1250 * A bhyve virtual machine has a flat PCI hierarchy with a root port 1251 * corresponding to each PCI bus. 1252 */ 1253 static void 1254 pci_bus_write_dsdt(int bus) 1255 { 1256 struct businfo *bi; 1257 struct slotinfo *si; 1258 struct pci_devinst *pi; 1259 int count, func, slot; 1260 1261 /* 1262 * If there are no devices on this 'bus' then just return. 1263 */ 1264 if ((bi = pci_businfo[bus]) == NULL) { 1265 /* 1266 * Bus 0 is special because it decodes the I/O ports used 1267 * for PCI config space access even if there are no devices 1268 * on it. 1269 */ 1270 if (bus != 0) 1271 return; 1272 } 1273 1274 dsdt_line(" Device (PC%02X)", bus); 1275 dsdt_line(" {"); 1276 dsdt_line(" Name (_HID, EisaId (\"PNP0A03\"))"); 1277 dsdt_line(" Name (_ADR, Zero)"); 1278 1279 dsdt_line(" Method (_BBN, 0, NotSerialized)"); 1280 dsdt_line(" {"); 1281 dsdt_line(" Return (0x%08X)", bus); 1282 dsdt_line(" }"); 1283 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 1284 dsdt_line(" {"); 1285 dsdt_line(" WordBusNumber (ResourceProducer, MinFixed, " 1286 "MaxFixed, PosDecode,"); 1287 dsdt_line(" 0x0000, // Granularity"); 1288 dsdt_line(" 0x%04X, // Range Minimum", bus); 1289 dsdt_line(" 0x%04X, // Range Maximum", bus); 1290 dsdt_line(" 0x0000, // Translation Offset"); 1291 dsdt_line(" 0x0001, // Length"); 1292 dsdt_line(" ,, )"); 1293 1294 if (bus == 0) { 1295 dsdt_indent(3); 1296 dsdt_fixed_ioport(0xCF8, 8); 1297 dsdt_unindent(3); 1298 1299 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1300 "PosDecode, EntireRange,"); 1301 dsdt_line(" 0x0000, // Granularity"); 1302 dsdt_line(" 0x0000, // Range Minimum"); 1303 dsdt_line(" 0x0CF7, // Range Maximum"); 1304 dsdt_line(" 0x0000, // Translation Offset"); 1305 dsdt_line(" 0x0CF8, // Length"); 1306 dsdt_line(" ,, , TypeStatic)"); 1307 1308 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1309 "PosDecode, EntireRange,"); 1310 dsdt_line(" 0x0000, // Granularity"); 1311 dsdt_line(" 0x0D00, // Range Minimum"); 1312 dsdt_line(" 0x%04X, // Range Maximum", 1313 PCI_EMUL_IOBASE - 1); 1314 dsdt_line(" 0x0000, // Translation Offset"); 1315 dsdt_line(" 0x%04X, // Length", 1316 PCI_EMUL_IOBASE - 0x0D00); 1317 dsdt_line(" ,, , TypeStatic)"); 1318 1319 if (bi == NULL) { 1320 dsdt_line(" })"); 1321 goto done; 1322 } 1323 } 1324 assert(bi != NULL); 1325 1326 /* i/o window */ 1327 dsdt_line(" WordIO (ResourceProducer, MinFixed, MaxFixed, " 1328 "PosDecode, EntireRange,"); 1329 dsdt_line(" 0x0000, // Granularity"); 1330 dsdt_line(" 0x%04X, // Range Minimum", bi->iobase); 1331 dsdt_line(" 0x%04X, // Range Maximum", 1332 bi->iolimit - 1); 1333 dsdt_line(" 0x0000, // Translation Offset"); 1334 dsdt_line(" 0x%04X, // Length", 1335 bi->iolimit - bi->iobase); 1336 dsdt_line(" ,, , TypeStatic)"); 1337 1338 /* mmio window (32-bit) */ 1339 dsdt_line(" DWordMemory (ResourceProducer, PosDecode, " 1340 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1341 dsdt_line(" 0x00000000, // Granularity"); 1342 dsdt_line(" 0x%08X, // Range Minimum\n", bi->membase32); 1343 dsdt_line(" 0x%08X, // Range Maximum\n", 1344 bi->memlimit32 - 1); 1345 dsdt_line(" 0x00000000, // Translation Offset"); 1346 dsdt_line(" 0x%08X, // Length\n", 1347 bi->memlimit32 - bi->membase32); 1348 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1349 1350 /* mmio window (64-bit) */ 1351 dsdt_line(" QWordMemory (ResourceProducer, PosDecode, " 1352 "MinFixed, MaxFixed, NonCacheable, ReadWrite,"); 1353 dsdt_line(" 0x0000000000000000, // Granularity"); 1354 dsdt_line(" 0x%016lX, // Range Minimum\n", bi->membase64); 1355 dsdt_line(" 0x%016lX, // Range Maximum\n", 1356 bi->memlimit64 - 1); 1357 dsdt_line(" 0x0000000000000000, // Translation Offset"); 1358 dsdt_line(" 0x%016lX, // Length\n", 1359 bi->memlimit64 - bi->membase64); 1360 dsdt_line(" ,, , AddressRangeMemory, TypeStatic)"); 1361 dsdt_line(" })"); 1362 1363 count = pci_count_lintr(bus); 1364 if (count != 0) { 1365 dsdt_indent(2); 1366 dsdt_line("Name (PPRT, Package ()"); 1367 dsdt_line("{"); 1368 pci_walk_lintr(bus, pci_pirq_prt_entry, NULL); 1369 dsdt_line("})"); 1370 dsdt_line("Name (APRT, Package ()"); 1371 dsdt_line("{"); 1372 pci_walk_lintr(bus, pci_apic_prt_entry, NULL); 1373 dsdt_line("})"); 1374 dsdt_line("Method (_PRT, 0, NotSerialized)"); 1375 dsdt_line("{"); 1376 dsdt_line(" If (PICM)"); 1377 dsdt_line(" {"); 1378 dsdt_line(" Return (APRT)"); 1379 dsdt_line(" }"); 1380 dsdt_line(" Else"); 1381 dsdt_line(" {"); 1382 dsdt_line(" Return (PPRT)"); 1383 dsdt_line(" }"); 1384 dsdt_line("}"); 1385 dsdt_unindent(2); 1386 } 1387 1388 dsdt_indent(2); 1389 for (slot = 0; slot < MAXSLOTS; slot++) { 1390 si = &bi->slotinfo[slot]; 1391 for (func = 0; func < MAXFUNCS; func++) { 1392 pi = si->si_funcs[func].fi_devi; 1393 if (pi != NULL && pi->pi_d->pe_write_dsdt != NULL) 1394 pi->pi_d->pe_write_dsdt(pi); 1395 } 1396 } 1397 dsdt_unindent(2); 1398 done: 1399 dsdt_line(" }"); 1400 } 1401 1402 void 1403 pci_write_dsdt(void) 1404 { 1405 int bus; 1406 1407 dsdt_indent(1); 1408 dsdt_line("Name (PICM, 0x00)"); 1409 dsdt_line("Method (_PIC, 1, NotSerialized)"); 1410 dsdt_line("{"); 1411 dsdt_line(" Store (Arg0, PICM)"); 1412 dsdt_line("}"); 1413 dsdt_line(""); 1414 dsdt_line("Scope (_SB)"); 1415 dsdt_line("{"); 1416 for (bus = 0; bus < MAXBUSES; bus++) 1417 pci_bus_write_dsdt(bus); 1418 dsdt_line("}"); 1419 dsdt_unindent(1); 1420 } 1421 1422 int 1423 pci_bus_configured(int bus) 1424 { 1425 assert(bus >= 0 && bus < MAXBUSES); 1426 return (pci_businfo[bus] != NULL); 1427 } 1428 1429 int 1430 pci_msi_enabled(struct pci_devinst *pi) 1431 { 1432 return (pi->pi_msi.enabled); 1433 } 1434 1435 int 1436 pci_msi_maxmsgnum(struct pci_devinst *pi) 1437 { 1438 if (pi->pi_msi.enabled) 1439 return (pi->pi_msi.maxmsgnum); 1440 else 1441 return (0); 1442 } 1443 1444 int 1445 pci_msix_enabled(struct pci_devinst *pi) 1446 { 1447 1448 return (pi->pi_msix.enabled && !pi->pi_msi.enabled); 1449 } 1450 1451 void 1452 pci_generate_msix(struct pci_devinst *pi, int index) 1453 { 1454 struct msix_table_entry *mte; 1455 1456 if (!pci_msix_enabled(pi)) 1457 return; 1458 1459 if (pi->pi_msix.function_mask) 1460 return; 1461 1462 if (index >= pi->pi_msix.table_count) 1463 return; 1464 1465 mte = &pi->pi_msix.table[index]; 1466 if ((mte->vector_control & PCIM_MSIX_VCTRL_MASK) == 0) { 1467 /* XXX Set PBA bit if interrupt is disabled */ 1468 vm_lapic_msi(pi->pi_vmctx, mte->addr, mte->msg_data); 1469 } 1470 } 1471 1472 void 1473 pci_generate_msi(struct pci_devinst *pi, int index) 1474 { 1475 1476 if (pci_msi_enabled(pi) && index < pci_msi_maxmsgnum(pi)) { 1477 vm_lapic_msi(pi->pi_vmctx, pi->pi_msi.addr, 1478 pi->pi_msi.msg_data + index); 1479 } 1480 } 1481 1482 static bool 1483 pci_lintr_permitted(struct pci_devinst *pi) 1484 { 1485 uint16_t cmd; 1486 1487 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); 1488 return (!(pi->pi_msi.enabled || pi->pi_msix.enabled || 1489 (cmd & PCIM_CMD_INTxDIS))); 1490 } 1491 1492 void 1493 pci_lintr_request(struct pci_devinst *pi) 1494 { 1495 struct businfo *bi; 1496 struct slotinfo *si; 1497 int bestpin, bestcount, pin; 1498 1499 bi = pci_businfo[pi->pi_bus]; 1500 assert(bi != NULL); 1501 1502 /* 1503 * Just allocate a pin from our slot. The pin will be 1504 * assigned IRQs later when interrupts are routed. 1505 */ 1506 si = &bi->slotinfo[pi->pi_slot]; 1507 bestpin = 0; 1508 bestcount = si->si_intpins[0].ii_count; 1509 for (pin = 1; pin < 4; pin++) { 1510 if (si->si_intpins[pin].ii_count < bestcount) { 1511 bestpin = pin; 1512 bestcount = si->si_intpins[pin].ii_count; 1513 } 1514 } 1515 1516 si->si_intpins[bestpin].ii_count++; 1517 pi->pi_lintr.pin = bestpin + 1; 1518 pci_set_cfgdata8(pi, PCIR_INTPIN, bestpin + 1); 1519 } 1520 1521 static void 1522 pci_lintr_route(struct pci_devinst *pi) 1523 { 1524 struct businfo *bi; 1525 struct intxinfo *ii; 1526 1527 if (pi->pi_lintr.pin == 0) 1528 return; 1529 1530 bi = pci_businfo[pi->pi_bus]; 1531 assert(bi != NULL); 1532 ii = &bi->slotinfo[pi->pi_slot].si_intpins[pi->pi_lintr.pin - 1]; 1533 1534 /* 1535 * Attempt to allocate an I/O APIC pin for this intpin if one 1536 * is not yet assigned. 1537 */ 1538 if (ii->ii_ioapic_irq == 0) 1539 ii->ii_ioapic_irq = ioapic_pci_alloc_irq(pi); 1540 assert(ii->ii_ioapic_irq > 0); 1541 1542 /* 1543 * Attempt to allocate a PIRQ pin for this intpin if one is 1544 * not yet assigned. 1545 */ 1546 if (ii->ii_pirq_pin == 0) 1547 ii->ii_pirq_pin = pirq_alloc_pin(pi); 1548 assert(ii->ii_pirq_pin > 0); 1549 1550 pi->pi_lintr.ioapic_irq = ii->ii_ioapic_irq; 1551 pi->pi_lintr.pirq_pin = ii->ii_pirq_pin; 1552 pci_set_cfgdata8(pi, PCIR_INTLINE, pirq_irq(ii->ii_pirq_pin)); 1553 } 1554 1555 void 1556 pci_lintr_assert(struct pci_devinst *pi) 1557 { 1558 1559 assert(pi->pi_lintr.pin > 0); 1560 1561 pthread_mutex_lock(&pi->pi_lintr.lock); 1562 if (pi->pi_lintr.state == IDLE) { 1563 if (pci_lintr_permitted(pi)) { 1564 pi->pi_lintr.state = ASSERTED; 1565 pci_irq_assert(pi); 1566 } else 1567 pi->pi_lintr.state = PENDING; 1568 } 1569 pthread_mutex_unlock(&pi->pi_lintr.lock); 1570 } 1571 1572 void 1573 pci_lintr_deassert(struct pci_devinst *pi) 1574 { 1575 1576 assert(pi->pi_lintr.pin > 0); 1577 1578 pthread_mutex_lock(&pi->pi_lintr.lock); 1579 if (pi->pi_lintr.state == ASSERTED) { 1580 pi->pi_lintr.state = IDLE; 1581 pci_irq_deassert(pi); 1582 } else if (pi->pi_lintr.state == PENDING) 1583 pi->pi_lintr.state = IDLE; 1584 pthread_mutex_unlock(&pi->pi_lintr.lock); 1585 } 1586 1587 static void 1588 pci_lintr_update(struct pci_devinst *pi) 1589 { 1590 1591 pthread_mutex_lock(&pi->pi_lintr.lock); 1592 if (pi->pi_lintr.state == ASSERTED && !pci_lintr_permitted(pi)) { 1593 pci_irq_deassert(pi); 1594 pi->pi_lintr.state = PENDING; 1595 } else if (pi->pi_lintr.state == PENDING && pci_lintr_permitted(pi)) { 1596 pi->pi_lintr.state = ASSERTED; 1597 pci_irq_assert(pi); 1598 } 1599 pthread_mutex_unlock(&pi->pi_lintr.lock); 1600 } 1601 1602 int 1603 pci_count_lintr(int bus) 1604 { 1605 int count, slot, pin; 1606 struct slotinfo *slotinfo; 1607 1608 count = 0; 1609 if (pci_businfo[bus] != NULL) { 1610 for (slot = 0; slot < MAXSLOTS; slot++) { 1611 slotinfo = &pci_businfo[bus]->slotinfo[slot]; 1612 for (pin = 0; pin < 4; pin++) { 1613 if (slotinfo->si_intpins[pin].ii_count != 0) 1614 count++; 1615 } 1616 } 1617 } 1618 return (count); 1619 } 1620 1621 void 1622 pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg) 1623 { 1624 struct businfo *bi; 1625 struct slotinfo *si; 1626 struct intxinfo *ii; 1627 int slot, pin; 1628 1629 if ((bi = pci_businfo[bus]) == NULL) 1630 return; 1631 1632 for (slot = 0; slot < MAXSLOTS; slot++) { 1633 si = &bi->slotinfo[slot]; 1634 for (pin = 0; pin < 4; pin++) { 1635 ii = &si->si_intpins[pin]; 1636 if (ii->ii_count != 0) 1637 cb(bus, slot, pin + 1, ii->ii_pirq_pin, 1638 ii->ii_ioapic_irq, arg); 1639 } 1640 } 1641 } 1642 1643 /* 1644 * Return 1 if the emulated device in 'slot' is a multi-function device. 1645 * Return 0 otherwise. 1646 */ 1647 static int 1648 pci_emul_is_mfdev(int bus, int slot) 1649 { 1650 struct businfo *bi; 1651 struct slotinfo *si; 1652 int f, numfuncs; 1653 1654 numfuncs = 0; 1655 if ((bi = pci_businfo[bus]) != NULL) { 1656 si = &bi->slotinfo[slot]; 1657 for (f = 0; f < MAXFUNCS; f++) { 1658 if (si->si_funcs[f].fi_devi != NULL) { 1659 numfuncs++; 1660 } 1661 } 1662 } 1663 return (numfuncs > 1); 1664 } 1665 1666 /* 1667 * Ensure that the PCIM_MFDEV bit is properly set (or unset) depending on 1668 * whether or not is a multi-function being emulated in the pci 'slot'. 1669 */ 1670 static void 1671 pci_emul_hdrtype_fixup(int bus, int slot, int off, int bytes, uint32_t *rv) 1672 { 1673 int mfdev; 1674 1675 if (off <= PCIR_HDRTYPE && off + bytes > PCIR_HDRTYPE) { 1676 mfdev = pci_emul_is_mfdev(bus, slot); 1677 switch (bytes) { 1678 case 1: 1679 case 2: 1680 *rv &= ~PCIM_MFDEV; 1681 if (mfdev) { 1682 *rv |= PCIM_MFDEV; 1683 } 1684 break; 1685 case 4: 1686 *rv &= ~(PCIM_MFDEV << 16); 1687 if (mfdev) { 1688 *rv |= (PCIM_MFDEV << 16); 1689 } 1690 break; 1691 } 1692 } 1693 } 1694 1695 static void 1696 pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes) 1697 { 1698 int i, rshift; 1699 uint32_t cmd, cmd2, changed, old, readonly; 1700 1701 cmd = pci_get_cfgdata16(pi, PCIR_COMMAND); /* stash old value */ 1702 1703 /* 1704 * From PCI Local Bus Specification 3.0 sections 6.2.2 and 6.2.3. 1705 * 1706 * XXX Bits 8, 11, 12, 13, 14 and 15 in the status register are 1707 * 'write 1 to clear'. However these bits are not set to '1' by 1708 * any device emulation so it is simpler to treat them as readonly. 1709 */ 1710 rshift = (coff & 0x3) * 8; 1711 readonly = 0xFFFFF880 >> rshift; 1712 1713 old = CFGREAD(pi, coff, bytes); 1714 new &= ~readonly; 1715 new |= (old & readonly); 1716 CFGWRITE(pi, coff, new, bytes); /* update config */ 1717 1718 cmd2 = pci_get_cfgdata16(pi, PCIR_COMMAND); /* get updated value */ 1719 changed = cmd ^ cmd2; 1720 1721 /* 1722 * If the MMIO or I/O address space decoding has changed then 1723 * register/unregister all BARs that decode that address space. 1724 */ 1725 for (i = 0; i <= PCI_BARMAX; i++) { 1726 switch (pi->pi_bar[i].type) { 1727 case PCIBAR_NONE: 1728 case PCIBAR_MEMHI64: 1729 break; 1730 case PCIBAR_IO: 1731 /* I/O address space decoding changed? */ 1732 if (changed & PCIM_CMD_PORTEN) { 1733 if (porten(pi)) 1734 register_bar(pi, i); 1735 else 1736 unregister_bar(pi, i); 1737 } 1738 break; 1739 case PCIBAR_MEM32: 1740 case PCIBAR_MEM64: 1741 /* MMIO address space decoding changed? */ 1742 if (changed & PCIM_CMD_MEMEN) { 1743 if (memen(pi)) 1744 register_bar(pi, i); 1745 else 1746 unregister_bar(pi, i); 1747 } 1748 break; 1749 default: 1750 assert(0); 1751 } 1752 } 1753 1754 /* 1755 * If INTx has been unmasked and is pending, assert the 1756 * interrupt. 1757 */ 1758 pci_lintr_update(pi); 1759 } 1760 1761 static void 1762 pci_cfgrw(struct vmctx *ctx, int vcpu, int in, int bus, int slot, int func, 1763 int coff, int bytes, uint32_t *eax) 1764 { 1765 struct businfo *bi; 1766 struct slotinfo *si; 1767 struct pci_devinst *pi; 1768 struct pci_devemu *pe; 1769 int idx, needcfg; 1770 uint64_t addr, mask; 1771 uint64_t bar = 0; 1772 1773 if ((bi = pci_businfo[bus]) != NULL) { 1774 si = &bi->slotinfo[slot]; 1775 pi = si->si_funcs[func].fi_devi; 1776 } else 1777 pi = NULL; 1778 1779 /* 1780 * Just return if there is no device at this slot:func or if the 1781 * the guest is doing an un-aligned access. 1782 */ 1783 if (pi == NULL || (bytes != 1 && bytes != 2 && bytes != 4) || 1784 (coff & (bytes - 1)) != 0) { 1785 if (in) 1786 *eax = 0xffffffff; 1787 return; 1788 } 1789 1790 /* 1791 * Ignore all writes beyond the standard config space and return all 1792 * ones on reads. 1793 */ 1794 if (coff >= PCI_REGMAX + 1) { 1795 if (in) { 1796 *eax = 0xffffffff; 1797 /* 1798 * Extended capabilities begin at offset 256 in config 1799 * space. Absence of extended capabilities is signaled 1800 * with all 0s in the extended capability header at 1801 * offset 256. 1802 */ 1803 if (coff <= PCI_REGMAX + 4) 1804 *eax = 0x00000000; 1805 } 1806 return; 1807 } 1808 1809 pe = pi->pi_d; 1810 1811 /* 1812 * Config read 1813 */ 1814 if (in) { 1815 /* Let the device emulation override the default handler */ 1816 if (pe->pe_cfgread != NULL) { 1817 needcfg = pe->pe_cfgread(ctx, vcpu, pi, coff, bytes, 1818 eax); 1819 } else { 1820 needcfg = 1; 1821 } 1822 1823 if (needcfg) 1824 *eax = CFGREAD(pi, coff, bytes); 1825 1826 pci_emul_hdrtype_fixup(bus, slot, coff, bytes, eax); 1827 } else { 1828 /* Let the device emulation override the default handler */ 1829 if (pe->pe_cfgwrite != NULL && 1830 (*pe->pe_cfgwrite)(ctx, vcpu, pi, coff, bytes, *eax) == 0) 1831 return; 1832 1833 /* 1834 * Special handling for write to BAR registers 1835 */ 1836 if (coff >= PCIR_BAR(0) && coff < PCIR_BAR(PCI_BARMAX + 1)) { 1837 /* 1838 * Ignore writes to BAR registers that are not 1839 * 4-byte aligned. 1840 */ 1841 if (bytes != 4 || (coff & 0x3) != 0) 1842 return; 1843 idx = (coff - PCIR_BAR(0)) / 4; 1844 mask = ~(pi->pi_bar[idx].size - 1); 1845 switch (pi->pi_bar[idx].type) { 1846 case PCIBAR_NONE: 1847 pi->pi_bar[idx].addr = bar = 0; 1848 break; 1849 case PCIBAR_IO: 1850 addr = *eax & mask; 1851 addr &= 0xffff; 1852 bar = addr | PCIM_BAR_IO_SPACE; 1853 /* 1854 * Register the new BAR value for interception 1855 */ 1856 if (addr != pi->pi_bar[idx].addr) { 1857 update_bar_address(pi, addr, idx, 1858 PCIBAR_IO); 1859 } 1860 break; 1861 case PCIBAR_MEM32: 1862 addr = bar = *eax & mask; 1863 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_32; 1864 if (addr != pi->pi_bar[idx].addr) { 1865 update_bar_address(pi, addr, idx, 1866 PCIBAR_MEM32); 1867 } 1868 break; 1869 case PCIBAR_MEM64: 1870 addr = bar = *eax & mask; 1871 bar |= PCIM_BAR_MEM_SPACE | PCIM_BAR_MEM_64 | 1872 PCIM_BAR_MEM_PREFETCH; 1873 if (addr != (uint32_t)pi->pi_bar[idx].addr) { 1874 update_bar_address(pi, addr, idx, 1875 PCIBAR_MEM64); 1876 } 1877 break; 1878 case PCIBAR_MEMHI64: 1879 mask = ~(pi->pi_bar[idx - 1].size - 1); 1880 addr = ((uint64_t)*eax << 32) & mask; 1881 bar = addr >> 32; 1882 if (bar != pi->pi_bar[idx - 1].addr >> 32) { 1883 update_bar_address(pi, addr, idx - 1, 1884 PCIBAR_MEMHI64); 1885 } 1886 break; 1887 default: 1888 assert(0); 1889 } 1890 pci_set_cfgdata32(pi, coff, bar); 1891 1892 } else if (pci_emul_iscap(pi, coff)) { 1893 pci_emul_capwrite(pi, coff, bytes, *eax); 1894 } else if (coff >= PCIR_COMMAND && coff < PCIR_REVID) { 1895 pci_emul_cmdsts_write(pi, coff, *eax, bytes); 1896 } else { 1897 CFGWRITE(pi, coff, *eax, bytes); 1898 } 1899 } 1900 } 1901 1902 static int cfgenable, cfgbus, cfgslot, cfgfunc, cfgoff; 1903 1904 static int 1905 pci_emul_cfgaddr(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1906 uint32_t *eax, void *arg) 1907 { 1908 uint32_t x; 1909 1910 if (bytes != 4) { 1911 if (in) 1912 *eax = (bytes == 2) ? 0xffff : 0xff; 1913 return (0); 1914 } 1915 1916 if (in) { 1917 x = (cfgbus << 16) | (cfgslot << 11) | (cfgfunc << 8) | cfgoff; 1918 if (cfgenable) 1919 x |= CONF1_ENABLE; 1920 *eax = x; 1921 } else { 1922 x = *eax; 1923 cfgenable = (x & CONF1_ENABLE) == CONF1_ENABLE; 1924 cfgoff = x & PCI_REGMAX; 1925 cfgfunc = (x >> 8) & PCI_FUNCMAX; 1926 cfgslot = (x >> 11) & PCI_SLOTMAX; 1927 cfgbus = (x >> 16) & PCI_BUSMAX; 1928 } 1929 1930 return (0); 1931 } 1932 INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr); 1933 1934 static int 1935 pci_emul_cfgdata(struct vmctx *ctx, int vcpu, int in, int port, int bytes, 1936 uint32_t *eax, void *arg) 1937 { 1938 int coff; 1939 1940 assert(bytes == 1 || bytes == 2 || bytes == 4); 1941 1942 coff = cfgoff + (port - CONF1_DATA_PORT); 1943 if (cfgenable) { 1944 pci_cfgrw(ctx, vcpu, in, cfgbus, cfgslot, cfgfunc, coff, bytes, 1945 eax); 1946 } else { 1947 /* Ignore accesses to cfgdata if not enabled by cfgaddr */ 1948 if (in) 1949 *eax = 0xffffffff; 1950 } 1951 return (0); 1952 } 1953 1954 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+0, IOPORT_F_INOUT, pci_emul_cfgdata); 1955 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+1, IOPORT_F_INOUT, pci_emul_cfgdata); 1956 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+2, IOPORT_F_INOUT, pci_emul_cfgdata); 1957 INOUT_PORT(pci_cfgdata, CONF1_DATA_PORT+3, IOPORT_F_INOUT, pci_emul_cfgdata); 1958 1959 #define PCI_EMUL_TEST 1960 #ifdef PCI_EMUL_TEST 1961 /* 1962 * Define a dummy test device 1963 */ 1964 #define DIOSZ 8 1965 #define DMEMSZ 4096 1966 struct pci_emul_dsoftc { 1967 uint8_t ioregs[DIOSZ]; 1968 uint8_t memregs[2][DMEMSZ]; 1969 }; 1970 1971 #define PCI_EMUL_MSI_MSGS 4 1972 #define PCI_EMUL_MSIX_MSGS 16 1973 1974 static int 1975 pci_emul_dinit(struct vmctx *ctx, struct pci_devinst *pi, char *opts) 1976 { 1977 int error; 1978 struct pci_emul_dsoftc *sc; 1979 1980 sc = calloc(1, sizeof(struct pci_emul_dsoftc)); 1981 1982 pi->pi_arg = sc; 1983 1984 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x0001); 1985 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x10DD); 1986 pci_set_cfgdata8(pi, PCIR_CLASS, 0x02); 1987 1988 error = pci_emul_add_msicap(pi, PCI_EMUL_MSI_MSGS); 1989 assert(error == 0); 1990 1991 error = pci_emul_alloc_bar(pi, 0, PCIBAR_IO, DIOSZ); 1992 assert(error == 0); 1993 1994 error = pci_emul_alloc_bar(pi, 1, PCIBAR_MEM32, DMEMSZ); 1995 assert(error == 0); 1996 1997 error = pci_emul_alloc_bar(pi, 2, PCIBAR_MEM32, DMEMSZ); 1998 assert(error == 0); 1999 2000 return (0); 2001 } 2002 2003 static void 2004 pci_emul_diow(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2005 uint64_t offset, int size, uint64_t value) 2006 { 2007 int i; 2008 struct pci_emul_dsoftc *sc = pi->pi_arg; 2009 2010 if (baridx == 0) { 2011 if (offset + size > DIOSZ) { 2012 printf("diow: iow too large, offset %ld size %d\n", 2013 offset, size); 2014 return; 2015 } 2016 2017 if (size == 1) { 2018 sc->ioregs[offset] = value & 0xff; 2019 } else if (size == 2) { 2020 *(uint16_t *)&sc->ioregs[offset] = value & 0xffff; 2021 } else if (size == 4) { 2022 *(uint32_t *)&sc->ioregs[offset] = value; 2023 } else { 2024 printf("diow: iow unknown size %d\n", size); 2025 } 2026 2027 /* 2028 * Special magic value to generate an interrupt 2029 */ 2030 if (offset == 4 && size == 4 && pci_msi_enabled(pi)) 2031 pci_generate_msi(pi, value % pci_msi_maxmsgnum(pi)); 2032 2033 if (value == 0xabcdef) { 2034 for (i = 0; i < pci_msi_maxmsgnum(pi); i++) 2035 pci_generate_msi(pi, i); 2036 } 2037 } 2038 2039 if (baridx == 1 || baridx == 2) { 2040 if (offset + size > DMEMSZ) { 2041 printf("diow: memw too large, offset %ld size %d\n", 2042 offset, size); 2043 return; 2044 } 2045 2046 i = baridx - 1; /* 'memregs' index */ 2047 2048 if (size == 1) { 2049 sc->memregs[i][offset] = value; 2050 } else if (size == 2) { 2051 *(uint16_t *)&sc->memregs[i][offset] = value; 2052 } else if (size == 4) { 2053 *(uint32_t *)&sc->memregs[i][offset] = value; 2054 } else if (size == 8) { 2055 *(uint64_t *)&sc->memregs[i][offset] = value; 2056 } else { 2057 printf("diow: memw unknown size %d\n", size); 2058 } 2059 2060 /* 2061 * magic interrupt ?? 2062 */ 2063 } 2064 2065 if (baridx > 2 || baridx < 0) { 2066 printf("diow: unknown bar idx %d\n", baridx); 2067 } 2068 } 2069 2070 static uint64_t 2071 pci_emul_dior(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx, 2072 uint64_t offset, int size) 2073 { 2074 struct pci_emul_dsoftc *sc = pi->pi_arg; 2075 uint32_t value; 2076 int i; 2077 2078 value = 0; 2079 if (baridx == 0) { 2080 if (offset + size > DIOSZ) { 2081 printf("dior: ior too large, offset %ld size %d\n", 2082 offset, size); 2083 return (0); 2084 } 2085 2086 value = 0; 2087 if (size == 1) { 2088 value = sc->ioregs[offset]; 2089 } else if (size == 2) { 2090 value = *(uint16_t *) &sc->ioregs[offset]; 2091 } else if (size == 4) { 2092 value = *(uint32_t *) &sc->ioregs[offset]; 2093 } else { 2094 printf("dior: ior unknown size %d\n", size); 2095 } 2096 } 2097 2098 if (baridx == 1 || baridx == 2) { 2099 if (offset + size > DMEMSZ) { 2100 printf("dior: memr too large, offset %ld size %d\n", 2101 offset, size); 2102 return (0); 2103 } 2104 2105 i = baridx - 1; /* 'memregs' index */ 2106 2107 if (size == 1) { 2108 value = sc->memregs[i][offset]; 2109 } else if (size == 2) { 2110 value = *(uint16_t *) &sc->memregs[i][offset]; 2111 } else if (size == 4) { 2112 value = *(uint32_t *) &sc->memregs[i][offset]; 2113 } else if (size == 8) { 2114 value = *(uint64_t *) &sc->memregs[i][offset]; 2115 } else { 2116 printf("dior: ior unknown size %d\n", size); 2117 } 2118 } 2119 2120 2121 if (baridx > 2 || baridx < 0) { 2122 printf("dior: unknown bar idx %d\n", baridx); 2123 return (0); 2124 } 2125 2126 return (value); 2127 } 2128 2129 struct pci_devemu pci_dummy = { 2130 .pe_emu = "dummy", 2131 .pe_init = pci_emul_dinit, 2132 .pe_barwrite = pci_emul_diow, 2133 .pe_barread = pci_emul_dior 2134 }; 2135 PCI_EMUL_SET(pci_dummy); 2136 2137 #endif /* PCI_EMUL_TEST */ 2138