xref: /illumos-gate/usr/src/cmd/bhyve/common/virtio.h (revision 5c4a5fe16715fb423db76577a6883b5bbecdbe45)
1*5c4a5fe1SAndy Fiddaman /*-
2*5c4a5fe1SAndy Fiddaman  * SPDX-License-Identifier: BSD-2-Clause
3*5c4a5fe1SAndy Fiddaman  *
4*5c4a5fe1SAndy Fiddaman  * Copyright (c) 2013  Chris Torek <torek @ torek net>
5*5c4a5fe1SAndy Fiddaman  * All rights reserved.
6*5c4a5fe1SAndy Fiddaman  *
7*5c4a5fe1SAndy Fiddaman  * Redistribution and use in source and binary forms, with or without
8*5c4a5fe1SAndy Fiddaman  * modification, are permitted provided that the following conditions
9*5c4a5fe1SAndy Fiddaman  * are met:
10*5c4a5fe1SAndy Fiddaman  * 1. Redistributions of source code must retain the above copyright
11*5c4a5fe1SAndy Fiddaman  *    notice, this list of conditions and the following disclaimer.
12*5c4a5fe1SAndy Fiddaman  * 2. Redistributions in binary form must reproduce the above copyright
13*5c4a5fe1SAndy Fiddaman  *    notice, this list of conditions and the following disclaimer in the
14*5c4a5fe1SAndy Fiddaman  *    documentation and/or other materials provided with the distribution.
15*5c4a5fe1SAndy Fiddaman  *
16*5c4a5fe1SAndy Fiddaman  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17*5c4a5fe1SAndy Fiddaman  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18*5c4a5fe1SAndy Fiddaman  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19*5c4a5fe1SAndy Fiddaman  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20*5c4a5fe1SAndy Fiddaman  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21*5c4a5fe1SAndy Fiddaman  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22*5c4a5fe1SAndy Fiddaman  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23*5c4a5fe1SAndy Fiddaman  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24*5c4a5fe1SAndy Fiddaman  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25*5c4a5fe1SAndy Fiddaman  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26*5c4a5fe1SAndy Fiddaman  * SUCH DAMAGE.
27*5c4a5fe1SAndy Fiddaman  */
28*5c4a5fe1SAndy Fiddaman 
29*5c4a5fe1SAndy Fiddaman #ifndef	_BHYVE_VIRTIO_H_
30*5c4a5fe1SAndy Fiddaman #define	_BHYVE_VIRTIO_H_
31*5c4a5fe1SAndy Fiddaman 
32*5c4a5fe1SAndy Fiddaman #include <pthread_np.h>
33*5c4a5fe1SAndy Fiddaman #include <machine/atomic.h>
34*5c4a5fe1SAndy Fiddaman 
35*5c4a5fe1SAndy Fiddaman #include <dev/virtio/virtio.h>
36*5c4a5fe1SAndy Fiddaman #ifdef __FreeBSD__
37*5c4a5fe1SAndy Fiddaman #include <dev/virtio/virtio_ring.h>
38*5c4a5fe1SAndy Fiddaman #include <dev/virtio/pci/virtio_pci_var.h>
39*5c4a5fe1SAndy Fiddaman #endif
40*5c4a5fe1SAndy Fiddaman 
41*5c4a5fe1SAndy Fiddaman /*
42*5c4a5fe1SAndy Fiddaman  * These are derived from several virtio specifications.
43*5c4a5fe1SAndy Fiddaman  *
44*5c4a5fe1SAndy Fiddaman  * Some useful links:
45*5c4a5fe1SAndy Fiddaman  *    https://github.com/rustyrussell/virtio-spec
46*5c4a5fe1SAndy Fiddaman  *    http://people.redhat.com/pbonzini/virtio-spec.pdf
47*5c4a5fe1SAndy Fiddaman  */
48*5c4a5fe1SAndy Fiddaman 
49*5c4a5fe1SAndy Fiddaman /*
50*5c4a5fe1SAndy Fiddaman  * A virtual device has zero or more "virtual queues" (virtqueue).
51*5c4a5fe1SAndy Fiddaman  * Each virtqueue uses at least two 4096-byte pages, laid out thus:
52*5c4a5fe1SAndy Fiddaman  *
53*5c4a5fe1SAndy Fiddaman  *      +-----------------------------------------------+
54*5c4a5fe1SAndy Fiddaman  *      |    "desc":  <N> descriptors, 16 bytes each    |
55*5c4a5fe1SAndy Fiddaman  *      |   -----------------------------------------   |
56*5c4a5fe1SAndy Fiddaman  *      |   "avail":   2 uint16; <N> uint16; 1 uint16   |
57*5c4a5fe1SAndy Fiddaman  *      |   -----------------------------------------   |
58*5c4a5fe1SAndy Fiddaman  *      |              pad to 4k boundary               |
59*5c4a5fe1SAndy Fiddaman  *      +-----------------------------------------------+
60*5c4a5fe1SAndy Fiddaman  *      |   "used": 2 x uint16; <N> elems; 1 uint16     |
61*5c4a5fe1SAndy Fiddaman  *      |   -----------------------------------------   |
62*5c4a5fe1SAndy Fiddaman  *      |              pad to 4k boundary               |
63*5c4a5fe1SAndy Fiddaman  *      +-----------------------------------------------+
64*5c4a5fe1SAndy Fiddaman  *
65*5c4a5fe1SAndy Fiddaman  * The number <N> that appears here is always a power of two and is
66*5c4a5fe1SAndy Fiddaman  * limited to no more than 32768 (as it must fit in a 16-bit field).
67*5c4a5fe1SAndy Fiddaman  * If <N> is sufficiently large, the above will occupy more than
68*5c4a5fe1SAndy Fiddaman  * two pages.  In any case, all pages must be physically contiguous
69*5c4a5fe1SAndy Fiddaman  * within the guest's physical address space.
70*5c4a5fe1SAndy Fiddaman  *
71*5c4a5fe1SAndy Fiddaman  * The <N> 16-byte "desc" descriptors consist of a 64-bit guest
72*5c4a5fe1SAndy Fiddaman  * physical address <addr>, a 32-bit length <len>, a 16-bit
73*5c4a5fe1SAndy Fiddaman  * <flags>, and a 16-bit <next> field (all in guest byte order).
74*5c4a5fe1SAndy Fiddaman  *
75*5c4a5fe1SAndy Fiddaman  * There are three flags that may be set :
76*5c4a5fe1SAndy Fiddaman  *	NEXT    descriptor is chained, so use its "next" field
77*5c4a5fe1SAndy Fiddaman  *	WRITE   descriptor is for host to write into guest RAM
78*5c4a5fe1SAndy Fiddaman  *		(else host is to read from guest RAM)
79*5c4a5fe1SAndy Fiddaman  *	INDIRECT   descriptor address field is (guest physical)
80*5c4a5fe1SAndy Fiddaman  *		address of a linear array of descriptors
81*5c4a5fe1SAndy Fiddaman  *
82*5c4a5fe1SAndy Fiddaman  * Unless INDIRECT is set, <len> is the number of bytes that may
83*5c4a5fe1SAndy Fiddaman  * be read/written from guest physical address <addr>.  If
84*5c4a5fe1SAndy Fiddaman  * INDIRECT is set, WRITE is ignored and <len> provides the length
85*5c4a5fe1SAndy Fiddaman  * of the indirect descriptors (and <len> must be a multiple of
86*5c4a5fe1SAndy Fiddaman  * 16).  Note that NEXT may still be set in the main descriptor
87*5c4a5fe1SAndy Fiddaman  * pointing to the indirect, and should be set in each indirect
88*5c4a5fe1SAndy Fiddaman  * descriptor that uses the next descriptor (these should generally
89*5c4a5fe1SAndy Fiddaman  * be numbered sequentially).  However, INDIRECT must not be set
90*5c4a5fe1SAndy Fiddaman  * in the indirect descriptors.  Upon reaching an indirect descriptor
91*5c4a5fe1SAndy Fiddaman  * without a NEXT bit, control returns to the direct descriptors.
92*5c4a5fe1SAndy Fiddaman  *
93*5c4a5fe1SAndy Fiddaman  * Except inside an indirect, each <next> value must be in the
94*5c4a5fe1SAndy Fiddaman  * range [0 .. N) (i.e., the half-open interval).  (Inside an
95*5c4a5fe1SAndy Fiddaman  * indirect, each <next> must be in the range [0 .. <len>/16).)
96*5c4a5fe1SAndy Fiddaman  *
97*5c4a5fe1SAndy Fiddaman  * The "avail" data structures reside in the same pages as the
98*5c4a5fe1SAndy Fiddaman  * "desc" structures since both together are used by the device to
99*5c4a5fe1SAndy Fiddaman  * pass information to the hypervisor's virtual driver.  These
100*5c4a5fe1SAndy Fiddaman  * begin with a 16-bit <flags> field and 16-bit index <idx>, then
101*5c4a5fe1SAndy Fiddaman  * have <N> 16-bit <ring> values, followed by one final 16-bit
102*5c4a5fe1SAndy Fiddaman  * field <used_event>.  The <N> <ring> entries are simply indices
103*5c4a5fe1SAndy Fiddaman  * into the descriptor ring (and thus must meet the same
104*5c4a5fe1SAndy Fiddaman  * constraints as each <next> value).  However, <idx> is counted
105*5c4a5fe1SAndy Fiddaman  * up from 0 (initially) and simply wraps around after 65535; it
106*5c4a5fe1SAndy Fiddaman  * is taken mod <N> to find the next available entry.
107*5c4a5fe1SAndy Fiddaman  *
108*5c4a5fe1SAndy Fiddaman  * The "used" ring occupies a separate page or pages, and contains
109*5c4a5fe1SAndy Fiddaman  * values written from the virtual driver back to the guest OS.
110*5c4a5fe1SAndy Fiddaman  * This begins with a 16-bit <flags> and 16-bit <idx>, then there
111*5c4a5fe1SAndy Fiddaman  * are <N> "vring_used" elements, followed by a 16-bit <avail_event>.
112*5c4a5fe1SAndy Fiddaman  * The <N> "vring_used" elements consist of a 32-bit <id> and a
113*5c4a5fe1SAndy Fiddaman  * 32-bit <len> (vu_tlen below).  The <id> is simply the index of
114*5c4a5fe1SAndy Fiddaman  * the head of a descriptor chain the guest made available
115*5c4a5fe1SAndy Fiddaman  * earlier, and the <len> is the number of bytes actually written,
116*5c4a5fe1SAndy Fiddaman  * e.g., in the case of a network driver that provided a large
117*5c4a5fe1SAndy Fiddaman  * receive buffer but received only a small amount of data.
118*5c4a5fe1SAndy Fiddaman  *
119*5c4a5fe1SAndy Fiddaman  * The two event fields, <used_event> and <avail_event>, in the
120*5c4a5fe1SAndy Fiddaman  * avail and used rings (respectively -- note the reversal!), are
121*5c4a5fe1SAndy Fiddaman  * always provided, but are used only if the virtual device
122*5c4a5fe1SAndy Fiddaman  * negotiates the VIRTIO_RING_F_EVENT_IDX feature during feature
123*5c4a5fe1SAndy Fiddaman  * negotiation.  Similarly, both rings provide a flag --
124*5c4a5fe1SAndy Fiddaman  * VRING_AVAIL_F_NO_INTERRUPT and VRING_USED_F_NO_NOTIFY -- in
125*5c4a5fe1SAndy Fiddaman  * their <flags> field, indicating that the guest does not need an
126*5c4a5fe1SAndy Fiddaman  * interrupt, or that the hypervisor driver does not need a
127*5c4a5fe1SAndy Fiddaman  * notify, when descriptors are added to the corresponding ring.
128*5c4a5fe1SAndy Fiddaman  * (These are provided only for interrupt optimization and need
129*5c4a5fe1SAndy Fiddaman  * not be implemented.)
130*5c4a5fe1SAndy Fiddaman  */
131*5c4a5fe1SAndy Fiddaman #define VRING_ALIGN	4096
132*5c4a5fe1SAndy Fiddaman 
133*5c4a5fe1SAndy Fiddaman /*
134*5c4a5fe1SAndy Fiddaman  * The address of any given virtual queue is determined by a single
135*5c4a5fe1SAndy Fiddaman  * Page Frame Number register.  The guest writes the PFN into the
136*5c4a5fe1SAndy Fiddaman  * PCI config space.  However, a device that has two or more
137*5c4a5fe1SAndy Fiddaman  * virtqueues can have a different PFN, and size, for each queue.
138*5c4a5fe1SAndy Fiddaman  * The number of queues is determinable via the PCI config space
139*5c4a5fe1SAndy Fiddaman  * VTCFG_R_QSEL register.  Writes to QSEL select the queue: 0 means
140*5c4a5fe1SAndy Fiddaman  * queue #0, 1 means queue#1, etc.  Once a queue is selected, the
141*5c4a5fe1SAndy Fiddaman  * remaining PFN and QNUM registers refer to that queue.
142*5c4a5fe1SAndy Fiddaman  *
143*5c4a5fe1SAndy Fiddaman  * QNUM is a read-only register containing a nonzero power of two
144*5c4a5fe1SAndy Fiddaman  * that indicates the (hypervisor's) queue size.  Or, if reading it
145*5c4a5fe1SAndy Fiddaman  * produces zero, the hypervisor does not have a corresponding
146*5c4a5fe1SAndy Fiddaman  * queue.  (The number of possible queues depends on the virtual
147*5c4a5fe1SAndy Fiddaman  * device.  The block device has just one; the network device
148*5c4a5fe1SAndy Fiddaman  * provides either two -- 0 = receive, 1 = transmit -- or three,
149*5c4a5fe1SAndy Fiddaman  * with 2 = control.)
150*5c4a5fe1SAndy Fiddaman  *
151*5c4a5fe1SAndy Fiddaman  * PFN is a read/write register giving the physical page address of
152*5c4a5fe1SAndy Fiddaman  * the virtqueue in guest memory (the guest must allocate enough space
153*5c4a5fe1SAndy Fiddaman  * based on the hypervisor's provided QNUM).
154*5c4a5fe1SAndy Fiddaman  *
155*5c4a5fe1SAndy Fiddaman  * QNOTIFY is effectively write-only: when the guest writes a queue
156*5c4a5fe1SAndy Fiddaman  * number to the register, the hypervisor should scan the specified
157*5c4a5fe1SAndy Fiddaman  * virtqueue. (Reading QNOTIFY currently always gets 0).
158*5c4a5fe1SAndy Fiddaman  */
159*5c4a5fe1SAndy Fiddaman 
160*5c4a5fe1SAndy Fiddaman /*
161*5c4a5fe1SAndy Fiddaman  * PFN register shift amount
162*5c4a5fe1SAndy Fiddaman  */
163*5c4a5fe1SAndy Fiddaman #define	VRING_PFN		12
164*5c4a5fe1SAndy Fiddaman 
165*5c4a5fe1SAndy Fiddaman /*
166*5c4a5fe1SAndy Fiddaman  * PCI vendor/device IDs
167*5c4a5fe1SAndy Fiddaman  */
168*5c4a5fe1SAndy Fiddaman #define	VIRTIO_VENDOR		0x1AF4
169*5c4a5fe1SAndy Fiddaman #define	VIRTIO_DEV_NET		0x1000
170*5c4a5fe1SAndy Fiddaman #define	VIRTIO_DEV_BLOCK	0x1001
171*5c4a5fe1SAndy Fiddaman #define	VIRTIO_DEV_CONSOLE	0x1003
172*5c4a5fe1SAndy Fiddaman #define	VIRTIO_DEV_SCSI		0x1004
173*5c4a5fe1SAndy Fiddaman #define	VIRTIO_DEV_RANDOM	0x1005
174*5c4a5fe1SAndy Fiddaman #define	VIRTIO_DEV_9P		0x1009
175*5c4a5fe1SAndy Fiddaman #define VIRTIO_DEV_INPUT	0x1052
176*5c4a5fe1SAndy Fiddaman 
177*5c4a5fe1SAndy Fiddaman /*
178*5c4a5fe1SAndy Fiddaman  * PCI revision IDs
179*5c4a5fe1SAndy Fiddaman  */
180*5c4a5fe1SAndy Fiddaman #define VIRTIO_REV_INPUT	1
181*5c4a5fe1SAndy Fiddaman 
182*5c4a5fe1SAndy Fiddaman /*
183*5c4a5fe1SAndy Fiddaman  * PCI subvendor IDs
184*5c4a5fe1SAndy Fiddaman  */
185*5c4a5fe1SAndy Fiddaman #define VIRTIO_SUBVEN_INPUT	0x108E
186*5c4a5fe1SAndy Fiddaman 
187*5c4a5fe1SAndy Fiddaman /*
188*5c4a5fe1SAndy Fiddaman  * PCI subdevice IDs
189*5c4a5fe1SAndy Fiddaman  */
190*5c4a5fe1SAndy Fiddaman #define VIRTIO_SUBDEV_INPUT	0x1100
191*5c4a5fe1SAndy Fiddaman 
192*5c4a5fe1SAndy Fiddaman /* From section 2.3, "Virtqueue Configuration", of the virtio specification */
193*5c4a5fe1SAndy Fiddaman static inline int
vring_size_aligned(u_int qsz)194*5c4a5fe1SAndy Fiddaman vring_size_aligned(u_int qsz)
195*5c4a5fe1SAndy Fiddaman {
196*5c4a5fe1SAndy Fiddaman 	return (roundup2(vring_size(qsz, VRING_ALIGN), VRING_ALIGN));
197*5c4a5fe1SAndy Fiddaman }
198*5c4a5fe1SAndy Fiddaman 
199*5c4a5fe1SAndy Fiddaman struct pci_devinst;
200*5c4a5fe1SAndy Fiddaman struct vqueue_info;
201*5c4a5fe1SAndy Fiddaman 
202*5c4a5fe1SAndy Fiddaman /*
203*5c4a5fe1SAndy Fiddaman  * A virtual device, with some number (possibly 0) of virtual
204*5c4a5fe1SAndy Fiddaman  * queues and some size (possibly 0) of configuration-space
205*5c4a5fe1SAndy Fiddaman  * registers private to the device.  The virtio_softc should come
206*5c4a5fe1SAndy Fiddaman  * at the front of each "derived class", so that a pointer to the
207*5c4a5fe1SAndy Fiddaman  * virtio_softc is also a pointer to the more specific, derived-
208*5c4a5fe1SAndy Fiddaman  * from-virtio driver's softc.
209*5c4a5fe1SAndy Fiddaman  *
210*5c4a5fe1SAndy Fiddaman  * Note: inside each hypervisor virtio driver, changes to these
211*5c4a5fe1SAndy Fiddaman  * data structures must be locked against other threads, if any.
212*5c4a5fe1SAndy Fiddaman  * Except for PCI config space register read/write, we assume each
213*5c4a5fe1SAndy Fiddaman  * driver does the required locking, but we need a pointer to the
214*5c4a5fe1SAndy Fiddaman  * lock (if there is one) for PCI config space read/write ops.
215*5c4a5fe1SAndy Fiddaman  *
216*5c4a5fe1SAndy Fiddaman  * When the guest reads or writes the device's config space, the
217*5c4a5fe1SAndy Fiddaman  * generic layer checks for operations on the special registers
218*5c4a5fe1SAndy Fiddaman  * described above.  If the offset of the register(s) being read
219*5c4a5fe1SAndy Fiddaman  * or written is past the CFG area (CFG0 or CFG1), the request is
220*5c4a5fe1SAndy Fiddaman  * passed on to the virtual device, after subtracting off the
221*5c4a5fe1SAndy Fiddaman  * generic-layer size.  (So, drivers can just use the offset as
222*5c4a5fe1SAndy Fiddaman  * an offset into "struct config", for instance.)
223*5c4a5fe1SAndy Fiddaman  *
224*5c4a5fe1SAndy Fiddaman  * (The virtio layer also makes sure that the read or write is to/
225*5c4a5fe1SAndy Fiddaman  * from a "good" config offset, hence vc_cfgsize, and on BAR #0.
226*5c4a5fe1SAndy Fiddaman  * However, the driver must verify the read or write size and offset
227*5c4a5fe1SAndy Fiddaman  * and that no one is writing a readonly register.)
228*5c4a5fe1SAndy Fiddaman  *
229*5c4a5fe1SAndy Fiddaman  * The BROKED flag ("this thing done gone and broked") is for future
230*5c4a5fe1SAndy Fiddaman  * use.
231*5c4a5fe1SAndy Fiddaman  */
232*5c4a5fe1SAndy Fiddaman #define	VIRTIO_USE_MSIX		0x01
233*5c4a5fe1SAndy Fiddaman #define	VIRTIO_EVENT_IDX	0x02	/* use the event-index values */
234*5c4a5fe1SAndy Fiddaman #define	VIRTIO_BROKED		0x08	/* ??? */
235*5c4a5fe1SAndy Fiddaman 
236*5c4a5fe1SAndy Fiddaman struct virtio_softc {
237*5c4a5fe1SAndy Fiddaman 	struct virtio_consts *vs_vc;	/* constants (see below) */
238*5c4a5fe1SAndy Fiddaman 	int	vs_flags;		/* VIRTIO_* flags from above */
239*5c4a5fe1SAndy Fiddaman 	pthread_mutex_t *vs_mtx;	/* POSIX mutex, if any */
240*5c4a5fe1SAndy Fiddaman 	struct pci_devinst *vs_pi;	/* PCI device instance */
241*5c4a5fe1SAndy Fiddaman 	uint32_t vs_negotiated_caps;	/* negotiated capabilities */
242*5c4a5fe1SAndy Fiddaman 	struct vqueue_info *vs_queues;	/* one per vc_nvq */
243*5c4a5fe1SAndy Fiddaman 	int	vs_curq;		/* current queue */
244*5c4a5fe1SAndy Fiddaman 	uint8_t	vs_status;		/* value from last status write */
245*5c4a5fe1SAndy Fiddaman 	uint8_t	vs_isr;			/* ISR flags, if not MSI-X */
246*5c4a5fe1SAndy Fiddaman 	uint16_t vs_msix_cfg_idx;	/* MSI-X vector for config event */
247*5c4a5fe1SAndy Fiddaman };
248*5c4a5fe1SAndy Fiddaman 
249*5c4a5fe1SAndy Fiddaman #define	VS_LOCK(vs)							\
250*5c4a5fe1SAndy Fiddaman do {									\
251*5c4a5fe1SAndy Fiddaman 	if (vs->vs_mtx)							\
252*5c4a5fe1SAndy Fiddaman 		pthread_mutex_lock(vs->vs_mtx);				\
253*5c4a5fe1SAndy Fiddaman } while (0)
254*5c4a5fe1SAndy Fiddaman 
255*5c4a5fe1SAndy Fiddaman #define	VS_UNLOCK(vs)							\
256*5c4a5fe1SAndy Fiddaman do {									\
257*5c4a5fe1SAndy Fiddaman 	if (vs->vs_mtx)							\
258*5c4a5fe1SAndy Fiddaman 		pthread_mutex_unlock(vs->vs_mtx);			\
259*5c4a5fe1SAndy Fiddaman } while (0)
260*5c4a5fe1SAndy Fiddaman 
261*5c4a5fe1SAndy Fiddaman struct virtio_consts {
262*5c4a5fe1SAndy Fiddaman 	const char *vc_name;		/* name of driver (for diagnostics) */
263*5c4a5fe1SAndy Fiddaman 	int	vc_nvq;			/* number of virtual queues */
264*5c4a5fe1SAndy Fiddaman 	size_t	vc_cfgsize;		/* size of dev-specific config regs */
265*5c4a5fe1SAndy Fiddaman 	void	(*vc_reset)(void *);	/* called on virtual device reset */
266*5c4a5fe1SAndy Fiddaman 	void	(*vc_qnotify)(void *, struct vqueue_info *);
267*5c4a5fe1SAndy Fiddaman 					/* called on QNOTIFY if no VQ notify */
268*5c4a5fe1SAndy Fiddaman 	int	(*vc_cfgread)(void *, int, int, uint32_t *);
269*5c4a5fe1SAndy Fiddaman 					/* called to read config regs */
270*5c4a5fe1SAndy Fiddaman 	int	(*vc_cfgwrite)(void *, int, int, uint32_t);
271*5c4a5fe1SAndy Fiddaman 					/* called to write config regs */
272*5c4a5fe1SAndy Fiddaman 	void    (*vc_apply_features)(void *, uint64_t);
273*5c4a5fe1SAndy Fiddaman 				/* called to apply negotiated features */
274*5c4a5fe1SAndy Fiddaman 	uint64_t vc_hv_caps;		/* hypervisor-provided capabilities */
275*5c4a5fe1SAndy Fiddaman };
276*5c4a5fe1SAndy Fiddaman 
277*5c4a5fe1SAndy Fiddaman /*
278*5c4a5fe1SAndy Fiddaman  * Data structure allocated (statically) per virtual queue.
279*5c4a5fe1SAndy Fiddaman  *
280*5c4a5fe1SAndy Fiddaman  * Drivers may change vq_qsize after a reset.  When the guest OS
281*5c4a5fe1SAndy Fiddaman  * requests a device reset, the hypervisor first calls
282*5c4a5fe1SAndy Fiddaman  * vs->vs_vc->vc_reset(); then the data structure below is
283*5c4a5fe1SAndy Fiddaman  * reinitialized (for each virtqueue: vs->vs_vc->vc_nvq).
284*5c4a5fe1SAndy Fiddaman  *
285*5c4a5fe1SAndy Fiddaman  * The remaining fields should only be fussed-with by the generic
286*5c4a5fe1SAndy Fiddaman  * code.
287*5c4a5fe1SAndy Fiddaman  *
288*5c4a5fe1SAndy Fiddaman  * Note: the addresses of vq_desc, vq_avail, and vq_used are all
289*5c4a5fe1SAndy Fiddaman  * computable from each other, but it's a lot simpler if we just
290*5c4a5fe1SAndy Fiddaman  * keep a pointer to each one.  The event indices are similarly
291*5c4a5fe1SAndy Fiddaman  * (but more easily) computable, and this time we'll compute them:
292*5c4a5fe1SAndy Fiddaman  * they're just XX_ring[N].
293*5c4a5fe1SAndy Fiddaman  */
294*5c4a5fe1SAndy Fiddaman #define	VQ_ALLOC	0x01	/* set once we have a pfn */
295*5c4a5fe1SAndy Fiddaman #define	VQ_BROKED	0x02	/* ??? */
296*5c4a5fe1SAndy Fiddaman struct vqueue_info {
297*5c4a5fe1SAndy Fiddaman 	uint16_t vq_qsize;	/* size of this queue (a power of 2) */
298*5c4a5fe1SAndy Fiddaman 	void	(*vq_notify)(void *, struct vqueue_info *);
299*5c4a5fe1SAndy Fiddaman 				/* called instead of vc_notify, if not NULL */
300*5c4a5fe1SAndy Fiddaman 
301*5c4a5fe1SAndy Fiddaman 	struct virtio_softc *vq_vs;	/* backpointer to softc */
302*5c4a5fe1SAndy Fiddaman 	uint16_t vq_num;	/* we're the num'th queue in the softc */
303*5c4a5fe1SAndy Fiddaman 
304*5c4a5fe1SAndy Fiddaman 	uint16_t vq_flags;	/* flags (see above) */
305*5c4a5fe1SAndy Fiddaman 	uint16_t vq_last_avail;	/* a recent value of vq_avail->idx */
306*5c4a5fe1SAndy Fiddaman 	uint16_t vq_next_used;	/* index of the next used slot to be filled */
307*5c4a5fe1SAndy Fiddaman 	uint16_t vq_save_used;	/* saved vq_used->idx; see vq_endchains */
308*5c4a5fe1SAndy Fiddaman 	uint16_t vq_msix_idx;	/* MSI-X index, or VIRTIO_MSI_NO_VECTOR */
309*5c4a5fe1SAndy Fiddaman 
310*5c4a5fe1SAndy Fiddaman 	uint32_t vq_pfn;	/* PFN of virt queue (not shifted!) */
311*5c4a5fe1SAndy Fiddaman 
312*5c4a5fe1SAndy Fiddaman 	struct vring_desc *vq_desc;	/* descriptor array */
313*5c4a5fe1SAndy Fiddaman 	struct vring_avail *vq_avail;	/* the "avail" ring */
314*5c4a5fe1SAndy Fiddaman 	struct vring_used *vq_used;	/* the "used" ring */
315*5c4a5fe1SAndy Fiddaman 
316*5c4a5fe1SAndy Fiddaman };
317*5c4a5fe1SAndy Fiddaman /* as noted above, these are sort of backwards, name-wise */
318*5c4a5fe1SAndy Fiddaman #define VQ_AVAIL_EVENT_IDX(vq) \
319*5c4a5fe1SAndy Fiddaman 	(*(uint16_t *)&(vq)->vq_used->ring[(vq)->vq_qsize])
320*5c4a5fe1SAndy Fiddaman #define VQ_USED_EVENT_IDX(vq) \
321*5c4a5fe1SAndy Fiddaman 	((vq)->vq_avail->ring[(vq)->vq_qsize])
322*5c4a5fe1SAndy Fiddaman 
323*5c4a5fe1SAndy Fiddaman /*
324*5c4a5fe1SAndy Fiddaman  * Is this ring ready for I/O?
325*5c4a5fe1SAndy Fiddaman  */
326*5c4a5fe1SAndy Fiddaman static inline int
vq_ring_ready(struct vqueue_info * vq)327*5c4a5fe1SAndy Fiddaman vq_ring_ready(struct vqueue_info *vq)
328*5c4a5fe1SAndy Fiddaman {
329*5c4a5fe1SAndy Fiddaman 
330*5c4a5fe1SAndy Fiddaman 	return (vq->vq_flags & VQ_ALLOC);
331*5c4a5fe1SAndy Fiddaman }
332*5c4a5fe1SAndy Fiddaman 
333*5c4a5fe1SAndy Fiddaman /*
334*5c4a5fe1SAndy Fiddaman  * Are there "available" descriptors?  (This does not count
335*5c4a5fe1SAndy Fiddaman  * how many, just returns True if there are some.)
336*5c4a5fe1SAndy Fiddaman  */
337*5c4a5fe1SAndy Fiddaman static inline int
vq_has_descs(struct vqueue_info * vq)338*5c4a5fe1SAndy Fiddaman vq_has_descs(struct vqueue_info *vq)
339*5c4a5fe1SAndy Fiddaman {
340*5c4a5fe1SAndy Fiddaman 
341*5c4a5fe1SAndy Fiddaman 	return (vq_ring_ready(vq) && vq->vq_last_avail !=
342*5c4a5fe1SAndy Fiddaman 	    vq->vq_avail->idx);
343*5c4a5fe1SAndy Fiddaman }
344*5c4a5fe1SAndy Fiddaman 
345*5c4a5fe1SAndy Fiddaman /*
346*5c4a5fe1SAndy Fiddaman  * Deliver an interrupt to the guest for a specific MSI-X queue or
347*5c4a5fe1SAndy Fiddaman  * event.
348*5c4a5fe1SAndy Fiddaman  */
349*5c4a5fe1SAndy Fiddaman static inline void
vi_interrupt(struct virtio_softc * vs,uint8_t isr,uint16_t msix_idx)350*5c4a5fe1SAndy Fiddaman vi_interrupt(struct virtio_softc *vs, uint8_t isr, uint16_t msix_idx)
351*5c4a5fe1SAndy Fiddaman {
352*5c4a5fe1SAndy Fiddaman 
353*5c4a5fe1SAndy Fiddaman 	if (pci_msix_enabled(vs->vs_pi))
354*5c4a5fe1SAndy Fiddaman 		pci_generate_msix(vs->vs_pi, msix_idx);
355*5c4a5fe1SAndy Fiddaman 	else {
356*5c4a5fe1SAndy Fiddaman #ifndef __FreeBSD__
357*5c4a5fe1SAndy Fiddaman 		boolean_t unlock = B_FALSE;
358*5c4a5fe1SAndy Fiddaman 
359*5c4a5fe1SAndy Fiddaman 		if (vs->vs_mtx && !pthread_mutex_isowned_np(vs->vs_mtx)) {
360*5c4a5fe1SAndy Fiddaman 			unlock = B_TRUE;
361*5c4a5fe1SAndy Fiddaman 			pthread_mutex_lock(vs->vs_mtx);
362*5c4a5fe1SAndy Fiddaman 		}
363*5c4a5fe1SAndy Fiddaman #else
364*5c4a5fe1SAndy Fiddaman 		VS_LOCK(vs);
365*5c4a5fe1SAndy Fiddaman #endif
366*5c4a5fe1SAndy Fiddaman 		vs->vs_isr |= isr;
367*5c4a5fe1SAndy Fiddaman 		pci_generate_msi(vs->vs_pi, 0);
368*5c4a5fe1SAndy Fiddaman 		pci_lintr_assert(vs->vs_pi);
369*5c4a5fe1SAndy Fiddaman #ifndef __FreeBSD__
370*5c4a5fe1SAndy Fiddaman 		if (unlock)
371*5c4a5fe1SAndy Fiddaman 			pthread_mutex_unlock(vs->vs_mtx);
372*5c4a5fe1SAndy Fiddaman #else
373*5c4a5fe1SAndy Fiddaman 		VS_UNLOCK(vs);
374*5c4a5fe1SAndy Fiddaman #endif
375*5c4a5fe1SAndy Fiddaman 	}
376*5c4a5fe1SAndy Fiddaman }
377*5c4a5fe1SAndy Fiddaman 
378*5c4a5fe1SAndy Fiddaman /*
379*5c4a5fe1SAndy Fiddaman  * Deliver an interrupt to the guest on the given virtual queue (if
380*5c4a5fe1SAndy Fiddaman  * possible, or a generic MSI interrupt if not using MSI-X).
381*5c4a5fe1SAndy Fiddaman  */
382*5c4a5fe1SAndy Fiddaman static inline void
vq_interrupt(struct virtio_softc * vs,struct vqueue_info * vq)383*5c4a5fe1SAndy Fiddaman vq_interrupt(struct virtio_softc *vs, struct vqueue_info *vq)
384*5c4a5fe1SAndy Fiddaman {
385*5c4a5fe1SAndy Fiddaman 
386*5c4a5fe1SAndy Fiddaman 	vi_interrupt(vs, VIRTIO_PCI_ISR_INTR, vq->vq_msix_idx);
387*5c4a5fe1SAndy Fiddaman }
388*5c4a5fe1SAndy Fiddaman 
389*5c4a5fe1SAndy Fiddaman static inline void
vq_kick_enable(struct vqueue_info * vq)390*5c4a5fe1SAndy Fiddaman vq_kick_enable(struct vqueue_info *vq)
391*5c4a5fe1SAndy Fiddaman {
392*5c4a5fe1SAndy Fiddaman 
393*5c4a5fe1SAndy Fiddaman 	vq->vq_used->flags &= ~VRING_USED_F_NO_NOTIFY;
394*5c4a5fe1SAndy Fiddaman 	/*
395*5c4a5fe1SAndy Fiddaman 	 * Full memory barrier to make sure the store to vq_used->flags
396*5c4a5fe1SAndy Fiddaman 	 * happens before the load from vq_avail->idx, which results from a
397*5c4a5fe1SAndy Fiddaman 	 * subsequent call to vq_has_descs().
398*5c4a5fe1SAndy Fiddaman 	 */
399*5c4a5fe1SAndy Fiddaman 	atomic_thread_fence_seq_cst();
400*5c4a5fe1SAndy Fiddaman }
401*5c4a5fe1SAndy Fiddaman 
402*5c4a5fe1SAndy Fiddaman static inline void
vq_kick_disable(struct vqueue_info * vq)403*5c4a5fe1SAndy Fiddaman vq_kick_disable(struct vqueue_info *vq)
404*5c4a5fe1SAndy Fiddaman {
405*5c4a5fe1SAndy Fiddaman 
406*5c4a5fe1SAndy Fiddaman 	vq->vq_used->flags |= VRING_USED_F_NO_NOTIFY;
407*5c4a5fe1SAndy Fiddaman }
408*5c4a5fe1SAndy Fiddaman 
409*5c4a5fe1SAndy Fiddaman struct iovec;
410*5c4a5fe1SAndy Fiddaman 
411*5c4a5fe1SAndy Fiddaman /*
412*5c4a5fe1SAndy Fiddaman  * Request description returned by vq_getchain.
413*5c4a5fe1SAndy Fiddaman  *
414*5c4a5fe1SAndy Fiddaman  * Writable iovecs start at iov[req.readable].
415*5c4a5fe1SAndy Fiddaman  */
416*5c4a5fe1SAndy Fiddaman struct vi_req {
417*5c4a5fe1SAndy Fiddaman 	int readable;		/* num of readable iovecs */
418*5c4a5fe1SAndy Fiddaman 	int writable;		/* num of writable iovecs */
419*5c4a5fe1SAndy Fiddaman 	unsigned int idx;	/* ring index */
420*5c4a5fe1SAndy Fiddaman };
421*5c4a5fe1SAndy Fiddaman 
422*5c4a5fe1SAndy Fiddaman void	vi_softc_linkup(struct virtio_softc *vs, struct virtio_consts *vc,
423*5c4a5fe1SAndy Fiddaman 			void *dev_softc, struct pci_devinst *pi,
424*5c4a5fe1SAndy Fiddaman 			struct vqueue_info *queues);
425*5c4a5fe1SAndy Fiddaman int	vi_intr_init(struct virtio_softc *vs, int barnum, int use_msix);
426*5c4a5fe1SAndy Fiddaman void	vi_reset_dev(struct virtio_softc *);
427*5c4a5fe1SAndy Fiddaman void	vi_set_io_bar(struct virtio_softc *, int);
428*5c4a5fe1SAndy Fiddaman 
429*5c4a5fe1SAndy Fiddaman int	vq_getchain(struct vqueue_info *vq, struct iovec *iov, int niov,
430*5c4a5fe1SAndy Fiddaman 	    struct vi_req *reqp);
431*5c4a5fe1SAndy Fiddaman void	vq_retchains(struct vqueue_info *vq, uint16_t n_chains);
432*5c4a5fe1SAndy Fiddaman void	vq_relchain_prepare(struct vqueue_info *vq, uint16_t idx,
433*5c4a5fe1SAndy Fiddaman 			    uint32_t iolen);
434*5c4a5fe1SAndy Fiddaman void	vq_relchain_publish(struct vqueue_info *vq);
435*5c4a5fe1SAndy Fiddaman void	vq_relchain(struct vqueue_info *vq, uint16_t idx, uint32_t iolen);
436*5c4a5fe1SAndy Fiddaman void	vq_endchains(struct vqueue_info *vq, int used_all_avail);
437*5c4a5fe1SAndy Fiddaman 
438*5c4a5fe1SAndy Fiddaman uint64_t vi_pci_read(struct pci_devinst *pi, int baridx, uint64_t offset,
439*5c4a5fe1SAndy Fiddaman 	    int size);
440*5c4a5fe1SAndy Fiddaman void	vi_pci_write(struct pci_devinst *pi, int baridx, uint64_t offset,
441*5c4a5fe1SAndy Fiddaman 	    int size, uint64_t value);
442*5c4a5fe1SAndy Fiddaman 
443*5c4a5fe1SAndy Fiddaman #ifndef __FreeBSD__
444*5c4a5fe1SAndy Fiddaman void	vi_vq_init(struct virtio_softc *, uint32_t);
445*5c4a5fe1SAndy Fiddaman #endif
446*5c4a5fe1SAndy Fiddaman 
447*5c4a5fe1SAndy Fiddaman #endif	/* _BHYVE_VIRTIO_H_ */
448