1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011 NetApp, Inc. 5 * Copyright (c) 2018 Joyent, Inc. 6 * Copyright 2021 Oxide Computer Company 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef __FreeBSD__ 32 #include <errno.h> 33 #include <stdlib.h> 34 #include <stdio.h> 35 #include <strings.h> 36 #include <err.h> 37 #endif 38 39 #include <stdlib.h> 40 41 #include "config.h" 42 #include "pci_emul.h" 43 #ifndef __FreeBSD__ 44 #include "bhyverun.h" 45 #endif 46 47 #ifndef __FreeBSD__ 48 static struct pci_hostbridge_model { 49 const char *phm_model; 50 uint16_t phm_vendor; 51 uint16_t phm_device; 52 } pci_hb_models[] = { 53 { "amd", 0x1022, 0x7432 }, /* AMD/made-up */ 54 { "netapp", 0x1275, 0x1275 }, /* NetApp/NetApp */ 55 { "i440fx", 0x8086, 0x1237 }, /* Intel/82441 */ 56 { "q35", 0x8086, 0x29b0 }, /* Intel/Q35 HB */ 57 }; 58 59 #define NUM_HB_MODELS (sizeof (pci_hb_models) / sizeof (pci_hb_models[0])) 60 #endif 61 62 static int 63 pci_hostbridge_init(struct pci_devinst *pi, nvlist_t *nvl) 64 { 65 const char *value; 66 u_int vendor, device; 67 68 #ifdef __FreeBSD__ 69 vendor = 0x1275; /* NetApp */ 70 device = 0x1275; /* NetApp */ 71 #else 72 vendor = device = 0; 73 #endif 74 75 value = get_config_value_node(nvl, "vendor"); 76 if (value != NULL) 77 vendor = strtol(value, NULL, 0); 78 else 79 vendor = pci_config_read_reg(NULL, nvl, PCIR_VENDOR, 2, vendor); 80 value = get_config_value_node(nvl, "devid"); 81 if (value != NULL) 82 device = strtol(value, NULL, 0); 83 else 84 device = pci_config_read_reg(NULL, nvl, PCIR_DEVICE, 2, device); 85 86 #ifndef __FreeBSD__ 87 const char *model = get_config_value_node(nvl, "model"); 88 89 if (model != NULL && (vendor != 0 || device != 0)) { 90 warnx("pci_hostbridge: cannot specify model and vendor/device"); 91 return (-1); 92 } else if ((vendor != 0 && device == 0) || 93 (vendor == 0 && device != 0)) { 94 warnx("pci_hostbridge: must specify both vendor and " 95 "device for custom hostbridge"); 96 return (-1); 97 } 98 if (model == NULL && vendor == 0 && device == 0) 99 model = "netapp"; 100 101 if (model != NULL) { 102 for (uint_t i = 0; i < NUM_HB_MODELS; i++) { 103 if (strcmp(model, pci_hb_models[i].phm_model) != 0) 104 continue; 105 106 /* found a model match */ 107 vendor = pci_hb_models[i].phm_vendor; 108 device = pci_hb_models[i].phm_device; 109 break; 110 } 111 if (vendor == 0) { 112 warnx("pci_hostbridge: invalid model '%s'", model); 113 return (-1); 114 } 115 } 116 117 /* Both i440fx and Q35 chipsets feature the concept of Programmable 118 * Address Memory (PAM), where certain physical address ranges can be 119 * configured to direct reads/writes to either DRAM, or to the PCI MMIO 120 * space instead. At boot, they default to bypassing DRAM, so in order 121 * to cheaply paper over our lack of emulation, the memory in PAM0 122 * (0xf0000-0xfffff, the System BIOS segment) should be zeroed. 123 * 124 * If this emulation is expanded in the future to truly support PAM 125 * behavior, this hack can be removed. 126 */ 127 if (vendor == 0x8086 && (device == 0x1237 || device == 0x29b0)) { 128 const uintptr_t start = 0xf0000; 129 const size_t len = 0x10000; 130 void *system_bios_region = paddr_guest2host(pi->pi_vmctx, 131 start, len); 132 assert(system_bios_region != NULL); 133 bzero(system_bios_region, len); 134 } 135 #endif /* !__FreeBSD__ */ 136 137 /* config space */ 138 pci_set_cfgdata16(pi, PCIR_VENDOR, vendor); 139 pci_set_cfgdata16(pi, PCIR_DEVICE, device); 140 pci_set_cfgdata8(pi, PCIR_HDRTYPE, PCIM_HDRTYPE_NORMAL); 141 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE); 142 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_HOST); 143 144 pci_emul_add_pciecap(pi, PCIEM_TYPE_ROOT_PORT); 145 146 return (0); 147 } 148 149 static int 150 pci_amd_hostbridge_legacy_config(nvlist_t *nvl, const char *opts __unused) 151 { 152 nvlist_t *pci_regs; 153 154 pci_regs = create_relative_config_node(nvl, "pcireg"); 155 if (pci_regs == NULL) { 156 warnx("amd_hostbridge: failed to create pciregs node"); 157 return (-1); 158 } 159 set_config_value_node(pci_regs, "vendor", "0x1022"); /* AMD */ 160 set_config_value_node(pci_regs, "device", "0x7432"); /* made up */ 161 162 return (0); 163 } 164 165 static const struct pci_devemu pci_de_amd_hostbridge = { 166 .pe_emu = "amd_hostbridge", 167 .pe_legacy_config = pci_amd_hostbridge_legacy_config, 168 .pe_alias = "hostbridge", 169 }; 170 PCI_EMUL_SET(pci_de_amd_hostbridge); 171 172 static const struct pci_devemu pci_de_hostbridge = { 173 .pe_emu = "hostbridge", 174 .pe_init = pci_hostbridge_init, 175 }; 176 PCI_EMUL_SET(pci_de_hostbridge); 177