1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org> 5 * Copyright (c) 2015-2016 Alexander Motin <mav@FreeBSD.org> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 31 #include <sys/param.h> 32 #include <sys/linker_set.h> 33 #include <sys/stat.h> 34 #include <sys/uio.h> 35 #include <sys/ioctl.h> 36 #include <sys/disk.h> 37 #include <sys/ata.h> 38 #include <sys/endian.h> 39 #ifndef __FreeBSD__ 40 #include <sys/debug.h> 41 #endif 42 43 #include <errno.h> 44 #include <fcntl.h> 45 #include <stdio.h> 46 #include <stdlib.h> 47 #include <stdint.h> 48 #include <string.h> 49 #include <strings.h> 50 #include <unistd.h> 51 #include <assert.h> 52 #include <pthread.h> 53 #include <pthread_np.h> 54 #include <inttypes.h> 55 #include <md5.h> 56 57 #include "bhyverun.h" 58 #include "config.h" 59 #include "debug.h" 60 #include "pci_emul.h" 61 #include "ahci.h" 62 #include "block_if.h" 63 64 #define DEF_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */ 65 #define MAX_PORTS 32 /* AHCI supports 32 ports */ 66 67 #define PxSIG_ATA 0x00000101 /* ATA drive */ 68 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */ 69 70 enum sata_fis_type { 71 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */ 72 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */ 73 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */ 74 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */ 75 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */ 76 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */ 77 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */ 78 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */ 79 }; 80 81 /* 82 * SCSI opcodes 83 */ 84 #define TEST_UNIT_READY 0x00 85 #define REQUEST_SENSE 0x03 86 #define INQUIRY 0x12 87 #define START_STOP_UNIT 0x1B 88 #define PREVENT_ALLOW 0x1E 89 #define READ_CAPACITY 0x25 90 #define READ_10 0x28 91 #define POSITION_TO_ELEMENT 0x2B 92 #define READ_TOC 0x43 93 #define GET_EVENT_STATUS_NOTIFICATION 0x4A 94 #define MODE_SENSE_10 0x5A 95 #define REPORT_LUNS 0xA0 96 #define READ_12 0xA8 97 #define READ_CD 0xBE 98 99 /* 100 * SCSI mode page codes 101 */ 102 #define MODEPAGE_RW_ERROR_RECOVERY 0x01 103 #define MODEPAGE_CD_CAPABILITIES 0x2A 104 105 /* 106 * ATA commands 107 */ 108 #define ATA_SF_ENAB_SATA_SF 0x10 109 #define ATA_SATA_SF_AN 0x05 110 #define ATA_SF_DIS_SATA_SF 0x90 111 112 /* 113 * Debug printf 114 */ 115 #ifdef AHCI_DEBUG 116 static FILE *dbg; 117 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0) 118 #else 119 #define DPRINTF(format, arg...) 120 #endif 121 122 #define AHCI_PORT_IDENT 20 + 1 123 124 struct ahci_ioreq { 125 struct blockif_req io_req; 126 struct ahci_port *io_pr; 127 STAILQ_ENTRY(ahci_ioreq) io_flist; 128 TAILQ_ENTRY(ahci_ioreq) io_blist; 129 uint8_t *cfis; 130 uint8_t *dsm; 131 uint32_t len; 132 uint32_t done; 133 int slot; 134 int more; 135 }; 136 137 struct ahci_port { 138 struct blockif_ctxt *bctx; 139 struct pci_ahci_softc *pr_sc; 140 struct ata_params ata_ident; 141 uint8_t *cmd_lst; 142 uint8_t *rfis; 143 int port; 144 int atapi; 145 int reset; 146 int waitforclear; 147 int mult_sectors; 148 uint8_t xfermode; 149 uint8_t err_cfis[20]; 150 uint8_t sense_key; 151 uint8_t asc; 152 u_int ccs; 153 uint32_t pending; 154 155 uint32_t clb; 156 uint32_t clbu; 157 uint32_t fb; 158 uint32_t fbu; 159 uint32_t is; 160 uint32_t ie; 161 uint32_t cmd; 162 uint32_t unused0; 163 uint32_t tfd; 164 uint32_t sig; 165 uint32_t ssts; 166 uint32_t sctl; 167 uint32_t serr; 168 uint32_t sact; 169 uint32_t ci; 170 uint32_t sntf; 171 uint32_t fbs; 172 173 /* 174 * i/o request info 175 */ 176 struct ahci_ioreq *ioreq; 177 int ioqsz; 178 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd; 179 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd; 180 }; 181 182 struct ahci_cmd_hdr { 183 uint16_t flags; 184 uint16_t prdtl; 185 uint32_t prdbc; 186 uint64_t ctba; 187 uint32_t reserved[4]; 188 }; 189 190 struct ahci_prdt_entry { 191 uint64_t dba; 192 uint32_t reserved; 193 #define DBCMASK 0x3fffff 194 uint32_t dbc; 195 }; 196 197 struct pci_ahci_softc { 198 struct pci_devinst *asc_pi; 199 pthread_mutex_t mtx; 200 int ports; 201 uint32_t cap; 202 uint32_t ghc; 203 uint32_t is; 204 uint32_t pi; 205 uint32_t vs; 206 uint32_t ccc_ctl; 207 uint32_t ccc_pts; 208 uint32_t em_loc; 209 uint32_t em_ctl; 210 uint32_t cap2; 211 uint32_t bohc; 212 uint32_t lintr; 213 struct ahci_port port[MAX_PORTS]; 214 }; 215 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx) 216 217 static void ahci_handle_next_trim(struct ahci_port *p, int slot, uint8_t *cfis, 218 uint8_t *buf, uint32_t len, uint32_t done); 219 static void ahci_handle_port(struct ahci_port *p); 220 221 static inline void lba_to_msf(uint8_t *buf, int lba) 222 { 223 lba += 150; 224 buf[0] = (lba / 75) / 60; 225 buf[1] = (lba / 75) % 60; 226 buf[2] = lba % 75; 227 } 228 229 /* 230 * Generate HBA interrupts on global IS register write. 231 */ 232 static void 233 ahci_generate_intr(struct pci_ahci_softc *sc, uint32_t mask) 234 { 235 struct pci_devinst *pi = sc->asc_pi; 236 struct ahci_port *p; 237 int i, nmsg; 238 uint32_t mmask; 239 240 /* Update global IS from PxIS/PxIE. */ 241 for (i = 0; i < sc->ports; i++) { 242 p = &sc->port[i]; 243 if (p->is & p->ie) 244 sc->is |= (1 << i); 245 } 246 DPRINTF("%s(%08x) %08x", __func__, mask, sc->is); 247 248 /* If there is nothing enabled -- clear legacy interrupt and exit. */ 249 if (sc->is == 0 || (sc->ghc & AHCI_GHC_IE) == 0) { 250 if (sc->lintr) { 251 pci_lintr_deassert(pi); 252 sc->lintr = 0; 253 } 254 return; 255 } 256 257 /* If there is anything and no MSI -- assert legacy interrupt. */ 258 nmsg = pci_msi_maxmsgnum(pi); 259 if (nmsg == 0) { 260 if (!sc->lintr) { 261 sc->lintr = 1; 262 pci_lintr_assert(pi); 263 } 264 return; 265 } 266 267 /* Assert respective MSIs for ports that were touched. */ 268 for (i = 0; i < nmsg; i++) { 269 if (sc->ports <= nmsg || i < nmsg - 1) 270 mmask = 1 << i; 271 else 272 mmask = 0xffffffff << i; 273 if (sc->is & mask && mmask & mask) 274 pci_generate_msi(pi, i); 275 } 276 } 277 278 /* 279 * Generate HBA interrupt on specific port event. 280 */ 281 static void 282 ahci_port_intr(struct ahci_port *p) 283 { 284 struct pci_ahci_softc *sc = p->pr_sc; 285 struct pci_devinst *pi = sc->asc_pi; 286 int nmsg; 287 288 DPRINTF("%s(%d) %08x/%08x %08x", __func__, 289 p->port, p->is, p->ie, sc->is); 290 291 /* If there is nothing enabled -- we are done. */ 292 if ((p->is & p->ie) == 0) 293 return; 294 295 /* In case of non-shared MSI always generate interrupt. */ 296 nmsg = pci_msi_maxmsgnum(pi); 297 if (sc->ports <= nmsg || p->port < nmsg - 1) { 298 sc->is |= (1 << p->port); 299 if ((sc->ghc & AHCI_GHC_IE) == 0) 300 return; 301 pci_generate_msi(pi, p->port); 302 return; 303 } 304 305 /* If IS for this port is already set -- do nothing. */ 306 if (sc->is & (1 << p->port)) 307 return; 308 309 sc->is |= (1 << p->port); 310 311 /* If interrupts are enabled -- generate one. */ 312 if ((sc->ghc & AHCI_GHC_IE) == 0) 313 return; 314 if (nmsg > 0) { 315 pci_generate_msi(pi, nmsg - 1); 316 } else if (!sc->lintr) { 317 sc->lintr = 1; 318 pci_lintr_assert(pi); 319 } 320 } 321 322 static void 323 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis) 324 { 325 int offset, len, irq; 326 327 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE)) 328 return; 329 330 switch (ft) { 331 case FIS_TYPE_REGD2H: 332 offset = 0x40; 333 len = 20; 334 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_DHR : 0; 335 break; 336 case FIS_TYPE_SETDEVBITS: 337 offset = 0x58; 338 len = 8; 339 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_SDB : 0; 340 break; 341 case FIS_TYPE_PIOSETUP: 342 offset = 0x20; 343 len = 20; 344 irq = (fis[1] & (1 << 6)) ? AHCI_P_IX_PS : 0; 345 break; 346 default: 347 EPRINTLN("unsupported fis type %d", ft); 348 return; 349 } 350 if (fis[2] & ATA_S_ERROR) { 351 p->waitforclear = 1; 352 irq |= AHCI_P_IX_TFE; 353 } 354 memcpy(p->rfis + offset, fis, len); 355 if (irq) { 356 if (~p->is & irq) { 357 p->is |= irq; 358 ahci_port_intr(p); 359 } 360 } 361 } 362 363 static void 364 ahci_write_fis_piosetup(struct ahci_port *p) 365 { 366 uint8_t fis[20]; 367 368 memset(fis, 0, sizeof(fis)); 369 fis[0] = FIS_TYPE_PIOSETUP; 370 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis); 371 } 372 373 static void 374 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 375 { 376 uint8_t fis[8]; 377 uint8_t error; 378 379 error = (tfd >> 8) & 0xff; 380 tfd &= 0x77; 381 memset(fis, 0, sizeof(fis)); 382 fis[0] = FIS_TYPE_SETDEVBITS; 383 fis[1] = (1 << 6); 384 fis[2] = tfd; 385 fis[3] = error; 386 if (fis[2] & ATA_S_ERROR) { 387 p->err_cfis[0] = slot; 388 p->err_cfis[2] = tfd; 389 p->err_cfis[3] = error; 390 memcpy(&p->err_cfis[4], cfis + 4, 16); 391 } else { 392 *(uint32_t *)(fis + 4) = (1 << slot); 393 p->sact &= ~(1 << slot); 394 } 395 p->tfd &= ~0x77; 396 p->tfd |= tfd; 397 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); 398 } 399 400 static void 401 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) 402 { 403 uint8_t fis[20]; 404 uint8_t error; 405 406 error = (tfd >> 8) & 0xff; 407 memset(fis, 0, sizeof(fis)); 408 fis[0] = FIS_TYPE_REGD2H; 409 fis[1] = (1 << 6); 410 fis[2] = tfd & 0xff; 411 fis[3] = error; 412 fis[4] = cfis[4]; 413 fis[5] = cfis[5]; 414 fis[6] = cfis[6]; 415 fis[7] = cfis[7]; 416 fis[8] = cfis[8]; 417 fis[9] = cfis[9]; 418 fis[10] = cfis[10]; 419 fis[11] = cfis[11]; 420 fis[12] = cfis[12]; 421 fis[13] = cfis[13]; 422 if (fis[2] & ATA_S_ERROR) { 423 p->err_cfis[0] = 0x80; 424 p->err_cfis[2] = tfd & 0xff; 425 p->err_cfis[3] = error; 426 memcpy(&p->err_cfis[4], cfis + 4, 16); 427 } else 428 p->ci &= ~(1 << slot); 429 p->tfd = tfd; 430 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 431 } 432 433 static void 434 ahci_write_fis_d2h_ncq(struct ahci_port *p, int slot) 435 { 436 uint8_t fis[20]; 437 438 p->tfd = ATA_S_READY | ATA_S_DSC; 439 memset(fis, 0, sizeof(fis)); 440 fis[0] = FIS_TYPE_REGD2H; 441 fis[1] = 0; /* No interrupt */ 442 fis[2] = p->tfd; /* Status */ 443 fis[3] = 0; /* No error */ 444 p->ci &= ~(1 << slot); 445 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 446 } 447 448 static void 449 ahci_write_reset_fis_d2h(struct ahci_port *p) 450 { 451 uint8_t fis[20]; 452 453 memset(fis, 0, sizeof(fis)); 454 fis[0] = FIS_TYPE_REGD2H; 455 fis[3] = 1; 456 fis[4] = 1; 457 if (p->atapi) { 458 fis[5] = 0x14; 459 fis[6] = 0xeb; 460 } 461 fis[12] = 1; 462 ahci_write_fis(p, FIS_TYPE_REGD2H, fis); 463 } 464 465 static void 466 ahci_check_stopped(struct ahci_port *p) 467 { 468 /* 469 * If we are no longer processing the command list and nothing 470 * is in-flight, clear the running bit, the current command 471 * slot, the command issue and active bits. 472 */ 473 if (!(p->cmd & AHCI_P_CMD_ST)) { 474 if (p->pending == 0) { 475 p->ccs = 0; 476 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK); 477 p->ci = 0; 478 p->sact = 0; 479 p->waitforclear = 0; 480 } 481 } 482 } 483 484 static void 485 ahci_port_stop(struct ahci_port *p) 486 { 487 struct ahci_ioreq *aior; 488 uint8_t *cfis; 489 int slot; 490 int error; 491 492 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx)); 493 494 TAILQ_FOREACH(aior, &p->iobhd, io_blist) { 495 /* 496 * Try to cancel the outstanding blockif request. 497 */ 498 error = blockif_cancel(p->bctx, &aior->io_req); 499 if (error != 0) 500 continue; 501 502 slot = aior->slot; 503 cfis = aior->cfis; 504 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 505 cfis[2] == ATA_READ_FPDMA_QUEUED || 506 cfis[2] == ATA_SEND_FPDMA_QUEUED) 507 p->sact &= ~(1 << slot); /* NCQ */ 508 else 509 p->ci &= ~(1 << slot); 510 511 /* 512 * This command is now done. 513 */ 514 p->pending &= ~(1 << slot); 515 516 /* 517 * Delete the blockif request from the busy list 518 */ 519 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 520 521 /* 522 * Move the blockif request back to the free list 523 */ 524 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 525 } 526 527 ahci_check_stopped(p); 528 } 529 530 static void 531 ahci_port_reset(struct ahci_port *pr) 532 { 533 pr->serr = 0; 534 pr->sact = 0; 535 pr->xfermode = ATA_UDMA6; 536 pr->mult_sectors = 128; 537 538 if (!pr->bctx) { 539 pr->ssts = ATA_SS_DET_NO_DEVICE; 540 pr->sig = 0xFFFFFFFF; 541 pr->tfd = 0x7F; 542 return; 543 } 544 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE; 545 if (pr->sctl & ATA_SC_SPD_MASK) 546 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK); 547 else 548 pr->ssts |= ATA_SS_SPD_GEN3; 549 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA; 550 if (!pr->atapi) { 551 pr->sig = PxSIG_ATA; 552 pr->tfd |= ATA_S_READY; 553 } else 554 pr->sig = PxSIG_ATAPI; 555 ahci_write_reset_fis_d2h(pr); 556 } 557 558 static void 559 ahci_reset(struct pci_ahci_softc *sc) 560 { 561 int i; 562 563 sc->ghc = AHCI_GHC_AE; 564 sc->is = 0; 565 566 if (sc->lintr) { 567 pci_lintr_deassert(sc->asc_pi); 568 sc->lintr = 0; 569 } 570 571 for (i = 0; i < sc->ports; i++) { 572 sc->port[i].ie = 0; 573 sc->port[i].is = 0; 574 sc->port[i].cmd = (AHCI_P_CMD_SUD | AHCI_P_CMD_POD); 575 if (sc->port[i].bctx) 576 sc->port[i].cmd |= AHCI_P_CMD_CPS; 577 sc->port[i].sctl = 0; 578 ahci_port_reset(&sc->port[i]); 579 } 580 } 581 582 static void 583 ata_string(uint8_t *dest, const char *src, int len) 584 { 585 int i; 586 587 for (i = 0; i < len; i++) { 588 if (*src) 589 dest[i ^ 1] = *src++; 590 else 591 dest[i ^ 1] = ' '; 592 } 593 } 594 595 static void 596 atapi_string(uint8_t *dest, const char *src, int len) 597 { 598 int i; 599 600 for (i = 0; i < len; i++) { 601 if (*src) 602 dest[i] = *src++; 603 else 604 dest[i] = ' '; 605 } 606 } 607 608 /* 609 * Build up the iovec based on the PRDT, 'done' and 'len'. 610 */ 611 static void 612 ahci_build_iov(struct ahci_port *p, struct ahci_ioreq *aior, 613 struct ahci_prdt_entry *prdt, uint16_t prdtl) 614 { 615 struct blockif_req *breq = &aior->io_req; 616 uint32_t dbcsz, extra, left, skip, todo; 617 int i, j; 618 619 assert(aior->len >= aior->done); 620 621 /* Copy part of PRDT between 'done' and 'len' bytes into the iov. */ 622 skip = aior->done; 623 left = aior->len - aior->done; 624 todo = 0; 625 for (i = 0, j = 0; i < prdtl && j < BLOCKIF_IOV_MAX && left > 0; 626 i++, prdt++) { 627 dbcsz = (prdt->dbc & DBCMASK) + 1; 628 /* Skip already done part of the PRDT */ 629 if (dbcsz <= skip) { 630 skip -= dbcsz; 631 continue; 632 } 633 dbcsz -= skip; 634 if (dbcsz > left) 635 dbcsz = left; 636 breq->br_iov[j].iov_base = paddr_guest2host(ahci_ctx(p->pr_sc), 637 prdt->dba + skip, dbcsz); 638 breq->br_iov[j].iov_len = dbcsz; 639 todo += dbcsz; 640 left -= dbcsz; 641 skip = 0; 642 j++; 643 } 644 645 /* If we got limited by IOV length, round I/O down to sector size. */ 646 if (j == BLOCKIF_IOV_MAX) { 647 extra = todo % blockif_sectsz(p->bctx); 648 todo -= extra; 649 assert(todo > 0); 650 while (extra > 0) { 651 if (breq->br_iov[j - 1].iov_len > extra) { 652 breq->br_iov[j - 1].iov_len -= extra; 653 break; 654 } 655 extra -= breq->br_iov[j - 1].iov_len; 656 j--; 657 } 658 } 659 660 breq->br_iovcnt = j; 661 breq->br_resid = todo; 662 aior->done += todo; 663 aior->more = (aior->done < aior->len && i < prdtl); 664 } 665 666 static void 667 ahci_handle_rw(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 668 { 669 struct ahci_ioreq *aior; 670 struct blockif_req *breq; 671 struct ahci_prdt_entry *prdt; 672 struct ahci_cmd_hdr *hdr; 673 uint64_t lba; 674 uint32_t len; 675 int err, first, ncq, readop; 676 677 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 678 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 679 ncq = 0; 680 readop = 1; 681 first = (done == 0); 682 683 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 || 684 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 || 685 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || 686 cfis[2] == ATA_WRITE_FPDMA_QUEUED) 687 readop = 0; 688 689 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 690 cfis[2] == ATA_READ_FPDMA_QUEUED) { 691 lba = ((uint64_t)cfis[10] << 40) | 692 ((uint64_t)cfis[9] << 32) | 693 ((uint64_t)cfis[8] << 24) | 694 ((uint64_t)cfis[6] << 16) | 695 ((uint64_t)cfis[5] << 8) | 696 cfis[4]; 697 len = cfis[11] << 8 | cfis[3]; 698 if (!len) 699 len = 65536; 700 ncq = 1; 701 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 || 702 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 || 703 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { 704 lba = ((uint64_t)cfis[10] << 40) | 705 ((uint64_t)cfis[9] << 32) | 706 ((uint64_t)cfis[8] << 24) | 707 ((uint64_t)cfis[6] << 16) | 708 ((uint64_t)cfis[5] << 8) | 709 cfis[4]; 710 len = cfis[13] << 8 | cfis[12]; 711 if (!len) 712 len = 65536; 713 } else { 714 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | 715 (cfis[5] << 8) | cfis[4]; 716 len = cfis[12]; 717 if (!len) 718 len = 256; 719 } 720 lba *= blockif_sectsz(p->bctx); 721 len *= blockif_sectsz(p->bctx); 722 723 /* Pull request off free list */ 724 aior = STAILQ_FIRST(&p->iofhd); 725 assert(aior != NULL); 726 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 727 728 aior->cfis = cfis; 729 aior->slot = slot; 730 aior->len = len; 731 aior->done = done; 732 breq = &aior->io_req; 733 breq->br_offset = lba + done; 734 ahci_build_iov(p, aior, prdt, hdr->prdtl); 735 736 /* Mark this command in-flight. */ 737 p->pending |= 1 << slot; 738 739 /* Stuff request onto busy list. */ 740 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 741 742 if (ncq && first) 743 ahci_write_fis_d2h_ncq(p, slot); 744 745 if (readop) 746 err = blockif_read(p->bctx, breq); 747 else 748 err = blockif_write(p->bctx, breq); 749 assert(err == 0); 750 } 751 752 static void 753 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis) 754 { 755 struct ahci_ioreq *aior; 756 struct blockif_req *breq; 757 int err; 758 759 /* 760 * Pull request off free list 761 */ 762 aior = STAILQ_FIRST(&p->iofhd); 763 assert(aior != NULL); 764 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 765 aior->cfis = cfis; 766 aior->slot = slot; 767 aior->len = 0; 768 aior->done = 0; 769 aior->more = 0; 770 breq = &aior->io_req; 771 772 /* 773 * Mark this command in-flight. 774 */ 775 p->pending |= 1 << slot; 776 777 /* 778 * Stuff request onto busy list 779 */ 780 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 781 782 err = blockif_flush(p->bctx, breq); 783 assert(err == 0); 784 } 785 786 static inline unsigned int 787 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf, 788 unsigned int size) 789 { 790 struct ahci_cmd_hdr *hdr; 791 struct ahci_prdt_entry *prdt; 792 uint8_t *to; 793 unsigned int len; 794 int i; 795 796 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 797 len = size; 798 to = buf; 799 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 800 for (i = 0; i < hdr->prdtl && len; i++) { 801 uint8_t *ptr; 802 uint32_t dbcsz; 803 unsigned int sublen; 804 805 dbcsz = (prdt->dbc & DBCMASK) + 1; 806 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 807 sublen = MIN(len, dbcsz); 808 memcpy(to, ptr, sublen); 809 len -= sublen; 810 to += sublen; 811 prdt++; 812 } 813 #ifndef __FreeBSD__ 814 VERIFY3U(size, >=, len); 815 #endif 816 return (size - len); 817 } 818 819 static void 820 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis) 821 { 822 uint32_t len; 823 int ncq; 824 uint8_t *buf; 825 unsigned int nread; 826 827 buf = NULL; 828 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) { 829 len = (uint16_t)cfis[13] << 8 | cfis[12]; 830 len *= 512; 831 ncq = 0; 832 } else { /* ATA_SEND_FPDMA_QUEUED */ 833 len = (uint16_t)cfis[11] << 8 | cfis[3]; 834 len *= 512; 835 ncq = 1; 836 } 837 838 /* Support for only a single block is advertised via IDENTIFY. */ 839 if (len > 512) { 840 goto invalid_command; 841 } 842 843 buf = malloc(len); 844 nread = read_prdt(p, slot, cfis, buf, len); 845 if (nread != len) { 846 goto invalid_command; 847 } 848 ahci_handle_next_trim(p, slot, cfis, buf, len, 0); 849 return; 850 851 invalid_command: 852 free(buf); 853 if (ncq) { 854 ahci_write_fis_d2h_ncq(p, slot); 855 ahci_write_fis_sdb(p, slot, cfis, 856 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 857 } else { 858 ahci_write_fis_d2h(p, slot, cfis, 859 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 860 } 861 } 862 863 static void 864 ahci_handle_next_trim(struct ahci_port *p, int slot, uint8_t *cfis, 865 uint8_t *buf, uint32_t len, uint32_t done) 866 { 867 struct ahci_ioreq *aior; 868 struct blockif_req *breq; 869 uint8_t *entry; 870 uint64_t elba; 871 uint32_t elen; 872 int err; 873 bool first, ncq; 874 875 #ifndef __FreeBSD__ 876 elba = 0; 877 #endif 878 879 first = (done == 0); 880 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) { 881 ncq = false; 882 } else { /* ATA_SEND_FPDMA_QUEUED */ 883 ncq = true; 884 } 885 886 /* Find the next range to TRIM. */ 887 while (done < len) { 888 entry = &buf[done]; 889 elba = ((uint64_t)entry[5] << 40) | 890 ((uint64_t)entry[4] << 32) | 891 ((uint64_t)entry[3] << 24) | 892 ((uint64_t)entry[2] << 16) | 893 ((uint64_t)entry[1] << 8) | 894 entry[0]; 895 elen = (uint16_t)entry[7] << 8 | entry[6]; 896 done += 8; 897 if (elen != 0) 898 break; 899 } 900 901 /* All remaining ranges were empty. */ 902 if (done == len) { 903 free(buf); 904 if (ncq) { 905 if (first) 906 ahci_write_fis_d2h_ncq(p, slot); 907 ahci_write_fis_sdb(p, slot, cfis, 908 ATA_S_READY | ATA_S_DSC); 909 } else { 910 ahci_write_fis_d2h(p, slot, cfis, 911 ATA_S_READY | ATA_S_DSC); 912 } 913 if (!first) { 914 p->pending &= ~(1 << slot); 915 ahci_check_stopped(p); 916 ahci_handle_port(p); 917 } 918 return; 919 } 920 921 /* 922 * Pull request off free list 923 */ 924 aior = STAILQ_FIRST(&p->iofhd); 925 assert(aior != NULL); 926 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 927 aior->cfis = cfis; 928 aior->slot = slot; 929 aior->len = len; 930 aior->done = done; 931 aior->dsm = buf; 932 aior->more = (len != done); 933 934 breq = &aior->io_req; 935 breq->br_offset = elba * blockif_sectsz(p->bctx); 936 breq->br_resid = elen * blockif_sectsz(p->bctx); 937 938 /* 939 * Mark this command in-flight. 940 */ 941 p->pending |= 1 << slot; 942 943 /* 944 * Stuff request onto busy list 945 */ 946 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 947 948 if (ncq && first) 949 ahci_write_fis_d2h_ncq(p, slot); 950 951 err = blockif_delete(p->bctx, breq); 952 assert(err == 0); 953 } 954 955 static inline void 956 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis, void *buf, 957 unsigned int size) 958 { 959 struct ahci_cmd_hdr *hdr; 960 struct ahci_prdt_entry *prdt; 961 uint8_t *from; 962 unsigned int len; 963 int i; 964 965 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 966 len = size; 967 from = buf; 968 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 969 for (i = 0; i < hdr->prdtl && len; i++) { 970 uint8_t *ptr; 971 uint32_t dbcsz; 972 int sublen; 973 974 dbcsz = (prdt->dbc & DBCMASK) + 1; 975 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz); 976 sublen = MIN(len, dbcsz); 977 memcpy(ptr, from, sublen); 978 len -= sublen; 979 from += sublen; 980 prdt++; 981 } 982 hdr->prdbc = size - len; 983 } 984 985 static void 986 ahci_checksum(uint8_t *buf, int size) 987 { 988 int i; 989 uint8_t sum = 0; 990 991 for (i = 0; i < size - 1; i++) 992 sum += buf[i]; 993 buf[size - 1] = 0x100 - sum; 994 } 995 996 static void 997 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis) 998 { 999 struct ahci_cmd_hdr *hdr; 1000 uint32_t buf[128]; 1001 uint8_t *buf8 = (uint8_t *)buf; 1002 uint16_t *buf16 = (uint16_t *)buf; 1003 1004 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1005 if (p->atapi || hdr->prdtl == 0 || cfis[5] != 0 || 1006 cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) { 1007 ahci_write_fis_d2h(p, slot, cfis, 1008 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1009 return; 1010 } 1011 1012 memset(buf, 0, sizeof(buf)); 1013 if (cfis[4] == 0x00) { /* Log directory */ 1014 buf16[0x00] = 1; /* Version -- 1 */ 1015 buf16[0x10] = 1; /* NCQ Command Error Log -- 1 page */ 1016 buf16[0x13] = 1; /* SATA NCQ Send and Receive Log -- 1 page */ 1017 } else if (cfis[4] == 0x10) { /* NCQ Command Error Log */ 1018 memcpy(buf8, p->err_cfis, sizeof(p->err_cfis)); 1019 ahci_checksum(buf8, sizeof(buf)); 1020 } else if (cfis[4] == 0x13) { /* SATA NCQ Send and Receive Log */ 1021 if (blockif_candelete(p->bctx) && !blockif_is_ro(p->bctx)) { 1022 buf[0x00] = 1; /* SFQ DSM supported */ 1023 buf[0x01] = 1; /* SFQ DSM TRIM supported */ 1024 } 1025 } else { 1026 ahci_write_fis_d2h(p, slot, cfis, 1027 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1028 return; 1029 } 1030 1031 if (cfis[2] == ATA_READ_LOG_EXT) 1032 ahci_write_fis_piosetup(p); 1033 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf)); 1034 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 1035 } 1036 1037 static void 1038 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis) 1039 { 1040 struct ahci_cmd_hdr *hdr; 1041 1042 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1043 if (p->atapi || hdr->prdtl == 0) { 1044 ahci_write_fis_d2h(p, slot, cfis, 1045 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1046 } else { 1047 ahci_write_fis_piosetup(p); 1048 write_prdt(p, slot, cfis, (void*)&p->ata_ident, sizeof(struct ata_params)); 1049 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 1050 } 1051 } 1052 1053 static void 1054 ata_identify_init(struct ahci_port* p, int atapi) 1055 { 1056 struct ata_params* ata_ident = &p->ata_ident; 1057 1058 if (atapi) { 1059 ata_ident->config = ATA_PROTO_ATAPI | ATA_ATAPI_TYPE_CDROM | 1060 ATA_ATAPI_REMOVABLE | ATA_DRQ_FAST; 1061 ata_ident->capabilities1 = ATA_SUPPORT_LBA | 1062 ATA_SUPPORT_DMA; 1063 ata_ident->capabilities2 = (1 << 14 | 1); 1064 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88; 1065 ata_ident->obsolete62 = 0x3f; 1066 ata_ident->mwdmamodes = 7; 1067 if (p->xfermode & ATA_WDMA0) 1068 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8)); 1069 ata_ident->apiomodes = 3; 1070 ata_ident->mwdmamin = 0x0078; 1071 ata_ident->mwdmarec = 0x0078; 1072 ata_ident->pioblind = 0x0078; 1073 ata_ident->pioiordy = 0x0078; 1074 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3); 1075 ata_ident->satacapabilities2 = ((p->ssts & ATA_SS_SPD_MASK) >> 3); 1076 ata_ident->satasupport = ATA_SUPPORT_NCQ_STREAM; 1077 ata_ident->version_major = 0x3f0; 1078 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET | 1079 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP); 1080 ata_ident->support.command2 = (1 << 14); 1081 ata_ident->support.extension = (1 << 14); 1082 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_PACKET | 1083 ATA_SUPPORT_RESET | ATA_SUPPORT_NOP); 1084 ata_ident->enabled.extension = (1 << 14); 1085 ata_ident->udmamodes = 0x7f; 1086 if (p->xfermode & ATA_UDMA0) 1087 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8)); 1088 ata_ident->transport_major = 0x1020; 1089 ata_ident->integrity = 0x00a5; 1090 } else { 1091 uint64_t sectors; 1092 int sectsz, psectsz, psectoff, candelete, ro; 1093 uint16_t cyl; 1094 uint8_t sech, heads; 1095 1096 ro = blockif_is_ro(p->bctx); 1097 candelete = blockif_candelete(p->bctx); 1098 sectsz = blockif_sectsz(p->bctx); 1099 sectors = blockif_size(p->bctx) / sectsz; 1100 blockif_chs(p->bctx, &cyl, &heads, &sech); 1101 blockif_psectsz(p->bctx, &psectsz, &psectoff); 1102 ata_ident->config = ATA_DRQ_FAST; 1103 ata_ident->cylinders = cyl; 1104 ata_ident->heads = heads; 1105 ata_ident->sectors = sech; 1106 1107 ata_ident->sectors_intr = (0x8000 | 128); 1108 ata_ident->tcg = 0; 1109 1110 ata_ident->capabilities1 = ATA_SUPPORT_DMA | 1111 ATA_SUPPORT_LBA | ATA_SUPPORT_IORDY; 1112 ata_ident->capabilities2 = (1 << 14); 1113 ata_ident->atavalid = ATA_FLAG_64_70 | ATA_FLAG_88; 1114 if (p->mult_sectors) 1115 ata_ident->multi = (ATA_MULTI_VALID | p->mult_sectors); 1116 if (sectors <= 0x0fffffff) { 1117 ata_ident->lba_size_1 = sectors; 1118 ata_ident->lba_size_2 = (sectors >> 16); 1119 } else { 1120 ata_ident->lba_size_1 = 0xffff; 1121 ata_ident->lba_size_2 = 0x0fff; 1122 } 1123 ata_ident->mwdmamodes = 0x7; 1124 if (p->xfermode & ATA_WDMA0) 1125 ata_ident->mwdmamodes |= (1 << ((p->xfermode & 7) + 8)); 1126 ata_ident->apiomodes = 0x3; 1127 ata_ident->mwdmamin = 0x0078; 1128 ata_ident->mwdmarec = 0x0078; 1129 ata_ident->pioblind = 0x0078; 1130 ata_ident->pioiordy = 0x0078; 1131 ata_ident->support3 = 0; 1132 ata_ident->queue = 31; 1133 ata_ident->satacapabilities = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 | 1134 ATA_SUPPORT_NCQ); 1135 ata_ident->satacapabilities2 = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED | 1136 (p->ssts & ATA_SS_SPD_MASK) >> 3); 1137 ata_ident->version_major = 0x3f0; 1138 ata_ident->version_minor = 0x28; 1139 ata_ident->support.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE | 1140 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 1141 ata_ident->support.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 1142 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14); 1143 ata_ident->support.extension = (1 << 14); 1144 ata_ident->enabled.command1 = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE | 1145 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP); 1146 ata_ident->enabled.command2 = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE | 1147 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15); 1148 ata_ident->enabled.extension = (1 << 14); 1149 ata_ident->udmamodes = 0x7f; 1150 if (p->xfermode & ATA_UDMA0) 1151 ata_ident->udmamodes |= (1 << ((p->xfermode & 7) + 8)); 1152 ata_ident->lba_size48_1 = sectors; 1153 ata_ident->lba_size48_2 = (sectors >> 16); 1154 ata_ident->lba_size48_3 = (sectors >> 32); 1155 ata_ident->lba_size48_4 = (sectors >> 48); 1156 1157 if (candelete && !ro) { 1158 ata_ident->support3 |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT; 1159 ata_ident->max_dsm_blocks = 1; 1160 ata_ident->support_dsm = ATA_SUPPORT_DSM_TRIM; 1161 } 1162 ata_ident->pss = ATA_PSS_VALID_VALUE; 1163 ata_ident->lsalign = 0x4000; 1164 if (psectsz > sectsz) { 1165 ata_ident->pss |= ATA_PSS_MULTLS; 1166 ata_ident->pss |= ffsl(psectsz / sectsz) - 1; 1167 ata_ident->lsalign |= (psectoff / sectsz); 1168 } 1169 if (sectsz > 512) { 1170 ata_ident->pss |= ATA_PSS_LSSABOVE512; 1171 ata_ident->lss_1 = sectsz / 2; 1172 ata_ident->lss_2 = ((sectsz / 2) >> 16); 1173 } 1174 ata_ident->support2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14); 1175 ata_ident->enabled2 = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14); 1176 ata_ident->transport_major = 0x1020; 1177 ata_ident->integrity = 0x00a5; 1178 } 1179 ahci_checksum((uint8_t*)ata_ident, sizeof(struct ata_params)); 1180 } 1181 1182 static void 1183 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis) 1184 { 1185 if (!p->atapi) { 1186 ahci_write_fis_d2h(p, slot, cfis, 1187 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1188 } else { 1189 ahci_write_fis_piosetup(p); 1190 write_prdt(p, slot, cfis, (void *)&p->ata_ident, sizeof(struct ata_params)); 1191 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY); 1192 } 1193 } 1194 1195 static void 1196 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis) 1197 { 1198 uint8_t buf[36]; 1199 uint8_t *acmd; 1200 unsigned int len; 1201 uint32_t tfd; 1202 1203 acmd = cfis + 0x40; 1204 1205 if (acmd[1] & 1) { /* VPD */ 1206 if (acmd[2] == 0) { /* Supported VPD pages */ 1207 buf[0] = 0x05; 1208 buf[1] = 0; 1209 buf[2] = 0; 1210 buf[3] = 1; 1211 buf[4] = 0; 1212 len = 4 + buf[3]; 1213 } else { 1214 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1215 p->asc = 0x24; 1216 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1217 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1218 ahci_write_fis_d2h(p, slot, cfis, tfd); 1219 return; 1220 } 1221 } else { 1222 buf[0] = 0x05; 1223 buf[1] = 0x80; 1224 buf[2] = 0x00; 1225 buf[3] = 0x21; 1226 buf[4] = 31; 1227 buf[5] = 0; 1228 buf[6] = 0; 1229 buf[7] = 0; 1230 atapi_string(buf + 8, "BHYVE", 8); 1231 atapi_string(buf + 16, "BHYVE DVD-ROM", 16); 1232 atapi_string(buf + 32, "001", 4); 1233 len = sizeof(buf); 1234 } 1235 1236 if (len > acmd[4]) 1237 len = acmd[4]; 1238 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1239 write_prdt(p, slot, cfis, buf, len); 1240 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1241 } 1242 1243 static void 1244 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis) 1245 { 1246 uint8_t buf[8]; 1247 uint64_t sectors; 1248 1249 sectors = blockif_size(p->bctx) / 2048; 1250 be32enc(buf, sectors - 1); 1251 be32enc(buf + 4, 2048); 1252 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1253 write_prdt(p, slot, cfis, buf, sizeof(buf)); 1254 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1255 } 1256 1257 static void 1258 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis) 1259 { 1260 uint8_t *acmd; 1261 uint8_t format; 1262 unsigned int len; 1263 1264 acmd = cfis + 0x40; 1265 1266 len = be16dec(acmd + 7); 1267 format = acmd[9] >> 6; 1268 switch (format) { 1269 case 0: 1270 { 1271 size_t size; 1272 int msf; 1273 uint64_t sectors; 1274 uint8_t start_track, buf[20], *bp; 1275 1276 msf = (acmd[1] >> 1) & 1; 1277 start_track = acmd[6]; 1278 if (start_track > 1 && start_track != 0xaa) { 1279 uint32_t tfd; 1280 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1281 p->asc = 0x24; 1282 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1283 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1284 ahci_write_fis_d2h(p, slot, cfis, tfd); 1285 return; 1286 } 1287 bp = buf + 2; 1288 *bp++ = 1; 1289 *bp++ = 1; 1290 if (start_track <= 1) { 1291 *bp++ = 0; 1292 *bp++ = 0x14; 1293 *bp++ = 1; 1294 *bp++ = 0; 1295 if (msf) { 1296 *bp++ = 0; 1297 lba_to_msf(bp, 0); 1298 bp += 3; 1299 } else { 1300 *bp++ = 0; 1301 *bp++ = 0; 1302 *bp++ = 0; 1303 *bp++ = 0; 1304 } 1305 } 1306 *bp++ = 0; 1307 *bp++ = 0x14; 1308 *bp++ = 0xaa; 1309 *bp++ = 0; 1310 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1311 sectors >>= 2; 1312 if (msf) { 1313 *bp++ = 0; 1314 lba_to_msf(bp, sectors); 1315 bp += 3; 1316 } else { 1317 be32enc(bp, sectors); 1318 bp += 4; 1319 } 1320 size = bp - buf; 1321 be16enc(buf, size - 2); 1322 if (len > size) 1323 len = size; 1324 write_prdt(p, slot, cfis, buf, len); 1325 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1326 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1327 break; 1328 } 1329 case 1: 1330 { 1331 uint8_t buf[12]; 1332 1333 memset(buf, 0, sizeof(buf)); 1334 buf[1] = 0xa; 1335 buf[2] = 0x1; 1336 buf[3] = 0x1; 1337 if (len > sizeof(buf)) 1338 len = sizeof(buf); 1339 write_prdt(p, slot, cfis, buf, len); 1340 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1341 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1342 break; 1343 } 1344 case 2: 1345 { 1346 size_t size; 1347 int msf; 1348 uint64_t sectors; 1349 uint8_t *bp, buf[50]; 1350 1351 msf = (acmd[1] >> 1) & 1; 1352 bp = buf + 2; 1353 *bp++ = 1; 1354 *bp++ = 1; 1355 1356 *bp++ = 1; 1357 *bp++ = 0x14; 1358 *bp++ = 0; 1359 *bp++ = 0xa0; 1360 *bp++ = 0; 1361 *bp++ = 0; 1362 *bp++ = 0; 1363 *bp++ = 0; 1364 *bp++ = 1; 1365 *bp++ = 0; 1366 *bp++ = 0; 1367 1368 *bp++ = 1; 1369 *bp++ = 0x14; 1370 *bp++ = 0; 1371 *bp++ = 0xa1; 1372 *bp++ = 0; 1373 *bp++ = 0; 1374 *bp++ = 0; 1375 *bp++ = 0; 1376 *bp++ = 1; 1377 *bp++ = 0; 1378 *bp++ = 0; 1379 1380 *bp++ = 1; 1381 *bp++ = 0x14; 1382 *bp++ = 0; 1383 *bp++ = 0xa2; 1384 *bp++ = 0; 1385 *bp++ = 0; 1386 *bp++ = 0; 1387 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx); 1388 sectors >>= 2; 1389 if (msf) { 1390 *bp++ = 0; 1391 lba_to_msf(bp, sectors); 1392 bp += 3; 1393 } else { 1394 be32enc(bp, sectors); 1395 bp += 4; 1396 } 1397 1398 *bp++ = 1; 1399 *bp++ = 0x14; 1400 *bp++ = 0; 1401 *bp++ = 1; 1402 *bp++ = 0; 1403 *bp++ = 0; 1404 *bp++ = 0; 1405 if (msf) { 1406 *bp++ = 0; 1407 lba_to_msf(bp, 0); 1408 bp += 3; 1409 } else { 1410 *bp++ = 0; 1411 *bp++ = 0; 1412 *bp++ = 0; 1413 *bp++ = 0; 1414 } 1415 1416 size = bp - buf; 1417 be16enc(buf, size - 2); 1418 if (len > size) 1419 len = size; 1420 write_prdt(p, slot, cfis, buf, len); 1421 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1422 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1423 break; 1424 } 1425 default: 1426 { 1427 uint32_t tfd; 1428 1429 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1430 p->asc = 0x24; 1431 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1432 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1433 ahci_write_fis_d2h(p, slot, cfis, tfd); 1434 break; 1435 } 1436 } 1437 } 1438 1439 static void 1440 atapi_report_luns(struct ahci_port *p, int slot, uint8_t *cfis) 1441 { 1442 uint8_t buf[16]; 1443 1444 memset(buf, 0, sizeof(buf)); 1445 buf[3] = 8; 1446 1447 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1448 write_prdt(p, slot, cfis, buf, sizeof(buf)); 1449 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1450 } 1451 1452 static void 1453 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done) 1454 { 1455 struct ahci_ioreq *aior; 1456 struct ahci_cmd_hdr *hdr; 1457 struct ahci_prdt_entry *prdt; 1458 struct blockif_req *breq; 1459 uint8_t *acmd; 1460 uint64_t lba; 1461 uint32_t len; 1462 int err; 1463 1464 acmd = cfis + 0x40; 1465 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1466 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1467 1468 lba = be32dec(acmd + 2); 1469 if (acmd[0] == READ_10) 1470 len = be16dec(acmd + 7); 1471 else 1472 len = be32dec(acmd + 6); 1473 if (len == 0) { 1474 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1475 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1476 } 1477 lba *= 2048; 1478 len *= 2048; 1479 1480 /* 1481 * Pull request off free list 1482 */ 1483 aior = STAILQ_FIRST(&p->iofhd); 1484 assert(aior != NULL); 1485 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist); 1486 aior->cfis = cfis; 1487 aior->slot = slot; 1488 aior->len = len; 1489 aior->done = done; 1490 breq = &aior->io_req; 1491 breq->br_offset = lba + done; 1492 ahci_build_iov(p, aior, prdt, hdr->prdtl); 1493 1494 /* Mark this command in-flight. */ 1495 p->pending |= 1 << slot; 1496 1497 /* Stuff request onto busy list. */ 1498 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist); 1499 1500 err = blockif_read(p->bctx, breq); 1501 assert(err == 0); 1502 } 1503 1504 static void 1505 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1506 { 1507 uint8_t buf[64]; 1508 uint8_t *acmd; 1509 unsigned int len; 1510 1511 acmd = cfis + 0x40; 1512 len = acmd[4]; 1513 if (len > sizeof(buf)) 1514 len = sizeof(buf); 1515 memset(buf, 0, len); 1516 buf[0] = 0x70 | (1 << 7); 1517 buf[2] = p->sense_key; 1518 buf[7] = 10; 1519 buf[12] = p->asc; 1520 write_prdt(p, slot, cfis, buf, len); 1521 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1522 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1523 } 1524 1525 static void 1526 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis) 1527 { 1528 uint8_t *acmd = cfis + 0x40; 1529 uint32_t tfd; 1530 1531 switch (acmd[4] & 3) { 1532 case 0: 1533 case 1: 1534 case 3: 1535 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1536 tfd = ATA_S_READY | ATA_S_DSC; 1537 break; 1538 case 2: 1539 /* TODO eject media */ 1540 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1541 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1542 p->asc = 0x53; 1543 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1544 break; 1545 } 1546 ahci_write_fis_d2h(p, slot, cfis, tfd); 1547 } 1548 1549 static void 1550 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis) 1551 { 1552 uint8_t *acmd; 1553 uint32_t tfd = 0; 1554 uint8_t pc, code; 1555 unsigned int len; 1556 1557 acmd = cfis + 0x40; 1558 len = be16dec(acmd + 7); 1559 pc = acmd[2] >> 6; 1560 code = acmd[2] & 0x3f; 1561 1562 switch (pc) { 1563 case 0: 1564 switch (code) { 1565 case MODEPAGE_RW_ERROR_RECOVERY: 1566 { 1567 uint8_t buf[16]; 1568 1569 if (len > sizeof(buf)) 1570 len = sizeof(buf); 1571 1572 memset(buf, 0, sizeof(buf)); 1573 be16enc(buf, 16 - 2); 1574 buf[2] = 0x70; 1575 buf[8] = 0x01; 1576 buf[9] = 16 - 10; 1577 buf[11] = 0x05; 1578 write_prdt(p, slot, cfis, buf, len); 1579 tfd = ATA_S_READY | ATA_S_DSC; 1580 break; 1581 } 1582 case MODEPAGE_CD_CAPABILITIES: 1583 { 1584 uint8_t buf[30]; 1585 1586 if (len > sizeof(buf)) 1587 len = sizeof(buf); 1588 1589 memset(buf, 0, sizeof(buf)); 1590 be16enc(buf, 30 - 2); 1591 buf[2] = 0x70; 1592 buf[8] = 0x2A; 1593 buf[9] = 30 - 10; 1594 buf[10] = 0x08; 1595 buf[12] = 0x71; 1596 be16enc(&buf[18], 2); 1597 be16enc(&buf[20], 512); 1598 write_prdt(p, slot, cfis, buf, len); 1599 tfd = ATA_S_READY | ATA_S_DSC; 1600 break; 1601 } 1602 default: 1603 goto error; 1604 break; 1605 } 1606 break; 1607 case 3: 1608 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1609 p->asc = 0x39; 1610 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1611 break; 1612 error: 1613 case 1: 1614 case 2: 1615 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1616 p->asc = 0x24; 1617 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1618 break; 1619 } 1620 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1621 ahci_write_fis_d2h(p, slot, cfis, tfd); 1622 } 1623 1624 static void 1625 atapi_get_event_status_notification(struct ahci_port *p, int slot, 1626 uint8_t *cfis) 1627 { 1628 uint8_t *acmd; 1629 uint32_t tfd; 1630 1631 acmd = cfis + 0x40; 1632 1633 /* we don't support asynchronous operation */ 1634 if (!(acmd[1] & 1)) { 1635 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1636 p->asc = 0x24; 1637 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 1638 } else { 1639 uint8_t buf[8]; 1640 unsigned int len; 1641 1642 len = be16dec(acmd + 7); 1643 if (len > sizeof(buf)) 1644 len = sizeof(buf); 1645 1646 memset(buf, 0, sizeof(buf)); 1647 be16enc(buf, 8 - 2); 1648 buf[2] = 0x04; 1649 buf[3] = 0x10; 1650 buf[5] = 0x02; 1651 write_prdt(p, slot, cfis, buf, len); 1652 tfd = ATA_S_READY | ATA_S_DSC; 1653 } 1654 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1655 ahci_write_fis_d2h(p, slot, cfis, tfd); 1656 } 1657 1658 static void 1659 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1660 { 1661 uint8_t *acmd; 1662 1663 acmd = cfis + 0x40; 1664 1665 #ifdef AHCI_DEBUG 1666 { 1667 int i; 1668 DPRINTF("ACMD:"); 1669 for (i = 0; i < 16; i++) 1670 DPRINTF("%02x ", acmd[i]); 1671 DPRINTF(""); 1672 } 1673 #endif 1674 1675 switch (acmd[0]) { 1676 case TEST_UNIT_READY: 1677 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1678 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1679 break; 1680 case INQUIRY: 1681 atapi_inquiry(p, slot, cfis); 1682 break; 1683 case READ_CAPACITY: 1684 atapi_read_capacity(p, slot, cfis); 1685 break; 1686 case PREVENT_ALLOW: 1687 /* TODO */ 1688 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1689 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1690 break; 1691 case READ_TOC: 1692 atapi_read_toc(p, slot, cfis); 1693 break; 1694 case REPORT_LUNS: 1695 atapi_report_luns(p, slot, cfis); 1696 break; 1697 case READ_10: 1698 case READ_12: 1699 atapi_read(p, slot, cfis, 0); 1700 break; 1701 case REQUEST_SENSE: 1702 atapi_request_sense(p, slot, cfis); 1703 break; 1704 case START_STOP_UNIT: 1705 atapi_start_stop_unit(p, slot, cfis); 1706 break; 1707 case MODE_SENSE_10: 1708 atapi_mode_sense(p, slot, cfis); 1709 break; 1710 case GET_EVENT_STATUS_NOTIFICATION: 1711 atapi_get_event_status_notification(p, slot, cfis); 1712 break; 1713 default: 1714 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 1715 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 1716 p->asc = 0x20; 1717 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) | 1718 ATA_S_READY | ATA_S_ERROR); 1719 break; 1720 } 1721 } 1722 1723 static void 1724 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis) 1725 { 1726 1727 p->tfd |= ATA_S_BUSY; 1728 switch (cfis[2]) { 1729 case ATA_ATA_IDENTIFY: 1730 handle_identify(p, slot, cfis); 1731 break; 1732 case ATA_SETFEATURES: 1733 { 1734 switch (cfis[3]) { 1735 case ATA_SF_ENAB_SATA_SF: 1736 switch (cfis[12]) { 1737 case ATA_SATA_SF_AN: 1738 p->tfd = ATA_S_DSC | ATA_S_READY; 1739 break; 1740 default: 1741 p->tfd = ATA_S_ERROR | ATA_S_READY; 1742 p->tfd |= (ATA_ERROR_ABORT << 8); 1743 break; 1744 } 1745 break; 1746 case ATA_SF_ENAB_WCACHE: 1747 case ATA_SF_DIS_WCACHE: 1748 case ATA_SF_ENAB_RCACHE: 1749 case ATA_SF_DIS_RCACHE: 1750 p->tfd = ATA_S_DSC | ATA_S_READY; 1751 break; 1752 case ATA_SF_SETXFER: 1753 { 1754 switch (cfis[12] & 0xf8) { 1755 case ATA_PIO: 1756 case ATA_PIO0: 1757 break; 1758 case ATA_WDMA0: 1759 case ATA_UDMA0: 1760 p->xfermode = (cfis[12] & 0x7); 1761 break; 1762 } 1763 p->tfd = ATA_S_DSC | ATA_S_READY; 1764 break; 1765 } 1766 default: 1767 p->tfd = ATA_S_ERROR | ATA_S_READY; 1768 p->tfd |= (ATA_ERROR_ABORT << 8); 1769 break; 1770 } 1771 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1772 break; 1773 } 1774 case ATA_SET_MULTI: 1775 if (cfis[12] != 0 && 1776 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) { 1777 p->tfd = ATA_S_ERROR | ATA_S_READY; 1778 p->tfd |= (ATA_ERROR_ABORT << 8); 1779 } else { 1780 p->mult_sectors = cfis[12]; 1781 p->tfd = ATA_S_DSC | ATA_S_READY; 1782 } 1783 ahci_write_fis_d2h(p, slot, cfis, p->tfd); 1784 break; 1785 case ATA_READ: 1786 case ATA_WRITE: 1787 case ATA_READ48: 1788 case ATA_WRITE48: 1789 case ATA_READ_MUL: 1790 case ATA_WRITE_MUL: 1791 case ATA_READ_MUL48: 1792 case ATA_WRITE_MUL48: 1793 case ATA_READ_DMA: 1794 case ATA_WRITE_DMA: 1795 case ATA_READ_DMA48: 1796 case ATA_WRITE_DMA48: 1797 case ATA_READ_FPDMA_QUEUED: 1798 case ATA_WRITE_FPDMA_QUEUED: 1799 ahci_handle_rw(p, slot, cfis, 0); 1800 break; 1801 case ATA_FLUSHCACHE: 1802 case ATA_FLUSHCACHE48: 1803 ahci_handle_flush(p, slot, cfis); 1804 break; 1805 case ATA_DATA_SET_MANAGEMENT: 1806 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM && 1807 cfis[13] == 0 && cfis[12] == 1) { 1808 ahci_handle_dsm_trim(p, slot, cfis); 1809 break; 1810 } 1811 ahci_write_fis_d2h(p, slot, cfis, 1812 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1813 break; 1814 case ATA_SEND_FPDMA_QUEUED: 1815 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM && 1816 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM && 1817 cfis[11] == 0 && cfis[3] == 1) { 1818 ahci_handle_dsm_trim(p, slot, cfis); 1819 break; 1820 } 1821 ahci_write_fis_d2h(p, slot, cfis, 1822 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1823 break; 1824 case ATA_READ_LOG_EXT: 1825 case ATA_READ_LOG_DMA_EXT: 1826 ahci_handle_read_log(p, slot, cfis); 1827 break; 1828 case ATA_SECURITY_FREEZE_LOCK: 1829 case ATA_SMART_CMD: 1830 case ATA_NOP: 1831 ahci_write_fis_d2h(p, slot, cfis, 1832 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1833 break; 1834 case ATA_CHECK_POWER_MODE: 1835 cfis[12] = 0xff; /* always on */ 1836 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1837 break; 1838 case ATA_STANDBY_CMD: 1839 case ATA_STANDBY_IMMEDIATE: 1840 case ATA_IDLE_CMD: 1841 case ATA_IDLE_IMMEDIATE: 1842 case ATA_SLEEP: 1843 case ATA_READ_VERIFY: 1844 case ATA_READ_VERIFY48: 1845 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC); 1846 break; 1847 case ATA_ATAPI_IDENTIFY: 1848 handle_atapi_identify(p, slot, cfis); 1849 break; 1850 case ATA_PACKET_CMD: 1851 if (!p->atapi) { 1852 ahci_write_fis_d2h(p, slot, cfis, 1853 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1854 } else 1855 handle_packet_cmd(p, slot, cfis); 1856 break; 1857 default: 1858 EPRINTLN("Unsupported cmd:%02x", cfis[2]); 1859 ahci_write_fis_d2h(p, slot, cfis, 1860 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR); 1861 break; 1862 } 1863 } 1864 1865 static void 1866 ahci_handle_slot(struct ahci_port *p, int slot) 1867 { 1868 struct ahci_cmd_hdr *hdr; 1869 #ifdef AHCI_DEBUG 1870 struct ahci_prdt_entry *prdt; 1871 #endif 1872 struct pci_ahci_softc *sc; 1873 uint8_t *cfis; 1874 #ifdef AHCI_DEBUG 1875 int cfl, i; 1876 #endif 1877 1878 sc = p->pr_sc; 1879 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1880 #ifdef AHCI_DEBUG 1881 cfl = (hdr->flags & 0x1f) * 4; 1882 #endif 1883 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba, 1884 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry)); 1885 #ifdef AHCI_DEBUG 1886 prdt = (struct ahci_prdt_entry *)(cfis + 0x80); 1887 1888 DPRINTF("cfis:"); 1889 for (i = 0; i < cfl; i++) { 1890 if (i % 10 == 0) 1891 DPRINTF(""); 1892 DPRINTF("%02x ", cfis[i]); 1893 } 1894 DPRINTF(""); 1895 1896 for (i = 0; i < hdr->prdtl; i++) { 1897 DPRINTF("%d@%08"PRIx64"", prdt->dbc & 0x3fffff, prdt->dba); 1898 prdt++; 1899 } 1900 #endif 1901 1902 if (cfis[0] != FIS_TYPE_REGH2D) { 1903 EPRINTLN("Not a H2D FIS:%02x", cfis[0]); 1904 return; 1905 } 1906 1907 if (cfis[1] & 0x80) { 1908 ahci_handle_cmd(p, slot, cfis); 1909 } else { 1910 if (cfis[15] & (1 << 2)) 1911 p->reset = 1; 1912 else if (p->reset) { 1913 p->reset = 0; 1914 ahci_port_reset(p); 1915 } 1916 p->ci &= ~(1 << slot); 1917 } 1918 } 1919 1920 static void 1921 ahci_handle_port(struct ahci_port *p) 1922 { 1923 1924 if (!(p->cmd & AHCI_P_CMD_ST)) 1925 return; 1926 1927 /* 1928 * Search for any new commands to issue ignoring those that 1929 * are already in-flight. Stop if device is busy or in error. 1930 */ 1931 for (; (p->ci & ~p->pending) != 0; p->ccs = ((p->ccs + 1) & 31)) { 1932 if ((p->tfd & (ATA_S_BUSY | ATA_S_DRQ)) != 0) 1933 break; 1934 if (p->waitforclear) 1935 break; 1936 if ((p->ci & ~p->pending & (1 << p->ccs)) != 0) { 1937 p->cmd &= ~AHCI_P_CMD_CCS_MASK; 1938 p->cmd |= p->ccs << AHCI_P_CMD_CCS_SHIFT; 1939 ahci_handle_slot(p, p->ccs); 1940 } 1941 } 1942 } 1943 1944 /* 1945 * blockif callback routine - this runs in the context of the blockif 1946 * i/o thread, so the mutex needs to be acquired. 1947 */ 1948 static void 1949 ata_ioreq_cb(struct blockif_req *br, int err) 1950 { 1951 struct ahci_cmd_hdr *hdr; 1952 struct ahci_ioreq *aior; 1953 struct ahci_port *p; 1954 struct pci_ahci_softc *sc; 1955 uint32_t tfd; 1956 uint8_t *cfis, *dsm; 1957 int slot, ncq; 1958 1959 DPRINTF("%s %d", __func__, err); 1960 1961 ncq = 0; 1962 aior = br->br_param; 1963 p = aior->io_pr; 1964 cfis = aior->cfis; 1965 slot = aior->slot; 1966 sc = p->pr_sc; 1967 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE); 1968 1969 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || 1970 cfis[2] == ATA_READ_FPDMA_QUEUED || 1971 cfis[2] == ATA_SEND_FPDMA_QUEUED) 1972 ncq = 1; 1973 dsm = aior->dsm; 1974 aior->dsm = NULL; 1975 1976 pthread_mutex_lock(&sc->mtx); 1977 1978 /* 1979 * Delete the blockif request from the busy list 1980 */ 1981 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 1982 1983 /* 1984 * Move the blockif request back to the free list 1985 */ 1986 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 1987 1988 if (!err) 1989 hdr->prdbc = aior->done; 1990 1991 if (!err && aior->more) { 1992 if (dsm != NULL) 1993 ahci_handle_next_trim(p, slot, cfis, dsm, 1994 aior->len, aior->done); 1995 else 1996 ahci_handle_rw(p, slot, cfis, aior->done); 1997 goto out; 1998 } 1999 2000 if (!err) 2001 tfd = ATA_S_READY | ATA_S_DSC; 2002 else 2003 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; 2004 if (ncq) 2005 ahci_write_fis_sdb(p, slot, cfis, tfd); 2006 else 2007 ahci_write_fis_d2h(p, slot, cfis, tfd); 2008 2009 /* 2010 * This command is now complete. 2011 */ 2012 p->pending &= ~(1 << slot); 2013 2014 ahci_check_stopped(p); 2015 ahci_handle_port(p); 2016 free(dsm); 2017 out: 2018 pthread_mutex_unlock(&sc->mtx); 2019 DPRINTF("%s exit", __func__); 2020 } 2021 2022 static void 2023 atapi_ioreq_cb(struct blockif_req *br, int err) 2024 { 2025 struct ahci_cmd_hdr *hdr; 2026 struct ahci_ioreq *aior; 2027 struct ahci_port *p; 2028 struct pci_ahci_softc *sc; 2029 uint8_t *cfis; 2030 uint32_t tfd; 2031 int slot; 2032 2033 DPRINTF("%s %d", __func__, err); 2034 2035 aior = br->br_param; 2036 p = aior->io_pr; 2037 cfis = aior->cfis; 2038 slot = aior->slot; 2039 sc = p->pr_sc; 2040 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE); 2041 2042 pthread_mutex_lock(&sc->mtx); 2043 2044 /* 2045 * Delete the blockif request from the busy list 2046 */ 2047 TAILQ_REMOVE(&p->iobhd, aior, io_blist); 2048 2049 /* 2050 * Move the blockif request back to the free list 2051 */ 2052 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist); 2053 2054 if (!err) 2055 hdr->prdbc = aior->done; 2056 2057 if (!err && aior->more) { 2058 atapi_read(p, slot, cfis, aior->done); 2059 goto out; 2060 } 2061 2062 if (!err) { 2063 tfd = ATA_S_READY | ATA_S_DSC; 2064 } else { 2065 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST; 2066 p->asc = 0x21; 2067 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR; 2068 } 2069 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN; 2070 ahci_write_fis_d2h(p, slot, cfis, tfd); 2071 2072 /* 2073 * This command is now complete. 2074 */ 2075 p->pending &= ~(1 << slot); 2076 2077 ahci_check_stopped(p); 2078 ahci_handle_port(p); 2079 out: 2080 pthread_mutex_unlock(&sc->mtx); 2081 DPRINTF("%s exit", __func__); 2082 } 2083 2084 static void 2085 pci_ahci_ioreq_init(struct ahci_port *pr) 2086 { 2087 struct ahci_ioreq *vr; 2088 int i; 2089 2090 pr->ioqsz = blockif_queuesz(pr->bctx); 2091 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq)); 2092 STAILQ_INIT(&pr->iofhd); 2093 2094 /* 2095 * Add all i/o request entries to the free queue 2096 */ 2097 for (i = 0; i < pr->ioqsz; i++) { 2098 vr = &pr->ioreq[i]; 2099 vr->io_pr = pr; 2100 if (!pr->atapi) 2101 vr->io_req.br_callback = ata_ioreq_cb; 2102 else 2103 vr->io_req.br_callback = atapi_ioreq_cb; 2104 vr->io_req.br_param = vr; 2105 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist); 2106 } 2107 2108 TAILQ_INIT(&pr->iobhd); 2109 } 2110 2111 static void 2112 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 2113 { 2114 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 2115 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 2116 struct ahci_port *p = &sc->port[port]; 2117 2118 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"", 2119 port, offset, value); 2120 2121 switch (offset) { 2122 case AHCI_P_CLB: 2123 p->clb = value; 2124 break; 2125 case AHCI_P_CLBU: 2126 p->clbu = value; 2127 break; 2128 case AHCI_P_FB: 2129 p->fb = value; 2130 break; 2131 case AHCI_P_FBU: 2132 p->fbu = value; 2133 break; 2134 case AHCI_P_IS: 2135 p->is &= ~value; 2136 ahci_port_intr(p); 2137 break; 2138 case AHCI_P_IE: 2139 p->ie = value & 0xFDC000FF; 2140 ahci_port_intr(p); 2141 break; 2142 case AHCI_P_CMD: 2143 { 2144 p->cmd &= ~(AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD | 2145 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE | 2146 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE | 2147 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK); 2148 p->cmd |= (AHCI_P_CMD_ST | AHCI_P_CMD_SUD | AHCI_P_CMD_POD | 2149 AHCI_P_CMD_CLO | AHCI_P_CMD_FRE | AHCI_P_CMD_APSTE | 2150 AHCI_P_CMD_ATAPI | AHCI_P_CMD_DLAE | AHCI_P_CMD_ALPE | 2151 AHCI_P_CMD_ASP | AHCI_P_CMD_ICC_MASK) & value; 2152 2153 if (!(value & AHCI_P_CMD_ST)) { 2154 ahci_port_stop(p); 2155 } else { 2156 uint64_t clb; 2157 2158 p->cmd |= AHCI_P_CMD_CR; 2159 clb = (uint64_t)p->clbu << 32 | p->clb; 2160 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb, 2161 AHCI_CL_SIZE * AHCI_MAX_SLOTS); 2162 } 2163 2164 if (value & AHCI_P_CMD_FRE) { 2165 uint64_t fb; 2166 2167 p->cmd |= AHCI_P_CMD_FR; 2168 fb = (uint64_t)p->fbu << 32 | p->fb; 2169 /* we don't support FBSCP, so rfis size is 256Bytes */ 2170 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256); 2171 } else { 2172 p->cmd &= ~AHCI_P_CMD_FR; 2173 } 2174 2175 if (value & AHCI_P_CMD_CLO) { 2176 p->tfd &= ~(ATA_S_BUSY | ATA_S_DRQ); 2177 p->cmd &= ~AHCI_P_CMD_CLO; 2178 } 2179 2180 if (value & AHCI_P_CMD_ICC_MASK) { 2181 p->cmd &= ~AHCI_P_CMD_ICC_MASK; 2182 } 2183 2184 ahci_handle_port(p); 2185 break; 2186 } 2187 case AHCI_P_TFD: 2188 case AHCI_P_SIG: 2189 case AHCI_P_SSTS: 2190 EPRINTLN("pci_ahci_port: read only registers 0x%"PRIx64"", offset); 2191 break; 2192 case AHCI_P_SCTL: 2193 p->sctl = value; 2194 if (!(p->cmd & AHCI_P_CMD_ST)) { 2195 if (value & ATA_SC_DET_RESET) 2196 ahci_port_reset(p); 2197 } 2198 break; 2199 case AHCI_P_SERR: 2200 p->serr &= ~value; 2201 break; 2202 case AHCI_P_SACT: 2203 p->sact |= value; 2204 break; 2205 case AHCI_P_CI: 2206 p->ci |= value; 2207 ahci_handle_port(p); 2208 break; 2209 case AHCI_P_SNTF: 2210 case AHCI_P_FBS: 2211 default: 2212 break; 2213 } 2214 } 2215 2216 static void 2217 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value) 2218 { 2219 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"", 2220 offset, value); 2221 2222 switch (offset) { 2223 case AHCI_CAP: 2224 case AHCI_PI: 2225 case AHCI_VS: 2226 case AHCI_CAP2: 2227 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"", offset); 2228 break; 2229 case AHCI_GHC: 2230 if (value & AHCI_GHC_HR) { 2231 ahci_reset(sc); 2232 break; 2233 } 2234 if (value & AHCI_GHC_IE) 2235 sc->ghc |= AHCI_GHC_IE; 2236 else 2237 sc->ghc &= ~AHCI_GHC_IE; 2238 ahci_generate_intr(sc, 0xffffffff); 2239 break; 2240 case AHCI_IS: 2241 sc->is &= ~value; 2242 ahci_generate_intr(sc, value); 2243 break; 2244 default: 2245 break; 2246 } 2247 } 2248 2249 static void 2250 pci_ahci_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size, 2251 uint64_t value) 2252 { 2253 struct pci_ahci_softc *sc = pi->pi_arg; 2254 2255 assert(baridx == 5); 2256 assert((offset % 4) == 0 && size == 4); 2257 2258 pthread_mutex_lock(&sc->mtx); 2259 2260 if (offset < AHCI_OFFSET) 2261 pci_ahci_host_write(sc, offset, value); 2262 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP) 2263 pci_ahci_port_write(sc, offset, value); 2264 else 2265 EPRINTLN("pci_ahci: unknown i/o write offset 0x%"PRIx64"", offset); 2266 2267 pthread_mutex_unlock(&sc->mtx); 2268 } 2269 2270 static uint64_t 2271 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset) 2272 { 2273 uint32_t value; 2274 2275 switch (offset) { 2276 case AHCI_CAP: 2277 case AHCI_GHC: 2278 case AHCI_IS: 2279 case AHCI_PI: 2280 case AHCI_VS: 2281 case AHCI_CCCC: 2282 case AHCI_CCCP: 2283 case AHCI_EM_LOC: 2284 case AHCI_EM_CTL: 2285 case AHCI_CAP2: 2286 { 2287 uint32_t *p = &sc->cap; 2288 p += (offset - AHCI_CAP) / sizeof(uint32_t); 2289 value = *p; 2290 break; 2291 } 2292 default: 2293 value = 0; 2294 break; 2295 } 2296 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x", 2297 offset, value); 2298 2299 return (value); 2300 } 2301 2302 static uint64_t 2303 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset) 2304 { 2305 uint32_t value; 2306 int port = (offset - AHCI_OFFSET) / AHCI_STEP; 2307 offset = (offset - AHCI_OFFSET) % AHCI_STEP; 2308 2309 switch (offset) { 2310 case AHCI_P_CLB: 2311 case AHCI_P_CLBU: 2312 case AHCI_P_FB: 2313 case AHCI_P_FBU: 2314 case AHCI_P_IS: 2315 case AHCI_P_IE: 2316 case AHCI_P_CMD: 2317 case AHCI_P_TFD: 2318 case AHCI_P_SIG: 2319 case AHCI_P_SSTS: 2320 case AHCI_P_SCTL: 2321 case AHCI_P_SERR: 2322 case AHCI_P_SACT: 2323 case AHCI_P_CI: 2324 case AHCI_P_SNTF: 2325 case AHCI_P_FBS: 2326 { 2327 uint32_t *p= &sc->port[port].clb; 2328 p += (offset - AHCI_P_CLB) / sizeof(uint32_t); 2329 value = *p; 2330 break; 2331 } 2332 default: 2333 value = 0; 2334 break; 2335 } 2336 2337 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x", 2338 port, offset, value); 2339 2340 return value; 2341 } 2342 2343 static uint64_t 2344 pci_ahci_read(struct pci_devinst *pi, int baridx, uint64_t regoff, int size) 2345 { 2346 struct pci_ahci_softc *sc = pi->pi_arg; 2347 uint64_t offset; 2348 uint32_t value; 2349 2350 assert(baridx == 5); 2351 assert(size == 1 || size == 2 || size == 4); 2352 assert((regoff & (size - 1)) == 0); 2353 2354 pthread_mutex_lock(&sc->mtx); 2355 2356 offset = regoff & ~0x3; /* round down to a multiple of 4 bytes */ 2357 if (offset < AHCI_OFFSET) 2358 value = pci_ahci_host_read(sc, offset); 2359 else if (offset < (uint64_t)AHCI_OFFSET + sc->ports * AHCI_STEP) 2360 value = pci_ahci_port_read(sc, offset); 2361 else { 2362 value = 0; 2363 EPRINTLN("pci_ahci: unknown i/o read offset 0x%"PRIx64"", 2364 regoff); 2365 } 2366 value >>= 8 * (regoff & 0x3); 2367 2368 pthread_mutex_unlock(&sc->mtx); 2369 2370 return (value); 2371 } 2372 2373 /* 2374 * Each AHCI controller has a "port" node which contains nodes for 2375 * each port named after the decimal number of the port (no leading 2376 * zeroes). Port nodes contain a "type" ("hd" or "cd"), as well as 2377 * options for blockif. For example: 2378 * 2379 * pci.0.1.0 2380 * .device="ahci" 2381 * .port 2382 * .0 2383 * .type="hd" 2384 * .path="/path/to/image" 2385 */ 2386 static int 2387 pci_ahci_legacy_config_port(nvlist_t *nvl, int port, const char *type, 2388 const char *opts) 2389 { 2390 char node_name[sizeof("XX")]; 2391 nvlist_t *port_nvl; 2392 2393 snprintf(node_name, sizeof(node_name), "%d", port); 2394 port_nvl = create_relative_config_node(nvl, node_name); 2395 set_config_value_node(port_nvl, "type", type); 2396 return (blockif_legacy_config(port_nvl, opts)); 2397 } 2398 2399 static int 2400 pci_ahci_legacy_config(nvlist_t *nvl, const char *opts) 2401 { 2402 nvlist_t *ports_nvl; 2403 const char *type; 2404 char *next, *next2, *str, *tofree; 2405 int p, ret; 2406 2407 if (opts == NULL) 2408 return (0); 2409 2410 ports_nvl = create_relative_config_node(nvl, "port"); 2411 ret = 1; 2412 tofree = str = strdup(opts); 2413 for (p = 0; p < MAX_PORTS && str != NULL; p++, str = next) { 2414 /* Identify and cut off type of present port. */ 2415 if (strncmp(str, "hd:", 3) == 0) { 2416 type = "hd"; 2417 str += 3; 2418 } else if (strncmp(str, "cd:", 3) == 0) { 2419 type = "cd"; 2420 str += 3; 2421 } else 2422 type = NULL; 2423 2424 /* Find and cut off the next port options. */ 2425 next = strstr(str, ",hd:"); 2426 next2 = strstr(str, ",cd:"); 2427 if (next == NULL || (next2 != NULL && next2 < next)) 2428 next = next2; 2429 if (next != NULL) { 2430 next[0] = 0; 2431 next++; 2432 } 2433 2434 if (str[0] == 0) 2435 continue; 2436 2437 if (type == NULL) { 2438 EPRINTLN("Missing or invalid type for port %d: \"%s\"", 2439 p, str); 2440 goto out; 2441 } 2442 2443 if (pci_ahci_legacy_config_port(ports_nvl, p, type, str) != 0) 2444 goto out; 2445 } 2446 ret = 0; 2447 out: 2448 free(tofree); 2449 return (ret); 2450 } 2451 2452 static int 2453 pci_ahci_cd_legacy_config(nvlist_t *nvl, const char *opts) 2454 { 2455 nvlist_t *ports_nvl; 2456 2457 ports_nvl = create_relative_config_node(nvl, "port"); 2458 return (pci_ahci_legacy_config_port(ports_nvl, 0, "cd", opts)); 2459 } 2460 2461 static int 2462 pci_ahci_hd_legacy_config(nvlist_t *nvl, const char *opts) 2463 { 2464 nvlist_t *ports_nvl; 2465 2466 ports_nvl = create_relative_config_node(nvl, "port"); 2467 return (pci_ahci_legacy_config_port(ports_nvl, 0, "hd", opts)); 2468 } 2469 2470 static int 2471 pci_ahci_init(struct pci_devinst *pi, nvlist_t *nvl) 2472 { 2473 char bident[sizeof("XXX:XXX:XXX")]; 2474 char node_name[sizeof("XX")]; 2475 struct blockif_ctxt *bctxt; 2476 struct pci_ahci_softc *sc; 2477 int atapi, ret, slots, p; 2478 MD5_CTX mdctx; 2479 u_char digest[16]; 2480 const char *path, *type, *value; 2481 nvlist_t *ports_nvl, *port_nvl; 2482 2483 ret = 0; 2484 2485 #ifdef AHCI_DEBUG 2486 dbg = fopen("/tmp/log", "w+"); 2487 #endif 2488 2489 sc = calloc(1, sizeof(struct pci_ahci_softc)); 2490 pi->pi_arg = sc; 2491 sc->asc_pi = pi; 2492 pthread_mutex_init(&sc->mtx, NULL); 2493 sc->ports = 0; 2494 sc->pi = 0; 2495 slots = 32; 2496 2497 ports_nvl = find_relative_config_node(nvl, "port"); 2498 for (p = 0; ports_nvl != NULL && p < MAX_PORTS; p++) { 2499 struct ata_params *ata_ident = &sc->port[p].ata_ident; 2500 char ident[AHCI_PORT_IDENT]; 2501 2502 snprintf(node_name, sizeof(node_name), "%d", p); 2503 port_nvl = find_relative_config_node(ports_nvl, node_name); 2504 if (port_nvl == NULL) 2505 continue; 2506 2507 type = get_config_value_node(port_nvl, "type"); 2508 if (type == NULL) 2509 continue; 2510 2511 if (strcmp(type, "hd") == 0) 2512 atapi = 0; 2513 else 2514 atapi = 1; 2515 2516 /* 2517 * Attempt to open the backing image. Use the PCI slot/func 2518 * and the port number for the identifier string. 2519 */ 2520 snprintf(bident, sizeof(bident), "%u:%u:%u", pi->pi_slot, 2521 pi->pi_func, p); 2522 2523 bctxt = blockif_open(port_nvl, bident); 2524 if (bctxt == NULL) { 2525 sc->ports = p; 2526 ret = 1; 2527 goto open_fail; 2528 } 2529 2530 ret = blockif_add_boot_device(pi, bctxt); 2531 if (ret) { 2532 sc->ports = p; 2533 goto open_fail; 2534 } 2535 2536 sc->port[p].bctx = bctxt; 2537 sc->port[p].pr_sc = sc; 2538 sc->port[p].port = p; 2539 sc->port[p].atapi = atapi; 2540 2541 /* 2542 * Create an identifier for the backing file. 2543 * Use parts of the md5 sum of the filename 2544 */ 2545 path = get_config_value_node(port_nvl, "path"); 2546 MD5Init(&mdctx); 2547 MD5Update(&mdctx, path, strlen(path)); 2548 MD5Final(digest, &mdctx); 2549 snprintf(ident, AHCI_PORT_IDENT, 2550 "BHYVE-%02X%02X-%02X%02X-%02X%02X", 2551 digest[0], digest[1], digest[2], digest[3], digest[4], 2552 digest[5]); 2553 2554 memset(ata_ident, 0, sizeof(struct ata_params)); 2555 ata_string((uint8_t*)&ata_ident->serial, ident, 20); 2556 ata_string((uint8_t*)&ata_ident->revision, "001", 8); 2557 if (atapi) 2558 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DVD ROM", 40); 2559 else 2560 ata_string((uint8_t*)&ata_ident->model, "BHYVE SATA DISK", 40); 2561 value = get_config_value_node(port_nvl, "nmrr"); 2562 if (value != NULL) 2563 ata_ident->media_rotation_rate = atoi(value); 2564 value = get_config_value_node(port_nvl, "ser"); 2565 if (value != NULL) 2566 ata_string((uint8_t*)(&ata_ident->serial), value, 20); 2567 value = get_config_value_node(port_nvl, "rev"); 2568 if (value != NULL) 2569 ata_string((uint8_t*)(&ata_ident->revision), value, 8); 2570 value = get_config_value_node(port_nvl, "model"); 2571 if (value != NULL) 2572 ata_string((uint8_t*)(&ata_ident->model), value, 40); 2573 ata_identify_init(&sc->port[p], atapi); 2574 2575 #ifndef __FreeBSD__ 2576 /* 2577 * Attempt to enable the write cache for this device, as the 2578 * guest will issue FLUSH commands when it requires durability. 2579 * 2580 * Failure here is fine, since an always-sync device will not 2581 * have an impact on correctness. 2582 */ 2583 (void) blockif_set_wce(bctxt, 1); 2584 #endif 2585 2586 /* 2587 * Allocate blockif request structures and add them 2588 * to the free list 2589 */ 2590 pci_ahci_ioreq_init(&sc->port[p]); 2591 2592 sc->pi |= (1 << p); 2593 if (sc->port[p].ioqsz < slots) 2594 slots = sc->port[p].ioqsz; 2595 } 2596 sc->ports = p; 2597 2598 /* Intel ICH8 AHCI */ 2599 --slots; 2600 if (sc->ports < DEF_PORTS) 2601 sc->ports = DEF_PORTS; 2602 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF | 2603 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP | 2604 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)| 2605 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC | 2606 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1); 2607 2608 sc->vs = 0x10300; 2609 sc->cap2 = AHCI_CAP2_APST; 2610 ahci_reset(sc); 2611 2612 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821); 2613 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086); 2614 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE); 2615 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA); 2616 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0); 2617 p = MIN(sc->ports, 16); 2618 p = flsl(p) - ((p & (p - 1)) ? 0 : 1); 2619 pci_emul_add_msicap(pi, 1 << p); 2620 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32, 2621 AHCI_OFFSET + sc->ports * AHCI_STEP); 2622 2623 pci_lintr_request(pi); 2624 2625 open_fail: 2626 if (ret) { 2627 for (p = 0; p < sc->ports; p++) { 2628 if (sc->port[p].bctx != NULL) 2629 blockif_close(sc->port[p].bctx); 2630 } 2631 free(sc); 2632 } 2633 2634 return (ret); 2635 } 2636 2637 /* 2638 * Use separate emulation names to distinguish drive and atapi devices 2639 */ 2640 static const struct pci_devemu pci_de_ahci = { 2641 .pe_emu = "ahci", 2642 .pe_init = pci_ahci_init, 2643 .pe_legacy_config = pci_ahci_legacy_config, 2644 .pe_barwrite = pci_ahci_write, 2645 .pe_barread = pci_ahci_read, 2646 }; 2647 PCI_EMUL_SET(pci_de_ahci); 2648 2649 static const struct pci_devemu pci_de_ahci_hd = { 2650 .pe_emu = "ahci-hd", 2651 .pe_legacy_config = pci_ahci_hd_legacy_config, 2652 .pe_alias = "ahci", 2653 }; 2654 PCI_EMUL_SET(pci_de_ahci_hd); 2655 2656 static const struct pci_devemu pci_de_ahci_cd = { 2657 .pe_emu = "ahci-cd", 2658 .pe_legacy_config = pci_ahci_cd_legacy_config, 2659 .pe_alias = "ahci", 2660 }; 2661 PCI_EMUL_SET(pci_de_ahci_cd); 2662