1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2013 Neel Natu <neel@freebsd.org> 5 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com> 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* 31 * Copyright 2018 Joyent, Inc. 32 */ 33 34 35 #include <sys/types.h> 36 #include <machine/vmm.h> 37 38 #include <err.h> 39 #include <stdio.h> 40 #include <stdlib.h> 41 #include <string.h> 42 43 #include <vmmapi.h> 44 45 #include "acpi.h" 46 #include "debug.h" 47 #include "bootrom.h" 48 #include "config.h" 49 #include "inout.h" 50 #include "pci_emul.h" 51 #include "pci_irq.h" 52 #include "pci_lpc.h" 53 #include "pci_passthru.h" 54 #include "pctestdev.h" 55 #include "tpm_device.h" 56 #include "uart_emul.h" 57 58 #define IO_ICU1 0x20 59 #define IO_ICU2 0xA0 60 61 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt); 62 SET_DECLARE(lpc_sysres_set, struct lpc_sysres); 63 64 #define ELCR_PORT 0x4d0 65 SYSRES_IO(ELCR_PORT, 2); 66 67 #define IO_TIMER1_PORT 0x40 68 69 #define NMISC_PORT 0x61 70 SYSRES_IO(NMISC_PORT, 1); 71 72 static struct pci_devinst *lpc_bridge; 73 74 #define LPC_UART_NUM 4 75 static struct lpc_uart_softc { 76 struct uart_ns16550_softc *uart_softc; 77 int iobase; 78 int irq; 79 int enabled; 80 } lpc_uart_softc[LPC_UART_NUM]; 81 82 static const char *lpc_uart_names[LPC_UART_NUM] = { 83 "com1", "com2", "com3", "com4" 84 }; 85 86 static const char *lpc_uart_acpi_names[LPC_UART_NUM] = { 87 "COM1", "COM2", "COM3", "COM4" 88 }; 89 90 /* 91 * LPC device configuration is in the following form: 92 * <lpc_device_name>[,<options>] 93 * For e.g. "com1,stdio" or "bootrom,/var/romfile" 94 */ 95 int 96 lpc_device_parse(const char *opts) 97 { 98 int unit, error; 99 char *str, *cpy, *lpcdev, *node_name; 100 const char *romfile, *varfile, *tpm_type, *tpm_path; 101 102 error = -1; 103 str = cpy = strdup(opts); 104 lpcdev = strsep(&str, ","); 105 if (lpcdev != NULL) { 106 if (strcasecmp(lpcdev, "bootrom") == 0) { 107 romfile = strsep(&str, ","); 108 if (romfile == NULL) { 109 errx(4, "invalid bootrom option \"%s\"", opts); 110 } 111 set_config_value("bootrom", romfile); 112 113 varfile = strsep(&str, ","); 114 if (varfile == NULL) { 115 error = 0; 116 goto done; 117 } 118 if (strchr(varfile, '=') == NULL) { 119 set_config_value("bootvars", varfile); 120 } else { 121 /* varfile doesn't exist, it's another config 122 * option */ 123 pci_parse_legacy_config(find_config_node("lpc"), 124 varfile); 125 } 126 127 pci_parse_legacy_config(find_config_node("lpc"), str); 128 error = 0; 129 goto done; 130 } 131 if (strcasecmp(lpcdev, "tpm") == 0) { 132 nvlist_t *nvl = create_config_node("tpm"); 133 134 tpm_type = strsep(&str, ","); 135 if (tpm_type == NULL) { 136 errx(4, "invalid tpm type \"%s\"", opts); 137 } 138 set_config_value_node(nvl, "type", tpm_type); 139 140 tpm_path = strsep(&str, ","); 141 if (tpm_path == NULL) { 142 errx(4, "invalid tpm path \"%s\"", opts); 143 } 144 set_config_value_node(nvl, "path", tpm_path); 145 146 pci_parse_legacy_config(find_config_node("tpm"), str); 147 148 set_config_value_node_if_unset(nvl, "version", "2.0"); 149 error = 0; 150 goto done; 151 } 152 for (unit = 0; unit < LPC_UART_NUM; unit++) { 153 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) { 154 asprintf(&node_name, "lpc.%s.path", 155 lpc_uart_names[unit]); 156 set_config_value(node_name, str); 157 free(node_name); 158 error = 0; 159 goto done; 160 } 161 } 162 if (strcasecmp(lpcdev, pctestdev_getname()) == 0) { 163 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 164 set_config_bool(node_name, true); 165 free(node_name); 166 error = 0; 167 goto done; 168 } 169 } 170 171 done: 172 free(cpy); 173 174 return (error); 175 } 176 177 void 178 lpc_print_supported_devices(void) 179 { 180 size_t i; 181 182 printf("bootrom\n"); 183 for (i = 0; i < LPC_UART_NUM; i++) 184 printf("%s\n", lpc_uart_names[i]); 185 printf("tpm\n"); 186 printf("%s\n", pctestdev_getname()); 187 } 188 189 const char * 190 lpc_fwcfg(void) 191 { 192 return (get_config_value("lpc.fwcfg")); 193 } 194 195 static void 196 lpc_uart_intr_assert(void *arg) 197 { 198 struct lpc_uart_softc *sc = arg; 199 200 assert(sc->irq >= 0); 201 202 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq); 203 } 204 205 static void 206 lpc_uart_intr_deassert(void *arg __unused) 207 { 208 /* 209 * The COM devices on the LPC bus generate edge triggered interrupts, 210 * so nothing more to do here. 211 */ 212 } 213 214 static int 215 lpc_uart_io_handler(struct vmctx *ctx __unused, int in, 216 int port, int bytes, uint32_t *eax, void *arg) 217 { 218 int offset; 219 struct lpc_uart_softc *sc = arg; 220 221 offset = port - sc->iobase; 222 223 switch (bytes) { 224 case 1: 225 if (in) 226 *eax = uart_ns16550_read(sc->uart_softc, offset); 227 else 228 uart_ns16550_write(sc->uart_softc, offset, *eax); 229 break; 230 case 2: 231 if (in) { 232 *eax = uart_ns16550_read(sc->uart_softc, offset); 233 *eax |= 234 uart_ns16550_read(sc->uart_softc, offset + 1) << 8; 235 } else { 236 uart_ns16550_write(sc->uart_softc, offset, *eax); 237 uart_ns16550_write(sc->uart_softc, offset + 1, 238 *eax >> 8); 239 } 240 break; 241 #ifndef __FreeBSD__ 242 case 4: 243 if (in) { 244 *eax = uart_ns16550_read(sc->uart_softc, offset); 245 *eax |= uart_ns16550_read(sc->uart_softc, 246 offset + 1) << 8; 247 *eax |= uart_ns16550_read(sc->uart_softc, 248 offset + 2) << 16; 249 *eax |= uart_ns16550_read(sc->uart_softc, 250 offset + 3) << 24; 251 } else { 252 uart_ns16550_write(sc->uart_softc, offset, *eax); 253 uart_ns16550_write(sc->uart_softc, 254 offset + 1, *eax >> 8); 255 uart_ns16550_write(sc->uart_softc, 256 offset + 2, *eax >> 16); 257 uart_ns16550_write(sc->uart_softc, 258 offset + 3, *eax >> 24); 259 } 260 break; 261 #endif 262 default: 263 return (-1); 264 } 265 266 return (0); 267 } 268 269 static int 270 lpc_init(struct vmctx *ctx) 271 { 272 struct lpc_uart_softc *sc; 273 struct inout_port iop; 274 const char *backend, *name; 275 char *node_name; 276 int unit, error; 277 278 /* COM1 and COM2 */ 279 for (unit = 0; unit < LPC_UART_NUM; unit++) { 280 sc = &lpc_uart_softc[unit]; 281 name = lpc_uart_names[unit]; 282 283 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) { 284 EPRINTLN("Unable to allocate resources for " 285 "LPC device %s", name); 286 return (-1); 287 } 288 pci_irq_reserve(sc->irq); 289 290 sc->uart_softc = uart_ns16550_init(lpc_uart_intr_assert, 291 lpc_uart_intr_deassert, sc); 292 293 asprintf(&node_name, "lpc.%s.path", name); 294 backend = get_config_value(node_name); 295 free(node_name); 296 if (backend != NULL && 297 uart_ns16550_tty_open(sc->uart_softc, backend) != 0) { 298 EPRINTLN("Unable to initialize backend '%s' " 299 "for LPC device %s", backend, name); 300 return (-1); 301 } 302 303 bzero(&iop, sizeof(struct inout_port)); 304 iop.name = name; 305 iop.port = sc->iobase; 306 iop.size = UART_NS16550_IO_BAR_SIZE; 307 iop.flags = IOPORT_F_INOUT; 308 iop.handler = lpc_uart_io_handler; 309 iop.arg = sc; 310 311 error = register_inout(&iop); 312 assert(error == 0); 313 sc->enabled = 1; 314 } 315 316 /* pc-testdev */ 317 asprintf(&node_name, "lpc.%s", pctestdev_getname()); 318 if (get_config_bool_default(node_name, false)) { 319 error = pctestdev_init(ctx); 320 if (error) 321 return (error); 322 } 323 free(node_name); 324 325 return (0); 326 } 327 328 static void 329 pci_lpc_write_dsdt(struct pci_devinst *pi) 330 { 331 struct lpc_dsdt **ldpp, *ldp; 332 333 dsdt_line(""); 334 dsdt_line("Device (ISA)"); 335 dsdt_line("{"); 336 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func); 337 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)"); 338 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)"); 339 dsdt_line(" {"); 340 dsdt_line(" Offset (0x60),"); 341 dsdt_line(" PIRA, 8,"); 342 dsdt_line(" PIRB, 8,"); 343 dsdt_line(" PIRC, 8,"); 344 dsdt_line(" PIRD, 8,"); 345 dsdt_line(" Offset (0x68),"); 346 dsdt_line(" PIRE, 8,"); 347 dsdt_line(" PIRF, 8,"); 348 dsdt_line(" PIRG, 8,"); 349 dsdt_line(" PIRH, 8"); 350 dsdt_line(" }"); 351 dsdt_line(""); 352 353 dsdt_indent(1); 354 SET_FOREACH(ldpp, lpc_dsdt_set) { 355 ldp = *ldpp; 356 ldp->handler(); 357 } 358 359 dsdt_line(""); 360 dsdt_line("Device (PIC)"); 361 dsdt_line("{"); 362 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))"); 363 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 364 dsdt_line(" {"); 365 dsdt_indent(2); 366 dsdt_fixed_ioport(IO_ICU1, 2); 367 dsdt_fixed_ioport(IO_ICU2, 2); 368 dsdt_fixed_irq(2); 369 dsdt_unindent(2); 370 dsdt_line(" })"); 371 dsdt_line("}"); 372 373 dsdt_line(""); 374 dsdt_line("Device (TIMR)"); 375 dsdt_line("{"); 376 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))"); 377 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 378 dsdt_line(" {"); 379 dsdt_indent(2); 380 dsdt_fixed_ioport(IO_TIMER1_PORT, 4); 381 dsdt_fixed_irq(0); 382 dsdt_unindent(2); 383 dsdt_line(" })"); 384 dsdt_line("}"); 385 dsdt_unindent(1); 386 387 dsdt_line("}"); 388 } 389 390 static void 391 pci_lpc_sysres_dsdt(void) 392 { 393 struct lpc_sysres **lspp, *lsp; 394 395 dsdt_line(""); 396 dsdt_line("Device (SIO)"); 397 dsdt_line("{"); 398 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))"); 399 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 400 dsdt_line(" {"); 401 402 dsdt_indent(2); 403 SET_FOREACH(lspp, lpc_sysres_set) { 404 lsp = *lspp; 405 switch (lsp->type) { 406 case LPC_SYSRES_IO: 407 dsdt_fixed_ioport(lsp->base, lsp->length); 408 break; 409 case LPC_SYSRES_MEM: 410 dsdt_fixed_mem32(lsp->base, lsp->length); 411 break; 412 } 413 } 414 dsdt_unindent(2); 415 416 dsdt_line(" })"); 417 dsdt_line("}"); 418 } 419 LPC_DSDT(pci_lpc_sysres_dsdt); 420 421 static void 422 pci_lpc_uart_dsdt(void) 423 { 424 struct lpc_uart_softc *sc; 425 int unit; 426 427 for (unit = 0; unit < LPC_UART_NUM; unit++) { 428 sc = &lpc_uart_softc[unit]; 429 if (!sc->enabled) 430 continue; 431 dsdt_line(""); 432 dsdt_line("Device (%s)", lpc_uart_acpi_names[unit]); 433 dsdt_line("{"); 434 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))"); 435 dsdt_line(" Name (_UID, %d)", unit + 1); 436 dsdt_line(" Name (_CRS, ResourceTemplate ()"); 437 dsdt_line(" {"); 438 dsdt_indent(2); 439 dsdt_fixed_ioport(sc->iobase, UART_NS16550_IO_BAR_SIZE); 440 dsdt_fixed_irq(sc->irq); 441 dsdt_unindent(2); 442 dsdt_line(" })"); 443 dsdt_line("}"); 444 } 445 } 446 LPC_DSDT(pci_lpc_uart_dsdt); 447 448 static int 449 pci_lpc_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val) 450 { 451 int pirq_pin; 452 453 if (bytes == 1) { 454 pirq_pin = 0; 455 if (coff >= 0x60 && coff <= 0x63) 456 pirq_pin = coff - 0x60 + 1; 457 if (coff >= 0x68 && coff <= 0x6b) 458 pirq_pin = coff - 0x68 + 5; 459 if (pirq_pin != 0) { 460 pirq_write(pi->pi_vmctx, pirq_pin, val); 461 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin)); 462 return (0); 463 } 464 } 465 return (-1); 466 } 467 468 static void 469 pci_lpc_write(struct pci_devinst *pi __unused, int baridx __unused, 470 uint64_t offset __unused, int size __unused, uint64_t value __unused) 471 { 472 } 473 474 static uint64_t 475 pci_lpc_read(struct pci_devinst *pi __unused, int baridx __unused, 476 uint64_t offset __unused, int size __unused) 477 { 478 return (0); 479 } 480 481 #define LPC_DEV 0x7000 482 #define LPC_VENDOR 0x8086 483 #define LPC_REVID 0x00 484 #define LPC_SUBVEND_0 0x0000 485 #define LPC_SUBDEV_0 0x0000 486 487 #ifdef __FreeBSD__ 488 static int 489 pci_lpc_get_sel(struct pcisel *const sel) 490 { 491 assert(sel != NULL); 492 493 memset(sel, 0, sizeof(*sel)); 494 495 for (uint8_t slot = 0; slot <= PCI_SLOTMAX; ++slot) { 496 uint8_t max_func = 0; 497 498 sel->pc_dev = slot; 499 sel->pc_func = 0; 500 501 if (pci_host_read_config(sel, PCIR_HDRTYPE, 1) & PCIM_MFDEV) 502 max_func = PCI_FUNCMAX; 503 504 for (uint8_t func = 0; func <= max_func; ++func) { 505 sel->pc_func = func; 506 507 if (pci_host_read_config(sel, PCIR_CLASS, 1) == 508 PCIC_BRIDGE && 509 pci_host_read_config(sel, PCIR_SUBCLASS, 1) == 510 PCIS_BRIDGE_ISA) { 511 return (0); 512 } 513 } 514 } 515 516 warnx("%s: Unable to find host selector of LPC bridge.", __func__); 517 518 return (-1); 519 } 520 #else 521 /* 522 * This function is used to find the PCI selector for the host's LPC so that 523 * its various IDs can be used to configure the guest LPC with the same values 524 * when the `host` keyword is used in the configuration. 525 * On illumos we always just report that we cannot find the host LPC. This is 526 * likely to be true in the case that we're running in a zone anyway. 527 */ 528 static int 529 pci_lpc_get_sel(struct pcisel *const sel __unused) 530 { 531 return (-1); 532 } 533 #endif 534 535 static int 536 pci_lpc_init(struct pci_devinst *pi, nvlist_t *nvl) 537 { 538 struct pcisel sel = { 0 }; 539 struct pcisel *selp = NULL; 540 uint16_t device, subdevice, subvendor, vendor; 541 uint8_t revid; 542 543 /* 544 * Do not allow more than one LPC bridge to be configured. 545 */ 546 if (lpc_bridge != NULL) { 547 EPRINTLN("Only one LPC bridge is allowed."); 548 return (-1); 549 } 550 551 /* 552 * Enforce that the LPC can only be configured on bus 0. This 553 * simplifies the ACPI DSDT because it can provide a decode for 554 * all legacy i/o ports behind bus 0. 555 */ 556 if (pi->pi_bus != 0) { 557 EPRINTLN("LPC bridge can be present only on bus 0."); 558 return (-1); 559 } 560 561 if (lpc_init(pi->pi_vmctx) != 0) 562 return (-1); 563 564 if (pci_lpc_get_sel(&sel) == 0) 565 selp = &sel; 566 567 vendor = pci_config_read_reg(selp, nvl, PCIR_VENDOR, 2, LPC_VENDOR); 568 device = pci_config_read_reg(selp, nvl, PCIR_DEVICE, 2, LPC_DEV); 569 revid = pci_config_read_reg(selp, nvl, PCIR_REVID, 1, LPC_REVID); 570 subvendor = pci_config_read_reg(selp, nvl, PCIR_SUBVEND_0, 2, 571 LPC_SUBVEND_0); 572 subdevice = pci_config_read_reg(selp, nvl, PCIR_SUBDEV_0, 2, 573 LPC_SUBDEV_0); 574 575 /* initialize config space */ 576 pci_set_cfgdata16(pi, PCIR_VENDOR, vendor); 577 pci_set_cfgdata16(pi, PCIR_DEVICE, device); 578 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE); 579 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA); 580 pci_set_cfgdata8(pi, PCIR_REVID, revid); 581 pci_set_cfgdata16(pi, PCIR_SUBVEND_0, subvendor); 582 pci_set_cfgdata16(pi, PCIR_SUBDEV_0, subdevice); 583 584 lpc_bridge = pi; 585 586 return (0); 587 } 588 589 char * 590 lpc_pirq_name(int pin) 591 { 592 char *name; 593 594 if (lpc_bridge == NULL) 595 return (NULL); 596 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1); 597 return (name); 598 } 599 600 void 601 lpc_pirq_routed(void) 602 { 603 int pin; 604 605 if (lpc_bridge == NULL) 606 return; 607 608 for (pin = 0; pin < 4; pin++) 609 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1)); 610 for (pin = 0; pin < 4; pin++) 611 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5)); 612 } 613 614 static const struct pci_devemu pci_de_lpc = { 615 .pe_emu = "lpc", 616 .pe_init = pci_lpc_init, 617 .pe_write_dsdt = pci_lpc_write_dsdt, 618 .pe_cfgwrite = pci_lpc_cfgwrite, 619 .pe_barwrite = pci_lpc_write, 620 .pe_barread = pci_lpc_read 621 }; 622 PCI_EMUL_SET(pci_de_lpc); 623