1 /* 2 * Copyright (c) 1996, Sujal M. Patel 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Sujal M. Patel 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef _I386_ISA_PNP_H_ 34 #define _I386_ISA_PNP_H_ 35 36 /* Maximum Number of PnP Devices. 8 should be plenty */ 37 #define MAX_PNP_CARDS 8 38 /* 39 * the following is the maximum number of PnP Logical devices that 40 * userconfig can handle. 41 */ 42 #define MAX_PNP_LDN 20 43 44 /* Static ports to access PnP state machine */ 45 #ifndef _KERNEL 46 /* pnp.h is included from pnpinfo.c. */ 47 #define _PNP_ADDRESS 0x279 48 #define _PNP_WRITE_DATA 0xa79 49 #endif 50 51 /* PnP Registers. Write to ADDRESS and then use WRITE/READ_DATA */ 52 #define SET_RD_DATA 0x00 53 /*** 54 Writing to this location modifies the address of the port used for 55 reading from the Plug and Play ISA cards. Bits[7:0] become I/O 56 read port address bits[9:2]. Reads from this register are ignored. 57 ***/ 58 59 #define SERIAL_ISOLATION 0x01 60 /*** 61 A read to this register causes a Plug and Play cards in the Isolation 62 state to compare one bit of the boards ID. 63 This register is read only. 64 ***/ 65 66 #define CONFIG_CONTROL 0x02 67 /*** 68 Bit[2] Reset CSN to 0 69 Bit[1] Return to the Wait for Key state 70 Bit[0] Reset all logical devices and restore configuration 71 registers to their power-up values. 72 73 A write to bit[0] of this register performs a reset function on 74 all logical devices. This resets the contents of configuration 75 registers to their default state. All card's logical devices 76 enter their default state and the CSN is preserved. 77 78 A write to bit[1] of this register causes all cards to enter the 79 Wait for Key state but all CSNs are preserved and logical devices 80 are not affected. 81 82 A write to bit[2] of this register causes all cards to reset their 83 CSN to zero . 84 85 This register is write-only. The values are not sticky, that is, 86 hardware will automatically clear them and there is no need for 87 software to clear the bits. 88 ***/ 89 90 #define WAKE 0x03 91 /*** 92 A write to this port will cause all cards that have a CSN that 93 matches the write data[7:0] to go from the Sleep state to the either 94 the Isolation state if the write data for this command is zero or 95 the Config state if the write data is not zero. Additionally, the 96 pointer to the byte-serial device is reset. This register is 97 writeonly. 98 ***/ 99 100 #define RESOURCE_DATA 0x04 101 /*** 102 A read from this address reads the next byte of resource information. 103 The Status register must be polled until bit[0] is set before this 104 register may be read. This register is read only. 105 ***/ 106 107 #define STATUS 0x05 108 /*** 109 Bit[0] when set indicates it is okay to read the next data byte 110 from the Resource Data register. This register is readonly. 111 ***/ 112 113 #define SET_CSN 0x06 114 /*** 115 A write to this port sets a card's CSN. The CSN is a value uniquely 116 assigned to each ISA card after the serial identification process 117 so that each card may be individually selected during a Wake[CSN] 118 command. This register is read/write. 119 ***/ 120 121 #define SET_LDN 0x07 122 /*** 123 Selects the current logical device. All reads and writes of memory, 124 I/O, interrupt and DMA configuration information access the registers 125 of the logical device written here. In addition, the I/O Range 126 Check and Activate commands operate only on the selected logical 127 device. This register is read/write. If a card has only 1 logical 128 device, this location should be a read-only value of 0x00. 129 ***/ 130 131 /*** addresses 0x08 - 0x1F Card Level Reserved for future use ***/ 132 /*** addresses 0x20 - 0x2F Card Level, Vendor Defined ***/ 133 134 #define ACTIVATE 0x30 135 /*** 136 For each logical device there is one activate register that controls 137 whether or not the logical device is active on the ISA bus. Bit[0], 138 if set, activates the logical device. Bits[7:1] are reserved and 139 must return 0 on reads. This is a read/write register. Before a 140 logical device is activated, I/O range check must be disabled. 141 ***/ 142 143 #define IO_RANGE_CHECK 0x31 144 /*** 145 This register is used to perform a conflict check on the I/O port 146 range programmed for use by a logical device. 147 148 Bit[7:2] Reserved and must return 0 on reads 149 Bit[1] Enable I/O Range check, if set then I/O Range Check 150 is enabled. I/O range check is only valid when the logical 151 device is inactive. 152 153 Bit[0], if set, forces the logical device to respond to I/O reads 154 of the logical device's assigned I/O range with a 0x55 when I/O 155 range check is in operation. If clear, the logical device drives 156 0xAA. This register is read/write. 157 ***/ 158 159 /*** addr 0x32 - 0x37 Logical Device Control Reserved for future use ***/ 160 /*** addr 0x38 - 0x3F Logical Device Control Vendor Define ***/ 161 162 #define MEM_CONFIG 0x40 163 /*** 164 Four memory resource registers per range, four ranges. 165 Fill with 0 if no ranges are enabled. 166 167 Offset 0: RW Memory base address bits[23:16] 168 Offset 1: RW Memory base address bits[15:8] 169 Offset 2: Memory control 170 Bit[1] specifies 8/16-bit control. This bit is set to indicate 171 16-bit memory, and cleared to indicate 8-bit memory. 172 Bit[0], if cleared, indicates the next field can be used as a range 173 length for decode (implies range length and base alignment of memory 174 descriptor are equal). 175 Bit[0], if set, indicates the next field is the upper limit for 176 the address. - - Bit[0] is read-only. 177 Offset 3: RW upper limit or range len, bits[23:16] 178 Offset 4: RW upper limit or range len, bits[15:8] 179 Offset 5-Offset 7: filler, unused. 180 ***/ 181 182 #define IO_CONFIG_BASE 0x60 183 /*** 184 Eight ranges, two bytes per range. 185 Offset 0: I/O port base address bits[15:8] 186 Offset 1: I/O port base address bits[7:0] 187 ***/ 188 189 #define IRQ_CONFIG 0x70 190 /*** 191 Two entries, two bytes per entry. 192 Offset 0: RW interrupt level (1..15, 0=unused). 193 Offset 1: Bit[1]: level(1:hi, 0:low), 194 Bit[0]: type (1:level, 0:edge) 195 byte 1 can be readonly if 1 type of int is used. 196 ***/ 197 198 #define DRQ_CONFIG 0x74 199 /*** 200 Two entries, one byte per entry. Bits[2:0] select 201 which DMA channel is in use for DMA 0. Zero selects DMA channel 202 0, seven selects DMA channel 7. DMA channel 4, the cascade channel 203 is used to indicate no DMA channel is active. 204 ***/ 205 206 /*** 32-bit memory accesses are at 0x76 ***/ 207 208 /* Macros to parse Resource IDs */ 209 #define PNP_RES_TYPE(a) (a >> 7) 210 #define PNP_SRES_NUM(a) (a >> 3) 211 #define PNP_SRES_LEN(a) (a & 0x07) 212 #define PNP_LRES_NUM(a) (a & 0x7f) 213 214 /* Small Resource Item names */ 215 #define PNP_VERSION 0x1 216 #define LOG_DEVICE_ID 0x2 217 #define COMP_DEVICE_ID 0x3 218 #define IRQ_FORMAT 0x4 219 #define DMA_FORMAT 0x5 220 #define START_DEPEND_FUNC 0x6 221 #define END_DEPEND_FUNC 0x7 222 #define IO_PORT_DESC 0x8 223 #define FIXED_IO_PORT_DESC 0x9 224 #define SM_RES_RESERVED 0xa-0xd 225 #define SM_VENDOR_DEFINED 0xe 226 #define END_TAG 0xf 227 228 /* Large Resource Item names */ 229 #define MEMORY_RANGE_DESC 0x1 230 #define ID_STRING_ANSI 0x2 231 #define ID_STRING_UNICODE 0x3 232 #define LG_VENDOR_DEFINED 0x4 233 #define _32BIT_MEM_RANGE_DESC 0x5 234 #define _32BIT_FIXED_LOC_DESC 0x6 235 #define LG_RES_RESERVED 0x7-0x7f 236 237 /* 238 * pnp_cinfo contains Configuration Information. They are used 239 * to communicate to the device driver the actual configuration 240 * of the device, and also by the userconfig menu to let the 241 * operating system override any configuration set by the bios. 242 * 243 */ 244 struct pnp_cinfo { 245 u_int vendor_id; /* board id */ 246 u_int serial; /* Board's Serial Number */ 247 u_long flags; /* OS-reserved flags */ 248 u_char csn; /* assigned Card Select Number */ 249 u_char ldn; /* Logical Device Number */ 250 u_char enable; /* pnp enable */ 251 u_char override; /* override bios parms (in userconfig) */ 252 u_char irq[2]; /* IRQ Number */ 253 u_char irq_type[2]; /* IRQ Type */ 254 u_char drq[2]; 255 u_short port[8]; /* The Base Address of the Port */ 256 struct { 257 u_long base; /* Memory Base Address */ 258 int control; /* Memory Control Register */ 259 u_long range; /* Memory Range *OR* Upper Limit */ 260 } mem[4]; 261 }; 262 263 #ifdef _KERNEL 264 265 struct pnp_device { 266 char *pd_name; 267 char * (*pd_probe ) (u_long csn, u_long vendor_id); 268 void (*pd_attach ) (u_long csn, u_long vend_id, char * name, 269 struct isa_device *dev); 270 u_long *pd_count; 271 u_int *imask ; 272 }; 273 274 struct _pnp_id { 275 u_long vendor_id; 276 u_long serial; 277 u_char checksum; 278 } ; 279 280 struct pnp_dlist_node { 281 struct pnp_device *pnp; 282 struct isa_device dev; 283 struct pnp_dlist_node *next; 284 }; 285 286 typedef struct _pnp_id pnp_id; 287 extern struct pnp_dlist_node *pnp_device_list; 288 extern pnp_id pnp_devices[MAX_PNP_CARDS]; 289 extern struct pnp_cinfo pnp_ldn_overrides[MAX_PNP_LDN]; 290 extern int pnp_overrides_valid; 291 292 /* 293 * these two functions are for use in drivers 294 */ 295 int read_pnp_parms(struct pnp_cinfo *d, int ldn); 296 int write_pnp_parms(struct pnp_cinfo *d, int ldn); 297 int enable_pnp_card(void); 298 299 /* 300 * used by autoconfigure to actually probe and attach drivers 301 */ 302 void pnp_configure(void); 303 304 #endif /* _KERNEL */ 305 306 #endif /* !_I386_ISA_PNP_H_ */ 307