1 /*- 2 * Copyright (c) 2007 Yahoo!, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef lint 32 static const char rcsid[] = 33 "$FreeBSD$"; 34 #endif /* not lint */ 35 36 #include <sys/types.h> 37 38 #include <err.h> 39 #include <stdio.h> 40 #include <strings.h> 41 #include <sys/agpio.h> 42 #include <sys/pciio.h> 43 44 #include <dev/agp/agpreg.h> 45 #include <dev/pci/pcireg.h> 46 47 #include "pciconf.h" 48 49 static void list_ecaps(int fd, struct pci_conf *p); 50 51 static void 52 cap_power(int fd, struct pci_conf *p, uint8_t ptr) 53 { 54 uint16_t cap, status; 55 56 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 57 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 58 printf("powerspec %d supports D0%s%s D3 current D%d", 59 cap & PCIM_PCAP_SPEC, 60 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 61 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 62 status & PCIM_PSTAT_DMASK); 63 } 64 65 static void 66 cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 67 { 68 uint32_t status, command; 69 70 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 71 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 72 printf("AGP "); 73 if (AGP_MODE_GET_MODE_3(status)) { 74 printf("v3 "); 75 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 76 printf("8x "); 77 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 78 printf("4x "); 79 } else { 80 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 81 printf("4x "); 82 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 83 printf("2x "); 84 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 85 printf("1x "); 86 } 87 if (AGP_MODE_GET_SBA(status)) 88 printf("SBA "); 89 if (AGP_MODE_GET_AGP(command)) { 90 printf("enabled at "); 91 if (AGP_MODE_GET_MODE_3(command)) { 92 printf("v3 "); 93 switch (AGP_MODE_GET_RATE(command)) { 94 case AGP_MODE_V3_RATE_8x: 95 printf("8x "); 96 break; 97 case AGP_MODE_V3_RATE_4x: 98 printf("4x "); 99 break; 100 } 101 } else 102 switch (AGP_MODE_GET_RATE(command)) { 103 case AGP_MODE_V2_RATE_4x: 104 printf("4x "); 105 break; 106 case AGP_MODE_V2_RATE_2x: 107 printf("2x "); 108 break; 109 case AGP_MODE_V2_RATE_1x: 110 printf("1x "); 111 break; 112 } 113 if (AGP_MODE_GET_SBA(command)) 114 printf("SBA "); 115 } else 116 printf("disabled"); 117 } 118 119 static void 120 cap_vpd(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 121 { 122 123 printf("VPD"); 124 } 125 126 static void 127 cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 128 { 129 uint16_t ctrl; 130 int msgnum; 131 132 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 133 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 134 printf("MSI supports %d message%s%s%s ", msgnum, 135 (msgnum == 1) ? "" : "s", 136 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 137 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 138 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 139 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 140 printf("enabled with %d message%s", msgnum, 141 (msgnum == 1) ? "" : "s"); 142 } 143 } 144 145 static void 146 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 147 { 148 uint32_t status; 149 int comma, max_splits, max_burst_read; 150 151 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 152 printf("PCI-X "); 153 if (status & PCIXM_STATUS_64BIT) 154 printf("64-bit "); 155 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 156 printf("bridge "); 157 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 158 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 159 printf("supports"); 160 comma = 0; 161 if (status & PCIXM_STATUS_133CAP) { 162 printf("%s 133MHz", comma ? "," : ""); 163 comma = 1; 164 } 165 if (status & PCIXM_STATUS_266CAP) { 166 printf("%s 266MHz", comma ? "," : ""); 167 comma = 1; 168 } 169 if (status & PCIXM_STATUS_533CAP) { 170 printf("%s 533MHz", comma ? "," : ""); 171 comma = 1; 172 } 173 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 174 return; 175 max_burst_read = 0; 176 switch (status & PCIXM_STATUS_MAX_READ) { 177 case PCIXM_STATUS_MAX_READ_512: 178 max_burst_read = 512; 179 break; 180 case PCIXM_STATUS_MAX_READ_1024: 181 max_burst_read = 1024; 182 break; 183 case PCIXM_STATUS_MAX_READ_2048: 184 max_burst_read = 2048; 185 break; 186 case PCIXM_STATUS_MAX_READ_4096: 187 max_burst_read = 4096; 188 break; 189 } 190 max_splits = 0; 191 switch (status & PCIXM_STATUS_MAX_SPLITS) { 192 case PCIXM_STATUS_MAX_SPLITS_1: 193 max_splits = 1; 194 break; 195 case PCIXM_STATUS_MAX_SPLITS_2: 196 max_splits = 2; 197 break; 198 case PCIXM_STATUS_MAX_SPLITS_3: 199 max_splits = 3; 200 break; 201 case PCIXM_STATUS_MAX_SPLITS_4: 202 max_splits = 4; 203 break; 204 case PCIXM_STATUS_MAX_SPLITS_8: 205 max_splits = 8; 206 break; 207 case PCIXM_STATUS_MAX_SPLITS_12: 208 max_splits = 12; 209 break; 210 case PCIXM_STATUS_MAX_SPLITS_16: 211 max_splits = 16; 212 break; 213 case PCIXM_STATUS_MAX_SPLITS_32: 214 max_splits = 32; 215 break; 216 } 217 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 218 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 219 } 220 221 static void 222 cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 223 { 224 uint32_t reg; 225 uint16_t command; 226 227 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 228 printf("HT "); 229 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 230 printf("slave"); 231 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 232 printf("host"); 233 else 234 switch (command & PCIM_HTCMD_CAP_MASK) { 235 case PCIM_HTCAP_SWITCH: 236 printf("switch"); 237 break; 238 case PCIM_HTCAP_INTERRUPT: 239 printf("interrupt"); 240 break; 241 case PCIM_HTCAP_REVISION_ID: 242 printf("revision ID"); 243 break; 244 case PCIM_HTCAP_UNITID_CLUMPING: 245 printf("unit ID clumping"); 246 break; 247 case PCIM_HTCAP_EXT_CONFIG_SPACE: 248 printf("extended config space"); 249 break; 250 case PCIM_HTCAP_ADDRESS_MAPPING: 251 printf("address mapping"); 252 break; 253 case PCIM_HTCAP_MSI_MAPPING: 254 printf("MSI %saddress window %s at 0x", 255 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 256 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 257 "disabled"); 258 if (command & PCIM_HTCMD_MSI_FIXED) 259 printf("fee00000"); 260 else { 261 reg = read_config(fd, &p->pc_sel, 262 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 263 if (reg != 0) 264 printf("%08x", reg); 265 reg = read_config(fd, &p->pc_sel, 266 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 267 printf("%08x", reg); 268 } 269 break; 270 case PCIM_HTCAP_DIRECT_ROUTE: 271 printf("direct route"); 272 break; 273 case PCIM_HTCAP_VCSET: 274 printf("VC set"); 275 break; 276 case PCIM_HTCAP_RETRY_MODE: 277 printf("retry mode"); 278 break; 279 case PCIM_HTCAP_X86_ENCODING: 280 printf("X86 encoding"); 281 break; 282 case PCIM_HTCAP_GEN3: 283 printf("Gen3"); 284 break; 285 case PCIM_HTCAP_FLE: 286 printf("function-level extension"); 287 break; 288 case PCIM_HTCAP_PM: 289 printf("power management"); 290 break; 291 case PCIM_HTCAP_HIGH_NODE_COUNT: 292 printf("high node count"); 293 break; 294 default: 295 printf("unknown %02x", command); 296 break; 297 } 298 } 299 300 static void 301 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 302 { 303 uint8_t length; 304 305 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 306 printf("vendor (length %d)", length); 307 if (p->pc_vendor == 0x8086) { 308 /* Intel */ 309 uint8_t version; 310 311 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 312 1); 313 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 314 if (version >> 4 == 1 && length == 12) { 315 /* Feature Detection */ 316 uint32_t fvec; 317 int comma; 318 319 comma = 0; 320 fvec = read_config(fd, &p->pc_sel, ptr + 321 PCIR_VENDOR_DATA + 5, 4); 322 printf("\n\t\t features:"); 323 if (fvec & (1 << 0)) { 324 printf(" AMT"); 325 comma = 1; 326 } 327 fvec = read_config(fd, &p->pc_sel, ptr + 328 PCIR_VENDOR_DATA + 1, 4); 329 if (fvec & (1 << 21)) { 330 printf("%s Quick Resume", comma ? "," : ""); 331 comma = 1; 332 } 333 if (fvec & (1 << 18)) { 334 printf("%s SATA RAID-5", comma ? "," : ""); 335 comma = 1; 336 } 337 if (fvec & (1 << 9)) { 338 printf("%s Mobile", comma ? "," : ""); 339 comma = 1; 340 } 341 if (fvec & (1 << 7)) { 342 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 343 comma = 1; 344 } else { 345 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 346 comma = 1; 347 } 348 if (fvec & (1 << 5)) { 349 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 350 comma = 1; 351 } 352 if (fvec & (1 << 3)) { 353 printf("%s SATA AHCI", comma ? "," : ""); 354 comma = 1; 355 } 356 } 357 } 358 } 359 360 static void 361 cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 362 { 363 uint16_t debug_port; 364 365 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 366 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 367 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 368 } 369 370 static void 371 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 372 { 373 uint32_t id; 374 375 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 376 printf("PCI Bridge card=0x%08x", id); 377 } 378 379 #define MAX_PAYLOAD(field) (128 << (field)) 380 381 static const char * 382 link_speed_string(uint8_t speed) 383 { 384 385 switch (speed) { 386 case 1: 387 return ("2.5"); 388 case 2: 389 return ("5.0"); 390 case 3: 391 return ("8.0"); 392 default: 393 return ("undef"); 394 } 395 } 396 397 static const char * 398 aspm_string(uint8_t aspm) 399 { 400 401 switch (aspm) { 402 case 1: 403 return ("L0s"); 404 case 2: 405 return ("L1"); 406 case 3: 407 return ("L0s/L1"); 408 default: 409 return ("disabled"); 410 } 411 } 412 413 static int 414 slot_power(uint32_t cap) 415 { 416 int mwatts; 417 418 mwatts = (cap & PCIEM_SLOT_CAP_SPLV) >> 7; 419 switch (cap & PCIEM_SLOT_CAP_SPLS) { 420 case 0x0: 421 mwatts *= 1000; 422 break; 423 case 0x1: 424 mwatts *= 100; 425 break; 426 case 0x2: 427 mwatts *= 10; 428 break; 429 default: 430 break; 431 } 432 return (mwatts); 433 } 434 435 static void 436 cap_express(int fd, struct pci_conf *p, uint8_t ptr) 437 { 438 uint32_t cap; 439 uint16_t ctl, flags, sta; 440 unsigned int version; 441 442 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 443 version = flags & PCIEM_FLAGS_VERSION; 444 printf("PCI-Express %u ", version); 445 switch (flags & PCIEM_FLAGS_TYPE) { 446 case PCIEM_TYPE_ENDPOINT: 447 printf("endpoint"); 448 break; 449 case PCIEM_TYPE_LEGACY_ENDPOINT: 450 printf("legacy endpoint"); 451 break; 452 case PCIEM_TYPE_ROOT_PORT: 453 printf("root port"); 454 break; 455 case PCIEM_TYPE_UPSTREAM_PORT: 456 printf("upstream port"); 457 break; 458 case PCIEM_TYPE_DOWNSTREAM_PORT: 459 printf("downstream port"); 460 break; 461 case PCIEM_TYPE_PCI_BRIDGE: 462 printf("PCI bridge"); 463 break; 464 case PCIEM_TYPE_PCIE_BRIDGE: 465 printf("PCI to PCIe bridge"); 466 break; 467 case PCIEM_TYPE_ROOT_INT_EP: 468 printf("root endpoint"); 469 break; 470 case PCIEM_TYPE_ROOT_EC: 471 printf("event collector"); 472 break; 473 default: 474 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 475 break; 476 } 477 if (flags & PCIEM_FLAGS_IRQ) 478 printf(" MSI %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 479 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 480 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 481 printf(" max data %d(%d)", 482 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5), 483 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD)); 484 if ((cap & PCIEM_CAP_FLR) != 0) 485 printf(" FLR"); 486 if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE) 487 printf(" RO"); 488 if (ctl & PCIEM_CTL_NOSNOOP_ENABLE) 489 printf(" NS"); 490 if (version >= 2) { 491 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4); 492 if ((cap & PCIEM_CAP2_ARI) != 0) { 493 ctl = read_config(fd, &p->pc_sel, 494 ptr + PCIER_DEVICE_CTL2, 4); 495 printf(" ARI %s", 496 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled"); 497 } 498 } 499 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 500 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2); 501 if (cap == 0 && sta == 0) 502 return; 503 printf("\n "); 504 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4, 505 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 506 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 507 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ? 508 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED), 509 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED)); 510 } 511 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 512 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 513 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC), 514 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10)); 515 } 516 if (!(flags & PCIEM_FLAGS_SLOT)) 517 return; 518 cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4); 519 sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_STA, 2); 520 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CTL, 2); 521 printf("\n "); 522 printf(" slot %d", (cap & PCIEM_SLOT_CAP_PSN) >> 19); 523 printf(" power limit %d mW", slot_power(cap)); 524 if (cap & PCIEM_SLOT_CAP_HPC) 525 printf(" HotPlug(%s)", sta & PCIEM_SLOT_STA_PDS ? "present" : 526 "empty"); 527 if (cap & PCIEM_SLOT_CAP_HPS) 528 printf(" surprise"); 529 if (cap & PCIEM_SLOT_CAP_APB) 530 printf(" Attn Button"); 531 if (cap & PCIEM_SLOT_CAP_PCP) 532 printf(" PC(%s)", ctl & PCIEM_SLOT_CTL_PCC ? "on" : "off"); 533 if (cap & PCIEM_SLOT_CAP_MRLSP) 534 printf(" MRL(%s)", sta & PCIEM_SLOT_STA_MRLSS ? "open" : 535 "closed"); 536 } 537 538 static void 539 cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 540 { 541 uint32_t pba_offset, table_offset, val; 542 int msgnum, pba_bar, table_bar; 543 uint16_t ctrl; 544 545 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 546 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 547 548 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 549 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 550 table_offset = val & ~PCIM_MSIX_BIR_MASK; 551 552 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 553 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 554 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 555 556 printf("MSI-X supports %d message%s%s\n", msgnum, 557 (msgnum == 1) ? "" : "s", 558 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 559 560 printf(" "); 561 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 562 table_bar, table_offset, pba_bar, pba_offset); 563 } 564 565 static void 566 cap_sata(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 567 { 568 569 printf("SATA Index-Data Pair"); 570 } 571 572 static void 573 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 574 { 575 uint8_t cap; 576 577 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 578 printf("PCI Advanced Features:%s%s", 579 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 580 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 581 } 582 583 static const char * 584 ea_bei_to_name(int bei) 585 { 586 static const char *barstr[] = { 587 "BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5" 588 }; 589 static const char *vfbarstr[] = { 590 "VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5" 591 }; 592 593 if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5)) 594 return (barstr[bei - PCIM_EA_BEI_BAR_0]); 595 if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5)) 596 return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]); 597 598 switch (bei) { 599 case PCIM_EA_BEI_BRIDGE: 600 return "BRIDGE"; 601 case PCIM_EA_BEI_ENI: 602 return "ENI"; 603 case PCIM_EA_BEI_ROM: 604 return "ROM"; 605 case PCIM_EA_BEI_RESERVED: 606 default: 607 return "RSVD"; 608 } 609 } 610 611 static const char * 612 ea_prop_to_name(uint8_t prop) 613 { 614 615 switch (prop) { 616 case PCIM_EA_P_MEM: 617 return "Non-Prefetchable Memory"; 618 case PCIM_EA_P_MEM_PREFETCH: 619 return "Prefetchable Memory"; 620 case PCIM_EA_P_IO: 621 return "I/O Space"; 622 case PCIM_EA_P_VF_MEM_PREFETCH: 623 return "VF Prefetchable Memory"; 624 case PCIM_EA_P_VF_MEM: 625 return "VF Non-Prefetchable Memory"; 626 case PCIM_EA_P_BRIDGE_MEM: 627 return "Bridge Non-Prefetchable Memory"; 628 case PCIM_EA_P_BRIDGE_MEM_PREFETCH: 629 return "Bridge Prefetchable Memory"; 630 case PCIM_EA_P_BRIDGE_IO: 631 return "Bridge I/O Space"; 632 case PCIM_EA_P_MEM_RESERVED: 633 return "Reserved Memory"; 634 case PCIM_EA_P_IO_RESERVED: 635 return "Reserved I/O Space"; 636 case PCIM_EA_P_UNAVAILABLE: 637 return "Unavailable"; 638 default: 639 return "Reserved"; 640 } 641 } 642 643 static void 644 cap_ea(int fd, struct pci_conf *p, uint8_t ptr) 645 { 646 int num_ent; 647 int a, b; 648 uint32_t bei; 649 uint32_t val; 650 int ent_size; 651 uint32_t dw[4]; 652 uint32_t flags, flags_pp, flags_sp; 653 uint64_t base, max_offset; 654 uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr; 655 656 /* Determine the number of entries */ 657 num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2); 658 num_ent &= PCIM_EA_NUM_ENT_MASK; 659 660 printf("PCI Enhanced Allocation (%d entries)", num_ent); 661 662 /* Find the first entry to care of */ 663 ptr += PCIR_EA_FIRST_ENT; 664 665 /* Print BUS numbers for bridges */ 666 if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) { 667 val = read_config(fd, &p->pc_sel, ptr, 4); 668 669 fixed_sec_bus_nr = PCIM_EA_SEC_NR(val); 670 fixed_sub_bus_nr = PCIM_EA_SUB_NR(val); 671 672 printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]", 673 fixed_sec_bus_nr, fixed_sub_bus_nr); 674 ptr += 4; 675 } 676 677 for (a = 0; a < num_ent; a++) { 678 /* Read a number of dwords in the entry */ 679 val = read_config(fd, &p->pc_sel, ptr, 4); 680 ptr += 4; 681 ent_size = (val & PCIM_EA_ES); 682 683 for (b = 0; b < ent_size; b++) { 684 dw[b] = read_config(fd, &p->pc_sel, ptr, 4); 685 ptr += 4; 686 } 687 688 flags = val; 689 flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET; 690 flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET; 691 bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 692 693 base = dw[0] & PCIM_EA_FIELD_MASK; 694 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 695 b = 2; 696 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 697 base |= (uint64_t)dw[b] << 32UL; 698 b++; 699 } 700 if (((dw[1] & PCIM_EA_IS_64) != 0) 701 && (b < ent_size)) { 702 max_offset |= (uint64_t)dw[b] << 32UL; 703 b++; 704 } 705 706 printf("\n\t\t [%d] %s, %s, %s, base [0x%jx], size [0x%jx]" 707 "\n\t\t\tPrimary properties [0x%x] (%s)" 708 "\n\t\t\tSecondary properties [0x%x] (%s)", 709 bei, ea_bei_to_name(bei), 710 (flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"), 711 (flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"), 712 (uintmax_t)base, (uintmax_t)(max_offset + 1), 713 flags_pp, ea_prop_to_name(flags_pp), 714 flags_sp, ea_prop_to_name(flags_sp)); 715 } 716 } 717 718 void 719 list_caps(int fd, struct pci_conf *p) 720 { 721 int express; 722 uint16_t sta; 723 uint8_t ptr, cap; 724 725 /* Are capabilities present for this device? */ 726 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 727 if (!(sta & PCIM_STATUS_CAPPRESENT)) 728 return; 729 730 switch (p->pc_hdr & PCIM_HDRTYPE) { 731 case PCIM_HDRTYPE_NORMAL: 732 case PCIM_HDRTYPE_BRIDGE: 733 ptr = PCIR_CAP_PTR; 734 break; 735 case PCIM_HDRTYPE_CARDBUS: 736 ptr = PCIR_CAP_PTR_2; 737 break; 738 default: 739 errx(1, "list_caps: bad header type"); 740 } 741 742 /* Walk the capability list. */ 743 express = 0; 744 ptr = read_config(fd, &p->pc_sel, ptr, 1); 745 while (ptr != 0 && ptr != 0xff) { 746 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 747 printf(" cap %02x[%02x] = ", cap, ptr); 748 switch (cap) { 749 case PCIY_PMG: 750 cap_power(fd, p, ptr); 751 break; 752 case PCIY_AGP: 753 cap_agp(fd, p, ptr); 754 break; 755 case PCIY_VPD: 756 cap_vpd(fd, p, ptr); 757 break; 758 case PCIY_MSI: 759 cap_msi(fd, p, ptr); 760 break; 761 case PCIY_PCIX: 762 cap_pcix(fd, p, ptr); 763 break; 764 case PCIY_HT: 765 cap_ht(fd, p, ptr); 766 break; 767 case PCIY_VENDOR: 768 cap_vendor(fd, p, ptr); 769 break; 770 case PCIY_DEBUG: 771 cap_debug(fd, p, ptr); 772 break; 773 case PCIY_SUBVENDOR: 774 cap_subvendor(fd, p, ptr); 775 break; 776 case PCIY_EXPRESS: 777 express = 1; 778 cap_express(fd, p, ptr); 779 break; 780 case PCIY_MSIX: 781 cap_msix(fd, p, ptr); 782 break; 783 case PCIY_SATA: 784 cap_sata(fd, p, ptr); 785 break; 786 case PCIY_PCIAF: 787 cap_pciaf(fd, p, ptr); 788 break; 789 case PCIY_EA: 790 cap_ea(fd, p, ptr); 791 break; 792 default: 793 printf("unknown"); 794 break; 795 } 796 printf("\n"); 797 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 798 } 799 800 if (express) 801 list_ecaps(fd, p); 802 } 803 804 /* From <sys/systm.h>. */ 805 static __inline uint32_t 806 bitcount32(uint32_t x) 807 { 808 809 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 810 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 811 x = (x + (x >> 4)) & 0x0f0f0f0f; 812 x = (x + (x >> 8)); 813 x = (x + (x >> 16)) & 0x000000ff; 814 return (x); 815 } 816 817 static void 818 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 819 { 820 uint32_t sta, mask; 821 822 printf("AER %d", ver); 823 if (ver < 1) 824 return; 825 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 826 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 827 printf(" %d fatal", bitcount32(sta & mask)); 828 printf(" %d non-fatal", bitcount32(sta & ~mask)); 829 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 830 printf(" %d corrected\n", bitcount32(sta)); 831 } 832 833 static void 834 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 835 { 836 uint32_t cap1; 837 838 printf("VC %d", ver); 839 if (ver < 1) 840 return; 841 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 842 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 843 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 844 printf(" lowpri VC0-VC%d", 845 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 846 printf("\n"); 847 } 848 849 static void 850 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 851 { 852 uint32_t high, low; 853 854 printf("Serial %d", ver); 855 if (ver < 1) 856 return; 857 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 858 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 859 printf(" %08x%08x\n", high, low); 860 } 861 862 static void 863 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 864 { 865 uint32_t val; 866 867 printf("Vendor %d", ver); 868 if (ver < 1) 869 return; 870 val = read_config(fd, &p->pc_sel, ptr + 4, 4); 871 printf(" ID %d\n", val & 0xffff); 872 } 873 874 static void 875 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 876 { 877 uint32_t val; 878 879 printf("PCIe Sec %d", ver); 880 if (ver < 1) 881 return; 882 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 883 printf(" lane errors %#x\n", val); 884 } 885 886 static const char * 887 check_enabled(int value) 888 { 889 890 return (value ? "enabled" : "disabled"); 891 } 892 893 static void 894 ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 895 { 896 const char *comma, *enabled; 897 uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did; 898 uint32_t page_caps, page_size, page_shift, size; 899 int i; 900 901 printf("SR-IOV %d ", ver); 902 903 iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2); 904 printf("IOV %s, Memory Space %s, ARI %s\n", 905 check_enabled(iov_ctl & PCIM_SRIOV_VF_EN), 906 check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE), 907 check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN)); 908 909 total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2); 910 num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2); 911 printf(" "); 912 printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs); 913 914 vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2); 915 vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2); 916 printf(" "); 917 printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset, 918 vf_stride); 919 920 vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2); 921 printf(" VF Device ID 0x%04x\n", vf_did); 922 923 page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4); 924 page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4); 925 printf(" "); 926 printf("Page Sizes: "); 927 comma = ""; 928 while (page_caps != 0) { 929 page_shift = ffs(page_caps) - 1; 930 931 if (page_caps & page_size) 932 enabled = " (enabled)"; 933 else 934 enabled = ""; 935 936 size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT)); 937 printf("%s%d%s", comma, size, enabled); 938 comma = ", "; 939 940 page_caps &= ~(1 << page_shift); 941 } 942 printf("\n"); 943 944 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 945 print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i)); 946 } 947 948 static struct { 949 uint16_t id; 950 const char *name; 951 } ecap_names[] = { 952 { PCIZ_PWRBDGT, "Power Budgeting" }, 953 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 954 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 955 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 956 { PCIZ_MFVC, "MFVC" }, 957 { PCIZ_RCRB, "RCRB" }, 958 { PCIZ_ACS, "ACS" }, 959 { PCIZ_ARI, "ARI" }, 960 { PCIZ_ATS, "ATS" }, 961 { PCIZ_MULTICAST, "Multicast" }, 962 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 963 { PCIZ_DPA, "DPA" }, 964 { PCIZ_TPH_REQ, "TPH Requester" }, 965 { PCIZ_LTR, "LTR" }, 966 { 0, NULL } 967 }; 968 969 static void 970 list_ecaps(int fd, struct pci_conf *p) 971 { 972 const char *name; 973 uint32_t ecap; 974 uint16_t ptr; 975 int i; 976 977 ptr = PCIR_EXTCAP; 978 ecap = read_config(fd, &p->pc_sel, ptr, 4); 979 if (ecap == 0xffffffff || ecap == 0) 980 return; 981 for (;;) { 982 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 983 switch (PCI_EXTCAP_ID(ecap)) { 984 case PCIZ_AER: 985 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 986 break; 987 case PCIZ_VC: 988 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 989 break; 990 case PCIZ_SERNUM: 991 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 992 break; 993 case PCIZ_VENDOR: 994 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 995 break; 996 case PCIZ_SEC_PCIE: 997 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 998 break; 999 case PCIZ_SRIOV: 1000 ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1001 break; 1002 default: 1003 name = "unknown"; 1004 for (i = 0; ecap_names[i].name != NULL; i++) 1005 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 1006 name = ecap_names[i].name; 1007 break; 1008 } 1009 printf("%s %d\n", name, PCI_EXTCAP_VER(ecap)); 1010 break; 1011 } 1012 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1013 if (ptr == 0) 1014 break; 1015 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1016 } 1017 } 1018 1019 /* Find offset of a specific capability. Returns 0 on failure. */ 1020 uint8_t 1021 pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 1022 { 1023 uint16_t sta; 1024 uint8_t ptr, cap; 1025 1026 /* Are capabilities present for this device? */ 1027 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 1028 if (!(sta & PCIM_STATUS_CAPPRESENT)) 1029 return (0); 1030 1031 switch (p->pc_hdr & PCIM_HDRTYPE) { 1032 case PCIM_HDRTYPE_NORMAL: 1033 case PCIM_HDRTYPE_BRIDGE: 1034 ptr = PCIR_CAP_PTR; 1035 break; 1036 case PCIM_HDRTYPE_CARDBUS: 1037 ptr = PCIR_CAP_PTR_2; 1038 break; 1039 default: 1040 return (0); 1041 } 1042 1043 ptr = read_config(fd, &p->pc_sel, ptr, 1); 1044 while (ptr != 0 && ptr != 0xff) { 1045 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 1046 if (cap == id) 1047 return (ptr); 1048 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 1049 } 1050 return (0); 1051 } 1052 1053 /* Find offset of a specific extended capability. Returns 0 on failure. */ 1054 uint16_t 1055 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 1056 { 1057 uint32_t ecap; 1058 uint16_t ptr; 1059 1060 ptr = PCIR_EXTCAP; 1061 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1062 if (ecap == 0xffffffff || ecap == 0) 1063 return (0); 1064 for (;;) { 1065 if (PCI_EXTCAP_ID(ecap) == id) 1066 return (ptr); 1067 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1068 if (ptr == 0) 1069 break; 1070 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1071 } 1072 return (0); 1073 } 1074