1 /*- 2 * Copyright (c) 2007 Yahoo!, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef lint 32 static const char rcsid[] = 33 "$FreeBSD$"; 34 #endif /* not lint */ 35 36 #include <sys/types.h> 37 38 #include <err.h> 39 #include <stdio.h> 40 #include <strings.h> 41 #include <sys/agpio.h> 42 #include <sys/pciio.h> 43 44 #include <dev/agp/agpreg.h> 45 #include <dev/pci/pcireg.h> 46 47 #include "pciconf.h" 48 49 static void list_ecaps(int fd, struct pci_conf *p); 50 51 static void 52 cap_power(int fd, struct pci_conf *p, uint8_t ptr) 53 { 54 uint16_t cap, status; 55 56 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 57 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 58 printf("powerspec %d supports D0%s%s D3 current D%d", 59 cap & PCIM_PCAP_SPEC, 60 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 61 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 62 status & PCIM_PSTAT_DMASK); 63 } 64 65 static void 66 cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 67 { 68 uint32_t status, command; 69 70 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 71 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 72 printf("AGP "); 73 if (AGP_MODE_GET_MODE_3(status)) { 74 printf("v3 "); 75 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 76 printf("8x "); 77 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 78 printf("4x "); 79 } else { 80 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 81 printf("4x "); 82 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 83 printf("2x "); 84 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 85 printf("1x "); 86 } 87 if (AGP_MODE_GET_SBA(status)) 88 printf("SBA "); 89 if (AGP_MODE_GET_AGP(command)) { 90 printf("enabled at "); 91 if (AGP_MODE_GET_MODE_3(command)) { 92 printf("v3 "); 93 switch (AGP_MODE_GET_RATE(command)) { 94 case AGP_MODE_V3_RATE_8x: 95 printf("8x "); 96 break; 97 case AGP_MODE_V3_RATE_4x: 98 printf("4x "); 99 break; 100 } 101 } else 102 switch (AGP_MODE_GET_RATE(command)) { 103 case AGP_MODE_V2_RATE_4x: 104 printf("4x "); 105 break; 106 case AGP_MODE_V2_RATE_2x: 107 printf("2x "); 108 break; 109 case AGP_MODE_V2_RATE_1x: 110 printf("1x "); 111 break; 112 } 113 if (AGP_MODE_GET_SBA(command)) 114 printf("SBA "); 115 } else 116 printf("disabled"); 117 } 118 119 static void 120 cap_vpd(int fd, struct pci_conf *p, uint8_t ptr) 121 { 122 123 printf("VPD"); 124 } 125 126 static void 127 cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 128 { 129 uint16_t ctrl; 130 int msgnum; 131 132 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 133 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 134 printf("MSI supports %d message%s%s%s ", msgnum, 135 (msgnum == 1) ? "" : "s", 136 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 137 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 138 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 139 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 140 printf("enabled with %d message%s", msgnum, 141 (msgnum == 1) ? "" : "s"); 142 } 143 } 144 145 static void 146 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 147 { 148 uint32_t status; 149 int comma, max_splits, max_burst_read; 150 151 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 152 printf("PCI-X "); 153 if (status & PCIXM_STATUS_64BIT) 154 printf("64-bit "); 155 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 156 printf("bridge "); 157 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 158 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 159 printf("supports"); 160 comma = 0; 161 if (status & PCIXM_STATUS_133CAP) { 162 printf("%s 133MHz", comma ? "," : ""); 163 comma = 1; 164 } 165 if (status & PCIXM_STATUS_266CAP) { 166 printf("%s 266MHz", comma ? "," : ""); 167 comma = 1; 168 } 169 if (status & PCIXM_STATUS_533CAP) { 170 printf("%s 533MHz", comma ? "," : ""); 171 comma = 1; 172 } 173 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 174 return; 175 switch (status & PCIXM_STATUS_MAX_READ) { 176 case PCIXM_STATUS_MAX_READ_512: 177 max_burst_read = 512; 178 break; 179 case PCIXM_STATUS_MAX_READ_1024: 180 max_burst_read = 1024; 181 break; 182 case PCIXM_STATUS_MAX_READ_2048: 183 max_burst_read = 2048; 184 break; 185 case PCIXM_STATUS_MAX_READ_4096: 186 max_burst_read = 4096; 187 break; 188 } 189 switch (status & PCIXM_STATUS_MAX_SPLITS) { 190 case PCIXM_STATUS_MAX_SPLITS_1: 191 max_splits = 1; 192 break; 193 case PCIXM_STATUS_MAX_SPLITS_2: 194 max_splits = 2; 195 break; 196 case PCIXM_STATUS_MAX_SPLITS_3: 197 max_splits = 3; 198 break; 199 case PCIXM_STATUS_MAX_SPLITS_4: 200 max_splits = 4; 201 break; 202 case PCIXM_STATUS_MAX_SPLITS_8: 203 max_splits = 8; 204 break; 205 case PCIXM_STATUS_MAX_SPLITS_12: 206 max_splits = 12; 207 break; 208 case PCIXM_STATUS_MAX_SPLITS_16: 209 max_splits = 16; 210 break; 211 case PCIXM_STATUS_MAX_SPLITS_32: 212 max_splits = 32; 213 break; 214 } 215 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 216 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 217 } 218 219 static void 220 cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 221 { 222 uint32_t reg; 223 uint16_t command; 224 225 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 226 printf("HT "); 227 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 228 printf("slave"); 229 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 230 printf("host"); 231 else 232 switch (command & PCIM_HTCMD_CAP_MASK) { 233 case PCIM_HTCAP_SWITCH: 234 printf("switch"); 235 break; 236 case PCIM_HTCAP_INTERRUPT: 237 printf("interrupt"); 238 break; 239 case PCIM_HTCAP_REVISION_ID: 240 printf("revision ID"); 241 break; 242 case PCIM_HTCAP_UNITID_CLUMPING: 243 printf("unit ID clumping"); 244 break; 245 case PCIM_HTCAP_EXT_CONFIG_SPACE: 246 printf("extended config space"); 247 break; 248 case PCIM_HTCAP_ADDRESS_MAPPING: 249 printf("address mapping"); 250 break; 251 case PCIM_HTCAP_MSI_MAPPING: 252 printf("MSI %saddress window %s at 0x", 253 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 254 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 255 "disabled"); 256 if (command & PCIM_HTCMD_MSI_FIXED) 257 printf("fee00000"); 258 else { 259 reg = read_config(fd, &p->pc_sel, 260 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 261 if (reg != 0) 262 printf("%08x", reg); 263 reg = read_config(fd, &p->pc_sel, 264 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 265 printf("%08x", reg); 266 } 267 break; 268 case PCIM_HTCAP_DIRECT_ROUTE: 269 printf("direct route"); 270 break; 271 case PCIM_HTCAP_VCSET: 272 printf("VC set"); 273 break; 274 case PCIM_HTCAP_RETRY_MODE: 275 printf("retry mode"); 276 break; 277 case PCIM_HTCAP_X86_ENCODING: 278 printf("X86 encoding"); 279 break; 280 case PCIM_HTCAP_GEN3: 281 printf("Gen3"); 282 break; 283 case PCIM_HTCAP_FLE: 284 printf("function-level extension"); 285 break; 286 case PCIM_HTCAP_PM: 287 printf("power management"); 288 break; 289 case PCIM_HTCAP_HIGH_NODE_COUNT: 290 printf("high node count"); 291 break; 292 default: 293 printf("unknown %02x", command); 294 break; 295 } 296 } 297 298 static void 299 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 300 { 301 uint8_t length; 302 303 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 304 printf("vendor (length %d)", length); 305 if (p->pc_vendor == 0x8086) { 306 /* Intel */ 307 uint8_t version; 308 309 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 310 1); 311 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 312 if (version >> 4 == 1 && length == 12) { 313 /* Feature Detection */ 314 uint32_t fvec; 315 int comma; 316 317 comma = 0; 318 fvec = read_config(fd, &p->pc_sel, ptr + 319 PCIR_VENDOR_DATA + 5, 4); 320 printf("\n\t\t features:"); 321 if (fvec & (1 << 0)) { 322 printf(" AMT"); 323 comma = 1; 324 } 325 fvec = read_config(fd, &p->pc_sel, ptr + 326 PCIR_VENDOR_DATA + 1, 4); 327 if (fvec & (1 << 21)) { 328 printf("%s Quick Resume", comma ? "," : ""); 329 comma = 1; 330 } 331 if (fvec & (1 << 18)) { 332 printf("%s SATA RAID-5", comma ? "," : ""); 333 comma = 1; 334 } 335 if (fvec & (1 << 9)) { 336 printf("%s Mobile", comma ? "," : ""); 337 comma = 1; 338 } 339 if (fvec & (1 << 7)) { 340 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 341 comma = 1; 342 } else { 343 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 344 comma = 1; 345 } 346 if (fvec & (1 << 5)) { 347 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 348 comma = 1; 349 } 350 if (fvec & (1 << 3)) { 351 printf("%s SATA AHCI", comma ? "," : ""); 352 comma = 1; 353 } 354 } 355 } 356 } 357 358 static void 359 cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 360 { 361 uint16_t debug_port; 362 363 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 364 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 365 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 366 } 367 368 static void 369 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 370 { 371 uint32_t id; 372 373 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 374 printf("PCI Bridge card=0x%08x", id); 375 } 376 377 #define MAX_PAYLOAD(field) (128 << (field)) 378 379 static const char * 380 link_speed_string(uint8_t speed) 381 { 382 383 switch (speed) { 384 case 1: 385 return ("2.5"); 386 case 2: 387 return ("5.0"); 388 case 3: 389 return ("8.0"); 390 default: 391 return ("undef"); 392 } 393 } 394 395 static const char * 396 aspm_string(uint8_t aspm) 397 { 398 399 switch (aspm) { 400 case 1: 401 return ("L0s"); 402 case 2: 403 return ("L1"); 404 case 3: 405 return ("L0s/L1"); 406 default: 407 return ("disabled"); 408 } 409 } 410 411 static void 412 cap_express(int fd, struct pci_conf *p, uint8_t ptr) 413 { 414 uint32_t cap, cap2; 415 uint16_t ctl, flags, sta; 416 417 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 418 printf("PCI-Express %d ", flags & PCIEM_FLAGS_VERSION); 419 switch (flags & PCIEM_FLAGS_TYPE) { 420 case PCIEM_TYPE_ENDPOINT: 421 printf("endpoint"); 422 break; 423 case PCIEM_TYPE_LEGACY_ENDPOINT: 424 printf("legacy endpoint"); 425 break; 426 case PCIEM_TYPE_ROOT_PORT: 427 printf("root port"); 428 break; 429 case PCIEM_TYPE_UPSTREAM_PORT: 430 printf("upstream port"); 431 break; 432 case PCIEM_TYPE_DOWNSTREAM_PORT: 433 printf("downstream port"); 434 break; 435 case PCIEM_TYPE_PCI_BRIDGE: 436 printf("PCI bridge"); 437 break; 438 case PCIEM_TYPE_PCIE_BRIDGE: 439 printf("PCI to PCIe bridge"); 440 break; 441 case PCIEM_TYPE_ROOT_INT_EP: 442 printf("root endpoint"); 443 break; 444 case PCIEM_TYPE_ROOT_EC: 445 printf("event collector"); 446 break; 447 default: 448 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 449 break; 450 } 451 if (flags & PCIEM_FLAGS_SLOT) 452 printf(" slot"); 453 if (flags & PCIEM_FLAGS_IRQ) 454 printf(" IRQ %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 455 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 456 cap2 = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4); 457 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 458 printf(" max data %d(%d)", 459 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5), 460 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD)); 461 if ((cap & PCIEM_CAP_FLR) != 0) 462 printf(" FLR"); 463 if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE) 464 printf(" RO"); 465 if (ctl & PCIEM_CTL_NOSNOOP_ENABLE) 466 printf(" NS"); 467 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 468 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2); 469 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4, 470 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 471 if ((cap & (PCIEM_LINK_CAP_MAX_WIDTH | PCIEM_LINK_CAP_ASPM)) != 0) 472 printf("\n "); 473 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 474 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ? 475 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED), 476 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED)); 477 } 478 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 479 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 480 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC), 481 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10)); 482 } 483 if ((cap2 & PCIEM_CAP2_ARI) != 0) { 484 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL2, 4); 485 printf(" ARI %s", 486 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled"); 487 } 488 } 489 490 static void 491 cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 492 { 493 uint32_t pba_offset, table_offset, val; 494 int msgnum, pba_bar, table_bar; 495 uint16_t ctrl; 496 497 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 498 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 499 500 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 501 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 502 table_offset = val & ~PCIM_MSIX_BIR_MASK; 503 504 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 505 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 506 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 507 508 printf("MSI-X supports %d message%s%s\n", msgnum, 509 (msgnum == 1) ? "" : "s", 510 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 511 512 printf(" "); 513 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 514 table_bar, table_offset, pba_bar, pba_offset); 515 } 516 517 static void 518 cap_sata(int fd, struct pci_conf *p, uint8_t ptr) 519 { 520 521 printf("SATA Index-Data Pair"); 522 } 523 524 static void 525 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 526 { 527 uint8_t cap; 528 529 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 530 printf("PCI Advanced Features:%s%s", 531 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 532 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 533 } 534 535 void 536 list_caps(int fd, struct pci_conf *p) 537 { 538 int express; 539 uint16_t sta; 540 uint8_t ptr, cap; 541 542 /* Are capabilities present for this device? */ 543 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 544 if (!(sta & PCIM_STATUS_CAPPRESENT)) 545 return; 546 547 switch (p->pc_hdr & PCIM_HDRTYPE) { 548 case PCIM_HDRTYPE_NORMAL: 549 case PCIM_HDRTYPE_BRIDGE: 550 ptr = PCIR_CAP_PTR; 551 break; 552 case PCIM_HDRTYPE_CARDBUS: 553 ptr = PCIR_CAP_PTR_2; 554 break; 555 default: 556 errx(1, "list_caps: bad header type"); 557 } 558 559 /* Walk the capability list. */ 560 express = 0; 561 ptr = read_config(fd, &p->pc_sel, ptr, 1); 562 while (ptr != 0 && ptr != 0xff) { 563 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 564 printf(" cap %02x[%02x] = ", cap, ptr); 565 switch (cap) { 566 case PCIY_PMG: 567 cap_power(fd, p, ptr); 568 break; 569 case PCIY_AGP: 570 cap_agp(fd, p, ptr); 571 break; 572 case PCIY_VPD: 573 cap_vpd(fd, p, ptr); 574 break; 575 case PCIY_MSI: 576 cap_msi(fd, p, ptr); 577 break; 578 case PCIY_PCIX: 579 cap_pcix(fd, p, ptr); 580 break; 581 case PCIY_HT: 582 cap_ht(fd, p, ptr); 583 break; 584 case PCIY_VENDOR: 585 cap_vendor(fd, p, ptr); 586 break; 587 case PCIY_DEBUG: 588 cap_debug(fd, p, ptr); 589 break; 590 case PCIY_SUBVENDOR: 591 cap_subvendor(fd, p, ptr); 592 break; 593 case PCIY_EXPRESS: 594 express = 1; 595 cap_express(fd, p, ptr); 596 break; 597 case PCIY_MSIX: 598 cap_msix(fd, p, ptr); 599 break; 600 case PCIY_SATA: 601 cap_sata(fd, p, ptr); 602 break; 603 case PCIY_PCIAF: 604 cap_pciaf(fd, p, ptr); 605 break; 606 default: 607 printf("unknown"); 608 break; 609 } 610 printf("\n"); 611 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 612 } 613 614 if (express) 615 list_ecaps(fd, p); 616 } 617 618 /* From <sys/systm.h>. */ 619 static __inline uint32_t 620 bitcount32(uint32_t x) 621 { 622 623 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 624 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 625 x = (x + (x >> 4)) & 0x0f0f0f0f; 626 x = (x + (x >> 8)); 627 x = (x + (x >> 16)) & 0x000000ff; 628 return (x); 629 } 630 631 static void 632 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 633 { 634 uint32_t sta, mask; 635 636 printf("AER %d", ver); 637 if (ver < 1) 638 return; 639 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 640 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 641 printf(" %d fatal", bitcount32(sta & mask)); 642 printf(" %d non-fatal", bitcount32(sta & ~mask)); 643 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 644 printf(" %d corrected\n", bitcount32(sta)); 645 } 646 647 static void 648 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 649 { 650 uint32_t cap1; 651 652 printf("VC %d", ver); 653 if (ver < 1) 654 return; 655 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 656 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 657 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 658 printf(" lowpri VC0-VC%d", 659 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 660 printf("\n"); 661 } 662 663 static void 664 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 665 { 666 uint32_t high, low; 667 668 printf("Serial %d", ver); 669 if (ver < 1) 670 return; 671 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 672 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 673 printf(" %08x%08x\n", high, low); 674 } 675 676 static void 677 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 678 { 679 uint32_t val; 680 681 printf("Vendor %d", ver); 682 if (ver < 1) 683 return; 684 val = read_config(fd, &p->pc_sel, ptr + 4, 4); 685 printf(" ID %d\n", val & 0xffff); 686 } 687 688 static void 689 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 690 { 691 uint32_t val; 692 693 printf("PCIe Sec %d", ver); 694 if (ver < 1) 695 return; 696 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 697 printf(" lane errors %#x\n", val); 698 } 699 700 static const char * 701 check_enabled(int value) 702 { 703 704 return (value ? "enabled" : "disabled"); 705 } 706 707 static void 708 ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 709 { 710 const char *comma, *enabled; 711 uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did; 712 uint32_t page_caps, page_size, page_shift, size; 713 int i; 714 715 printf("SR-IOV %d ", ver); 716 717 iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2); 718 printf("IOV %s, Memory Space %s, ARI %s\n", 719 check_enabled(iov_ctl & PCIM_SRIOV_VF_EN), 720 check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE), 721 check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN)); 722 723 total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2); 724 num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2); 725 printf(" "); 726 printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs); 727 728 vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2); 729 vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2); 730 printf(" "); 731 printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset, 732 vf_stride); 733 734 vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2); 735 printf(" VF Device ID 0x%04x\n", vf_did); 736 737 page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4); 738 page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4); 739 printf(" "); 740 printf("Page Sizes: "); 741 comma = ""; 742 while (page_caps != 0) { 743 page_shift = ffs(page_caps) - 1; 744 745 if (page_caps & page_size) 746 enabled = " (enabled)"; 747 else 748 enabled = ""; 749 750 size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT)); 751 printf("%s%d%s", comma, size, enabled); 752 comma = ", "; 753 754 page_caps &= ~(1 << page_shift); 755 } 756 printf("\n"); 757 758 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 759 print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i)); 760 } 761 762 struct { 763 uint16_t id; 764 const char *name; 765 } ecap_names[] = { 766 { PCIZ_PWRBDGT, "Power Budgeting" }, 767 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 768 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 769 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 770 { PCIZ_MFVC, "MFVC" }, 771 { PCIZ_RCRB, "RCRB" }, 772 { PCIZ_ACS, "ACS" }, 773 { PCIZ_ARI, "ARI" }, 774 { PCIZ_ATS, "ATS" }, 775 { PCIZ_MULTICAST, "Multicast" }, 776 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 777 { PCIZ_DPA, "DPA" }, 778 { PCIZ_TPH_REQ, "TPH Requester" }, 779 { PCIZ_LTR, "LTR" }, 780 { 0, NULL } 781 }; 782 783 static void 784 list_ecaps(int fd, struct pci_conf *p) 785 { 786 const char *name; 787 uint32_t ecap; 788 uint16_t ptr; 789 int i; 790 791 ptr = PCIR_EXTCAP; 792 ecap = read_config(fd, &p->pc_sel, ptr, 4); 793 if (ecap == 0xffffffff || ecap == 0) 794 return; 795 for (;;) { 796 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 797 switch (PCI_EXTCAP_ID(ecap)) { 798 case PCIZ_AER: 799 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 800 break; 801 case PCIZ_VC: 802 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 803 break; 804 case PCIZ_SERNUM: 805 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 806 break; 807 case PCIZ_VENDOR: 808 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 809 break; 810 case PCIZ_SEC_PCIE: 811 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 812 break; 813 case PCIZ_SRIOV: 814 ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 815 break; 816 default: 817 name = "unknown"; 818 for (i = 0; ecap_names[i].name != NULL; i++) 819 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 820 name = ecap_names[i].name; 821 break; 822 } 823 printf("%s %d\n", name, PCI_EXTCAP_VER(ecap)); 824 break; 825 } 826 ptr = PCI_EXTCAP_NEXTPTR(ecap); 827 if (ptr == 0) 828 break; 829 ecap = read_config(fd, &p->pc_sel, ptr, 4); 830 } 831 } 832 833 /* Find offset of a specific capability. Returns 0 on failure. */ 834 uint8_t 835 pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 836 { 837 uint16_t sta; 838 uint8_t ptr, cap; 839 840 /* Are capabilities present for this device? */ 841 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 842 if (!(sta & PCIM_STATUS_CAPPRESENT)) 843 return (0); 844 845 switch (p->pc_hdr & PCIM_HDRTYPE) { 846 case PCIM_HDRTYPE_NORMAL: 847 case PCIM_HDRTYPE_BRIDGE: 848 ptr = PCIR_CAP_PTR; 849 break; 850 case PCIM_HDRTYPE_CARDBUS: 851 ptr = PCIR_CAP_PTR_2; 852 break; 853 default: 854 return (0); 855 } 856 857 ptr = read_config(fd, &p->pc_sel, ptr, 1); 858 while (ptr != 0 && ptr != 0xff) { 859 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 860 if (cap == id) 861 return (ptr); 862 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 863 } 864 return (0); 865 } 866 867 /* Find offset of a specific extended capability. Returns 0 on failure. */ 868 uint16_t 869 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 870 { 871 uint32_t ecap; 872 uint16_t ptr; 873 874 ptr = PCIR_EXTCAP; 875 ecap = read_config(fd, &p->pc_sel, ptr, 4); 876 if (ecap == 0xffffffff || ecap == 0) 877 return (0); 878 for (;;) { 879 if (PCI_EXTCAP_ID(ecap) == id) 880 return (ptr); 881 ptr = PCI_EXTCAP_NEXTPTR(ecap); 882 if (ptr == 0) 883 break; 884 ecap = read_config(fd, &p->pc_sel, ptr, 4); 885 } 886 return (0); 887 } 888