1 /*- 2 * Copyright (c) 2007 Yahoo!, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef lint 32 static const char rcsid[] = 33 "$FreeBSD$"; 34 #endif /* not lint */ 35 36 #include <sys/types.h> 37 38 #include <err.h> 39 #include <stdio.h> 40 #include <sys/agpio.h> 41 #include <sys/pciio.h> 42 43 #include <dev/agp/agpreg.h> 44 #include <dev/pci/pcireg.h> 45 46 #include "pciconf.h" 47 48 static void list_ecaps(int fd, struct pci_conf *p); 49 50 static void 51 cap_power(int fd, struct pci_conf *p, uint8_t ptr) 52 { 53 uint16_t cap, status; 54 55 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 56 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 57 printf("powerspec %d supports D0%s%s D3 current D%d", 58 cap & PCIM_PCAP_SPEC, 59 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 60 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 61 status & PCIM_PSTAT_DMASK); 62 } 63 64 static void 65 cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 66 { 67 uint32_t status, command; 68 69 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 70 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 71 printf("AGP "); 72 if (AGP_MODE_GET_MODE_3(status)) { 73 printf("v3 "); 74 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 75 printf("8x "); 76 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 77 printf("4x "); 78 } else { 79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 80 printf("4x "); 81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 82 printf("2x "); 83 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 84 printf("1x "); 85 } 86 if (AGP_MODE_GET_SBA(status)) 87 printf("SBA "); 88 if (AGP_MODE_GET_AGP(command)) { 89 printf("enabled at "); 90 if (AGP_MODE_GET_MODE_3(command)) { 91 printf("v3 "); 92 switch (AGP_MODE_GET_RATE(command)) { 93 case AGP_MODE_V3_RATE_8x: 94 printf("8x "); 95 break; 96 case AGP_MODE_V3_RATE_4x: 97 printf("4x "); 98 break; 99 } 100 } else 101 switch (AGP_MODE_GET_RATE(command)) { 102 case AGP_MODE_V2_RATE_4x: 103 printf("4x "); 104 break; 105 case AGP_MODE_V2_RATE_2x: 106 printf("2x "); 107 break; 108 case AGP_MODE_V2_RATE_1x: 109 printf("1x "); 110 break; 111 } 112 if (AGP_MODE_GET_SBA(command)) 113 printf("SBA "); 114 } else 115 printf("disabled"); 116 } 117 118 static void 119 cap_vpd(int fd, struct pci_conf *p, uint8_t ptr) 120 { 121 122 printf("VPD"); 123 } 124 125 static void 126 cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 127 { 128 uint16_t ctrl; 129 int msgnum; 130 131 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 132 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 133 printf("MSI supports %d message%s%s%s ", msgnum, 134 (msgnum == 1) ? "" : "s", 135 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 136 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 137 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 138 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 139 printf("enabled with %d message%s", msgnum, 140 (msgnum == 1) ? "" : "s"); 141 } 142 } 143 144 static void 145 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 146 { 147 uint32_t status; 148 int comma, max_splits, max_burst_read; 149 150 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 151 printf("PCI-X "); 152 if (status & PCIXM_STATUS_64BIT) 153 printf("64-bit "); 154 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 155 printf("bridge "); 156 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 157 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 158 printf("supports"); 159 comma = 0; 160 if (status & PCIXM_STATUS_133CAP) { 161 printf("%s 133MHz", comma ? "," : ""); 162 comma = 1; 163 } 164 if (status & PCIXM_STATUS_266CAP) { 165 printf("%s 266MHz", comma ? "," : ""); 166 comma = 1; 167 } 168 if (status & PCIXM_STATUS_533CAP) { 169 printf("%s 533MHz", comma ? "," : ""); 170 comma = 1; 171 } 172 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 173 return; 174 switch (status & PCIXM_STATUS_MAX_READ) { 175 case PCIXM_STATUS_MAX_READ_512: 176 max_burst_read = 512; 177 break; 178 case PCIXM_STATUS_MAX_READ_1024: 179 max_burst_read = 1024; 180 break; 181 case PCIXM_STATUS_MAX_READ_2048: 182 max_burst_read = 2048; 183 break; 184 case PCIXM_STATUS_MAX_READ_4096: 185 max_burst_read = 4096; 186 break; 187 } 188 switch (status & PCIXM_STATUS_MAX_SPLITS) { 189 case PCIXM_STATUS_MAX_SPLITS_1: 190 max_splits = 1; 191 break; 192 case PCIXM_STATUS_MAX_SPLITS_2: 193 max_splits = 2; 194 break; 195 case PCIXM_STATUS_MAX_SPLITS_3: 196 max_splits = 3; 197 break; 198 case PCIXM_STATUS_MAX_SPLITS_4: 199 max_splits = 4; 200 break; 201 case PCIXM_STATUS_MAX_SPLITS_8: 202 max_splits = 8; 203 break; 204 case PCIXM_STATUS_MAX_SPLITS_12: 205 max_splits = 12; 206 break; 207 case PCIXM_STATUS_MAX_SPLITS_16: 208 max_splits = 16; 209 break; 210 case PCIXM_STATUS_MAX_SPLITS_32: 211 max_splits = 32; 212 break; 213 } 214 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 215 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 216 } 217 218 static void 219 cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 220 { 221 uint32_t reg; 222 uint16_t command; 223 224 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 225 printf("HT "); 226 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 227 printf("slave"); 228 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 229 printf("host"); 230 else 231 switch (command & PCIM_HTCMD_CAP_MASK) { 232 case PCIM_HTCAP_SWITCH: 233 printf("switch"); 234 break; 235 case PCIM_HTCAP_INTERRUPT: 236 printf("interrupt"); 237 break; 238 case PCIM_HTCAP_REVISION_ID: 239 printf("revision ID"); 240 break; 241 case PCIM_HTCAP_UNITID_CLUMPING: 242 printf("unit ID clumping"); 243 break; 244 case PCIM_HTCAP_EXT_CONFIG_SPACE: 245 printf("extended config space"); 246 break; 247 case PCIM_HTCAP_ADDRESS_MAPPING: 248 printf("address mapping"); 249 break; 250 case PCIM_HTCAP_MSI_MAPPING: 251 printf("MSI %saddress window %s at 0x", 252 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 253 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 254 "disabled"); 255 if (command & PCIM_HTCMD_MSI_FIXED) 256 printf("fee00000"); 257 else { 258 reg = read_config(fd, &p->pc_sel, 259 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 260 if (reg != 0) 261 printf("%08x", reg); 262 reg = read_config(fd, &p->pc_sel, 263 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 264 printf("%08x", reg); 265 } 266 break; 267 case PCIM_HTCAP_DIRECT_ROUTE: 268 printf("direct route"); 269 break; 270 case PCIM_HTCAP_VCSET: 271 printf("VC set"); 272 break; 273 case PCIM_HTCAP_RETRY_MODE: 274 printf("retry mode"); 275 break; 276 case PCIM_HTCAP_X86_ENCODING: 277 printf("X86 encoding"); 278 break; 279 case PCIM_HTCAP_GEN3: 280 printf("Gen3"); 281 break; 282 case PCIM_HTCAP_FLE: 283 printf("function-level extension"); 284 break; 285 case PCIM_HTCAP_PM: 286 printf("power management"); 287 break; 288 case PCIM_HTCAP_HIGH_NODE_COUNT: 289 printf("high node count"); 290 break; 291 default: 292 printf("unknown %02x", command); 293 break; 294 } 295 } 296 297 static void 298 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 299 { 300 uint8_t length; 301 302 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 303 printf("vendor (length %d)", length); 304 if (p->pc_vendor == 0x8086) { 305 /* Intel */ 306 uint8_t version; 307 308 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 309 1); 310 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 311 if (version >> 4 == 1 && length == 12) { 312 /* Feature Detection */ 313 uint32_t fvec; 314 int comma; 315 316 comma = 0; 317 fvec = read_config(fd, &p->pc_sel, ptr + 318 PCIR_VENDOR_DATA + 5, 4); 319 printf("\n\t\t features:"); 320 if (fvec & (1 << 0)) { 321 printf(" AMT"); 322 comma = 1; 323 } 324 fvec = read_config(fd, &p->pc_sel, ptr + 325 PCIR_VENDOR_DATA + 1, 4); 326 if (fvec & (1 << 21)) { 327 printf("%s Quick Resume", comma ? "," : ""); 328 comma = 1; 329 } 330 if (fvec & (1 << 18)) { 331 printf("%s SATA RAID-5", comma ? "," : ""); 332 comma = 1; 333 } 334 if (fvec & (1 << 9)) { 335 printf("%s Mobile", comma ? "," : ""); 336 comma = 1; 337 } 338 if (fvec & (1 << 7)) { 339 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 340 comma = 1; 341 } else { 342 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 343 comma = 1; 344 } 345 if (fvec & (1 << 5)) { 346 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 347 comma = 1; 348 } 349 if (fvec & (1 << 3)) { 350 printf("%s SATA AHCI", comma ? "," : ""); 351 comma = 1; 352 } 353 } 354 } 355 } 356 357 static void 358 cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 359 { 360 uint16_t debug_port; 361 362 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 363 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 364 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 365 } 366 367 static void 368 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 369 { 370 uint32_t id; 371 372 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 373 printf("PCI Bridge card=0x%08x", id); 374 } 375 376 #define MAX_PAYLOAD(field) (128 << (field)) 377 378 static const char * 379 link_speed_string(uint8_t speed) 380 { 381 382 switch (speed) { 383 case 1: 384 return ("2.5"); 385 case 2: 386 return ("5.0"); 387 case 3: 388 return ("8.0"); 389 default: 390 return ("undef"); 391 } 392 } 393 394 static const char * 395 aspm_string(uint8_t aspm) 396 { 397 398 switch (aspm) { 399 case 1: 400 return ("L0s"); 401 case 2: 402 return ("L1"); 403 case 3: 404 return ("L0s/L1"); 405 default: 406 return ("disabled"); 407 } 408 } 409 410 static void 411 cap_express(int fd, struct pci_conf *p, uint8_t ptr) 412 { 413 uint32_t cap, cap2; 414 uint16_t ctl, flags, sta; 415 416 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 417 printf("PCI-Express %d ", flags & PCIEM_FLAGS_VERSION); 418 switch (flags & PCIEM_FLAGS_TYPE) { 419 case PCIEM_TYPE_ENDPOINT: 420 printf("endpoint"); 421 break; 422 case PCIEM_TYPE_LEGACY_ENDPOINT: 423 printf("legacy endpoint"); 424 break; 425 case PCIEM_TYPE_ROOT_PORT: 426 printf("root port"); 427 break; 428 case PCIEM_TYPE_UPSTREAM_PORT: 429 printf("upstream port"); 430 break; 431 case PCIEM_TYPE_DOWNSTREAM_PORT: 432 printf("downstream port"); 433 break; 434 case PCIEM_TYPE_PCI_BRIDGE: 435 printf("PCI bridge"); 436 break; 437 case PCIEM_TYPE_PCIE_BRIDGE: 438 printf("PCI to PCIe bridge"); 439 break; 440 case PCIEM_TYPE_ROOT_INT_EP: 441 printf("root endpoint"); 442 break; 443 case PCIEM_TYPE_ROOT_EC: 444 printf("event collector"); 445 break; 446 default: 447 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 448 break; 449 } 450 if (flags & PCIEM_FLAGS_SLOT) 451 printf(" slot"); 452 if (flags & PCIEM_FLAGS_IRQ) 453 printf(" IRQ %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 454 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 455 cap2 = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4); 456 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 457 printf(" max data %d(%d)", 458 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5), 459 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD)); 460 if ((cap & PCIEM_CAP_FLR) != 0) 461 printf(" FLR"); 462 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 463 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2); 464 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4, 465 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 466 if ((cap & (PCIEM_LINK_CAP_MAX_WIDTH | PCIEM_LINK_CAP_ASPM)) != 0) 467 printf("\n "); 468 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 469 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ? 470 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED), 471 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED)); 472 } 473 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 474 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 475 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC), 476 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10)); 477 } 478 if ((cap2 & PCIEM_CAP2_ARI) != 0) { 479 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL2, 4); 480 printf(" ARI %s", 481 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled"); 482 } 483 } 484 485 static void 486 cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 487 { 488 uint32_t pba_offset, table_offset, val; 489 int msgnum, pba_bar, table_bar; 490 uint16_t ctrl; 491 492 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 493 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 494 495 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 496 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 497 table_offset = val & ~PCIM_MSIX_BIR_MASK; 498 499 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 500 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 501 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 502 503 printf("MSI-X supports %d message%s%s\n", msgnum, 504 (msgnum == 1) ? "" : "s", 505 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 506 507 printf(" "); 508 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 509 table_bar, table_offset, pba_bar, pba_offset); 510 } 511 512 static void 513 cap_sata(int fd, struct pci_conf *p, uint8_t ptr) 514 { 515 516 printf("SATA Index-Data Pair"); 517 } 518 519 static void 520 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 521 { 522 uint8_t cap; 523 524 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 525 printf("PCI Advanced Features:%s%s", 526 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 527 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 528 } 529 530 void 531 list_caps(int fd, struct pci_conf *p) 532 { 533 int express; 534 uint16_t sta; 535 uint8_t ptr, cap; 536 537 /* Are capabilities present for this device? */ 538 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 539 if (!(sta & PCIM_STATUS_CAPPRESENT)) 540 return; 541 542 switch (p->pc_hdr & PCIM_HDRTYPE) { 543 case PCIM_HDRTYPE_NORMAL: 544 case PCIM_HDRTYPE_BRIDGE: 545 ptr = PCIR_CAP_PTR; 546 break; 547 case PCIM_HDRTYPE_CARDBUS: 548 ptr = PCIR_CAP_PTR_2; 549 break; 550 default: 551 errx(1, "list_caps: bad header type"); 552 } 553 554 /* Walk the capability list. */ 555 express = 0; 556 ptr = read_config(fd, &p->pc_sel, ptr, 1); 557 while (ptr != 0 && ptr != 0xff) { 558 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 559 printf(" cap %02x[%02x] = ", cap, ptr); 560 switch (cap) { 561 case PCIY_PMG: 562 cap_power(fd, p, ptr); 563 break; 564 case PCIY_AGP: 565 cap_agp(fd, p, ptr); 566 break; 567 case PCIY_VPD: 568 cap_vpd(fd, p, ptr); 569 break; 570 case PCIY_MSI: 571 cap_msi(fd, p, ptr); 572 break; 573 case PCIY_PCIX: 574 cap_pcix(fd, p, ptr); 575 break; 576 case PCIY_HT: 577 cap_ht(fd, p, ptr); 578 break; 579 case PCIY_VENDOR: 580 cap_vendor(fd, p, ptr); 581 break; 582 case PCIY_DEBUG: 583 cap_debug(fd, p, ptr); 584 break; 585 case PCIY_SUBVENDOR: 586 cap_subvendor(fd, p, ptr); 587 break; 588 case PCIY_EXPRESS: 589 express = 1; 590 cap_express(fd, p, ptr); 591 break; 592 case PCIY_MSIX: 593 cap_msix(fd, p, ptr); 594 break; 595 case PCIY_SATA: 596 cap_sata(fd, p, ptr); 597 break; 598 case PCIY_PCIAF: 599 cap_pciaf(fd, p, ptr); 600 break; 601 default: 602 printf("unknown"); 603 break; 604 } 605 printf("\n"); 606 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 607 } 608 609 if (express) 610 list_ecaps(fd, p); 611 } 612 613 /* From <sys/systm.h>. */ 614 static __inline uint32_t 615 bitcount32(uint32_t x) 616 { 617 618 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 619 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 620 x = (x + (x >> 4)) & 0x0f0f0f0f; 621 x = (x + (x >> 8)); 622 x = (x + (x >> 16)) & 0x000000ff; 623 return (x); 624 } 625 626 static void 627 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 628 { 629 uint32_t sta, mask; 630 631 printf("AER %d", ver); 632 if (ver < 1) 633 return; 634 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 635 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 636 printf(" %d fatal", bitcount32(sta & mask)); 637 printf(" %d non-fatal", bitcount32(sta & ~mask)); 638 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 639 printf(" %d corrected", bitcount32(sta)); 640 } 641 642 static void 643 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 644 { 645 uint32_t cap1; 646 647 printf("VC %d", ver); 648 if (ver < 1) 649 return; 650 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 651 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 652 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 653 printf(" lowpri VC0-VC%d", 654 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 655 } 656 657 static void 658 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 659 { 660 uint32_t high, low; 661 662 printf("Serial %d", ver); 663 if (ver < 1) 664 return; 665 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 666 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 667 printf(" %08x%08x", high, low); 668 } 669 670 static void 671 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 672 { 673 uint32_t val; 674 675 printf("Vendor %d", ver); 676 if (ver < 1) 677 return; 678 val = read_config(fd, &p->pc_sel, ptr + 4, 4); 679 printf(" ID %d", val & 0xffff); 680 } 681 682 static void 683 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 684 { 685 uint32_t val; 686 687 printf("PCIe Sec %d", ver); 688 if (ver < 1) 689 return; 690 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 691 printf(" lane errors %#x", val); 692 } 693 694 struct { 695 uint16_t id; 696 const char *name; 697 } ecap_names[] = { 698 { PCIZ_PWRBDGT, "Power Budgeting" }, 699 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 700 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 701 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 702 { PCIZ_MFVC, "MFVC" }, 703 { PCIZ_RCRB, "RCRB" }, 704 { PCIZ_ACS, "ACS" }, 705 { PCIZ_ARI, "ARI" }, 706 { PCIZ_ATS, "ATS" }, 707 { PCIZ_SRIOV, "SRIOV" }, 708 { PCIZ_MULTICAST, "Multicast" }, 709 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 710 { PCIZ_DPA, "DPA" }, 711 { PCIZ_TPH_REQ, "TPH Requester" }, 712 { PCIZ_LTR, "LTR" }, 713 { 0, NULL } 714 }; 715 716 static void 717 list_ecaps(int fd, struct pci_conf *p) 718 { 719 const char *name; 720 uint32_t ecap; 721 uint16_t ptr; 722 int i; 723 724 ptr = PCIR_EXTCAP; 725 ecap = read_config(fd, &p->pc_sel, ptr, 4); 726 if (ecap == 0xffffffff || ecap == 0) 727 return; 728 for (;;) { 729 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 730 switch (PCI_EXTCAP_ID(ecap)) { 731 case PCIZ_AER: 732 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 733 break; 734 case PCIZ_VC: 735 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 736 break; 737 case PCIZ_SERNUM: 738 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 739 break; 740 case PCIZ_VENDOR: 741 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 742 break; 743 case PCIZ_SEC_PCIE: 744 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 745 break; 746 default: 747 name = "unknown"; 748 for (i = 0; ecap_names[i].name != NULL; i++) 749 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 750 name = ecap_names[i].name; 751 break; 752 } 753 printf("%s %d", name, PCI_EXTCAP_VER(ecap)); 754 break; 755 } 756 printf("\n"); 757 ptr = PCI_EXTCAP_NEXTPTR(ecap); 758 if (ptr == 0) 759 break; 760 ecap = read_config(fd, &p->pc_sel, ptr, 4); 761 } 762 } 763 764 /* Find offset of a specific capability. Returns 0 on failure. */ 765 uint8_t 766 pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 767 { 768 uint16_t sta; 769 uint8_t ptr, cap; 770 771 /* Are capabilities present for this device? */ 772 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 773 if (!(sta & PCIM_STATUS_CAPPRESENT)) 774 return (0); 775 776 switch (p->pc_hdr & PCIM_HDRTYPE) { 777 case PCIM_HDRTYPE_NORMAL: 778 case PCIM_HDRTYPE_BRIDGE: 779 ptr = PCIR_CAP_PTR; 780 break; 781 case PCIM_HDRTYPE_CARDBUS: 782 ptr = PCIR_CAP_PTR_2; 783 break; 784 default: 785 return (0); 786 } 787 788 ptr = read_config(fd, &p->pc_sel, ptr, 1); 789 while (ptr != 0 && ptr != 0xff) { 790 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 791 if (cap == id) 792 return (ptr); 793 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 794 } 795 return (0); 796 } 797 798 /* Find offset of a specific extended capability. Returns 0 on failure. */ 799 uint16_t 800 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 801 { 802 uint32_t ecap; 803 uint16_t ptr; 804 805 ptr = PCIR_EXTCAP; 806 ecap = read_config(fd, &p->pc_sel, ptr, 4); 807 if (ecap == 0xffffffff || ecap == 0) 808 return (0); 809 for (;;) { 810 if (PCI_EXTCAP_ID(ecap) == id) 811 return (ptr); 812 ptr = PCI_EXTCAP_NEXTPTR(ecap); 813 if (ptr == 0) 814 break; 815 ecap = read_config(fd, &p->pc_sel, ptr, 4); 816 } 817 return (0); 818 } 819