1 /*- 2 * Copyright (c) 2007 Yahoo!, Inc. 3 * All rights reserved. 4 * Written by: John Baldwin <jhb@FreeBSD.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31 #ifndef lint 32 static const char rcsid[] = 33 "$FreeBSD$"; 34 #endif /* not lint */ 35 36 #include <sys/types.h> 37 38 #include <err.h> 39 #include <stdio.h> 40 #include <strings.h> 41 #include <sys/agpio.h> 42 #include <sys/pciio.h> 43 44 #include <dev/agp/agpreg.h> 45 #include <dev/pci/pcireg.h> 46 47 #include "pciconf.h" 48 49 static void list_ecaps(int fd, struct pci_conf *p); 50 51 static void 52 cap_power(int fd, struct pci_conf *p, uint8_t ptr) 53 { 54 uint16_t cap, status; 55 56 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 57 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 58 printf("powerspec %d supports D0%s%s D3 current D%d", 59 cap & PCIM_PCAP_SPEC, 60 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 61 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 62 status & PCIM_PSTAT_DMASK); 63 } 64 65 static void 66 cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 67 { 68 uint32_t status, command; 69 70 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 71 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 72 printf("AGP "); 73 if (AGP_MODE_GET_MODE_3(status)) { 74 printf("v3 "); 75 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 76 printf("8x "); 77 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 78 printf("4x "); 79 } else { 80 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 81 printf("4x "); 82 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 83 printf("2x "); 84 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 85 printf("1x "); 86 } 87 if (AGP_MODE_GET_SBA(status)) 88 printf("SBA "); 89 if (AGP_MODE_GET_AGP(command)) { 90 printf("enabled at "); 91 if (AGP_MODE_GET_MODE_3(command)) { 92 printf("v3 "); 93 switch (AGP_MODE_GET_RATE(command)) { 94 case AGP_MODE_V3_RATE_8x: 95 printf("8x "); 96 break; 97 case AGP_MODE_V3_RATE_4x: 98 printf("4x "); 99 break; 100 } 101 } else 102 switch (AGP_MODE_GET_RATE(command)) { 103 case AGP_MODE_V2_RATE_4x: 104 printf("4x "); 105 break; 106 case AGP_MODE_V2_RATE_2x: 107 printf("2x "); 108 break; 109 case AGP_MODE_V2_RATE_1x: 110 printf("1x "); 111 break; 112 } 113 if (AGP_MODE_GET_SBA(command)) 114 printf("SBA "); 115 } else 116 printf("disabled"); 117 } 118 119 static void 120 cap_vpd(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 121 { 122 123 printf("VPD"); 124 } 125 126 static void 127 cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 128 { 129 uint16_t ctrl; 130 int msgnum; 131 132 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 133 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 134 printf("MSI supports %d message%s%s%s ", msgnum, 135 (msgnum == 1) ? "" : "s", 136 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 137 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 138 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 139 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 140 printf("enabled with %d message%s", msgnum, 141 (msgnum == 1) ? "" : "s"); 142 } 143 } 144 145 static void 146 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 147 { 148 uint32_t status; 149 int comma, max_splits, max_burst_read; 150 151 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 152 printf("PCI-X "); 153 if (status & PCIXM_STATUS_64BIT) 154 printf("64-bit "); 155 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 156 printf("bridge "); 157 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 158 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 159 printf("supports"); 160 comma = 0; 161 if (status & PCIXM_STATUS_133CAP) { 162 printf("%s 133MHz", comma ? "," : ""); 163 comma = 1; 164 } 165 if (status & PCIXM_STATUS_266CAP) { 166 printf("%s 266MHz", comma ? "," : ""); 167 comma = 1; 168 } 169 if (status & PCIXM_STATUS_533CAP) { 170 printf("%s 533MHz", comma ? "," : ""); 171 comma = 1; 172 } 173 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 174 return; 175 max_burst_read = 0; 176 switch (status & PCIXM_STATUS_MAX_READ) { 177 case PCIXM_STATUS_MAX_READ_512: 178 max_burst_read = 512; 179 break; 180 case PCIXM_STATUS_MAX_READ_1024: 181 max_burst_read = 1024; 182 break; 183 case PCIXM_STATUS_MAX_READ_2048: 184 max_burst_read = 2048; 185 break; 186 case PCIXM_STATUS_MAX_READ_4096: 187 max_burst_read = 4096; 188 break; 189 } 190 max_splits = 0; 191 switch (status & PCIXM_STATUS_MAX_SPLITS) { 192 case PCIXM_STATUS_MAX_SPLITS_1: 193 max_splits = 1; 194 break; 195 case PCIXM_STATUS_MAX_SPLITS_2: 196 max_splits = 2; 197 break; 198 case PCIXM_STATUS_MAX_SPLITS_3: 199 max_splits = 3; 200 break; 201 case PCIXM_STATUS_MAX_SPLITS_4: 202 max_splits = 4; 203 break; 204 case PCIXM_STATUS_MAX_SPLITS_8: 205 max_splits = 8; 206 break; 207 case PCIXM_STATUS_MAX_SPLITS_12: 208 max_splits = 12; 209 break; 210 case PCIXM_STATUS_MAX_SPLITS_16: 211 max_splits = 16; 212 break; 213 case PCIXM_STATUS_MAX_SPLITS_32: 214 max_splits = 32; 215 break; 216 } 217 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 218 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 219 } 220 221 static void 222 cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 223 { 224 uint32_t reg; 225 uint16_t command; 226 227 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 228 printf("HT "); 229 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 230 printf("slave"); 231 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 232 printf("host"); 233 else 234 switch (command & PCIM_HTCMD_CAP_MASK) { 235 case PCIM_HTCAP_SWITCH: 236 printf("switch"); 237 break; 238 case PCIM_HTCAP_INTERRUPT: 239 printf("interrupt"); 240 break; 241 case PCIM_HTCAP_REVISION_ID: 242 printf("revision ID"); 243 break; 244 case PCIM_HTCAP_UNITID_CLUMPING: 245 printf("unit ID clumping"); 246 break; 247 case PCIM_HTCAP_EXT_CONFIG_SPACE: 248 printf("extended config space"); 249 break; 250 case PCIM_HTCAP_ADDRESS_MAPPING: 251 printf("address mapping"); 252 break; 253 case PCIM_HTCAP_MSI_MAPPING: 254 printf("MSI %saddress window %s at 0x", 255 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 256 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 257 "disabled"); 258 if (command & PCIM_HTCMD_MSI_FIXED) 259 printf("fee00000"); 260 else { 261 reg = read_config(fd, &p->pc_sel, 262 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 263 if (reg != 0) 264 printf("%08x", reg); 265 reg = read_config(fd, &p->pc_sel, 266 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 267 printf("%08x", reg); 268 } 269 break; 270 case PCIM_HTCAP_DIRECT_ROUTE: 271 printf("direct route"); 272 break; 273 case PCIM_HTCAP_VCSET: 274 printf("VC set"); 275 break; 276 case PCIM_HTCAP_RETRY_MODE: 277 printf("retry mode"); 278 break; 279 case PCIM_HTCAP_X86_ENCODING: 280 printf("X86 encoding"); 281 break; 282 case PCIM_HTCAP_GEN3: 283 printf("Gen3"); 284 break; 285 case PCIM_HTCAP_FLE: 286 printf("function-level extension"); 287 break; 288 case PCIM_HTCAP_PM: 289 printf("power management"); 290 break; 291 case PCIM_HTCAP_HIGH_NODE_COUNT: 292 printf("high node count"); 293 break; 294 default: 295 printf("unknown %02x", command); 296 break; 297 } 298 } 299 300 static void 301 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 302 { 303 uint8_t length; 304 305 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 306 printf("vendor (length %d)", length); 307 if (p->pc_vendor == 0x8086) { 308 /* Intel */ 309 uint8_t version; 310 311 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 312 1); 313 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 314 if (version >> 4 == 1 && length == 12) { 315 /* Feature Detection */ 316 uint32_t fvec; 317 int comma; 318 319 comma = 0; 320 fvec = read_config(fd, &p->pc_sel, ptr + 321 PCIR_VENDOR_DATA + 5, 4); 322 printf("\n\t\t features:"); 323 if (fvec & (1 << 0)) { 324 printf(" AMT"); 325 comma = 1; 326 } 327 fvec = read_config(fd, &p->pc_sel, ptr + 328 PCIR_VENDOR_DATA + 1, 4); 329 if (fvec & (1 << 21)) { 330 printf("%s Quick Resume", comma ? "," : ""); 331 comma = 1; 332 } 333 if (fvec & (1 << 18)) { 334 printf("%s SATA RAID-5", comma ? "," : ""); 335 comma = 1; 336 } 337 if (fvec & (1 << 9)) { 338 printf("%s Mobile", comma ? "," : ""); 339 comma = 1; 340 } 341 if (fvec & (1 << 7)) { 342 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 343 comma = 1; 344 } else { 345 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 346 comma = 1; 347 } 348 if (fvec & (1 << 5)) { 349 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 350 comma = 1; 351 } 352 if (fvec & (1 << 3)) { 353 printf("%s SATA AHCI", comma ? "," : ""); 354 comma = 1; 355 } 356 } 357 } 358 } 359 360 static void 361 cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 362 { 363 uint16_t debug_port; 364 365 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 366 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 367 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 368 } 369 370 static void 371 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 372 { 373 uint32_t id; 374 375 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 376 printf("PCI Bridge card=0x%08x", id); 377 } 378 379 #define MAX_PAYLOAD(field) (128 << (field)) 380 381 static const char * 382 link_speed_string(uint8_t speed) 383 { 384 385 switch (speed) { 386 case 1: 387 return ("2.5"); 388 case 2: 389 return ("5.0"); 390 case 3: 391 return ("8.0"); 392 default: 393 return ("undef"); 394 } 395 } 396 397 static const char * 398 aspm_string(uint8_t aspm) 399 { 400 401 switch (aspm) { 402 case 1: 403 return ("L0s"); 404 case 2: 405 return ("L1"); 406 case 3: 407 return ("L0s/L1"); 408 default: 409 return ("disabled"); 410 } 411 } 412 413 static void 414 cap_express(int fd, struct pci_conf *p, uint8_t ptr) 415 { 416 uint32_t cap, cap2; 417 uint16_t ctl, flags, sta; 418 419 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 420 printf("PCI-Express %d ", flags & PCIEM_FLAGS_VERSION); 421 switch (flags & PCIEM_FLAGS_TYPE) { 422 case PCIEM_TYPE_ENDPOINT: 423 printf("endpoint"); 424 break; 425 case PCIEM_TYPE_LEGACY_ENDPOINT: 426 printf("legacy endpoint"); 427 break; 428 case PCIEM_TYPE_ROOT_PORT: 429 printf("root port"); 430 break; 431 case PCIEM_TYPE_UPSTREAM_PORT: 432 printf("upstream port"); 433 break; 434 case PCIEM_TYPE_DOWNSTREAM_PORT: 435 printf("downstream port"); 436 break; 437 case PCIEM_TYPE_PCI_BRIDGE: 438 printf("PCI bridge"); 439 break; 440 case PCIEM_TYPE_PCIE_BRIDGE: 441 printf("PCI to PCIe bridge"); 442 break; 443 case PCIEM_TYPE_ROOT_INT_EP: 444 printf("root endpoint"); 445 break; 446 case PCIEM_TYPE_ROOT_EC: 447 printf("event collector"); 448 break; 449 default: 450 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 451 break; 452 } 453 if (flags & PCIEM_FLAGS_SLOT) 454 printf(" slot"); 455 if (flags & PCIEM_FLAGS_IRQ) 456 printf(" IRQ %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 457 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 458 cap2 = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4); 459 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 460 printf(" max data %d(%d)", 461 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5), 462 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD)); 463 if ((cap & PCIEM_CAP_FLR) != 0) 464 printf(" FLR"); 465 if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE) 466 printf(" RO"); 467 if (ctl & PCIEM_CTL_NOSNOOP_ENABLE) 468 printf(" NS"); 469 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 470 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2); 471 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4, 472 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 473 if ((cap & (PCIEM_LINK_CAP_MAX_WIDTH | PCIEM_LINK_CAP_ASPM)) != 0) 474 printf("\n "); 475 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 476 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ? 477 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED), 478 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED)); 479 } 480 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 481 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 482 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC), 483 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10)); 484 } 485 if ((cap2 & PCIEM_CAP2_ARI) != 0) { 486 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL2, 4); 487 printf(" ARI %s", 488 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled"); 489 } 490 } 491 492 static void 493 cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 494 { 495 uint32_t pba_offset, table_offset, val; 496 int msgnum, pba_bar, table_bar; 497 uint16_t ctrl; 498 499 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 500 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 501 502 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 503 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 504 table_offset = val & ~PCIM_MSIX_BIR_MASK; 505 506 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 507 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 508 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 509 510 printf("MSI-X supports %d message%s%s\n", msgnum, 511 (msgnum == 1) ? "" : "s", 512 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 513 514 printf(" "); 515 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 516 table_bar, table_offset, pba_bar, pba_offset); 517 } 518 519 static void 520 cap_sata(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 521 { 522 523 printf("SATA Index-Data Pair"); 524 } 525 526 static void 527 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 528 { 529 uint8_t cap; 530 531 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 532 printf("PCI Advanced Features:%s%s", 533 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 534 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 535 } 536 537 static const char * 538 ea_bei_to_name(int bei) 539 { 540 static const char *barstr[] = { 541 "BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5" 542 }; 543 static const char *vfbarstr[] = { 544 "VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5" 545 }; 546 547 if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5)) 548 return (barstr[bei - PCIM_EA_BEI_BAR_0]); 549 if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5)) 550 return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]); 551 552 switch (bei) { 553 case PCIM_EA_BEI_BRIDGE: 554 return "BRIDGE"; 555 case PCIM_EA_BEI_ENI: 556 return "ENI"; 557 case PCIM_EA_BEI_ROM: 558 return "ROM"; 559 case PCIM_EA_BEI_RESERVED: 560 default: 561 return "RSVD"; 562 } 563 } 564 565 static const char * 566 ea_prop_to_name(uint8_t prop) 567 { 568 569 switch (prop) { 570 case PCIM_EA_P_MEM: 571 return "Non-Prefetchable Memory"; 572 case PCIM_EA_P_MEM_PREFETCH: 573 return "Prefetchable Memory"; 574 case PCIM_EA_P_IO: 575 return "I/O Space"; 576 case PCIM_EA_P_VF_MEM_PREFETCH: 577 return "VF Prefetchable Memory"; 578 case PCIM_EA_P_VF_MEM: 579 return "VF Non-Prefetchable Memory"; 580 case PCIM_EA_P_BRIDGE_MEM: 581 return "Bridge Non-Prefetchable Memory"; 582 case PCIM_EA_P_BRIDGE_MEM_PREFETCH: 583 return "Bridge Prefetchable Memory"; 584 case PCIM_EA_P_BRIDGE_IO: 585 return "Bridge I/O Space"; 586 case PCIM_EA_P_MEM_RESERVED: 587 return "Reserved Memory"; 588 case PCIM_EA_P_IO_RESERVED: 589 return "Reserved I/O Space"; 590 case PCIM_EA_P_UNAVAILABLE: 591 return "Unavailable"; 592 default: 593 return "Reserved"; 594 } 595 } 596 597 static void 598 cap_ea(int fd, struct pci_conf *p, uint8_t ptr) 599 { 600 int num_ent; 601 int a, b; 602 uint32_t bei; 603 uint32_t val; 604 int ent_size; 605 uint32_t dw[4]; 606 uint32_t flags, flags_pp, flags_sp; 607 uint64_t base, max_offset; 608 uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr; 609 610 /* Determine the number of entries */ 611 num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2); 612 num_ent &= PCIM_EA_NUM_ENT_MASK; 613 614 printf("PCI Enhanced Allocation (%d entries)", num_ent); 615 616 /* Find the first entry to care of */ 617 ptr += PCIR_EA_FIRST_ENT; 618 619 /* Print BUS numbers for bridges */ 620 if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) { 621 val = read_config(fd, &p->pc_sel, ptr, 4); 622 623 fixed_sec_bus_nr = PCIM_EA_SEC_NR(val); 624 fixed_sub_bus_nr = PCIM_EA_SUB_NR(val); 625 626 printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]", 627 fixed_sec_bus_nr, fixed_sub_bus_nr); 628 ptr += 4; 629 } 630 631 for (a = 0; a < num_ent; a++) { 632 /* Read a number of dwords in the entry */ 633 val = read_config(fd, &p->pc_sel, ptr, 4); 634 ptr += 4; 635 ent_size = (val & PCIM_EA_ES); 636 637 for (b = 0; b < ent_size; b++) { 638 dw[b] = read_config(fd, &p->pc_sel, ptr, 4); 639 ptr += 4; 640 } 641 642 flags = val; 643 flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET; 644 flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET; 645 bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 646 647 base = dw[0] & PCIM_EA_FIELD_MASK; 648 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 649 b = 2; 650 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 651 base |= (uint64_t)dw[b] << 32UL; 652 b++; 653 } 654 if (((dw[1] & PCIM_EA_IS_64) != 0) 655 && (b < ent_size)) { 656 max_offset |= (uint64_t)dw[b] << 32UL; 657 b++; 658 } 659 660 printf("\n\t\t [%d] %s, %s, %s, base [0x%jx], size [0x%jx]" 661 "\n\t\t\tPrimary properties [0x%x] (%s)" 662 "\n\t\t\tSecondary properties [0x%x] (%s)", 663 bei, ea_bei_to_name(bei), 664 (flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"), 665 (flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"), 666 (uintmax_t)base, (uintmax_t)(max_offset + 1), 667 flags_pp, ea_prop_to_name(flags_pp), 668 flags_sp, ea_prop_to_name(flags_sp)); 669 } 670 } 671 672 void 673 list_caps(int fd, struct pci_conf *p) 674 { 675 int express; 676 uint16_t sta; 677 uint8_t ptr, cap; 678 679 /* Are capabilities present for this device? */ 680 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 681 if (!(sta & PCIM_STATUS_CAPPRESENT)) 682 return; 683 684 switch (p->pc_hdr & PCIM_HDRTYPE) { 685 case PCIM_HDRTYPE_NORMAL: 686 case PCIM_HDRTYPE_BRIDGE: 687 ptr = PCIR_CAP_PTR; 688 break; 689 case PCIM_HDRTYPE_CARDBUS: 690 ptr = PCIR_CAP_PTR_2; 691 break; 692 default: 693 errx(1, "list_caps: bad header type"); 694 } 695 696 /* Walk the capability list. */ 697 express = 0; 698 ptr = read_config(fd, &p->pc_sel, ptr, 1); 699 while (ptr != 0 && ptr != 0xff) { 700 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 701 printf(" cap %02x[%02x] = ", cap, ptr); 702 switch (cap) { 703 case PCIY_PMG: 704 cap_power(fd, p, ptr); 705 break; 706 case PCIY_AGP: 707 cap_agp(fd, p, ptr); 708 break; 709 case PCIY_VPD: 710 cap_vpd(fd, p, ptr); 711 break; 712 case PCIY_MSI: 713 cap_msi(fd, p, ptr); 714 break; 715 case PCIY_PCIX: 716 cap_pcix(fd, p, ptr); 717 break; 718 case PCIY_HT: 719 cap_ht(fd, p, ptr); 720 break; 721 case PCIY_VENDOR: 722 cap_vendor(fd, p, ptr); 723 break; 724 case PCIY_DEBUG: 725 cap_debug(fd, p, ptr); 726 break; 727 case PCIY_SUBVENDOR: 728 cap_subvendor(fd, p, ptr); 729 break; 730 case PCIY_EXPRESS: 731 express = 1; 732 cap_express(fd, p, ptr); 733 break; 734 case PCIY_MSIX: 735 cap_msix(fd, p, ptr); 736 break; 737 case PCIY_SATA: 738 cap_sata(fd, p, ptr); 739 break; 740 case PCIY_PCIAF: 741 cap_pciaf(fd, p, ptr); 742 break; 743 case PCIY_EA: 744 cap_ea(fd, p, ptr); 745 break; 746 default: 747 printf("unknown"); 748 break; 749 } 750 printf("\n"); 751 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 752 } 753 754 if (express) 755 list_ecaps(fd, p); 756 } 757 758 /* From <sys/systm.h>. */ 759 static __inline uint32_t 760 bitcount32(uint32_t x) 761 { 762 763 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 764 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 765 x = (x + (x >> 4)) & 0x0f0f0f0f; 766 x = (x + (x >> 8)); 767 x = (x + (x >> 16)) & 0x000000ff; 768 return (x); 769 } 770 771 static void 772 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 773 { 774 uint32_t sta, mask; 775 776 printf("AER %d", ver); 777 if (ver < 1) 778 return; 779 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 780 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 781 printf(" %d fatal", bitcount32(sta & mask)); 782 printf(" %d non-fatal", bitcount32(sta & ~mask)); 783 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 784 printf(" %d corrected\n", bitcount32(sta)); 785 } 786 787 static void 788 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 789 { 790 uint32_t cap1; 791 792 printf("VC %d", ver); 793 if (ver < 1) 794 return; 795 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 796 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 797 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 798 printf(" lowpri VC0-VC%d", 799 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 800 printf("\n"); 801 } 802 803 static void 804 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 805 { 806 uint32_t high, low; 807 808 printf("Serial %d", ver); 809 if (ver < 1) 810 return; 811 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 812 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 813 printf(" %08x%08x\n", high, low); 814 } 815 816 static void 817 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 818 { 819 uint32_t val; 820 821 printf("Vendor %d", ver); 822 if (ver < 1) 823 return; 824 val = read_config(fd, &p->pc_sel, ptr + 4, 4); 825 printf(" ID %d\n", val & 0xffff); 826 } 827 828 static void 829 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 830 { 831 uint32_t val; 832 833 printf("PCIe Sec %d", ver); 834 if (ver < 1) 835 return; 836 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 837 printf(" lane errors %#x\n", val); 838 } 839 840 static const char * 841 check_enabled(int value) 842 { 843 844 return (value ? "enabled" : "disabled"); 845 } 846 847 static void 848 ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 849 { 850 const char *comma, *enabled; 851 uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did; 852 uint32_t page_caps, page_size, page_shift, size; 853 int i; 854 855 printf("SR-IOV %d ", ver); 856 857 iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2); 858 printf("IOV %s, Memory Space %s, ARI %s\n", 859 check_enabled(iov_ctl & PCIM_SRIOV_VF_EN), 860 check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE), 861 check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN)); 862 863 total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2); 864 num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2); 865 printf(" "); 866 printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs); 867 868 vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2); 869 vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2); 870 printf(" "); 871 printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset, 872 vf_stride); 873 874 vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2); 875 printf(" VF Device ID 0x%04x\n", vf_did); 876 877 page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4); 878 page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4); 879 printf(" "); 880 printf("Page Sizes: "); 881 comma = ""; 882 while (page_caps != 0) { 883 page_shift = ffs(page_caps) - 1; 884 885 if (page_caps & page_size) 886 enabled = " (enabled)"; 887 else 888 enabled = ""; 889 890 size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT)); 891 printf("%s%d%s", comma, size, enabled); 892 comma = ", "; 893 894 page_caps &= ~(1 << page_shift); 895 } 896 printf("\n"); 897 898 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 899 print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i)); 900 } 901 902 static struct { 903 uint16_t id; 904 const char *name; 905 } ecap_names[] = { 906 { PCIZ_PWRBDGT, "Power Budgeting" }, 907 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 908 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 909 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 910 { PCIZ_MFVC, "MFVC" }, 911 { PCIZ_RCRB, "RCRB" }, 912 { PCIZ_ACS, "ACS" }, 913 { PCIZ_ARI, "ARI" }, 914 { PCIZ_ATS, "ATS" }, 915 { PCIZ_MULTICAST, "Multicast" }, 916 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 917 { PCIZ_DPA, "DPA" }, 918 { PCIZ_TPH_REQ, "TPH Requester" }, 919 { PCIZ_LTR, "LTR" }, 920 { 0, NULL } 921 }; 922 923 static void 924 list_ecaps(int fd, struct pci_conf *p) 925 { 926 const char *name; 927 uint32_t ecap; 928 uint16_t ptr; 929 int i; 930 931 ptr = PCIR_EXTCAP; 932 ecap = read_config(fd, &p->pc_sel, ptr, 4); 933 if (ecap == 0xffffffff || ecap == 0) 934 return; 935 for (;;) { 936 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 937 switch (PCI_EXTCAP_ID(ecap)) { 938 case PCIZ_AER: 939 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 940 break; 941 case PCIZ_VC: 942 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 943 break; 944 case PCIZ_SERNUM: 945 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 946 break; 947 case PCIZ_VENDOR: 948 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 949 break; 950 case PCIZ_SEC_PCIE: 951 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 952 break; 953 case PCIZ_SRIOV: 954 ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 955 break; 956 default: 957 name = "unknown"; 958 for (i = 0; ecap_names[i].name != NULL; i++) 959 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 960 name = ecap_names[i].name; 961 break; 962 } 963 printf("%s %d\n", name, PCI_EXTCAP_VER(ecap)); 964 break; 965 } 966 ptr = PCI_EXTCAP_NEXTPTR(ecap); 967 if (ptr == 0) 968 break; 969 ecap = read_config(fd, &p->pc_sel, ptr, 4); 970 } 971 } 972 973 /* Find offset of a specific capability. Returns 0 on failure. */ 974 uint8_t 975 pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 976 { 977 uint16_t sta; 978 uint8_t ptr, cap; 979 980 /* Are capabilities present for this device? */ 981 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 982 if (!(sta & PCIM_STATUS_CAPPRESENT)) 983 return (0); 984 985 switch (p->pc_hdr & PCIM_HDRTYPE) { 986 case PCIM_HDRTYPE_NORMAL: 987 case PCIM_HDRTYPE_BRIDGE: 988 ptr = PCIR_CAP_PTR; 989 break; 990 case PCIM_HDRTYPE_CARDBUS: 991 ptr = PCIR_CAP_PTR_2; 992 break; 993 default: 994 return (0); 995 } 996 997 ptr = read_config(fd, &p->pc_sel, ptr, 1); 998 while (ptr != 0 && ptr != 0xff) { 999 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 1000 if (cap == id) 1001 return (ptr); 1002 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 1003 } 1004 return (0); 1005 } 1006 1007 /* Find offset of a specific extended capability. Returns 0 on failure. */ 1008 uint16_t 1009 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 1010 { 1011 uint32_t ecap; 1012 uint16_t ptr; 1013 1014 ptr = PCIR_EXTCAP; 1015 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1016 if (ecap == 0xffffffff || ecap == 0) 1017 return (0); 1018 for (;;) { 1019 if (PCI_EXTCAP_ID(ecap) == id) 1020 return (ptr); 1021 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1022 if (ptr == 0) 1023 break; 1024 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1025 } 1026 return (0); 1027 } 1028