1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 Yahoo!, Inc. 5 * All rights reserved. 6 * Written by: John Baldwin <jhb@FreeBSD.org> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #ifndef lint 34 static const char rcsid[] = 35 "$FreeBSD$"; 36 #endif /* not lint */ 37 38 #include <sys/types.h> 39 40 #include <err.h> 41 #include <stdio.h> 42 #include <strings.h> 43 #include <sys/agpio.h> 44 #include <sys/pciio.h> 45 46 #include <dev/agp/agpreg.h> 47 #include <dev/pci/pcireg.h> 48 49 #include "pciconf.h" 50 51 static void list_ecaps(int fd, struct pci_conf *p); 52 53 static int cap_level; 54 55 static void 56 cap_power(int fd, struct pci_conf *p, uint8_t ptr) 57 { 58 uint16_t cap, status; 59 60 cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2); 61 status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2); 62 printf("powerspec %d supports D0%s%s D3 current D%d", 63 cap & PCIM_PCAP_SPEC, 64 cap & PCIM_PCAP_D1SUPP ? " D1" : "", 65 cap & PCIM_PCAP_D2SUPP ? " D2" : "", 66 status & PCIM_PSTAT_DMASK); 67 } 68 69 static void 70 cap_agp(int fd, struct pci_conf *p, uint8_t ptr) 71 { 72 uint32_t status, command; 73 74 status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4); 75 command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4); 76 printf("AGP "); 77 if (AGP_MODE_GET_MODE_3(status)) { 78 printf("v3 "); 79 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x) 80 printf("8x "); 81 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x) 82 printf("4x "); 83 } else { 84 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x) 85 printf("4x "); 86 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x) 87 printf("2x "); 88 if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x) 89 printf("1x "); 90 } 91 if (AGP_MODE_GET_SBA(status)) 92 printf("SBA "); 93 if (AGP_MODE_GET_AGP(command)) { 94 printf("enabled at "); 95 if (AGP_MODE_GET_MODE_3(command)) { 96 printf("v3 "); 97 switch (AGP_MODE_GET_RATE(command)) { 98 case AGP_MODE_V3_RATE_8x: 99 printf("8x "); 100 break; 101 case AGP_MODE_V3_RATE_4x: 102 printf("4x "); 103 break; 104 } 105 } else 106 switch (AGP_MODE_GET_RATE(command)) { 107 case AGP_MODE_V2_RATE_4x: 108 printf("4x "); 109 break; 110 case AGP_MODE_V2_RATE_2x: 111 printf("2x "); 112 break; 113 case AGP_MODE_V2_RATE_1x: 114 printf("1x "); 115 break; 116 } 117 if (AGP_MODE_GET_SBA(command)) 118 printf("SBA "); 119 } else 120 printf("disabled"); 121 } 122 123 static void 124 cap_vpd(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 125 { 126 127 printf("VPD"); 128 } 129 130 static void 131 cap_msi(int fd, struct pci_conf *p, uint8_t ptr) 132 { 133 uint16_t ctrl; 134 int msgnum; 135 136 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2); 137 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1); 138 printf("MSI supports %d message%s%s%s ", msgnum, 139 (msgnum == 1) ? "" : "s", 140 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "", 141 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : ""); 142 if (ctrl & PCIM_MSICTRL_MSI_ENABLE) { 143 msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4); 144 printf("enabled with %d message%s", msgnum, 145 (msgnum == 1) ? "" : "s"); 146 } 147 } 148 149 static void 150 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr) 151 { 152 uint32_t status; 153 int comma, max_splits, max_burst_read; 154 155 status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4); 156 printf("PCI-X "); 157 if (status & PCIXM_STATUS_64BIT) 158 printf("64-bit "); 159 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 160 printf("bridge "); 161 if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP | 162 PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0) 163 printf("supports"); 164 comma = 0; 165 if (status & PCIXM_STATUS_133CAP) { 166 printf(" 133MHz"); 167 comma = 1; 168 } 169 if (status & PCIXM_STATUS_266CAP) { 170 printf("%s 266MHz", comma ? "," : ""); 171 comma = 1; 172 } 173 if (status & PCIXM_STATUS_533CAP) { 174 printf("%s 533MHz", comma ? "," : ""); 175 comma = 1; 176 } 177 if ((p->pc_hdr & PCIM_HDRTYPE) == 1) 178 return; 179 max_burst_read = 0; 180 switch (status & PCIXM_STATUS_MAX_READ) { 181 case PCIXM_STATUS_MAX_READ_512: 182 max_burst_read = 512; 183 break; 184 case PCIXM_STATUS_MAX_READ_1024: 185 max_burst_read = 1024; 186 break; 187 case PCIXM_STATUS_MAX_READ_2048: 188 max_burst_read = 2048; 189 break; 190 case PCIXM_STATUS_MAX_READ_4096: 191 max_burst_read = 4096; 192 break; 193 } 194 max_splits = 0; 195 switch (status & PCIXM_STATUS_MAX_SPLITS) { 196 case PCIXM_STATUS_MAX_SPLITS_1: 197 max_splits = 1; 198 break; 199 case PCIXM_STATUS_MAX_SPLITS_2: 200 max_splits = 2; 201 break; 202 case PCIXM_STATUS_MAX_SPLITS_3: 203 max_splits = 3; 204 break; 205 case PCIXM_STATUS_MAX_SPLITS_4: 206 max_splits = 4; 207 break; 208 case PCIXM_STATUS_MAX_SPLITS_8: 209 max_splits = 8; 210 break; 211 case PCIXM_STATUS_MAX_SPLITS_12: 212 max_splits = 12; 213 break; 214 case PCIXM_STATUS_MAX_SPLITS_16: 215 max_splits = 16; 216 break; 217 case PCIXM_STATUS_MAX_SPLITS_32: 218 max_splits = 32; 219 break; 220 } 221 printf("%s %d burst read, %d split transaction%s", comma ? "," : "", 222 max_burst_read, max_splits, max_splits == 1 ? "" : "s"); 223 } 224 225 static void 226 cap_ht(int fd, struct pci_conf *p, uint8_t ptr) 227 { 228 uint32_t reg; 229 uint16_t command; 230 231 command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2); 232 printf("HT "); 233 if ((command & 0xe000) == PCIM_HTCAP_SLAVE) 234 printf("slave"); 235 else if ((command & 0xe000) == PCIM_HTCAP_HOST) 236 printf("host"); 237 else 238 switch (command & PCIM_HTCMD_CAP_MASK) { 239 case PCIM_HTCAP_SWITCH: 240 printf("switch"); 241 break; 242 case PCIM_HTCAP_INTERRUPT: 243 printf("interrupt"); 244 break; 245 case PCIM_HTCAP_REVISION_ID: 246 printf("revision ID"); 247 break; 248 case PCIM_HTCAP_UNITID_CLUMPING: 249 printf("unit ID clumping"); 250 break; 251 case PCIM_HTCAP_EXT_CONFIG_SPACE: 252 printf("extended config space"); 253 break; 254 case PCIM_HTCAP_ADDRESS_MAPPING: 255 printf("address mapping"); 256 break; 257 case PCIM_HTCAP_MSI_MAPPING: 258 printf("MSI %saddress window %s at 0x", 259 command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "", 260 command & PCIM_HTCMD_MSI_ENABLE ? "enabled" : 261 "disabled"); 262 if (command & PCIM_HTCMD_MSI_FIXED) 263 printf("fee00000"); 264 else { 265 reg = read_config(fd, &p->pc_sel, 266 ptr + PCIR_HTMSI_ADDRESS_HI, 4); 267 if (reg != 0) 268 printf("%08x", reg); 269 reg = read_config(fd, &p->pc_sel, 270 ptr + PCIR_HTMSI_ADDRESS_LO, 4); 271 printf("%08x", reg); 272 } 273 break; 274 case PCIM_HTCAP_DIRECT_ROUTE: 275 printf("direct route"); 276 break; 277 case PCIM_HTCAP_VCSET: 278 printf("VC set"); 279 break; 280 case PCIM_HTCAP_RETRY_MODE: 281 printf("retry mode"); 282 break; 283 case PCIM_HTCAP_X86_ENCODING: 284 printf("X86 encoding"); 285 break; 286 case PCIM_HTCAP_GEN3: 287 printf("Gen3"); 288 break; 289 case PCIM_HTCAP_FLE: 290 printf("function-level extension"); 291 break; 292 case PCIM_HTCAP_PM: 293 printf("power management"); 294 break; 295 case PCIM_HTCAP_HIGH_NODE_COUNT: 296 printf("high node count"); 297 break; 298 default: 299 printf("unknown %02x", command); 300 break; 301 } 302 } 303 304 static void 305 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr) 306 { 307 uint8_t length; 308 309 length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1); 310 printf("vendor (length %d)", length); 311 if (p->pc_vendor == 0x8086) { 312 /* Intel */ 313 uint8_t version; 314 315 version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA, 316 1); 317 printf(" Intel cap %d version %d", version >> 4, version & 0xf); 318 if (version >> 4 == 1 && length == 12) { 319 /* Feature Detection */ 320 uint32_t fvec; 321 int comma; 322 323 comma = 0; 324 fvec = read_config(fd, &p->pc_sel, ptr + 325 PCIR_VENDOR_DATA + 5, 4); 326 printf("\n\t\t features:"); 327 if (fvec & (1 << 0)) { 328 printf(" AMT"); 329 comma = 1; 330 } 331 fvec = read_config(fd, &p->pc_sel, ptr + 332 PCIR_VENDOR_DATA + 1, 4); 333 if (fvec & (1 << 21)) { 334 printf("%s Quick Resume", comma ? "," : ""); 335 comma = 1; 336 } 337 if (fvec & (1 << 18)) { 338 printf("%s SATA RAID-5", comma ? "," : ""); 339 comma = 1; 340 } 341 if (fvec & (1 << 9)) { 342 printf("%s Mobile", comma ? "," : ""); 343 comma = 1; 344 } 345 if (fvec & (1 << 7)) { 346 printf("%s 6 PCI-e x1 slots", comma ? "," : ""); 347 comma = 1; 348 } else { 349 printf("%s 4 PCI-e x1 slots", comma ? "," : ""); 350 comma = 1; 351 } 352 if (fvec & (1 << 5)) { 353 printf("%s SATA RAID-0/1/10", comma ? "," : ""); 354 comma = 1; 355 } 356 if (fvec & (1 << 3)) 357 printf(", SATA AHCI"); 358 } 359 } 360 } 361 362 static void 363 cap_debug(int fd, struct pci_conf *p, uint8_t ptr) 364 { 365 uint16_t debug_port; 366 367 debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2); 368 printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port & 369 PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13)); 370 } 371 372 static void 373 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr) 374 { 375 uint32_t id; 376 uint16_t ssid, ssvid; 377 378 id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4); 379 ssid = id >> 16; 380 ssvid = id & 0xffff; 381 printf("PCI Bridge subvendor=0x%04x subdevice=0x%04x", ssvid, ssid); 382 } 383 384 #define MAX_PAYLOAD(field) (128 << (field)) 385 386 static const char * 387 link_speed_string(uint8_t speed) 388 { 389 390 switch (speed) { 391 case 1: 392 return ("2.5"); 393 case 2: 394 return ("5.0"); 395 case 3: 396 return ("8.0"); 397 case 4: 398 return ("16.0"); 399 case 5: 400 return ("32.0"); 401 case 6: 402 return ("64.0"); 403 default: 404 return ("undef"); 405 } 406 } 407 408 static const char * 409 max_read_string(u_int max_read) 410 { 411 412 switch (max_read) { 413 case 0x0: 414 return ("128"); 415 case 0x1: 416 return ("256"); 417 case 0x2: 418 return ("512"); 419 case 0x3: 420 return ("1024"); 421 case 0x4: 422 return ("2048"); 423 case 0x5: 424 return ("4096"); 425 default: 426 return ("undef"); 427 } 428 } 429 430 static const char * 431 aspm_string(uint8_t aspm) 432 { 433 434 switch (aspm) { 435 case 1: 436 return ("L0s"); 437 case 2: 438 return ("L1"); 439 case 3: 440 return ("L0s/L1"); 441 default: 442 return ("disabled"); 443 } 444 } 445 446 static int 447 slot_power(uint32_t cap) 448 { 449 int mwatts; 450 451 mwatts = (cap & PCIEM_SLOT_CAP_SPLV) >> 7; 452 switch (cap & PCIEM_SLOT_CAP_SPLS) { 453 case 0x0: 454 mwatts *= 1000; 455 break; 456 case 0x1: 457 mwatts *= 100; 458 break; 459 case 0x2: 460 mwatts *= 10; 461 break; 462 default: 463 break; 464 } 465 return (mwatts); 466 } 467 468 static void 469 cap_express(int fd, struct pci_conf *p, uint8_t ptr) 470 { 471 uint32_t cap; 472 uint16_t ctl, flags, sta; 473 unsigned int version; 474 475 flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2); 476 version = flags & PCIEM_FLAGS_VERSION; 477 printf("PCI-Express %u ", version); 478 switch (flags & PCIEM_FLAGS_TYPE) { 479 case PCIEM_TYPE_ENDPOINT: 480 printf("endpoint"); 481 break; 482 case PCIEM_TYPE_LEGACY_ENDPOINT: 483 printf("legacy endpoint"); 484 break; 485 case PCIEM_TYPE_ROOT_PORT: 486 printf("root port"); 487 break; 488 case PCIEM_TYPE_UPSTREAM_PORT: 489 printf("upstream port"); 490 break; 491 case PCIEM_TYPE_DOWNSTREAM_PORT: 492 printf("downstream port"); 493 break; 494 case PCIEM_TYPE_PCI_BRIDGE: 495 printf("PCI bridge"); 496 break; 497 case PCIEM_TYPE_PCIE_BRIDGE: 498 printf("PCI to PCIe bridge"); 499 break; 500 case PCIEM_TYPE_ROOT_INT_EP: 501 printf("root endpoint"); 502 break; 503 case PCIEM_TYPE_ROOT_EC: 504 printf("event collector"); 505 break; 506 default: 507 printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4); 508 break; 509 } 510 if (flags & PCIEM_FLAGS_IRQ) 511 printf(" MSI %d", (flags & PCIEM_FLAGS_IRQ) >> 9); 512 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4); 513 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2); 514 printf(" max data %d(%d)", 515 MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5), 516 MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD)); 517 if ((cap & PCIEM_CAP_FLR) != 0) 518 printf(" FLR"); 519 if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE) 520 printf(" RO"); 521 if (ctl & PCIEM_CTL_NOSNOOP_ENABLE) 522 printf(" NS"); 523 if (version >= 2) { 524 cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4); 525 if ((cap & PCIEM_CAP2_ARI) != 0) { 526 ctl = read_config(fd, &p->pc_sel, 527 ptr + PCIER_DEVICE_CTL2, 4); 528 printf(" ARI %s", 529 (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled"); 530 } 531 } 532 printf("\n max read %s", max_read_string((ctl & 533 PCIEM_CTL_MAX_READ_REQUEST) >> 12)); 534 cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4); 535 sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2); 536 if (cap == 0 && sta == 0) 537 return; 538 printf("\n "); 539 printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4, 540 (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4); 541 if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) { 542 printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ? 543 "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED), 544 link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED)); 545 } 546 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 547 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 548 printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC), 549 aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10)); 550 } 551 if ((cap & PCIEM_LINK_CAP_CLOCK_PM) != 0) { 552 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2); 553 printf(" ClockPM %s", (ctl & PCIEM_LINK_CTL_ECPM) ? 554 "enabled" : "disabled"); 555 } 556 if (!(flags & PCIEM_FLAGS_SLOT)) 557 return; 558 cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4); 559 sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_STA, 2); 560 ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CTL, 2); 561 printf("\n "); 562 printf(" slot %d", (cap & PCIEM_SLOT_CAP_PSN) >> 19); 563 printf(" power limit %d mW", slot_power(cap)); 564 if (cap & PCIEM_SLOT_CAP_HPC) 565 printf(" HotPlug(%s)", sta & PCIEM_SLOT_STA_PDS ? "present" : 566 "empty"); 567 if (cap & PCIEM_SLOT_CAP_HPS) 568 printf(" surprise"); 569 if (cap & PCIEM_SLOT_CAP_APB) 570 printf(" Attn Button"); 571 if (cap & PCIEM_SLOT_CAP_PCP) 572 printf(" PC(%s)", ctl & PCIEM_SLOT_CTL_PCC ? "off" : "on"); 573 if (cap & PCIEM_SLOT_CAP_MRLSP) 574 printf(" MRL(%s)", sta & PCIEM_SLOT_STA_MRLSS ? "open" : 575 "closed"); 576 if (cap & PCIEM_SLOT_CAP_EIP) 577 printf(" EI(%s)", sta & PCIEM_SLOT_STA_EIS ? "engaged" : 578 "disengaged"); 579 } 580 581 static void 582 cap_msix(int fd, struct pci_conf *p, uint8_t ptr) 583 { 584 uint32_t pba_offset, table_offset, val; 585 int msgnum, pba_bar, table_bar; 586 uint16_t ctrl; 587 588 ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2); 589 msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1; 590 591 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4); 592 table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 593 table_offset = val & ~PCIM_MSIX_BIR_MASK; 594 595 val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4); 596 pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK); 597 pba_offset = val & ~PCIM_MSIX_BIR_MASK; 598 599 printf("MSI-X supports %d message%s%s\n", msgnum, 600 (msgnum == 1) ? "" : "s", 601 (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : ""); 602 603 printf(" "); 604 printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]", 605 table_bar, table_offset, pba_bar, pba_offset); 606 } 607 608 static void 609 cap_sata(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused) 610 { 611 612 printf("SATA Index-Data Pair"); 613 } 614 615 static void 616 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr) 617 { 618 uint8_t cap; 619 620 cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1); 621 printf("PCI Advanced Features:%s%s", 622 cap & PCIM_PCIAFCAP_FLR ? " FLR" : "", 623 cap & PCIM_PCIAFCAP_TP ? " TP" : ""); 624 } 625 626 static const char * 627 ea_bei_to_name(int bei) 628 { 629 static const char *barstr[] = { 630 "BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5" 631 }; 632 static const char *vfbarstr[] = { 633 "VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5" 634 }; 635 636 if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5)) 637 return (barstr[bei - PCIM_EA_BEI_BAR_0]); 638 if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5)) 639 return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]); 640 641 switch (bei) { 642 case PCIM_EA_BEI_BRIDGE: 643 return "BRIDGE"; 644 case PCIM_EA_BEI_ENI: 645 return "ENI"; 646 case PCIM_EA_BEI_ROM: 647 return "ROM"; 648 case PCIM_EA_BEI_RESERVED: 649 default: 650 return "RSVD"; 651 } 652 } 653 654 static const char * 655 ea_prop_to_name(uint8_t prop) 656 { 657 658 switch (prop) { 659 case PCIM_EA_P_MEM: 660 return "Non-Prefetchable Memory"; 661 case PCIM_EA_P_MEM_PREFETCH: 662 return "Prefetchable Memory"; 663 case PCIM_EA_P_IO: 664 return "I/O Space"; 665 case PCIM_EA_P_VF_MEM_PREFETCH: 666 return "VF Prefetchable Memory"; 667 case PCIM_EA_P_VF_MEM: 668 return "VF Non-Prefetchable Memory"; 669 case PCIM_EA_P_BRIDGE_MEM: 670 return "Bridge Non-Prefetchable Memory"; 671 case PCIM_EA_P_BRIDGE_MEM_PREFETCH: 672 return "Bridge Prefetchable Memory"; 673 case PCIM_EA_P_BRIDGE_IO: 674 return "Bridge I/O Space"; 675 case PCIM_EA_P_MEM_RESERVED: 676 return "Reserved Memory"; 677 case PCIM_EA_P_IO_RESERVED: 678 return "Reserved I/O Space"; 679 case PCIM_EA_P_UNAVAILABLE: 680 return "Unavailable"; 681 default: 682 return "Reserved"; 683 } 684 } 685 686 static void 687 cap_ea(int fd, struct pci_conf *p, uint8_t ptr) 688 { 689 int num_ent; 690 int a, b; 691 uint32_t bei; 692 uint32_t val; 693 int ent_size; 694 uint32_t dw[4]; 695 uint32_t flags, flags_pp, flags_sp; 696 uint64_t base, max_offset; 697 uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr; 698 699 /* Determine the number of entries */ 700 num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2); 701 num_ent &= PCIM_EA_NUM_ENT_MASK; 702 703 printf("PCI Enhanced Allocation (%d entries)", num_ent); 704 705 /* Find the first entry to care of */ 706 ptr += PCIR_EA_FIRST_ENT; 707 708 /* Print BUS numbers for bridges */ 709 if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) { 710 val = read_config(fd, &p->pc_sel, ptr, 4); 711 712 fixed_sec_bus_nr = PCIM_EA_SEC_NR(val); 713 fixed_sub_bus_nr = PCIM_EA_SUB_NR(val); 714 715 printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]", 716 fixed_sec_bus_nr, fixed_sub_bus_nr); 717 ptr += 4; 718 } 719 720 for (a = 0; a < num_ent; a++) { 721 /* Read a number of dwords in the entry */ 722 val = read_config(fd, &p->pc_sel, ptr, 4); 723 ptr += 4; 724 ent_size = (val & PCIM_EA_ES); 725 726 for (b = 0; b < ent_size; b++) { 727 dw[b] = read_config(fd, &p->pc_sel, ptr, 4); 728 ptr += 4; 729 } 730 731 flags = val; 732 flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET; 733 flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET; 734 bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET; 735 736 base = dw[0] & PCIM_EA_FIELD_MASK; 737 max_offset = dw[1] | ~PCIM_EA_FIELD_MASK; 738 b = 2; 739 if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) { 740 base |= (uint64_t)dw[b] << 32UL; 741 b++; 742 } 743 if (((dw[1] & PCIM_EA_IS_64) != 0) 744 && (b < ent_size)) { 745 max_offset |= (uint64_t)dw[b] << 32UL; 746 b++; 747 } 748 749 printf("\n\t\t [%d] %s, %s, %s, base [0x%jx], size [0x%jx]" 750 "\n\t\t\tPrimary properties [0x%x] (%s)" 751 "\n\t\t\tSecondary properties [0x%x] (%s)", 752 bei, ea_bei_to_name(bei), 753 (flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"), 754 (flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"), 755 (uintmax_t)base, (uintmax_t)(max_offset + 1), 756 flags_pp, ea_prop_to_name(flags_pp), 757 flags_sp, ea_prop_to_name(flags_sp)); 758 } 759 } 760 761 void 762 list_caps(int fd, struct pci_conf *p, int level) 763 { 764 int express; 765 uint16_t sta; 766 uint8_t ptr, cap; 767 768 /* Are capabilities present for this device? */ 769 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 770 if (!(sta & PCIM_STATUS_CAPPRESENT)) 771 return; 772 773 cap_level = level; 774 775 switch (p->pc_hdr & PCIM_HDRTYPE) { 776 case PCIM_HDRTYPE_NORMAL: 777 case PCIM_HDRTYPE_BRIDGE: 778 ptr = PCIR_CAP_PTR; 779 break; 780 case PCIM_HDRTYPE_CARDBUS: 781 ptr = PCIR_CAP_PTR_2; 782 break; 783 default: 784 errx(1, "list_caps: bad header type"); 785 } 786 787 /* Walk the capability list. */ 788 express = 0; 789 ptr = read_config(fd, &p->pc_sel, ptr, 1); 790 while (ptr != 0 && ptr != 0xff) { 791 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 792 printf(" cap %02x[%02x] = ", cap, ptr); 793 switch (cap) { 794 case PCIY_PMG: 795 cap_power(fd, p, ptr); 796 break; 797 case PCIY_AGP: 798 cap_agp(fd, p, ptr); 799 break; 800 case PCIY_VPD: 801 cap_vpd(fd, p, ptr); 802 break; 803 case PCIY_MSI: 804 cap_msi(fd, p, ptr); 805 break; 806 case PCIY_PCIX: 807 cap_pcix(fd, p, ptr); 808 break; 809 case PCIY_HT: 810 cap_ht(fd, p, ptr); 811 break; 812 case PCIY_VENDOR: 813 cap_vendor(fd, p, ptr); 814 break; 815 case PCIY_DEBUG: 816 cap_debug(fd, p, ptr); 817 break; 818 case PCIY_SUBVENDOR: 819 cap_subvendor(fd, p, ptr); 820 break; 821 case PCIY_EXPRESS: 822 express = 1; 823 cap_express(fd, p, ptr); 824 break; 825 case PCIY_MSIX: 826 cap_msix(fd, p, ptr); 827 break; 828 case PCIY_SATA: 829 cap_sata(fd, p, ptr); 830 break; 831 case PCIY_PCIAF: 832 cap_pciaf(fd, p, ptr); 833 break; 834 case PCIY_EA: 835 cap_ea(fd, p, ptr); 836 break; 837 default: 838 printf("unknown"); 839 break; 840 } 841 printf("\n"); 842 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 843 } 844 845 if (express) 846 list_ecaps(fd, p); 847 } 848 849 /* From <sys/systm.h>. */ 850 static __inline uint32_t 851 bitcount32(uint32_t x) 852 { 853 854 x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1); 855 x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2); 856 x = (x + (x >> 4)) & 0x0f0f0f0f; 857 x = (x + (x >> 8)); 858 x = (x + (x >> 16)) & 0x000000ff; 859 return (x); 860 } 861 862 static void 863 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 864 { 865 uint32_t sta, mask; 866 867 printf("AER %d", ver); 868 if (ver < 1) { 869 printf("\n"); 870 return; 871 } 872 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4); 873 mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4); 874 printf(" %d fatal", bitcount32(sta & mask)); 875 printf(" %d non-fatal", bitcount32(sta & ~mask)); 876 sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4); 877 printf(" %d corrected\n", bitcount32(sta)); 878 } 879 880 static void 881 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 882 { 883 uint32_t cap1; 884 885 printf("VC %d", ver); 886 if (ver < 1) { 887 printf("\n"); 888 return; 889 } 890 cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4); 891 printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT); 892 if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0) 893 printf(" lowpri VC0-VC%d", 894 (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4); 895 printf("\n"); 896 } 897 898 static void 899 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 900 { 901 uint32_t high, low; 902 903 printf("Serial %d", ver); 904 if (ver < 1) { 905 printf("\n"); 906 return; 907 } 908 low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4); 909 high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4); 910 printf(" %08x%08x\n", high, low); 911 } 912 913 static void 914 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 915 { 916 uint32_t val, hdr; 917 uint16_t nextptr, len; 918 int i; 919 920 val = read_config(fd, &p->pc_sel, ptr, 4); 921 nextptr = PCI_EXTCAP_NEXTPTR(val); 922 hdr = read_config(fd, &p->pc_sel, ptr + PCIR_VSEC_HEADER, 4); 923 len = PCIR_VSEC_LENGTH(hdr); 924 if (len == 0) { 925 if (nextptr == 0) 926 nextptr = 0x1000; 927 len = nextptr - ptr; 928 } 929 930 printf("Vendor [%d] ID %04x Rev %d Length %d\n", ver, 931 PCIR_VSEC_ID(hdr), PCIR_VSEC_REV(hdr), len); 932 if ((ver < 1) || (cap_level <= 1)) 933 return; 934 for (i = 0; i < len; i += 4) { 935 val = read_config(fd, &p->pc_sel, ptr + i, 4); 936 if ((i % 16) == 0) 937 printf(" "); 938 printf("%02x %02x %02x %02x", val & 0xff, (val >> 8) & 0xff, 939 (val >> 16) & 0xff, (val >> 24) & 0xff); 940 if ((((i + 4) % 16) == 0 ) || ((i + 4) >= len)) 941 printf("\n"); 942 else 943 printf(" "); 944 } 945 } 946 947 static void 948 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 949 { 950 uint32_t val; 951 952 printf("PCIe Sec %d", ver); 953 if (ver < 1) { 954 printf("\n"); 955 return; 956 } 957 val = read_config(fd, &p->pc_sel, ptr + 8, 4); 958 printf(" lane errors %#x\n", val); 959 } 960 961 static const char * 962 check_enabled(int value) 963 { 964 965 return (value ? "enabled" : "disabled"); 966 } 967 968 static void 969 ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 970 { 971 const char *comma, *enabled; 972 uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did; 973 uint32_t page_caps, page_size, page_shift, size; 974 int i; 975 976 printf("SR-IOV %d ", ver); 977 978 iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2); 979 printf("IOV %s, Memory Space %s, ARI %s\n", 980 check_enabled(iov_ctl & PCIM_SRIOV_VF_EN), 981 check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE), 982 check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN)); 983 984 total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2); 985 num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2); 986 printf(" "); 987 printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs); 988 989 vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2); 990 vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2); 991 printf(" "); 992 printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset, 993 vf_stride); 994 995 vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2); 996 printf(" VF Device ID 0x%04x\n", vf_did); 997 998 page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4); 999 page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4); 1000 printf(" "); 1001 printf("Page Sizes: "); 1002 comma = ""; 1003 while (page_caps != 0) { 1004 page_shift = ffs(page_caps) - 1; 1005 1006 if (page_caps & page_size) 1007 enabled = " (enabled)"; 1008 else 1009 enabled = ""; 1010 1011 size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT)); 1012 printf("%s%d%s", comma, size, enabled); 1013 comma = ", "; 1014 1015 page_caps &= ~(1 << page_shift); 1016 } 1017 printf("\n"); 1018 1019 for (i = 0; i <= PCIR_MAX_BAR_0; i++) 1020 print_bar(fd, p, "iov bar ", ptr + PCIR_SRIOV_BAR(i)); 1021 } 1022 1023 static const char * 1024 check_avail_and_state(u_int cap, u_int capbit, u_int ctl, u_int ctlbit) 1025 { 1026 1027 if (cap & capbit) 1028 return (ctl & ctlbit ? "enabled" : "disabled"); 1029 else 1030 return "unavailable"; 1031 } 1032 1033 static void 1034 ecap_acs(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver) 1035 { 1036 uint16_t acs_cap, acs_ctl; 1037 static const char *const acc[] = { "access enabled", "blocking enabled", 1038 "redirect enabled", "reserved" }; 1039 1040 printf("ACS %d ", ver); 1041 if (ver != 1) { 1042 printf("\n"); 1043 return; 1044 } 1045 1046 #define CHECK_AVAIL_STATE(bit) \ 1047 check_avail_and_state(acs_cap, bit, acs_ctl, bit##_ENABLE) 1048 1049 acs_cap = read_config(fd, &p->pc_sel, ptr + PCIR_ACS_CAP, 2); 1050 acs_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_ACS_CTL, 2); 1051 printf("Source Validation %s, Translation Blocking %s\n", 1052 CHECK_AVAIL_STATE(PCIM_ACS_SOURCE_VALIDATION), 1053 CHECK_AVAIL_STATE(PCIM_ACS_TRANSLATION_BLOCKING)); 1054 1055 printf(" "); 1056 printf("P2P Req Redirect %s, P2P Cmpl Redirect %s\n", 1057 CHECK_AVAIL_STATE(PCIM_ACS_P2P_REQ_REDIRECT), 1058 CHECK_AVAIL_STATE(PCIM_ACS_P2P_CMP_REDIRECT)); 1059 printf(" "); 1060 printf("P2P Upstream Forwarding %s, P2P Egress Control %s\n", 1061 CHECK_AVAIL_STATE(PCIM_ACS_P2P_UPSTREAM_FORWARDING), 1062 CHECK_AVAIL_STATE(PCIM_ACS_P2P_EGRESS_CTL)); 1063 printf(" "); 1064 printf("P2P Direct Translated %s, Enhanced Capability %s\n", 1065 CHECK_AVAIL_STATE(PCIM_ACS_P2P_DIRECT_TRANSLATED), 1066 acs_ctl & PCIM_ACS_ENHANCED_CAP ? "available" : "unavailable"); 1067 #undef CHECK_AVAIL_STATE 1068 1069 if (acs_cap & PCIM_ACS_ENHANCED_CAP) { 1070 printf(" "); 1071 printf("I/O Req Blocking %s, Unclaimed Req Redirect Control %s\n", 1072 check_enabled(acs_ctl & PCIM_ACS_IO_REQ_BLOCKING_ENABLE), 1073 check_enabled(acs_ctl & PCIM_ACS_UNCLAIMED_REQ_REDIRECT_CTL)); 1074 printf(" "); 1075 printf("DSP BAR %s, USP BAR %s\n", 1076 acc[(acs_cap & PCIM_ACS_DSP_MEM_TGT_ACC_CTL) >> 8], 1077 acc[(acs_cap & PCIM_ACS_USP_MEM_TGT_ACC_CTL) >> 10]); 1078 } 1079 } 1080 1081 static struct { 1082 uint16_t id; 1083 const char *name; 1084 } ecap_names[] = { 1085 { PCIZ_AER, "AER" }, 1086 { PCIZ_VC, "Virtual Channel" }, 1087 { PCIZ_SERNUM, "Device Serial Number" }, 1088 { PCIZ_PWRBDGT, "Power Budgeting" }, 1089 { PCIZ_RCLINK_DCL, "Root Complex Link Declaration" }, 1090 { PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" }, 1091 { PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" }, 1092 { PCIZ_MFVC, "MFVC" }, 1093 { PCIZ_VC2, "Virtual Channel 2" }, 1094 { PCIZ_RCRB, "RCRB" }, 1095 { PCIZ_CAC, "Configuration Access Correction" }, 1096 { PCIZ_ACS, "ACS" }, 1097 { PCIZ_ARI, "ARI" }, 1098 { PCIZ_ATS, "ATS" }, 1099 { PCIZ_SRIOV, "SRIOV" }, 1100 { PCIZ_MRIOV, "MRIOV" }, 1101 { PCIZ_MULTICAST, "Multicast" }, 1102 { PCIZ_PAGE_REQ, "Page Page Request" }, 1103 { PCIZ_AMD, "AMD proprietary "}, 1104 { PCIZ_RESIZE_BAR, "Resizable BAR" }, 1105 { PCIZ_DPA, "DPA" }, 1106 { PCIZ_TPH_REQ, "TPH Requester" }, 1107 { PCIZ_LTR, "LTR" }, 1108 { PCIZ_SEC_PCIE, "Secondary PCI Express" }, 1109 { PCIZ_PMUX, "Protocol Multiplexing" }, 1110 { PCIZ_PASID, "Process Address Space ID" }, 1111 { PCIZ_LN_REQ, "LN Requester" }, 1112 { PCIZ_DPC, "Downstream Port Containment" }, 1113 { PCIZ_L1PM, "L1 PM Substates" }, 1114 { PCIZ_PTM, "Precision Time Measurement" }, 1115 { PCIZ_M_PCIE, "PCIe over M-PHY" }, 1116 { PCIZ_FRS, "FRS Queuing" }, 1117 { PCIZ_RTR, "Readiness Time Reporting" }, 1118 { PCIZ_DVSEC, "Designated Vendor-Specific" }, 1119 { PCIZ_VF_REBAR, "VF Resizable BAR" }, 1120 { PCIZ_DLNK, "Data Link Feature" }, 1121 { PCIZ_16GT, "Physical Layer 16.0 GT/s" }, 1122 { PCIZ_LMR, "Lane Margining at Receiver" }, 1123 { PCIZ_HIER_ID, "Hierarchy ID" }, 1124 { PCIZ_NPEM, "Native PCIe Enclosure Management" }, 1125 { PCIZ_PL32, "Physical Layer 32.0 GT/s" }, 1126 { PCIZ_AP, "Alternate Protocol" }, 1127 { PCIZ_SFI, "System Firmware Intermediary" }, 1128 { 0, NULL } 1129 }; 1130 1131 static void 1132 list_ecaps(int fd, struct pci_conf *p) 1133 { 1134 const char *name; 1135 uint32_t ecap; 1136 uint16_t ptr; 1137 int i; 1138 1139 ptr = PCIR_EXTCAP; 1140 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1141 if (ecap == 0xffffffff || ecap == 0) 1142 return; 1143 for (;;) { 1144 printf(" ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr); 1145 switch (PCI_EXTCAP_ID(ecap)) { 1146 case PCIZ_AER: 1147 ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1148 break; 1149 case PCIZ_VC: 1150 ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1151 break; 1152 case PCIZ_SERNUM: 1153 ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1154 break; 1155 case PCIZ_VENDOR: 1156 ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1157 break; 1158 case PCIZ_SEC_PCIE: 1159 ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1160 break; 1161 case PCIZ_SRIOV: 1162 ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1163 break; 1164 case PCIZ_ACS: 1165 ecap_acs(fd, p, ptr, PCI_EXTCAP_VER(ecap)); 1166 break; 1167 default: 1168 name = "unknown"; 1169 for (i = 0; ecap_names[i].name != NULL; i++) 1170 if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) { 1171 name = ecap_names[i].name; 1172 break; 1173 } 1174 printf("%s %d\n", name, PCI_EXTCAP_VER(ecap)); 1175 break; 1176 } 1177 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1178 if (ptr == 0) 1179 break; 1180 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1181 } 1182 } 1183 1184 /* Find offset of a specific capability. Returns 0 on failure. */ 1185 uint8_t 1186 pci_find_cap(int fd, struct pci_conf *p, uint8_t id) 1187 { 1188 uint16_t sta; 1189 uint8_t ptr, cap; 1190 1191 /* Are capabilities present for this device? */ 1192 sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2); 1193 if (!(sta & PCIM_STATUS_CAPPRESENT)) 1194 return (0); 1195 1196 switch (p->pc_hdr & PCIM_HDRTYPE) { 1197 case PCIM_HDRTYPE_NORMAL: 1198 case PCIM_HDRTYPE_BRIDGE: 1199 ptr = PCIR_CAP_PTR; 1200 break; 1201 case PCIM_HDRTYPE_CARDBUS: 1202 ptr = PCIR_CAP_PTR_2; 1203 break; 1204 default: 1205 return (0); 1206 } 1207 1208 ptr = read_config(fd, &p->pc_sel, ptr, 1); 1209 while (ptr != 0 && ptr != 0xff) { 1210 cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1); 1211 if (cap == id) 1212 return (ptr); 1213 ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1); 1214 } 1215 return (0); 1216 } 1217 1218 /* Find offset of a specific extended capability. Returns 0 on failure. */ 1219 uint16_t 1220 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id) 1221 { 1222 uint32_t ecap; 1223 uint16_t ptr; 1224 1225 ptr = PCIR_EXTCAP; 1226 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1227 if (ecap == 0xffffffff || ecap == 0) 1228 return (0); 1229 for (;;) { 1230 if (PCI_EXTCAP_ID(ecap) == id) 1231 return (ptr); 1232 ptr = PCI_EXTCAP_NEXTPTR(ecap); 1233 if (ptr == 0) 1234 break; 1235 ecap = read_config(fd, &p->pc_sel, ptr, 4); 1236 } 1237 return (0); 1238 } 1239