xref: /freebsd/usr.sbin/pciconf/cap.c (revision 20bd59416dcacbd2b776fe49dfa193900f303287)
1 /*-
2  * SPDX-License-Identifier: BSD-3-Clause
3  *
4  * Copyright (c) 2007 Yahoo!, Inc.
5  * All rights reserved.
6  * Written by: John Baldwin <jhb@FreeBSD.org>
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. Neither the name of the author nor the names of any co-contributors
17  *    may be used to endorse or promote products derived from this software
18  *    without specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
21  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
24  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30  * SUCH DAMAGE.
31  */
32 
33 #ifndef lint
34 static const char rcsid[] =
35   "$FreeBSD$";
36 #endif /* not lint */
37 
38 #include <sys/types.h>
39 
40 #include <err.h>
41 #include <stdio.h>
42 #include <strings.h>
43 #include <sys/agpio.h>
44 #include <sys/pciio.h>
45 
46 #include <dev/agp/agpreg.h>
47 #include <dev/pci/pcireg.h>
48 
49 #include "pciconf.h"
50 
51 static void	list_ecaps(int fd, struct pci_conf *p);
52 
53 static void
54 cap_power(int fd, struct pci_conf *p, uint8_t ptr)
55 {
56 	uint16_t cap, status;
57 
58 	cap = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_CAP, 2);
59 	status = read_config(fd, &p->pc_sel, ptr + PCIR_POWER_STATUS, 2);
60 	printf("powerspec %d  supports D0%s%s D3  current D%d",
61 	    cap & PCIM_PCAP_SPEC,
62 	    cap & PCIM_PCAP_D1SUPP ? " D1" : "",
63 	    cap & PCIM_PCAP_D2SUPP ? " D2" : "",
64 	    status & PCIM_PSTAT_DMASK);
65 }
66 
67 static void
68 cap_agp(int fd, struct pci_conf *p, uint8_t ptr)
69 {
70 	uint32_t status, command;
71 
72 	status = read_config(fd, &p->pc_sel, ptr + AGP_STATUS, 4);
73 	command = read_config(fd, &p->pc_sel, ptr + AGP_CAPID, 4);
74 	printf("AGP ");
75 	if (AGP_MODE_GET_MODE_3(status)) {
76 		printf("v3 ");
77 		if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_8x)
78 			printf("8x ");
79 		if (AGP_MODE_GET_RATE(status) & AGP_MODE_V3_RATE_4x)
80 			printf("4x ");
81 	} else {
82 		if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_4x)
83 			printf("4x ");
84 		if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_2x)
85 			printf("2x ");
86 		if (AGP_MODE_GET_RATE(status) & AGP_MODE_V2_RATE_1x)
87 			printf("1x ");
88 	}
89 	if (AGP_MODE_GET_SBA(status))
90 		printf("SBA ");
91 	if (AGP_MODE_GET_AGP(command)) {
92 		printf("enabled at ");
93 		if (AGP_MODE_GET_MODE_3(command)) {
94 			printf("v3 ");
95 			switch (AGP_MODE_GET_RATE(command)) {
96 			case AGP_MODE_V3_RATE_8x:
97 				printf("8x ");
98 				break;
99 			case AGP_MODE_V3_RATE_4x:
100 				printf("4x ");
101 				break;
102 			}
103 		} else
104 			switch (AGP_MODE_GET_RATE(command)) {
105 			case AGP_MODE_V2_RATE_4x:
106 				printf("4x ");
107 				break;
108 			case AGP_MODE_V2_RATE_2x:
109 				printf("2x ");
110 				break;
111 			case AGP_MODE_V2_RATE_1x:
112 				printf("1x ");
113 				break;
114 			}
115 		if (AGP_MODE_GET_SBA(command))
116 			printf("SBA ");
117 	} else
118 		printf("disabled");
119 }
120 
121 static void
122 cap_vpd(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused)
123 {
124 
125 	printf("VPD");
126 }
127 
128 static void
129 cap_msi(int fd, struct pci_conf *p, uint8_t ptr)
130 {
131 	uint16_t ctrl;
132 	int msgnum;
133 
134 	ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSI_CTRL, 2);
135 	msgnum = 1 << ((ctrl & PCIM_MSICTRL_MMC_MASK) >> 1);
136 	printf("MSI supports %d message%s%s%s ", msgnum,
137 	    (msgnum == 1) ? "" : "s",
138 	    (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
139 	    (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks" : "");
140 	if (ctrl & PCIM_MSICTRL_MSI_ENABLE) {
141 		msgnum = 1 << ((ctrl & PCIM_MSICTRL_MME_MASK) >> 4);
142 		printf("enabled with %d message%s", msgnum,
143 		    (msgnum == 1) ? "" : "s");
144 	}
145 }
146 
147 static void
148 cap_pcix(int fd, struct pci_conf *p, uint8_t ptr)
149 {
150 	uint32_t status;
151 	int comma, max_splits, max_burst_read;
152 
153 	status = read_config(fd, &p->pc_sel, ptr + PCIXR_STATUS, 4);
154 	printf("PCI-X ");
155 	if (status & PCIXM_STATUS_64BIT)
156 		printf("64-bit ");
157 	if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
158 		printf("bridge ");
159 	if ((p->pc_hdr & PCIM_HDRTYPE) != 1 || (status & (PCIXM_STATUS_133CAP |
160 	    PCIXM_STATUS_266CAP | PCIXM_STATUS_533CAP)) != 0)
161 		printf("supports");
162 	comma = 0;
163 	if (status & PCIXM_STATUS_133CAP) {
164 		printf(" 133MHz");
165 		comma = 1;
166 	}
167 	if (status & PCIXM_STATUS_266CAP) {
168 		printf("%s 266MHz", comma ? "," : "");
169 		comma = 1;
170 	}
171 	if (status & PCIXM_STATUS_533CAP) {
172 		printf("%s 533MHz", comma ? "," : "");
173 		comma = 1;
174 	}
175 	if ((p->pc_hdr & PCIM_HDRTYPE) == 1)
176 		return;
177 	max_burst_read = 0;
178 	switch (status & PCIXM_STATUS_MAX_READ) {
179 	case PCIXM_STATUS_MAX_READ_512:
180 		max_burst_read = 512;
181 		break;
182 	case PCIXM_STATUS_MAX_READ_1024:
183 		max_burst_read = 1024;
184 		break;
185 	case PCIXM_STATUS_MAX_READ_2048:
186 		max_burst_read = 2048;
187 		break;
188 	case PCIXM_STATUS_MAX_READ_4096:
189 		max_burst_read = 4096;
190 		break;
191 	}
192 	max_splits = 0;
193 	switch (status & PCIXM_STATUS_MAX_SPLITS) {
194 	case PCIXM_STATUS_MAX_SPLITS_1:
195 		max_splits = 1;
196 		break;
197 	case PCIXM_STATUS_MAX_SPLITS_2:
198 		max_splits = 2;
199 		break;
200 	case PCIXM_STATUS_MAX_SPLITS_3:
201 		max_splits = 3;
202 		break;
203 	case PCIXM_STATUS_MAX_SPLITS_4:
204 		max_splits = 4;
205 		break;
206 	case PCIXM_STATUS_MAX_SPLITS_8:
207 		max_splits = 8;
208 		break;
209 	case PCIXM_STATUS_MAX_SPLITS_12:
210 		max_splits = 12;
211 		break;
212 	case PCIXM_STATUS_MAX_SPLITS_16:
213 		max_splits = 16;
214 		break;
215 	case PCIXM_STATUS_MAX_SPLITS_32:
216 		max_splits = 32;
217 		break;
218 	}
219 	printf("%s %d burst read, %d split transaction%s", comma ? "," : "",
220 	    max_burst_read, max_splits, max_splits == 1 ? "" : "s");
221 }
222 
223 static void
224 cap_ht(int fd, struct pci_conf *p, uint8_t ptr)
225 {
226 	uint32_t reg;
227 	uint16_t command;
228 
229 	command = read_config(fd, &p->pc_sel, ptr + PCIR_HT_COMMAND, 2);
230 	printf("HT ");
231 	if ((command & 0xe000) == PCIM_HTCAP_SLAVE)
232 		printf("slave");
233 	else if ((command & 0xe000) == PCIM_HTCAP_HOST)
234 		printf("host");
235 	else
236 		switch (command & PCIM_HTCMD_CAP_MASK) {
237 		case PCIM_HTCAP_SWITCH:
238 			printf("switch");
239 			break;
240 		case PCIM_HTCAP_INTERRUPT:
241 			printf("interrupt");
242 			break;
243 		case PCIM_HTCAP_REVISION_ID:
244 			printf("revision ID");
245 			break;
246 		case PCIM_HTCAP_UNITID_CLUMPING:
247 			printf("unit ID clumping");
248 			break;
249 		case PCIM_HTCAP_EXT_CONFIG_SPACE:
250 			printf("extended config space");
251 			break;
252 		case PCIM_HTCAP_ADDRESS_MAPPING:
253 			printf("address mapping");
254 			break;
255 		case PCIM_HTCAP_MSI_MAPPING:
256 			printf("MSI %saddress window %s at 0x",
257 			    command & PCIM_HTCMD_MSI_FIXED ? "fixed " : "",
258 			    command & PCIM_HTCMD_MSI_ENABLE ? "enabled" :
259 			    "disabled");
260 			if (command & PCIM_HTCMD_MSI_FIXED)
261 				printf("fee00000");
262 			else {
263 				reg = read_config(fd, &p->pc_sel,
264 				    ptr + PCIR_HTMSI_ADDRESS_HI, 4);
265 				if (reg != 0)
266 					printf("%08x", reg);
267 				reg = read_config(fd, &p->pc_sel,
268 				    ptr + PCIR_HTMSI_ADDRESS_LO, 4);
269 				printf("%08x", reg);
270 			}
271 			break;
272 		case PCIM_HTCAP_DIRECT_ROUTE:
273 			printf("direct route");
274 			break;
275 		case PCIM_HTCAP_VCSET:
276 			printf("VC set");
277 			break;
278 		case PCIM_HTCAP_RETRY_MODE:
279 			printf("retry mode");
280 			break;
281 		case PCIM_HTCAP_X86_ENCODING:
282 			printf("X86 encoding");
283 			break;
284 		case PCIM_HTCAP_GEN3:
285 			printf("Gen3");
286 			break;
287 		case PCIM_HTCAP_FLE:
288 			printf("function-level extension");
289 			break;
290 		case PCIM_HTCAP_PM:
291 			printf("power management");
292 			break;
293 		case PCIM_HTCAP_HIGH_NODE_COUNT:
294 			printf("high node count");
295 			break;
296 		default:
297 			printf("unknown %02x", command);
298 			break;
299 		}
300 }
301 
302 static void
303 cap_vendor(int fd, struct pci_conf *p, uint8_t ptr)
304 {
305 	uint8_t length;
306 
307 	length = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_LENGTH, 1);
308 	printf("vendor (length %d)", length);
309 	if (p->pc_vendor == 0x8086) {
310 		/* Intel */
311 		uint8_t version;
312 
313 		version = read_config(fd, &p->pc_sel, ptr + PCIR_VENDOR_DATA,
314 		    1);
315 		printf(" Intel cap %d version %d", version >> 4, version & 0xf);
316 		if (version >> 4 == 1 && length == 12) {
317 			/* Feature Detection */
318 			uint32_t fvec;
319 			int comma;
320 
321 			comma = 0;
322 			fvec = read_config(fd, &p->pc_sel, ptr +
323 			    PCIR_VENDOR_DATA + 5, 4);
324 			printf("\n\t\t features:");
325 			if (fvec & (1 << 0)) {
326 				printf(" AMT");
327 				comma = 1;
328 			}
329 			fvec = read_config(fd, &p->pc_sel, ptr +
330 			    PCIR_VENDOR_DATA + 1, 4);
331 			if (fvec & (1 << 21)) {
332 				printf("%s Quick Resume", comma ? "," : "");
333 				comma = 1;
334 			}
335 			if (fvec & (1 << 18)) {
336 				printf("%s SATA RAID-5", comma ? "," : "");
337 				comma = 1;
338 			}
339 			if (fvec & (1 << 9)) {
340 				printf("%s Mobile", comma ? "," : "");
341 				comma = 1;
342 			}
343 			if (fvec & (1 << 7)) {
344 				printf("%s 6 PCI-e x1 slots", comma ? "," : "");
345 				comma = 1;
346 			} else {
347 				printf("%s 4 PCI-e x1 slots", comma ? "," : "");
348 				comma = 1;
349 			}
350 			if (fvec & (1 << 5)) {
351 				printf("%s SATA RAID-0/1/10", comma ? "," : "");
352 				comma = 1;
353 			}
354 			if (fvec & (1 << 3))
355 				printf(", SATA AHCI");
356 		}
357 	}
358 }
359 
360 static void
361 cap_debug(int fd, struct pci_conf *p, uint8_t ptr)
362 {
363 	uint16_t debug_port;
364 
365 	debug_port = read_config(fd, &p->pc_sel, ptr + PCIR_DEBUG_PORT, 2);
366 	printf("EHCI Debug Port at offset 0x%x in map 0x%x", debug_port &
367 	    PCIM_DEBUG_PORT_OFFSET, PCIR_BAR(debug_port >> 13));
368 }
369 
370 static void
371 cap_subvendor(int fd, struct pci_conf *p, uint8_t ptr)
372 {
373 	uint32_t id;
374 
375 	id = read_config(fd, &p->pc_sel, ptr + PCIR_SUBVENDCAP_ID, 4);
376 	printf("PCI Bridge card=0x%08x", id);
377 }
378 
379 #define	MAX_PAYLOAD(field)		(128 << (field))
380 
381 static const char *
382 link_speed_string(uint8_t speed)
383 {
384 
385 	switch (speed) {
386 	case 1:
387 		return ("2.5");
388 	case 2:
389 		return ("5.0");
390 	case 3:
391 		return ("8.0");
392 	case 4:
393 		return ("16.0");
394 	default:
395 		return ("undef");
396 	}
397 }
398 
399 static const char *
400 aspm_string(uint8_t aspm)
401 {
402 
403 	switch (aspm) {
404 	case 1:
405 		return ("L0s");
406 	case 2:
407 		return ("L1");
408 	case 3:
409 		return ("L0s/L1");
410 	default:
411 		return ("disabled");
412 	}
413 }
414 
415 static int
416 slot_power(uint32_t cap)
417 {
418 	int mwatts;
419 
420 	mwatts = (cap & PCIEM_SLOT_CAP_SPLV) >> 7;
421 	switch (cap & PCIEM_SLOT_CAP_SPLS) {
422 	case 0x0:
423 		mwatts *= 1000;
424 		break;
425 	case 0x1:
426 		mwatts *= 100;
427 		break;
428 	case 0x2:
429 		mwatts *= 10;
430 		break;
431 	default:
432 		break;
433 	}
434 	return (mwatts);
435 }
436 
437 static void
438 cap_express(int fd, struct pci_conf *p, uint8_t ptr)
439 {
440 	uint32_t cap;
441 	uint16_t ctl, flags, sta;
442 	unsigned int version;
443 
444 	flags = read_config(fd, &p->pc_sel, ptr + PCIER_FLAGS, 2);
445 	version = flags & PCIEM_FLAGS_VERSION;
446 	printf("PCI-Express %u ", version);
447 	switch (flags & PCIEM_FLAGS_TYPE) {
448 	case PCIEM_TYPE_ENDPOINT:
449 		printf("endpoint");
450 		break;
451 	case PCIEM_TYPE_LEGACY_ENDPOINT:
452 		printf("legacy endpoint");
453 		break;
454 	case PCIEM_TYPE_ROOT_PORT:
455 		printf("root port");
456 		break;
457 	case PCIEM_TYPE_UPSTREAM_PORT:
458 		printf("upstream port");
459 		break;
460 	case PCIEM_TYPE_DOWNSTREAM_PORT:
461 		printf("downstream port");
462 		break;
463 	case PCIEM_TYPE_PCI_BRIDGE:
464 		printf("PCI bridge");
465 		break;
466 	case PCIEM_TYPE_PCIE_BRIDGE:
467 		printf("PCI to PCIe bridge");
468 		break;
469 	case PCIEM_TYPE_ROOT_INT_EP:
470 		printf("root endpoint");
471 		break;
472 	case PCIEM_TYPE_ROOT_EC:
473 		printf("event collector");
474 		break;
475 	default:
476 		printf("type %d", (flags & PCIEM_FLAGS_TYPE) >> 4);
477 		break;
478 	}
479 	if (flags & PCIEM_FLAGS_IRQ)
480 		printf(" MSI %d", (flags & PCIEM_FLAGS_IRQ) >> 9);
481 	cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP, 4);
482 	ctl = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CTL, 2);
483 	printf(" max data %d(%d)",
484 	    MAX_PAYLOAD((ctl & PCIEM_CTL_MAX_PAYLOAD) >> 5),
485 	    MAX_PAYLOAD(cap & PCIEM_CAP_MAX_PAYLOAD));
486 	if ((cap & PCIEM_CAP_FLR) != 0)
487 		printf(" FLR");
488 	if (ctl & PCIEM_CTL_RELAXED_ORD_ENABLE)
489 		printf(" RO");
490 	if (ctl & PCIEM_CTL_NOSNOOP_ENABLE)
491 		printf(" NS");
492 	if (version >= 2) {
493 		cap = read_config(fd, &p->pc_sel, ptr + PCIER_DEVICE_CAP2, 4);
494 		if ((cap & PCIEM_CAP2_ARI) != 0) {
495 			ctl = read_config(fd, &p->pc_sel,
496 			    ptr + PCIER_DEVICE_CTL2, 4);
497 			printf(" ARI %s",
498 			    (ctl & PCIEM_CTL2_ARI) ? "enabled" : "disabled");
499 		}
500 	}
501 	cap = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CAP, 4);
502 	sta = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_STA, 2);
503 	if (cap == 0 && sta == 0)
504 		return;
505 	printf("\n                ");
506 	printf(" link x%d(x%d)", (sta & PCIEM_LINK_STA_WIDTH) >> 4,
507 	    (cap & PCIEM_LINK_CAP_MAX_WIDTH) >> 4);
508 	if ((cap & PCIEM_LINK_CAP_MAX_WIDTH) != 0) {
509 		printf(" speed %s(%s)", (sta & PCIEM_LINK_STA_WIDTH) == 0 ?
510 		    "0.0" : link_speed_string(sta & PCIEM_LINK_STA_SPEED),
511 	    	    link_speed_string(cap & PCIEM_LINK_CAP_MAX_SPEED));
512 	}
513 	if ((cap & PCIEM_LINK_CAP_ASPM) != 0) {
514 		ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2);
515 		printf(" ASPM %s(%s)", aspm_string(ctl & PCIEM_LINK_CTL_ASPMC),
516 		    aspm_string((cap & PCIEM_LINK_CAP_ASPM) >> 10));
517 	}
518 	if ((cap & PCIEM_LINK_CAP_CLOCK_PM) != 0) {
519 		ctl = read_config(fd, &p->pc_sel, ptr + PCIER_LINK_CTL, 2);
520 		printf(" ClockPM %s", (ctl & PCIEM_LINK_CTL_ECPM) ?
521 		    "enabled" : "disabled");
522 	}
523 	if (!(flags & PCIEM_FLAGS_SLOT))
524 		return;
525 	cap = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CAP, 4);
526 	sta = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_STA, 2);
527 	ctl = read_config(fd, &p->pc_sel, ptr + PCIER_SLOT_CTL, 2);
528 	printf("\n                ");
529 	printf(" slot %d", (cap & PCIEM_SLOT_CAP_PSN) >> 19);
530 	printf(" power limit %d mW", slot_power(cap));
531 	if (cap & PCIEM_SLOT_CAP_HPC)
532 		printf(" HotPlug(%s)", sta & PCIEM_SLOT_STA_PDS ? "present" :
533 		    "empty");
534 	if (cap & PCIEM_SLOT_CAP_HPS)
535 		printf(" surprise");
536 	if (cap & PCIEM_SLOT_CAP_APB)
537 		printf(" Attn Button");
538 	if (cap & PCIEM_SLOT_CAP_PCP)
539 		printf(" PC(%s)", ctl & PCIEM_SLOT_CTL_PCC ? "off" : "on");
540 	if (cap & PCIEM_SLOT_CAP_MRLSP)
541 		printf(" MRL(%s)", sta & PCIEM_SLOT_STA_MRLSS ? "open" :
542 		    "closed");
543 	if (cap & PCIEM_SLOT_CAP_EIP)
544 		printf(" EI(%s)", sta & PCIEM_SLOT_STA_EIS ? "engaged" :
545 		    "disengaged");
546 }
547 
548 static void
549 cap_msix(int fd, struct pci_conf *p, uint8_t ptr)
550 {
551 	uint32_t pba_offset, table_offset, val;
552 	int msgnum, pba_bar, table_bar;
553 	uint16_t ctrl;
554 
555 	ctrl = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_CTRL, 2);
556 	msgnum = (ctrl & PCIM_MSIXCTRL_TABLE_SIZE) + 1;
557 
558 	val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_TABLE, 4);
559 	table_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
560 	table_offset = val & ~PCIM_MSIX_BIR_MASK;
561 
562 	val = read_config(fd, &p->pc_sel, ptr + PCIR_MSIX_PBA, 4);
563 	pba_bar = PCIR_BAR(val & PCIM_MSIX_BIR_MASK);
564 	pba_offset = val & ~PCIM_MSIX_BIR_MASK;
565 
566 	printf("MSI-X supports %d message%s%s\n", msgnum,
567 	    (msgnum == 1) ? "" : "s",
568 	    (ctrl & PCIM_MSIXCTRL_MSIX_ENABLE) ? ", enabled" : "");
569 
570 	printf("                 ");
571 	printf("Table in map 0x%x[0x%x], PBA in map 0x%x[0x%x]",
572 	    table_bar, table_offset, pba_bar, pba_offset);
573 }
574 
575 static void
576 cap_sata(int fd __unused, struct pci_conf *p __unused, uint8_t ptr __unused)
577 {
578 
579 	printf("SATA Index-Data Pair");
580 }
581 
582 static void
583 cap_pciaf(int fd, struct pci_conf *p, uint8_t ptr)
584 {
585 	uint8_t cap;
586 
587 	cap = read_config(fd, &p->pc_sel, ptr + PCIR_PCIAF_CAP, 1);
588 	printf("PCI Advanced Features:%s%s",
589 	    cap & PCIM_PCIAFCAP_FLR ? " FLR" : "",
590 	    cap & PCIM_PCIAFCAP_TP  ? " TP"  : "");
591 }
592 
593 static const char *
594 ea_bei_to_name(int bei)
595 {
596 	static const char *barstr[] = {
597 		"BAR0", "BAR1", "BAR2", "BAR3", "BAR4", "BAR5"
598 	};
599 	static const char *vfbarstr[] = {
600 		"VFBAR0", "VFBAR1", "VFBAR2", "VFBAR3", "VFBAR4", "VFBAR5"
601 	};
602 
603 	if ((bei >= PCIM_EA_BEI_BAR_0) && (bei <= PCIM_EA_BEI_BAR_5))
604 		return (barstr[bei - PCIM_EA_BEI_BAR_0]);
605 	if ((bei >= PCIM_EA_BEI_VF_BAR_0) && (bei <= PCIM_EA_BEI_VF_BAR_5))
606 		return (vfbarstr[bei - PCIM_EA_BEI_VF_BAR_0]);
607 
608 	switch (bei) {
609 	case PCIM_EA_BEI_BRIDGE:
610 		return "BRIDGE";
611 	case PCIM_EA_BEI_ENI:
612 		return "ENI";
613 	case PCIM_EA_BEI_ROM:
614 		return "ROM";
615 	case PCIM_EA_BEI_RESERVED:
616 	default:
617 		return "RSVD";
618 	}
619 }
620 
621 static const char *
622 ea_prop_to_name(uint8_t prop)
623 {
624 
625 	switch (prop) {
626 	case PCIM_EA_P_MEM:
627 		return "Non-Prefetchable Memory";
628 	case PCIM_EA_P_MEM_PREFETCH:
629 		return "Prefetchable Memory";
630 	case PCIM_EA_P_IO:
631 		return "I/O Space";
632 	case PCIM_EA_P_VF_MEM_PREFETCH:
633 		return "VF Prefetchable Memory";
634 	case PCIM_EA_P_VF_MEM:
635 		return "VF Non-Prefetchable Memory";
636 	case PCIM_EA_P_BRIDGE_MEM:
637 		return "Bridge Non-Prefetchable Memory";
638 	case PCIM_EA_P_BRIDGE_MEM_PREFETCH:
639 		return "Bridge Prefetchable Memory";
640 	case PCIM_EA_P_BRIDGE_IO:
641 		return "Bridge I/O Space";
642 	case PCIM_EA_P_MEM_RESERVED:
643 		return "Reserved Memory";
644 	case PCIM_EA_P_IO_RESERVED:
645 		return "Reserved I/O Space";
646 	case PCIM_EA_P_UNAVAILABLE:
647 		return "Unavailable";
648 	default:
649 		return "Reserved";
650 	}
651 }
652 
653 static void
654 cap_ea(int fd, struct pci_conf *p, uint8_t ptr)
655 {
656 	int num_ent;
657 	int a, b;
658 	uint32_t bei;
659 	uint32_t val;
660 	int ent_size;
661 	uint32_t dw[4];
662 	uint32_t flags, flags_pp, flags_sp;
663 	uint64_t base, max_offset;
664 	uint8_t fixed_sub_bus_nr, fixed_sec_bus_nr;
665 
666 	/* Determine the number of entries */
667 	num_ent = read_config(fd, &p->pc_sel, ptr + PCIR_EA_NUM_ENT, 2);
668 	num_ent &= PCIM_EA_NUM_ENT_MASK;
669 
670 	printf("PCI Enhanced Allocation (%d entries)", num_ent);
671 
672 	/* Find the first entry to care of */
673 	ptr += PCIR_EA_FIRST_ENT;
674 
675 	/* Print BUS numbers for bridges */
676 	if ((p->pc_hdr & PCIM_HDRTYPE) == PCIM_HDRTYPE_BRIDGE) {
677 		val = read_config(fd, &p->pc_sel, ptr, 4);
678 
679 		fixed_sec_bus_nr = PCIM_EA_SEC_NR(val);
680 		fixed_sub_bus_nr = PCIM_EA_SUB_NR(val);
681 
682 		printf("\n\t\t BRIDGE, sec bus [%d], sub bus [%d]",
683 		    fixed_sec_bus_nr, fixed_sub_bus_nr);
684 		ptr += 4;
685 	}
686 
687 	for (a = 0; a < num_ent; a++) {
688 		/* Read a number of dwords in the entry */
689 		val = read_config(fd, &p->pc_sel, ptr, 4);
690 		ptr += 4;
691 		ent_size = (val & PCIM_EA_ES);
692 
693 		for (b = 0; b < ent_size; b++) {
694 			dw[b] = read_config(fd, &p->pc_sel, ptr, 4);
695 			ptr += 4;
696 		}
697 
698 		flags = val;
699 		flags_pp = (flags & PCIM_EA_PP) >> PCIM_EA_PP_OFFSET;
700 		flags_sp = (flags & PCIM_EA_SP) >> PCIM_EA_SP_OFFSET;
701 		bei = (PCIM_EA_BEI & val) >> PCIM_EA_BEI_OFFSET;
702 
703 		base = dw[0] & PCIM_EA_FIELD_MASK;
704 		max_offset = dw[1] | ~PCIM_EA_FIELD_MASK;
705 		b = 2;
706 		if (((dw[0] & PCIM_EA_IS_64) != 0) && (b < ent_size)) {
707 			base |= (uint64_t)dw[b] << 32UL;
708 			b++;
709 		}
710 		if (((dw[1] & PCIM_EA_IS_64) != 0)
711 			&& (b < ent_size)) {
712 			max_offset |= (uint64_t)dw[b] << 32UL;
713 			b++;
714 		}
715 
716 		printf("\n\t\t [%d] %s, %s, %s, base [0x%jx], size [0x%jx]"
717 		    "\n\t\t\tPrimary properties [0x%x] (%s)"
718 		    "\n\t\t\tSecondary properties [0x%x] (%s)",
719 		    bei, ea_bei_to_name(bei),
720 		    (flags & PCIM_EA_ENABLE ? "Enabled" : "Disabled"),
721 		    (flags & PCIM_EA_WRITABLE ? "Writable" : "Read-only"),
722 		    (uintmax_t)base, (uintmax_t)(max_offset + 1),
723 		    flags_pp, ea_prop_to_name(flags_pp),
724 		    flags_sp, ea_prop_to_name(flags_sp));
725 	}
726 }
727 
728 void
729 list_caps(int fd, struct pci_conf *p)
730 {
731 	int express;
732 	uint16_t sta;
733 	uint8_t ptr, cap;
734 
735 	/* Are capabilities present for this device? */
736 	sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
737 	if (!(sta & PCIM_STATUS_CAPPRESENT))
738 		return;
739 
740 	switch (p->pc_hdr & PCIM_HDRTYPE) {
741 	case PCIM_HDRTYPE_NORMAL:
742 	case PCIM_HDRTYPE_BRIDGE:
743 		ptr = PCIR_CAP_PTR;
744 		break;
745 	case PCIM_HDRTYPE_CARDBUS:
746 		ptr = PCIR_CAP_PTR_2;
747 		break;
748 	default:
749 		errx(1, "list_caps: bad header type");
750 	}
751 
752 	/* Walk the capability list. */
753 	express = 0;
754 	ptr = read_config(fd, &p->pc_sel, ptr, 1);
755 	while (ptr != 0 && ptr != 0xff) {
756 		cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
757 		printf("    cap %02x[%02x] = ", cap, ptr);
758 		switch (cap) {
759 		case PCIY_PMG:
760 			cap_power(fd, p, ptr);
761 			break;
762 		case PCIY_AGP:
763 			cap_agp(fd, p, ptr);
764 			break;
765 		case PCIY_VPD:
766 			cap_vpd(fd, p, ptr);
767 			break;
768 		case PCIY_MSI:
769 			cap_msi(fd, p, ptr);
770 			break;
771 		case PCIY_PCIX:
772 			cap_pcix(fd, p, ptr);
773 			break;
774 		case PCIY_HT:
775 			cap_ht(fd, p, ptr);
776 			break;
777 		case PCIY_VENDOR:
778 			cap_vendor(fd, p, ptr);
779 			break;
780 		case PCIY_DEBUG:
781 			cap_debug(fd, p, ptr);
782 			break;
783 		case PCIY_SUBVENDOR:
784 			cap_subvendor(fd, p, ptr);
785 			break;
786 		case PCIY_EXPRESS:
787 			express = 1;
788 			cap_express(fd, p, ptr);
789 			break;
790 		case PCIY_MSIX:
791 			cap_msix(fd, p, ptr);
792 			break;
793 		case PCIY_SATA:
794 			cap_sata(fd, p, ptr);
795 			break;
796 		case PCIY_PCIAF:
797 			cap_pciaf(fd, p, ptr);
798 			break;
799 		case PCIY_EA:
800 			cap_ea(fd, p, ptr);
801 			break;
802 		default:
803 			printf("unknown");
804 			break;
805 		}
806 		printf("\n");
807 		ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
808 	}
809 
810 	if (express)
811 		list_ecaps(fd, p);
812 }
813 
814 /* From <sys/systm.h>. */
815 static __inline uint32_t
816 bitcount32(uint32_t x)
817 {
818 
819 	x = (x & 0x55555555) + ((x & 0xaaaaaaaa) >> 1);
820 	x = (x & 0x33333333) + ((x & 0xcccccccc) >> 2);
821 	x = (x + (x >> 4)) & 0x0f0f0f0f;
822 	x = (x + (x >> 8));
823 	x = (x + (x >> 16)) & 0x000000ff;
824 	return (x);
825 }
826 
827 static void
828 ecap_aer(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
829 {
830 	uint32_t sta, mask;
831 
832 	printf("AER %d", ver);
833 	if (ver < 1)
834 		return;
835 	sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_STATUS, 4);
836 	mask = read_config(fd, &p->pc_sel, ptr + PCIR_AER_UC_SEVERITY, 4);
837 	printf(" %d fatal", bitcount32(sta & mask));
838 	printf(" %d non-fatal", bitcount32(sta & ~mask));
839 	sta = read_config(fd, &p->pc_sel, ptr + PCIR_AER_COR_STATUS, 4);
840 	printf(" %d corrected\n", bitcount32(sta));
841 }
842 
843 static void
844 ecap_vc(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
845 {
846 	uint32_t cap1;
847 
848 	printf("VC %d", ver);
849 	if (ver < 1)
850 		return;
851 	cap1 = read_config(fd, &p->pc_sel, ptr + PCIR_VC_CAP1, 4);
852 	printf(" max VC%d", cap1 & PCIM_VC_CAP1_EXT_COUNT);
853 	if ((cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) != 0)
854 		printf(" lowpri VC0-VC%d",
855 		    (cap1 & PCIM_VC_CAP1_LOWPRI_EXT_COUNT) >> 4);
856 	printf("\n");
857 }
858 
859 static void
860 ecap_sernum(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
861 {
862 	uint32_t high, low;
863 
864 	printf("Serial %d", ver);
865 	if (ver < 1)
866 		return;
867 	low = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_LOW, 4);
868 	high = read_config(fd, &p->pc_sel, ptr + PCIR_SERIAL_HIGH, 4);
869 	printf(" %08x%08x\n", high, low);
870 }
871 
872 static void
873 ecap_vendor(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
874 {
875 	uint32_t val;
876 
877 	printf("Vendor %d", ver);
878 	if (ver < 1)
879 		return;
880 	val = read_config(fd, &p->pc_sel, ptr + 4, 4);
881 	printf(" ID %d\n", val & 0xffff);
882 }
883 
884 static void
885 ecap_sec_pcie(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
886 {
887 	uint32_t val;
888 
889 	printf("PCIe Sec %d", ver);
890 	if (ver < 1)
891 		return;
892 	val = read_config(fd, &p->pc_sel, ptr + 8, 4);
893 	printf(" lane errors %#x\n", val);
894 }
895 
896 static const char *
897 check_enabled(int value)
898 {
899 
900 	return (value ? "enabled" : "disabled");
901 }
902 
903 static void
904 ecap_sriov(int fd, struct pci_conf *p, uint16_t ptr, uint8_t ver)
905 {
906 	const char *comma, *enabled;
907 	uint16_t iov_ctl, total_vfs, num_vfs, vf_offset, vf_stride, vf_did;
908 	uint32_t page_caps, page_size, page_shift, size;
909 	int i;
910 
911 	printf("SR-IOV %d ", ver);
912 
913 	iov_ctl = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_CTL, 2);
914 	printf("IOV %s, Memory Space %s, ARI %s\n",
915 	    check_enabled(iov_ctl & PCIM_SRIOV_VF_EN),
916 	    check_enabled(iov_ctl & PCIM_SRIOV_VF_MSE),
917 	    check_enabled(iov_ctl & PCIM_SRIOV_ARI_EN));
918 
919 	total_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_TOTAL_VFS, 2);
920 	num_vfs = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_NUM_VFS, 2);
921 	printf("                     ");
922 	printf("%d VFs configured out of %d supported\n", num_vfs, total_vfs);
923 
924 	vf_offset = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_OFF, 2);
925 	vf_stride = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_STRIDE, 2);
926 	printf("                     ");
927 	printf("First VF RID Offset 0x%04x, VF RID Stride 0x%04x\n", vf_offset,
928 	    vf_stride);
929 
930 	vf_did = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_VF_DID, 2);
931 	printf("                     VF Device ID 0x%04x\n", vf_did);
932 
933 	page_caps = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_CAP, 4);
934 	page_size = read_config(fd, &p->pc_sel, ptr + PCIR_SRIOV_PAGE_SIZE, 4);
935 	printf("                     ");
936 	printf("Page Sizes: ");
937 	comma = "";
938 	while (page_caps != 0) {
939 		page_shift = ffs(page_caps) - 1;
940 
941 		if (page_caps & page_size)
942 			enabled = " (enabled)";
943 		else
944 			enabled = "";
945 
946 		size = (1 << (page_shift + PCI_SRIOV_BASE_PAGE_SHIFT));
947 		printf("%s%d%s", comma, size, enabled);
948 		comma = ", ";
949 
950 		page_caps &= ~(1 << page_shift);
951 	}
952 	printf("\n");
953 
954 	for (i = 0; i <= PCIR_MAX_BAR_0; i++)
955 		print_bar(fd, p, "iov bar  ", ptr + PCIR_SRIOV_BAR(i));
956 }
957 
958 static struct {
959 	uint16_t id;
960 	const char *name;
961 } ecap_names[] = {
962 	{ PCIZ_PWRBDGT, "Power Budgeting" },
963 	{ PCIZ_RCLINK_DCL, "Root Complex Link Declaration" },
964 	{ PCIZ_RCLINK_CTL, "Root Complex Internal Link Control" },
965 	{ PCIZ_RCEC_ASSOC, "Root Complex Event Collector ASsociation" },
966 	{ PCIZ_MFVC, "MFVC" },
967 	{ PCIZ_RCRB, "RCRB" },
968 	{ PCIZ_ACS, "ACS" },
969 	{ PCIZ_ARI, "ARI" },
970 	{ PCIZ_ATS, "ATS" },
971 	{ PCIZ_MULTICAST, "Multicast" },
972 	{ PCIZ_RESIZE_BAR, "Resizable BAR" },
973 	{ PCIZ_DPA, "DPA" },
974 	{ PCIZ_TPH_REQ, "TPH Requester" },
975 	{ PCIZ_LTR, "LTR" },
976 	{ 0, NULL }
977 };
978 
979 static void
980 list_ecaps(int fd, struct pci_conf *p)
981 {
982 	const char *name;
983 	uint32_t ecap;
984 	uint16_t ptr;
985 	int i;
986 
987 	ptr = PCIR_EXTCAP;
988 	ecap = read_config(fd, &p->pc_sel, ptr, 4);
989 	if (ecap == 0xffffffff || ecap == 0)
990 		return;
991 	for (;;) {
992 		printf("    ecap %04x[%03x] = ", PCI_EXTCAP_ID(ecap), ptr);
993 		switch (PCI_EXTCAP_ID(ecap)) {
994 		case PCIZ_AER:
995 			ecap_aer(fd, p, ptr, PCI_EXTCAP_VER(ecap));
996 			break;
997 		case PCIZ_VC:
998 			ecap_vc(fd, p, ptr, PCI_EXTCAP_VER(ecap));
999 			break;
1000 		case PCIZ_SERNUM:
1001 			ecap_sernum(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1002 			break;
1003 		case PCIZ_VENDOR:
1004 			ecap_vendor(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1005 			break;
1006 		case PCIZ_SEC_PCIE:
1007 			ecap_sec_pcie(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1008 			break;
1009 		case PCIZ_SRIOV:
1010 			ecap_sriov(fd, p, ptr, PCI_EXTCAP_VER(ecap));
1011 			break;
1012 		default:
1013 			name = "unknown";
1014 			for (i = 0; ecap_names[i].name != NULL; i++)
1015 				if (ecap_names[i].id == PCI_EXTCAP_ID(ecap)) {
1016 					name = ecap_names[i].name;
1017 					break;
1018 				}
1019 			printf("%s %d\n", name, PCI_EXTCAP_VER(ecap));
1020 			break;
1021 		}
1022 		ptr = PCI_EXTCAP_NEXTPTR(ecap);
1023 		if (ptr == 0)
1024 			break;
1025 		ecap = read_config(fd, &p->pc_sel, ptr, 4);
1026 	}
1027 }
1028 
1029 /* Find offset of a specific capability.  Returns 0 on failure. */
1030 uint8_t
1031 pci_find_cap(int fd, struct pci_conf *p, uint8_t id)
1032 {
1033 	uint16_t sta;
1034 	uint8_t ptr, cap;
1035 
1036 	/* Are capabilities present for this device? */
1037 	sta = read_config(fd, &p->pc_sel, PCIR_STATUS, 2);
1038 	if (!(sta & PCIM_STATUS_CAPPRESENT))
1039 		return (0);
1040 
1041 	switch (p->pc_hdr & PCIM_HDRTYPE) {
1042 	case PCIM_HDRTYPE_NORMAL:
1043 	case PCIM_HDRTYPE_BRIDGE:
1044 		ptr = PCIR_CAP_PTR;
1045 		break;
1046 	case PCIM_HDRTYPE_CARDBUS:
1047 		ptr = PCIR_CAP_PTR_2;
1048 		break;
1049 	default:
1050 		return (0);
1051 	}
1052 
1053 	ptr = read_config(fd, &p->pc_sel, ptr, 1);
1054 	while (ptr != 0 && ptr != 0xff) {
1055 		cap = read_config(fd, &p->pc_sel, ptr + PCICAP_ID, 1);
1056 		if (cap == id)
1057 			return (ptr);
1058 		ptr = read_config(fd, &p->pc_sel, ptr + PCICAP_NEXTPTR, 1);
1059 	}
1060 	return (0);
1061 }
1062 
1063 /* Find offset of a specific extended capability.  Returns 0 on failure. */
1064 uint16_t
1065 pcie_find_cap(int fd, struct pci_conf *p, uint16_t id)
1066 {
1067 	uint32_t ecap;
1068 	uint16_t ptr;
1069 
1070 	ptr = PCIR_EXTCAP;
1071 	ecap = read_config(fd, &p->pc_sel, ptr, 4);
1072 	if (ecap == 0xffffffff || ecap == 0)
1073 		return (0);
1074 	for (;;) {
1075 		if (PCI_EXTCAP_ID(ecap) == id)
1076 			return (ptr);
1077 		ptr = PCI_EXTCAP_NEXTPTR(ecap);
1078 		if (ptr == 0)
1079 			break;
1080 		ecap = read_config(fd, &p->pc_sel, ptr, 4);
1081 	}
1082 	return (0);
1083 }
1084