1.\" 2.\" Copyright (C) 2008-2009 Semihalf, Michal Hajduk and Bartlomiej Sieka 3.\" All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 14.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17.\" ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24.\" SUCH DAMAGE. 25.\" 26.\" $FreeBSD$ 27.\" 28.Dd May 22, 2019 29.Dt I2C 8 30.Os 31.Sh NAME 32.Nm i2c 33.Nd test I2C bus and slave devices 34.Sh SYNOPSIS 35.Nm 36.Cm -a Ar address 37.Op Fl f Ar device 38.Op Fl d Ar r|w 39.Op Fl w Ar 0|8|16|16LE|16BE 40.Op Fl o Ar offset 41.Op Fl c Ar count 42.Op Fl m Ar tr|ss|rs|no 43.Op Fl b 44.Op Fl v 45.Nm 46.Cm -s 47.Op Fl f Ar device 48.Op Fl n Ar skip_addr 49.Op Fl v 50.Nm 51.Cm -r 52.Op Fl f Ar device 53.Op Fl v 54.Sh DESCRIPTION 55The 56.Nm 57utility can be used to perform raw data transfers (read or write) with devices 58on the I2C bus. 59It can also scan the bus for available devices and reset the I2C controller. 60.Pp 61The options are as follows: 62.Bl -tag -width ".Fl d Ar direction" 63.It Fl a Ar address 647-bit address on the I2C device to operate on (hex). 65.It Fl b 66binary mode - when performing a read operation, the data read from the device 67is output in binary format on stdout. 68.It Fl c Ar count 69number of bytes to transfer (decimal). 70.It Fl d Ar r|w 71transfer direction: r - read, w - write. 72Data to be written is read from stdin as binary bytes. 73.It Fl f Ar device 74I2C bus to use (default is /dev/iic0). 75.It Fl m Ar tr|ss|rs|no 76addressing mode, i.e., I2C bus operations performed after the offset for the 77transfer has been written to the device and before the actual read/write 78operation. 79.Bl -tag -compact -offset indent 80.It Va tr 81complete-transfer 82.It Va ss 83stop then start 84.It Va rs 85repeated start 86.It Va no 87none 88.El 89Some I2C bus hardware does not provide control over the individual start, 90repeat-start, and stop operations. 91Such hardware can only perform a complete transfer of the offset and the 92data as a single operation. 93The 94.Va tr 95mode creates control structures describing the transfer and submits them 96to the driver as a single complete transaction. 97This mode works on all types of I2C hardware. 98.It Fl n Ar skip_addr 99address(es) to be skipped during bus scan. 100One or more addresses ([0x]xx) or ranges of addresses 101([0x]xx-[0x]xx or [0x]xx..[0x]xx) separated by commas or colons. 102.It Fl o Ar offset 103offset within the device for data transfer (hex). 104The default is zero. 105Use 106.Dq -w 0 107to disable writing of the offset to the slave. 108.It Fl r 109reset the controller. 110.It Fl s 111scan the bus for devices. 112.It Fl v 113be verbose. 114.It Fl w Ar 0|8|16|16LE|16BE 115device offset width (in bits). 116This is used to determine how to pass 117.Ar offset 118specified with 119.Fl o 120to the slave. 121Zero means that the offset is ignored and not passed to the slave at all. 122The endianess defaults to little-endian. 123.El 124.Sh EXAMPLES 125.Bl -bullet 126.It 127Scan the default bus (/dev/iic0) for devices: 128.Pp 129i2c -s 130.It 131Scan the default bus (/dev/iic0) for devices and skip addresses 1320x45 to 0x47 (inclusive) and 0x56. 133.Pp 134i2c -s -n 0x56,45-47 135.It 136Read 8 bytes of data from device at address 0x56 (e.g., an EEPROM): 137.Pp 138i2c -a 0x56 -d r -c 8 139.It 140Write 16 bytes of data from file data.bin to device 0x56 at offset 0x10: 141.Pp 142i2c -a 0x56 -d w -c 16 -o 0x10 -b < data.bin 143.It 144Copy 4 bytes between two EEPROMs (0x56 on /dev/iic1 to 0x57 on /dev/iic0): 145.Pp 146i2c -a 0x56 -f /dev/iic1 -d r -c 0x4 -b | i2c -a 0x57 -f /dev/iic0 -d w -c 4 -b 147.It 148Reset the controller: 149.Pp 150i2c -f /dev/iic1 -r 151.El 152.Sh WARNING 153Many systems store critical low-level information in I2C memories, and 154may contain other I2C devices, such as temperature or voltage sensors. 155Reading these can disturb the firmware's operation and writing to them 156can "brick" the hardware. 157.Sh SEE ALSO 158.Xr iic 4 , 159.Xr iicbus 4 160.Xr smbus 4 161.Sh HISTORY 162The 163.Nm 164utility appeared in 165.Fx 8.0 . 166.Sh AUTHORS 167.An -nosplit 168The 169.Nm 170utility and this manual page were written by 171.An Bartlomiej Sieka Aq Mt tur@semihalf.com 172and 173.An Michal Hajduk Aq Mt mih@semihalf.com . 174