1.\" 2.\" Copyright (C) 2008-2009 Semihalf, Michal Hajduk and Bartlomiej Sieka 3.\" All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 14.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17.\" ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24.\" SUCH DAMAGE. 25.\" 26.\" $FreeBSD$ 27.\" 28.Dd January 23, 2009 29.Dt I2C 8 30.Os 31.Sh NAME 32.Nm i2c 33.Nd test I2C bus and slave devices 34.Sh SYNOPSIS 35.Nm 36.Cm -a Ar address 37.Op Fl f Ar device 38.Op Fl d Ar r|w 39.Op Fl w Ar 0|8|16 40.Op Fl o Ar offset 41.Op Fl c Ar count 42.Op Fl m Ar ss|rs|no 43.Op Fl b 44.Op Fl v 45.Nm 46.Cm -s 47.Op Fl f Ar device 48.Op Fl n Ar skip_addr 49.Op Fl v 50.Nm 51.Cm -r 52.Op Fl f Ar device 53.Op Fl v 54.Sh DESCRIPTION 55The 56.Nm 57utility can be used to perform raw data transfers (read or write) with devices 58on the I2C bus. It can also scan the bus for available devices and reset the 59I2C controller. 60.Pp 61The options are as follows: 62.Bl -tag -width ".Fl d Ar direction" 63.It Fl a Ar address 647-bit address on the I2C device to operate on (hex). 65.It Fl b 66binary mode - when performing a read operation, the data read from the device 67is output in binary format on stdout; when doing a write, the binary data to 68be written to the device is read from stdin. 69.It Fl c Ar count 70number of bytes to transfer (dec). 71.It Fl d Ar r|w 72transfer direction: r - read, w - write. 73.It Fl f Ar device 74I2C bus to use (default is /dev/iic0). 75.It Fl m Ar ss|rs|no 76addressing mode, i.e., I2C bus operations performed after the offset for the 77transfer has been written to the device and before the actual read/write 78operation. rs - repeated start; ss - stop start; no - none. 79.It Fl n Ar skip_addr 80skip address - address(es) to be skipped during bus scan. 81The are two ways to specify addresses to ignore: by range 'a..b' or 82using selected addresses 'a:b:c'. This option is available only when "-s" is 83used. 84.It Fl o Ar offset 85offset within the device for data transfer (hex). 86.It Fl r 87reset the controller. 88.It Fl s 89scan the bus for devices. 90.It Fl v 91be verbose 92.It Fl w Ar 0|8|16 93device addressing width (in bits). 94.El 95.Sh WARNINGS 96Great care must be taken when manipulating slave I2C devices with the 97.Nm 98utility. Often times important configuration data for the system is kept in 99non-volatile but write enabled memories located on the I2C bus, for example 100Ethernet hardware addresses, RAM module parameters (SPD), processor reset 101configuration word etc. 102.Pp 103It is very easy to render the whole system unusable when such configuration 104data is deleted or altered, so use the 105.Dq -d w 106(write) command only if you know exactly what you are doing. 107.Pp 108Also avoid ungraceful interrupting of an ongoing transaction on the I2C bus, 109as it can lead to potentially dangerous effects. Consider the following 110scenario: when the host CPU is reset (for whatever reason) in the middle of a 111started I2C transaction, the I2C slave device could be left in write mode 112waiting for data or offset to arrive. When the CPU reinitializes itself and 113talks to this I2C slave device again, the commands and other control info it 114sends are treated by the slave device as data or offset it was waiting for, 115and there's great potential for corruption if such a write is performed. 116.Sh EXAMPLES 117.Pp 118.Bl -bullet 119.It 120Scan the default bus (/dev/iic0) for devices: 121.Pp 122i2c -s 123.It 124Scan the default bus (/dev/iic0) for devices and skip addresses 0x56 and 1250x45. 126.Pp 127i2c -s -n 0x56:0x45 128.It 129Scan the default bus (/dev/iic0) for devices and skip address range 1300x34 to 0x56. 131.Pp 132i2c -s -n 0x34..0x56 133.It 134Read 8 bytes of data from device at address 0x56 (e.g., an EEPROM): 135.Pp 136i2c -a 0x56 -d r -c 8 137.It 138Write 16 bytes of data from file data.bin to device 0x56 at offset 0x10: 139.Pp 140i2c -a 0x56 -d w -c 16 -o 0x10 -b < data.bin 141.It 142Copy 4 bytes between two EEPROMs (0x56 on /dev/iic1 to 0x57 on /dev/iic0): 143.Pp 144i2c -a 0x56 -f /dev/iic1 -d r -c 0x4 -b | i2c -a 0x57 -f /dev/iic0 -d w -c 4 -b 145.It 146Reset the controller: 147.Pp 148i2c -f /dev/iic1 -r 149.El 150.Sh SEE ALSO 151.Xr iic 4 , 152.Xr iicbus 4 153.Sh HISTORY 154The 155.Nm 156utility appeared in 157.Fx 8.0 . 158.Sh AUTHORS 159.An -nosplit 160The 161.Nm 162utility and this manual page were written by 163.An Bartlomiej Sieka 164.Aq tur@semihalf.com 165and 166.An Michal Hajduk 167.Aq mih@semihalf.com . 168