1.\" 2.\" Copyright (C) 2008-2009 Semihalf, Michal Hajduk and Bartlomiej Sieka 3.\" All rights reserved. 4.\" 5.\" Redistribution and use in source and binary forms, with or without 6.\" modification, are permitted provided that the following conditions 7.\" are met: 8.\" 1. Redistributions of source code must retain the above copyright 9.\" notice, this list of conditions and the following disclaimer. 10.\" 2. Redistributions in binary form must reproduce the above copyright 11.\" notice, this list of conditions and the following disclaimer in the 12.\" documentation and/or other materials provided with the distribution. 13.\" 14.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17.\" ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 18.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24.\" SUCH DAMAGE. 25.\" 26.\" $FreeBSD$ 27.\" 28 29.Dd Jan 23, 2009 30.Dt I2C 8 31.Os 32.Sh NAME 33.Nm i2c 34.Nd test I2C bus and slave devices 35.Sh SYNOPSIS 36.Nm 37.Cm -a Ar address 38.Op Fl f Ar device 39.Op Fl d Ar r|w 40.Op Fl w Ar 0|8|16 41.Op Fl o Ar offset 42.Op Fl c Ar count 43.Op Fl m Ar ss|rs|no 44.Op Fl b 45.Op Fl v 46.Nm 47.Cm -s 48.Op Fl f Ar device 49.Op Fl n Ar skip_addr 50.Op Fl v 51.Nm 52.Cm -r 53.Op Fl f Ar device 54.Op Fl v 55.Sh DESCRIPTION 56The 57.Nm 58utility can be used to perform raw data transfers (read or write) with devices 59on the I2C bus. It can also scan the bus for available devices and reset the 60I2C controller. 61.Pp 62The options are as follows: 63.Bl -tag -width ".Fl d Ar direction" 64.It Fl a Ar address 657-bit address on the I2C device to operate on (hex). 66.It Fl b 67binary mode - when performing a read operation, the data read from the device 68is output in binary format on stdout; when doing a write, the binary data to 69be written to the device is read from stdin. 70.It Fl c Ar count 71number of bytes to transfer (dec). 72.It Fl d Ar r|w 73transfer direction: r - read, w - write. 74.It Fl f Ar device 75I2C bus to use (default is /dev/iic0). 76.It Fl m Ar ss|rs|no 77addressing mode, i.e., I2C bus operations performed after the offset for the 78transfer has been written to the device and before the actual read/write 79operation. rs - repeated start; ss - stop start; no - none. 80.It Fl n Ar skip_addr 81skip address - address(es) to be skipped during bus scan. 82The are two ways to specify addresses to ignore: by range 'a..b' or 83using selected addresses 'a:b:c'. This option is available only when "-s" is 84used. 85.It Fl o Ar offset 86offset within the device for data transfer (hex). 87.It Fl r 88reset the controller. 89.It Fl s 90scan the bus for devices. 91.It Fl v 92be verbose 93.It Fl w Ar 0|8|16 94device addressing width (in bits). 95.El 96.Sh WARNINGS 97Great care must be taken when manipulating slave I2C devices with the 98.Nm 99utility. Often times important configuration data for the system is kept in 100non-volatile but write enabled memories located on the I2C bus, for example 101Ethernet hardware addresses, RAM module parameters (SPD), processor reset 102configuration word etc. 103.Pp 104It is very easy to render the whole system unusable when such configuration 105data is deleted or altered, so use the 106.Dq -d w 107(write) command only if you know exactly what you are doing. 108.Pp 109Also avoid ungraceful interrupting of an ongoing transaction on the I2C bus, 110as it can lead to potentially dangerous effects. Consider the following 111scenario: when the host CPU is reset (for whatever reason) in the middle of a 112started I2C transaction, the I2C slave device could be left in write mode 113waiting for data or offset to arrive. When the CPU reinitializes itself and 114talks to this I2C slave device again, the commands and other control info it 115sends are treated by the slave device as data or offset it was waiting for, 116and there's great potential for corruption if such a write is performed. 117.Sh EXAMPLES 118.Pp 119.Bl -bullet 120.It 121Scan the default bus (/dev/iic0) for devices: 122.Pp 123i2c -s 124.It 125Scan the default bus (/dev/iic0) for devices and skip addresses 0x56 and 1260x45. 127.Pp 128i2c -s -n 0x56:0x45 129.It 130Scan the default bus (/dev/iic0) for devices and skip address range 1310x34 to 0x56. 132.Pp 133i2c -s -n 0x34..0x56 134.It 135Read 8 bytes of data from device at address 0x56 (e.g., an EEPROM): 136.Pp 137i2c -a 0x56 -d r -c 8 138.It 139Write 16 bytes of data from file data.bin to device 0x56 at offset 0x10: 140.Pp 141i2c -a 0x56 -d w -c 16 -o 0x10 -b < data.bin 142.It 143Copy 4 bytes between two EEPROMs (0x56 on /dev/iic1 to 0x57 on /dev/iic0): 144.Pp 145i2c -a 0x56 -f /dev/iic1 -d r -c 0x4 -b | i2c -a 0x57 -f /dev/iic0 -d w -c 4 -b 146.It 147Reset the controller: 148.Pp 149i2c -f /dev/iic1 -r 150.El 151.Sh SEE ALSO 152.Xr iic 4 , 153.Xr iicbus 4 154.Sh HISTORY 155The 156.Nm 157utility appeared in 158.Fx 8.0 . 159.Sh AUTHORS 160.An -nosplit 161The 162.Nm 163utility and this manual page were written by 164.An Bartlomiej Sieka 165.Aq tur@semihalf.com 166and 167.An Michal Hajduk 168.Aq mih@semihalf.com . 169