xref: /freebsd/usr.sbin/i2c/i2c.8 (revision a30555576cd9497620112304600f66643318904c)
1477f656bSRafal Jaworowski.\"
2477f656bSRafal Jaworowski.\" Copyright (C) 2008-2009 Semihalf, Michal Hajduk and Bartlomiej Sieka
3477f656bSRafal Jaworowski.\" All rights reserved.
4477f656bSRafal Jaworowski.\"
5477f656bSRafal Jaworowski.\" Redistribution and use in source and binary forms, with or without
6477f656bSRafal Jaworowski.\" modification, are permitted provided that the following conditions
7477f656bSRafal Jaworowski.\" are met:
8477f656bSRafal Jaworowski.\" 1. Redistributions of source code must retain the above copyright
9477f656bSRafal Jaworowski.\"    notice, this list of conditions and the following disclaimer.
10477f656bSRafal Jaworowski.\" 2. Redistributions in binary form must reproduce the above copyright
11477f656bSRafal Jaworowski.\"    notice, this list of conditions and the following disclaimer in the
12477f656bSRafal Jaworowski.\"    documentation and/or other materials provided with the distribution.
13477f656bSRafal Jaworowski.\"
14477f656bSRafal Jaworowski.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15477f656bSRafal Jaworowski.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16477f656bSRafal Jaworowski.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17477f656bSRafal Jaworowski.\" ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18477f656bSRafal Jaworowski.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19477f656bSRafal Jaworowski.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20477f656bSRafal Jaworowski.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21477f656bSRafal Jaworowski.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22477f656bSRafal Jaworowski.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23477f656bSRafal Jaworowski.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24477f656bSRafal Jaworowski.\" SUCH DAMAGE.
25477f656bSRafal Jaworowski.\"
26477f656bSRafal Jaworowski.\" $FreeBSD$
27477f656bSRafal Jaworowski.\"
28*a3055557SIan Lepore.Dd May 22, 2019
29477f656bSRafal Jaworowski.Dt I2C 8
30477f656bSRafal Jaworowski.Os
31477f656bSRafal Jaworowski.Sh NAME
32477f656bSRafal Jaworowski.Nm i2c
33477f656bSRafal Jaworowski.Nd test I2C bus and slave devices
34477f656bSRafal Jaworowski.Sh SYNOPSIS
35477f656bSRafal Jaworowski.Nm
36477f656bSRafal Jaworowski.Cm -a Ar address
37477f656bSRafal Jaworowski.Op Fl f Ar device
38477f656bSRafal Jaworowski.Op Fl d Ar r|w
39477f656bSRafal Jaworowski.Op Fl w Ar 0|8|16
40477f656bSRafal Jaworowski.Op Fl o Ar offset
41477f656bSRafal Jaworowski.Op Fl c Ar count
42*a3055557SIan Lepore.Op Fl m Ar tr|ss|rs|no
43477f656bSRafal Jaworowski.Op Fl b
44477f656bSRafal Jaworowski.Op Fl v
45477f656bSRafal Jaworowski.Nm
46477f656bSRafal Jaworowski.Cm -s
47477f656bSRafal Jaworowski.Op Fl f Ar device
48477f656bSRafal Jaworowski.Op Fl n Ar skip_addr
49477f656bSRafal Jaworowski.Op Fl v
50477f656bSRafal Jaworowski.Nm
51477f656bSRafal Jaworowski.Cm -r
52477f656bSRafal Jaworowski.Op Fl f Ar device
53477f656bSRafal Jaworowski.Op Fl v
54477f656bSRafal Jaworowski.Sh DESCRIPTION
55477f656bSRafal JaworowskiThe
56477f656bSRafal Jaworowski.Nm
57477f656bSRafal Jaworowskiutility can be used to perform raw data transfers (read or write) with devices
58477f656bSRafal Jaworowskion the I2C bus. It can also scan the bus for available devices and reset the
59477f656bSRafal JaworowskiI2C controller.
60477f656bSRafal Jaworowski.Pp
61477f656bSRafal JaworowskiThe options are as follows:
62477f656bSRafal Jaworowski.Bl -tag -width ".Fl d Ar direction"
63477f656bSRafal Jaworowski.It Fl a Ar address
64477f656bSRafal Jaworowski7-bit address on the I2C device to operate on (hex).
65477f656bSRafal Jaworowski.It Fl b
66477f656bSRafal Jaworowskibinary mode - when performing a read operation, the data read from the device
67477f656bSRafal Jaworowskiis output in binary format on stdout; when doing a write, the binary data to
68477f656bSRafal Jaworowskibe written to the device is read from stdin.
69477f656bSRafal Jaworowski.It Fl c Ar count
70477f656bSRafal Jaworowskinumber of bytes to transfer (dec).
71477f656bSRafal Jaworowski.It Fl d Ar r|w
72477f656bSRafal Jaworowskitransfer direction: r - read, w - write.
73477f656bSRafal Jaworowski.It Fl f Ar device
74477f656bSRafal JaworowskiI2C bus to use (default is /dev/iic0).
75*a3055557SIan Lepore.It Fl m Ar tr|ss|rs|no
76477f656bSRafal Jaworowskiaddressing mode, i.e., I2C bus operations performed after the offset for the
77477f656bSRafal Jaworowskitransfer has been written to the device and before the actual read/write
78*a3055557SIan Leporeoperation.
79*a3055557SIan Lepore.Bl -tag -compact -offset indent
80*a3055557SIan Lepore.It Va tr
81*a3055557SIan Leporecomplete-transfer
82*a3055557SIan Lepore.It Va ss
83*a3055557SIan Leporestop then start
84*a3055557SIan Lepore.It Va rs
85*a3055557SIan Leporerepeated start
86*a3055557SIan Lepore.It Va no
87*a3055557SIan Leporenone
88*a3055557SIan Lepore.El
89*a3055557SIan LeporeSome I2C bus hardware does not provide control over the individual start,
90*a3055557SIan Leporerepeat-start, and stop operations.
91*a3055557SIan LeporeSuch hardware can only perform a complete transfer of the offset and the
92*a3055557SIan Leporedata as a single operation.
93*a3055557SIan LeporeThe
94*a3055557SIan Lepore.Va tr
95*a3055557SIan Leporemode creates control structures describing the transfer and submits them
96*a3055557SIan Leporeto the driver as a single complete transaction.
97*a3055557SIan LeporeThis mode works on all types of I2C hardware.
98477f656bSRafal Jaworowski.It Fl n Ar skip_addr
99477f656bSRafal Jaworowskiskip address - address(es) to be skipped during bus scan.
100c2025a76SJoel DahlThere are two ways to specify addresses to ignore: by range 'a..b' or
101477f656bSRafal Jaworowskiusing selected addresses 'a:b:c'. This option is available only when "-s" is
102477f656bSRafal Jaworowskiused.
103477f656bSRafal Jaworowski.It Fl o Ar offset
104477f656bSRafal Jaworowskioffset within the device for data transfer (hex).
105668f9cbeSAndriy GaponThe default is zero.
106668f9cbeSAndriy GaponUse
107668f9cbeSAndriy Gapon.Dq -w 0
108668f9cbeSAndriy Gaponto disable writing of the offset to the slave.
109477f656bSRafal Jaworowski.It Fl r
110477f656bSRafal Jaworowskireset the controller.
111477f656bSRafal Jaworowski.It Fl s
112477f656bSRafal Jaworowskiscan the bus for devices.
113477f656bSRafal Jaworowski.It Fl v
114344c81a1SWarren Blockbe verbose.
115477f656bSRafal Jaworowski.It Fl w Ar 0|8|16
116477f656bSRafal Jaworowskidevice addressing width (in bits).
117668f9cbeSAndriy GaponThis is used to determine how to pass
118668f9cbeSAndriy Gapon.Ar offset
119668f9cbeSAndriy Gaponspecified with
120668f9cbeSAndriy Gapon.Fl o
121668f9cbeSAndriy Gaponto the slave.
122668f9cbeSAndriy GaponZero means that the offset is ignored and not passed to the slave at all.
123477f656bSRafal Jaworowski.El
124477f656bSRafal Jaworowski.Sh WARNINGS
125477f656bSRafal JaworowskiGreat care must be taken when manipulating slave I2C devices with the
126477f656bSRafal Jaworowski.Nm
127477f656bSRafal Jaworowskiutility. Often times important configuration data for the system is kept in
128477f656bSRafal Jaworowskinon-volatile but write enabled memories located on the I2C bus, for example
129477f656bSRafal JaworowskiEthernet hardware addresses, RAM module parameters (SPD), processor reset
130477f656bSRafal Jaworowskiconfiguration word etc.
131477f656bSRafal Jaworowski.Pp
132477f656bSRafal JaworowskiIt is very easy to render the whole system unusable when such configuration
133477f656bSRafal Jaworowskidata is deleted or altered, so use the
134477f656bSRafal Jaworowski.Dq -d w
135477f656bSRafal Jaworowski(write) command only if you know exactly what you are doing.
136477f656bSRafal Jaworowski.Pp
137477f656bSRafal JaworowskiAlso avoid ungraceful interrupting of an ongoing transaction on the I2C bus,
138477f656bSRafal Jaworowskias it can lead to potentially dangerous effects. Consider the following
139477f656bSRafal Jaworowskiscenario: when the host CPU is reset (for whatever reason) in the middle of a
140477f656bSRafal Jaworowskistarted I2C transaction, the I2C slave device could be left in write mode
141477f656bSRafal Jaworowskiwaiting for data or offset to arrive. When the CPU reinitializes itself and
142477f656bSRafal Jaworowskitalks to this I2C slave device again, the commands and other control info it
143477f656bSRafal Jaworowskisends are treated by the slave device as data or offset it was waiting for,
144477f656bSRafal Jaworowskiand there's great potential for corruption if such a write is performed.
145477f656bSRafal Jaworowski.Sh EXAMPLES
146477f656bSRafal Jaworowski.Bl -bullet
147477f656bSRafal Jaworowski.It
148477f656bSRafal JaworowskiScan the default bus (/dev/iic0) for devices:
149477f656bSRafal Jaworowski.Pp
150477f656bSRafal Jaworowskii2c -s
151477f656bSRafal Jaworowski.It
152477f656bSRafal JaworowskiScan the default bus (/dev/iic0) for devices and skip addresses 0x56 and
153477f656bSRafal Jaworowski0x45.
154477f656bSRafal Jaworowski.Pp
155477f656bSRafal Jaworowskii2c -s -n 0x56:0x45
156477f656bSRafal Jaworowski.It
157477f656bSRafal JaworowskiScan the default bus (/dev/iic0) for devices and skip address range
158477f656bSRafal Jaworowski0x34 to 0x56.
159477f656bSRafal Jaworowski.Pp
160477f656bSRafal Jaworowskii2c -s -n 0x34..0x56
161477f656bSRafal Jaworowski.It
162477f656bSRafal JaworowskiRead 8 bytes of data from device at address 0x56 (e.g., an EEPROM):
163477f656bSRafal Jaworowski.Pp
164477f656bSRafal Jaworowskii2c -a 0x56 -d r -c 8
165477f656bSRafal Jaworowski.It
166477f656bSRafal JaworowskiWrite 16 bytes of data from file data.bin to device 0x56 at offset 0x10:
167477f656bSRafal Jaworowski.Pp
168477f656bSRafal Jaworowskii2c -a 0x56 -d w -c 16 -o 0x10 -b < data.bin
169477f656bSRafal Jaworowski.It
170477f656bSRafal JaworowskiCopy 4 bytes between two EEPROMs (0x56 on /dev/iic1 to 0x57 on /dev/iic0):
171477f656bSRafal Jaworowski.Pp
172477f656bSRafal Jaworowskii2c -a 0x56 -f /dev/iic1 -d r -c 0x4 -b | i2c -a 0x57 -f /dev/iic0 -d w -c 4 -b
173477f656bSRafal Jaworowski.It
174477f656bSRafal JaworowskiReset the controller:
175477f656bSRafal Jaworowski.Pp
176477f656bSRafal Jaworowskii2c -f /dev/iic1 -r
177477f656bSRafal Jaworowski.El
178477f656bSRafal Jaworowski.Sh SEE ALSO
179477f656bSRafal Jaworowski.Xr iic 4 ,
180477f656bSRafal Jaworowski.Xr iicbus 4
181477f656bSRafal Jaworowski.Sh HISTORY
182477f656bSRafal JaworowskiThe
183477f656bSRafal Jaworowski.Nm
184477f656bSRafal Jaworowskiutility appeared in
185477f656bSRafal Jaworowski.Fx 8.0 .
186477f656bSRafal Jaworowski.Sh AUTHORS
187477f656bSRafal Jaworowski.An -nosplit
188477f656bSRafal JaworowskiThe
189477f656bSRafal Jaworowski.Nm
190477f656bSRafal Jaworowskiutility and this manual page were written by
19101c2b8acSBaptiste Daroussin.An Bartlomiej Sieka Aq Mt tur@semihalf.com
192477f656bSRafal Jaworowskiand
19301c2b8acSBaptiste Daroussin.An Michal Hajduk Aq Mt mih@semihalf.com .
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